Cache storage system

Abstract

In one embodiment, a computer server system includes: a memory for storing data across memory locations; a plurality of processing cores including corresponding local caches in which cache lines read from the memory are cached; an interconnect for managing read operations and write operations to the memory and the local caches, maintaining local cache location data for cache lines of the cache based on the corresponding memory location from which the cache line of the cache was read from the memory, receiving a write request for a data element to be written to one of the memory locations, responsive to the local cache location data and the memory location of the write request, locating the local cache location to which the data element is to be written, and sending an update request to a first processing core to update the corresponding first local cache with the data element in response to the located local cache location.

Description

Technical Field

[0001] The present invention relates to computer systems and, in particular but not exclusively, to cache loading. Background Art

[0002] In a multi-core system, a buffer in memory (e.g., in DRAM) is allocated to each core. The buffer is managed by the core, and the buffer space may also be allocated to a network interface controller (NIC), which transmits packets between the core and the device in the network. Packet data received from the network and destined for a particular core is stored in a buffer in the memory allocated to the core together with a descriptor. In some systems, the NIC may use receive side scaling (RSS) to classify received packets and place the received packet data into a corresponding queue associated with the corresponding core based on the classification. The NIC may also notify the core (e.g., via an interrupt) that there is received packet data in the memory, from which the core retrieves the packet descriptor and then retrieves the packet data (e.g., packet payload) for updating its local cache. A similar process may be used for other peripheral devices, such as fast non-volatile memory (NVMe) solid-state drive (SSD) devices. Summary of the invention

[0003] According to an embodiment of the present disclosure, a computer server system is provided, comprising: a memory configured to store data across memory locations; a plurality of processing cores including corresponding local caches in which cache lines read from the memory are cached; and an interconnect configured to: manage read operations and write operations of the memory and the local cache, maintain local cache location data of the cache lines of the cache based on the corresponding memory locations of the cache lines read from the memory, receive a write request for a data element to be written to one of the memory locations, and in response to the local cache location data and the memory location of the write request, find the local cache location to which the data element is written, and send an update request to a first processing core among the processing cores to update the corresponding first local cache in the processing core with the data element in response to the found local cache location.

[0004] Further in accordance with an embodiment of the present disclosure, the first processing core is configured to update the first local cache with the data element in response to the sent update request.

[0005] Still further in accordance with an embodiment of the present disclosure, the interconnect includes a directory configured to store local cache location data for cache lines of the cache based on corresponding ones of the memory locations of the cache lines of the cache, and the interconnect is configured to query the directory in response to the memory location of a write request, thereby generating a found local cache location.

[0006] In addition, according to an embodiment of the present disclosure, the system includes an interface controller configured to receive a packet from at least one device, the packet including a data element, and generate a write request.

[0007] Furthermore, according to an embodiment of the present disclosure, the interface controller is configured to tag a write request with an indication to push the data element to the first local cache even if the interface controller is not aware of the local cache location.

[0008] Further according to an embodiment of the present disclosure, the interface controller is configured to: classify the received packet in response to header data of the received packet, find one of the memory locations to which the data element of the received packet is written in response to the classification of the received packet; and generate a write request for the data element in response to the found memory location.

[0009] Still further according to an embodiment of the present disclosure, the interface controller is configured to: search for a queue for receiving packets in response to classification of the received packets, search for a buffer descriptor for receiving packets in response to the found queue, and search for a memory location to which data elements of the received packets are written in response to the found buffer descriptor.

[0010] In addition, according to an embodiment of the present disclosure, the interface controller includes a network interface controller for managing receiving packets through a network, and the at least one device includes at least one node in the network.

[0011] Furthermore, according to an embodiment of the present disclosure, the interface controller includes a peripheral device controller, and the at least one device includes at least one peripheral device.

[0012] Furthermore, according to an embodiment of the present disclosure, at least one peripheral device includes one or more of the following disk drive or hardware accelerator.

[0013] According to another embodiment of the present disclosure, a computer server method is also provided, including: storing data in a memory across memory locations; caching cache lines read from the memory in local caches of multiple processing cores; managing read operations and write operations of the memory and the local cache, maintaining local cache location data of the cache lines of the cache based on the corresponding memory locations of the cache lines read from the memory, receiving a write request for a data element to be written to one of the memory locations, responsive to the local cache location data and the memory location of the write request, searching the local cache location to which the data element is to be written, and sending an update request to a first processing core among the processing cores to update a corresponding first local cache in the local cache with the data element in response to the corresponding local cache location found.

[0014] According still further to an embodiment of the present disclosure, the method includes updating the first local cache with the data element in response to the sent update request.

[0015] In addition, according to an embodiment of the present disclosure, the method includes: storing local cache location data of cache lines of the cache in a directory according to corresponding memory locations in the memory locations of the cache lines of the cache; and querying the directory in response to the memory location of the write request, thereby generating a found local cache location.

[0016] Furthermore, according to an embodiment of the present disclosure, the method includes: receiving a packet from at least one device, the packet including a data element; and generating a write request.

[0017] Further in accordance with an embodiment of the present disclosure, the method includes marking, by the interface controller, the write request with an indication to push the data elements of the packet to the first local cache even if the interface controller is not aware of the local cache location.

[0018] Still further according to an embodiment of the present disclosure, the method includes: classifying the received packet in response to header data of the received packet; searching one of the memory locations to which the data elements of the received packet are written in response to the classification of the received packet; and generating a write request for the received packet in response to the found memory location.

[0019] In addition, according to an embodiment of the present disclosure, the method includes: in response to the classification of the received packet, searching for a queue for receiving the packet; in response to the found queue, searching for a buffer descriptor for receiving the packet; and in response to the found buffer descriptor, searching for a memory location to which the data elements of the received packet are written.

[0020] In addition, according to an embodiment of the present disclosure, receiving the packet is performed by a network interface controller, and the method further includes: the network interface controller manages receiving the packet through a network, and the at least one device includes at least one node in the network.

[0021] Furthermore, according to an embodiment of the present disclosure, receiving the packet is performed by a peripheral device controller, and the at least one device includes at least one peripheral device.

[0022] Still further in accordance with an embodiment of the present disclosure, the at least one peripheral device includes one or more of the following: a disk drive or a hardware accelerator. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a block diagram of a computer server system constructed and operative in accordance with an embodiment of the present invention;

[0025] Figure 2 is included in Figure 1 A flowchart of the steps in the method of operation of interconnection in a system;

[0026] Figure 3 is included in Figure 1 A flowchart of steps in a method of operating an interface controller in a system;

[0027] Figure 4 Is management included in Figure 1 A flowchart of the steps in a method of updating a local cache in a system; and

[0028] Figure 5 The update is included in Figure 1 A flow chart of the steps in a method of local caching in a system. DETAILED DESCRIPTION

[0029] As mentioned previously, in a multi-core system, a network interface controller (NIC) may notify the relevant core (e.g., via an interrupt) that receive packet data is present in a memory (e.g., DRAM or SRAM), and the core then retrieves the packet descriptor and then the packet data from the memory for updating its local cache. For example, using Peripheral Component Interconnect Express (PCIe) message signaling interrupts (MSI / MSI-x), the interrupt message is targeted to the correct core, but the descriptor and packet data are typically written to a memory location in the memory, rather than the core's local cache. A scheme known as receive side scaling (RSS) may be used to write the descriptor and packet data to a dedicated queue that is typically associated with a core, thereby avoiding contention when different cores access a shared queue. However, the NIC hardware typically does not know which queue belongs to which core.

[0030] The above method lacks performance because the packet data is first written to the memory, rather than the associated local cache.Performance can be improved by writing the packet data directly to the associated cache.

[0031] One possible solution to the above problem is to make the NIC aware of which core the RSS queue is associated with so that the NIC pushes the data into the cache of that core. This solution depends on specific support for the feature in the NIC and is therefore suboptimal and device dependent.

[0032] Embodiments of the present invention solve the above problems by writing packet descriptors and payload data directly to relevant local cache locations at the central processing unit (CPU) chip interconnect level of the device hosting the multi-core system. Therefore, support and resulting efficiencies can be achieved by any NIC or other suitable device using memory buffers (e.g., allocated to the NIC or other suitable device by the CPU) to transmit data to the CPU software, regardless of whether the NIC (or other device) supports it. In some embodiments, the CPU can be replaced by a graphics processing unit (GPU) or any suitable processing device.

[0033] In some embodiments, any suitable data elements (e.g., payload data or other data) may be written directly to the associated local cache location, whether the data elements come from the NIC, another interface controller, or another element such as a graphics processing unit (GPU) or other CPU.

[0034] It is assumed that information tracked as part of the memory consistency protocol provides a best estimate of where to write the payload data into the local cache based on the latest history of the local cache relative to the same memory location (e.g., memory address) to which the payload data would be written if the payload data was written directly to memory. Therefore, the CPU interconnect uses information tracked as part of the memory consistency protocol (described in more detail below) that tracks local cache usage by memory location (e.g., memory address) from which the processing core reads a cache line from memory. The tracked information includes cache memory locations and their currently corresponding local cache locations. The interconnect handles write requests (write payload data) from the NIC by looking up the cache locations corresponding to the memory locations included in the write request, and directs the relevant cores to update their local caches accordingly with the received payload data. If no corresponding cache locations are found for some memory locations, the relevant payload data is written to memory at the corresponding memory locations.

[0035] Memory consistency is an issue that affects the design of computer systems in which two or more processors or cores share a common memory area. In a multiprocessor or multi-core system, there are two or more processing elements working simultaneously, so they have the potential to access the same memory location at the same time. If none of them change the data in this location, they can share it indefinitely and cache it as much as they need. However, once one updates the location, the other may be working on an outdated copy, such as the one residing in its local cache. Therefore, a scheme (e.g., a memory consistency protocol) is needed to notify all processing elements of changes to all shared values, thereby providing consistent memory for the system. The consistency protocol can be, for example, directory-based and / or snoop-based.

[0036] Therefore, in such a multi-core system, reads and writes to memory and cache updates are managed according to a memory consistency protocol in which the CPU interconnect maintains a directory that includes a table that lists the cache locations of cache lines that are currently locally cached and their associated states and the memory location (e.g., memory address) from which the cache line is read from the memory (e.g., DRAM or SRAM).

[0037] For example, whenever a core accesses a memory location in DRAM that is not already in the local cache, the CPU interconnect is notified that an access has occurred via the memory location using a table in the directory and keeping track of the cached memory location.

[0038] As another example, if a core requests to read a line from DRAM, the CPU interconnect receives the read request and checks the directory to check whether the latest updated version associated with the memory location is in DRAM or in the local cache. The latest version of the data can then be used by the requesting core.

[0039] As yet another example, if a core wants to update a cache line of a cache, the core notifies the interconnect about the update, and all other cached copies of that cache line (as listed in the directory) are invalidated. The interconnect may send a snoop request to invalidate the other cache lines, and then grant the core write permission to the entire cache line of that memory location.

[0040] For example, for a write transaction, the CPU interconnect may receive a write request to write data to a memory location in memory. The CPU interconnect checks the directory to determine if there is a cached copy of the memory location. If there is a cached copy, the CPU interconnect may send a snoop request to the associated core(s) to invalidate their copies. After receiving an invalidation confirmation, the CPU interconnect writes the data to the memory (e.g., DRAM) at the memory location.

[0041] In an embodiment of the present invention, upon receiving a write request from an interface controller such as a NIC, the CPU interconnect does not invalidate the copy on the relevant core, but instead writes the data directly to the local cache of the relevant processing core based on the known cache location data in the directory. If there is no cache copy for the memory location in the local cache, the data will be written to the memory at the memory location.

[0042] Writing data directly to the local cache has several advantages. First, the round-trip delay of listening for ineffectiveness before forwarding the data is avoided. Second, with respect to packet descriptors, typically the relevant processing cores poll the descriptors so that the memory address is cached in the local cache of the correct core. Third, with respect to packet data, a buffer pool (of memory buffers assigned to different cores) is typically implemented for each core, so the last packet using the memory buffer has been processed by the core that will process the new packet. In this case, the memory address will also be cached in the local cache of the correct target core. Fourth, the CPU interconnect naturally tracks the cache location as part of its cache coherence implementation without explicit knowledge of the behavior of the interface controller and the application type.

[0043] System Description

[0044] Now to Figure 1 For reference, Figure 11 is a block diagram of a computer server system 10 constructed and operated according to an embodiment of the present invention. The computer server system 10 includes a plurality of processing cores 12, a memory 14 (such as a dynamic random access memory (DRAM) or a static random access memory (SRAM)), a CPU interconnect 16, and an interface controller 18. The memory 14 is configured to store data across a plurality of memory locations. The processing cores 12 include respective local caches 20 (e.g., one local cache 20 per processing core 12) in which cache lines read from the memory 14 from some memory locations in the memory 14 are cached. In some embodiments, the processing cores 12 may be included in a processing unit such as a central processing unit or a graphics processing unit (GPU). The CPU interconnect 16 may be replaced by any suitable interconnect, such as, but not limited to, a GPU interconnect. The interconnect 16 includes a directory 22 configured to store local cache location data and status data of cache lines of a cache according to the corresponding memory locations from which the cache lines of the cache are read from the memory 14. The directory 22 may include a table indexed by memory location and, for each listed memory location, a corresponding local cache location that currently stores data from the memory location. Each listed memory location may also include a state of the corresponding cache line. The state may include: "dirty", which indicates that the cached data has been modified from the corresponding data included in the memory 14; and "clean", which indicates that the cached data has not been modified; "exclusive", which indicates that only one core has a copy of the data; "shared", which indicates that there are multiple copies of the data cached from the memory 14. The state may depend on the consistency protocol used. Cache lines removed from the cache are typically also removed from the table. The directory 22 is updated by the interconnect 16, which receives read and write requests and update notifications used to update the directory 22. The interconnect 16 also performs other memory consistency tasks according to any suitable memory consistency protocol.

[0045] The interface controller 18 may include any suitable interface controller that receives packets from and sends packets to at least one device 26. In some implementations, the interface controller 18 includes a network interface controller (NIC) to manage receiving packets over a network from (one or more) devices 26, which may be one (or more) nodes in the network 24.

[0046] In some implementations, interface controller 18 includes a peripheral device controller, and device(s) 26 include at least one peripheral device. In some implementations, the peripheral device includes a disk drive and / or a hardware accelerator.

[0047] Now to Figure 2 For reference, Figure 2 Yes Figure 1 Flowchart 28 of steps in a method of operating the interconnect 16 in the system 10. Figure 1 Reference is made to. The interconnect 16 is configured to manage (box 30) read operations and write operations to the memory 14 and the local cache 20, including updates and invalidations to the local cache 20, while maintaining memory consistency according to any suitable memory consistency protocol. The interconnect 16 is configured to maintain (box 32) state data of cache lines currently cached and local cache location data in the directory 22 based on the corresponding memory location of the cache line cached from the memory 14. The local cache data and state data can be stored in a table indexed according to the memory location. For example, each cache line cached in the local cache 20 may include a row in the table, which includes: the memory location of the cache line cached from the memory 14; the cache location in the local cache 20 where the cache line is cached; and the state of the cache line.

[0048] Now to Figure 3 For reference, Figure 3 Yes Figure 1 Flowchart 40 of steps in a method of operating the interface controller 18 in the system 10. Figure 1 Reference is made. The interface controller 18 is configured to receive (block 42) packets from the device(s) 26. The interface controller 18 is configured to classify (block 44) the received packets in response to header data of the received packets. Classification may be performed according to any suitable mechanism, such as, but not limited to, RSS.

[0049] In some embodiments, the interface controller 18 is configured to look up (block 46) a receive queue for the received packet (in which the received packet is posted) in response to the classification of the received packet. The interface controller 18 is configured to look up (block 48) a buffer descriptor for the received packet in response to the found queue. The interface controller 18 is configured to look up (block 50) a memory location to which the payload data of the received packet is written in response to the classification of the received packet. In some embodiments, the interface controller 18 is configured to look up the memory location to which the payload data of the received packet is written in response to the found buffer descriptor.

[0050] In some embodiments, the interface controller 18 writes the payload data of the received packet to a memory buffer (a logical buffer that can be in any suitable physical location), from which the payload data is then transferred to one of the local caches 20, and an indication of the packet (e.g., a packet has arrived) and a buffer descriptor (e.g., a completion queue element (CQE)) are written to the memory location.

[0051] The interface controller 18 is configured to generate (block 52) a write request for the payload data (of the received packet) to be written to the located memory location (located in the step of block 50). In some embodiments, the interface controller 18 is configured to tag the write request with an indication to push the payload data of the packet to one of the local caches 20 even if the interface controller is not aware of the local cache location.

[0052] In practice, some or all of the functions of the interface controller 18 may be combined in a single physical component, or alternatively, implemented using multiple physical components. These physical components may include hardwired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of the interface controller 18 may be performed by a programmable processor under the control of suitable software. For example, the software may be downloaded to the device in electronic form over a network. Alternatively or additionally, the software may be stored in a tangible, non-temporary computer-readable storage medium, such as an optical, magnetic or electronic memory.

[0053] The steps of blocks 42-52 described above may be repeated for subsequent packets or any other suitable data.The term "payload data" is used above and below as an example of a data element, and any other suitable data element may replace the payload data.

[0054] Now to Figure 4 For reference, Figure 4 is included in Figure 1 60 of steps in a method of managing local cache updates in the system 20 of FIG.

[0055] The interconnect 16 is configured to receive (block 62) a write request from the interface controller 18 (to write the payload data to the memory location looked up by the interface controller 18). The interconnect 16 is configured to look up (block 64) a local cache location of the (currently used) local cache 20 in which the payload data of the received packet is written in response to the local cache location data (stored in the directory 22) and the memory location of the write request. As a sub-step of block 64, the interconnect 16 is configured to query (block 66) the directory 22 in response to the memory location of the write request (e.g., the corresponding memory location included in the write request), thereby generating a local cache location of the local cache 20 in which to write the payload data of the received packet.

[0056] The interconnect 16 is configured to send an update request to the corresponding processing core 12 (associated with the local cache location found) to update (block 68) the corresponding local cache 20 with the payload data of the received packet in response to the found (currently used) local cache location. In other words, an update request to update a local cache 20 with the payload data of the packet is sent to the processing core 12 including the local cache 20 including the relevant (currently used) local cache location found for the packet. If the memory location is not found in the step of block 66, which means that the memory location is not associated with one of the cache lines of the current cache, the interconnect 16 is configured to write the relevant payload data to the memory location in the memory 14.

[0057] In practice, some or all of the functions of interconnect 16 may be combined in a single physical component, or alternatively, implemented using multiple physical components. These physical components may include hardwired or programmable devices, or a combination of both. In some embodiments, at least some of the functions of interconnect 16 may be performed by a programmable processor under appropriate software control. For example, the software may be downloaded to the device in electronic form over a network. Alternatively or additionally, the software may be stored in a tangible, non-transitory computer-readable storage medium, such as an optical, magnetic or electronic memory.

[0058] For subsequent write requests, the steps of blocks 62 - 68 described above may be repeated.

[0059] Now to Figure 5 For reference, Figure 5 is included in Figure 1 Flowchart 80 of steps in a method of updating a local cache 20 in a system. Figure 1Reference is made to. The associated processing core 12 is configured to receive (block 82) an update request from the interconnect 16. In other words, each processing core 12 receives an update request addressed to the processing core 12. The associated processing core 12 is configured to retrieve the payload data of the corresponding packet from the memory buffer in which the payload data is stored, and in response to the sent update request, update the corresponding local cache 20 with the payload data of the corresponding packet (i.e., each processing core 12 updates its own local cache 20).

[0060] For subsequent update requests, the steps of blocks 82-84 described above may be repeated.

[0061] In practice, some or all of the processing cores 12 may be combined in a single physical component, or alternatively, implemented using multiple physical components. These physical components may include hardwired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of the processing core 12 may be performed by a programmable processor under appropriate software control. The software may be downloaded to the device in electronic form, for example, over a network. Alternatively or additionally, the software may be stored in a tangible, non-temporary computer-readable storage medium, such as an optical, magnetic or electronic memory.

[0062] For the sake of clarity, various features of the invention described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features of the invention described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0063] The above embodiments are illustrated by way of example, and the present invention is not limited to what has been specifically shown and described above. On the contrary, the scope of the present invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications that will occur to those skilled in the art after reading the foregoing description and that are not disclosed in the prior art.

Claims

1. A computer server system, comprising: a memory configured to store data across memory locations; a plurality of processing cores including respective local caches in which cache lines read from the memory are cached; An interconnect portion, the interconnect portion being configured to: managing read operations and write operations of the memory and the local cache; maintaining local cache location data for the cache line of a cache based on corresponding ones of the memory locations from which the cache line of a cache was read from the memory; receiving a write request for a data element to be written to one of the memory locations; responsive to the local cache location data and the memory location of the write request, looking up a local cache location to write the data element to; as well as An update request is sent to a first one of the processing cores to update a corresponding first one of the local caches with the data element in response to the located local cache location.

2. The system of claim 1, wherein the first processing core is configured to update the first local cache with the data element in response to the sent update request.

3. The system of claim 1, wherein: the interconnect comprising a directory configured to store the local cache location data for the cache line of cache according to respective ones of the memory locations for the cache line of cache; as well as The interconnect is configured to query the directory in response to the memory location of the write request, thereby generating the looked-up local cache location.

4. The system according to claim 1, further comprising an interface controller, wherein the interface controller is configured to: receiving a packet from at least one device, the packet comprising the data element; and The write request is generated.

5. The system of claim 4, wherein the interface controller is configured to tag the write request with an indication to push the data element to the first local cache even if the interface controller is not aware of the local cache location.

6. The system of claim 4, wherein the interface controller is configured to: classifying the received packets in response to header data of the received packets; responsive to the classification of the received packet, looking up one of the memory locations to which to write the data element of the received packet; and In response to the memory location being found, the write request for the data element is generated.

7. The system of claim 6, wherein the interface controller is configured to: responsive to the classification of the received packet, looking up a queue for the received packet; In response to the found queue, searching for a buffer descriptor for the received packet; and In response to the buffer descriptor being found, the memory location to which the data element of the received packet is to be written is found.

8. The system of claim 4, wherein the interface controller comprises a network interface controller for managing reception of packets over a network, the at least one device comprising at least one node in the network.

9. The system of claim 4, wherein the interface controller comprises a peripheral device controller and the at least one device comprises at least one peripheral device.

10. The system of claim 9, wherein the at least one peripheral device comprises one or more of: a disk drive; or a hardware accelerator.

11. A computer server method comprising: storing data in memory across memory locations; caching cache lines read from the memory in local caches of a plurality of processing cores; managing read operations and write operations of the memory and the local cache; maintaining local cache location data for the cache line of a cache based on corresponding ones of the memory locations from which the cache line of a cache was read from the memory; receiving a write request for a data element to be written to one of the memory locations; responsive to the local cache location data and the memory location of the write request, looking up a local cache location to write the data element to; as well as An update request is sent to a first one of the processing cores to update a corresponding first one of the local caches with the data element in response to the located corresponding local cache location.

12. The method according to claim 11, further comprising: In response to the sent update request, the first local cache is updated with the data element.

13. The method according to claim 11, further comprising: storing the local cache location data for the cache line of the cache in a directory according to corresponding ones of the memory locations for the cache line of the cache; as well as The directory is queried in response to the memory location of the write request, resulting in a looked-up local cache location.

14. The method according to claim 11, further comprising: receiving a packet from at least one device, the packet comprising the data element; as well as The write request is generated.

15. The method according to claim 14, further comprising: The write request is marked by the interface controller with an indication to push the data elements of the packet to the first local cache even though the interface controller is not aware of the local cache location.

16. The method according to claim 14, further comprising: classifying the received packets in response to header data of the received packets; responsive to the classification of the received packet, looking up one of the memory locations to which the data element of the received packet is to be written; as well as In response to the memory location being found, the write request for the received packet is generated.

17. The method according to claim 16, further comprising: responsive to the classification of the received packet, looking up a queue for the received packet; In response to the found queue, searching for a buffer descriptor for the received packet; as well as In response to the buffer descriptor being found, the memory location to which the data element of the received packet is to be written is found.

18. The method of claim 14, wherein receiving the packet is performed by a network interface controller, the method further comprising: The network interface controller manages receiving packets over a network, and the at least one device comprises at least one node in the network.

19. The method of claim 14, wherein receiving the packet is performed by a peripheral device controller, and the at least one device comprises at least one peripheral device.

20. The method of claim 19, wherein the at least one peripheral device comprises one or more of: a disk drive; or a hardware accelerator.

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