Memory system and method of operating the same

Abstract

This invention provides a memory system and its operation method. The memory system includes multiple pseudo-static random access memory (PSRAM) chips and a memory controller. The PSRAM chips are coupled to each other. When each PSRAM chip receives an action command, it determines whether a refresh conflict will occur and generates a conflict signal accordingly. The memory controller controls the PSRAM chips based on the conflict signal. All PSRAM chips share their respective conflict signals to synchronously perform the same delay.

Description

Technical Field

[0001] The present invention relates to a memory system, and in particular to a memory system suitable for a pseudo static random access memory (PSRAM) chip and an operation method thereof. Background Art

[0002] Pseudo Static Random Access Memory has the advantages of large capacity and low cost, but it is necessary to consider the need to perform refresh operations regularly. In order to avoid the impact caused by refresh conflicts, the existing pseudo static random access memory has a variable delay time (VL) mode. The length of the delay in the variable delay time (VL) mode depends on whether there will be a refresh conflict with the write action or the read action. When a refresh conflict occurs, a long delay is used, and when it does not occur, a short delay is used. The long delay time is, for example, twice the short delay time.

[0003] In order to reduce the size of electronic devices, multi-chip package (MCP) has become one of the inevitable trends in future development. Under the architecture of multi-chip package, when one pseudo-static random access memory chip generates a refresh conflict, the other pseudo-static random access memory chips may not also generate refresh conflicts at the same time, and the delay time applicable to the two may also be different. Since it is difficult to adjust the delay time in real time, the difficulty in operation increases. Therefore, how to design pseudo-static random access memory chips using multi-chip package becomes an important issue. Summary of the invention

[0004] The invention provides a memory system and an operation method thereof, which can share the refresh conflict information to all memory chips so as to synchronously perform the same delay.

[0005] The memory system of the present invention includes a plurality of pseudo-static random access memory chips and a memory controller. The pseudo-static random access memory chips are coupled to each other. When each pseudo-static random access memory chip receives an action command, it determines whether a refresh conflict will occur in itself, and generates a conflict signal accordingly. The memory controller controls the pseudo-static random access memory chip according to the conflict signal. All pseudo-static random access memory chips share their own conflict signals to synchronously perform the same delay.

[0006] The memory system operation method of the present invention is applicable to a memory system including a plurality of pseudo-static random access memory chips. The operation method includes: receiving an action command; determining whether a refresh conflict will occur and generating a conflict signal accordingly; and sharing the conflict signal to all pseudo-static random access memory chips to synchronously perform the same delay.

[0007] Based on the above, in the memory system of the present invention, all memory chips can share their respective conflict information (conflict signals). When a refresh conflict occurs in at least one memory chip, the delay time can be set to a long delay. When there is no refresh conflict in all memory chips, the delay time can be set to a short delay. Since the delay time of all memory chips is the same, a variable delay time mode can be used in a multi-chip package architecture, and the delay time can be adjusted in real time to improve the execution speed of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing a memory system according to an embodiment of the present invention;

[0009] Figure 2 A circuit diagram showing a memory system according to an embodiment of the present invention;

[0010] Figure 3 A schematic diagram showing the structure of an output drive circuit according to an embodiment of the present invention is shown;

[0011] Figure 4 A circuit diagram showing a memory system according to another embodiment of the present invention;

[0012] Figure 5 A schematic diagram showing the structure of an output drive circuit according to another embodiment of the present invention;

[0013] Figure 6 A flow chart showing an operating method of a memory system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] Please refer to Figure 1 , Figure 1 The memory system 100 includes a plurality of pseudo-static random access memory chips (eg, pseudo-static random access memory chips 110_0 and 110_1 ) and a memory controller 120 .

[0015] The pseudo-static random access memory chips 110_0 and 110_1 are, for example, pseudo-static random access memory chips configured using multi-chip packaging technology. The pseudo-static random access memory chips 110_0 and 110_1 are coupled to each other. In this embodiment, when each pseudo-static random access memory chip 110_0 and 110_1 receives an action command ACMD, each pseudo-static random access memory chip 110_0 and 110_1 determines whether a refresh conflict occurs in itself, and generates a conflict signal accordingly.

[0016] The memory controller 120 is coupled to the pseudo-static random access memory chips 110_0 and 110_1. The memory controller 120 can control the pseudo-static random access memory chips 110_0 and 110_1 according to the conflict signal. For example, when performing a write operation or a read operation, the memory controller 120 can appropriately adjust the actions of the pseudo-static random access memory chips 110_0 and 110_1 according to the conflict signal from the access memory chips 110_0 and 110_1, so as to smoothly perform the write operation or the read operation while taking into account the data reliability.

[0017] In addition, in the present embodiment, the pseudo-static random access memory chips 110_0 and 110_1 can share their own conflict signals to synchronously perform the same delay. For example, when a refresh conflict occurs in the pseudo-static random access memory chip 110_0, the pseudo-static random access memory chip 110_0 will generate a corresponding conflict signal. Since the pins for transmitting the conflict signal in the pseudo-static random access memory chips 110_0 and 110_1 are coupled to each other, the pseudo-static random access memory chip 110_1 can set its own delay time according to the conflict signal received from the pseudo-static random access memory chip 110_0, so as to synchronously perform the same delay with the pseudo-static random access memory chip 110_0.

[0018] In this embodiment, the memory controller 120 can be a logic circuit composed of multiple logic gates, or a central processing unit (CPU), a programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), other similar devices or a combination of these devices, but the embodiments of the present invention are not limited thereto.

[0019] It should be noted that, although the present embodiment is described with the memory system 100 including two pseudo-static random access memory chips 110_0 and 110_1, the number of the above chips is not limited thereto in the present invention. Those skilled in the art can infer the number of pseudo-static random access memory chips to be larger according to their actual needs and with reference to the teachings of the present embodiment.

[0020] The memory system 100 of the present invention can be configured in two ways, for example, an address expansion type and an IO expansion type. The following describes the two ways with examples.

[0021] Figure 2 FIG. 2 is a circuit diagram of a memory system according to an embodiment of the present invention. The memory system 200 is suitable for an address extension type configuration. Figure 2 As shown, the memory system 200 includes a plurality of pseudo-static random access memory chips (eg, pseudo-static random access memory chips 210_0 and 210_1) and a memory controller 220. The number of the pseudo-static random access memory chips is not limited to this in the present invention.

[0022] like Figure 2 As shown, the pseudo-static random access memory chip 210_0 includes a strobe pin DQS_0, a data pin ADQ_0, a driver controller 230_0, an output driver circuit 240_0, and a receiver 250_0. The pseudo-static random access memory chip 210_1 includes a strobe pin DQS_1, a data pin ADQ_1, a driver controller 230_1, an output driver circuit 240_1, and a receiver 250_1. Among them, the select pin DQS_0 of the pseudo-static random access memory chip 210_0 is coupled to the select pins of all other pseudo-static random access memory chips (for example, the select pin DQS_1 of the pseudo-static random access memory chip 210_1) and the select pin DQS_C of the memory controller 220, and the data pin ADQ_0 of the pseudo-static random access memory chip 210_0 is coupled to the data pins of all other pseudo-static random access memory chips (the data pin ADQ_1 of the pseudo-static random access memory chip 210_1) and the data pin ADQ_C of the memory controller 220.

[0023] Taking the pseudo-static random access memory chip 210_0 as an example, the driving controller 230_0 can receive the action command ACMD from the memory controller 220 through the data pin ADQ_0.

[0024] For example, the pseudo-static random access memory chip 210_0 may be a 256M-bit, 8IO pseudo-static random access memory chip. The action command ACMD sent by the memory controller 220 may include 8-bit command information, 25-bit address information A<24:0>, and 1-bit chip information A<24:0>. <25> When chip information A <25> When the chip information A is 0 (low logic level), it indicates that the memory controller 220 selects the pseudo-static random access memory chip 210_0. <25> When the chip information A is 1 (high logic level), it indicates that the memory controller 220 selects the pseudo-static random access memory chip 210_1. Thus, when the pseudo-static random access memory chip 210_0 receives the action command ACMD, the driving controller 230_0 can, for example, <25> And determine whether to take corresponding action.

[0025] Next, when the PSRAM chip 210_0 is selected, the driving controller 230_0 may determine whether a refresh conflict occurs in the PSRAM chip 210_0 according to the time point and content of the received action command ACMD, and generate the control signal CL1_0 accordingly.

[0026] The output driving circuit 240_0 is coupled to the strobe pin DQS_0 and the driving controller 230_0. The output driving circuit 240_0 provides a conflict signal CF1_0 to the strobe pin DQS_0 according to the control signal CL1_0.

[0027] The receiver 250_0 is coupled to the strobe pin DQS_0. The receiver 250_0 can determine the delay time according to the conflict signal CF1_0 to delay the corresponding pseudo-static random access memory chip 210_0. In this embodiment, the receiver 250_0 can be a logic circuit including a counter and a plurality of logic gates, but the embodiment of the present invention is not limited thereto.

[0028] The operation of the PSRAM chip 210_1 is substantially the same as that of the PSRAM chip 210_0 , so the operation of the actions and signals (including the control signal CL1_1 and the conflict signal CF1_1 ) thereof may refer to that of the PSRAM chip 210_0 .

[0029] The following example illustrates the detailed circuit structure and operation of the output driving circuit 240_0. Figure 3 The output driving circuit 240_0 includes a transistor T1, a transistor T2, a transistor T3 and a resistor R1. In this embodiment, the control signal CL1_0 includes sub-control signals CL1, CL2 and CL3, which are used to control the transistor T1, the transistor T2 and the transistor T3 respectively.

[0030] exist Figure 3 In the embodiment, a first terminal of the transistor T1 receives a driving voltage VDD, a second terminal of the transistor T1 is coupled to a strobe pin DQS_0, and a control terminal of the transistor T1 receives a sub-control signal CL1.

[0031] The first terminal of the transistor T2 is coupled to the second terminal of the transistor T1 , the second terminal of the transistor T2 receives the ground voltage VSS, and the control terminal of the transistor T2 receives the sub-control signal CL2 .

[0032] The first terminal of the transistor T3 is coupled to the second terminal of the transistor T1. The control terminal of the transistor T3 receives the sub-control signal CL3. The first terminal of the resistor R1 is coupled to the second terminal of the transistor T3, and the second terminal of the resistor R1 receives the ground voltage VSS.

[0033] like Figure 3 As shown, transistor T1 is a P-type transistor, and transistors T2 and T3 are N-type transistors. The operation of control signals CL1-CL3 is as follows:

[0034] Table 1

[0035]

[0036] In Table 1, H is a high logic level, and L is a low logic level. V is a high logic level or a low logic level. When H is output to the select pin DQS_0, CL1 and CL2 = L. When L is output to the select pin DQS_0, CL1 and CL2 = H.

[0037] Please also refer to Figure 3 As shown in Table 1, in the operation of the circuit, when the driver controller 230_0 receives the action command ACMD and determines that the corresponding pseudo-static random access memory chip 210_0 will not have a refresh conflict, the control signal CL1 is at a high logic level (H), the control signal CL2 is at a low logic level (L), and the control signal CL3 in the output driver circuit 240_0 is at a high logic level (H). At this time, the transistors T1 and T2 in the output driver circuit 240_0 are disconnected, so the output driver circuit 240_0 will not drive the logic level of the strobe pin DQS_0. In the case that no refresh conflict occurs in all pseudo-static random access memory chips 210_0 and 210_1, since only the transistor T3 in the output driver circuit 240_0 is turned on, the strobe pin DQS_0 will be pulled down to the ground voltage VSS to output the corresponding conflict signal CF1_0 to the strobe pin DQS_0.

[0038] On the other hand, when the driver controller 230_0 receives the action command ACMD and determines that the corresponding pseudo-static random access memory chip 210_0 will have a refresh conflict, the control signal CL1 is at a low logic level (L), the control signal CL2 is at a low logic level (L), and the control signal CL3 in the output driver circuit 240_0 is at a high logic level (H). At this time, the transistor T1 in the output driver circuit 240_0 is turned on, and the transistor T2 is turned off, so the output driver circuit 240_0 will pull up the logic level of the selection pin DQS_0 to output the corresponding conflict signal CF1_0 to the selection pin DQS_0.

[0039] Through the above operation, among the multiple PSRAM chips (eg, PSRAM chips 210_0 and 210_1) of the present invention, the chip with refresh conflict can drive the select pin to a high logic level, while the chip without refresh conflict will not drive the select pin.

[0040] Moreover, such operation mode is not easy to generate bus fight on the pin. When the selection pin DQS_0 is driven to a high logic level, a DC current flows through the transistor T3 and the resistor R1. This current depends on the resistance value of the resistor R1. For example, when the resistor R1 is 10K ohms and VDD is 2.0 volts, the DC current through the transistor T3 is 200u amperes, which is less than the activated current of the pseudo-static random access memory chip.

[0041] As shown in Table 1, during the period when the driving controller 230_0 receives the action command ACMD, no matter whether a refresh conflict occurs or not, only the control signal CL3 in the output driving circuit 240_0 is at a high logic level (H), and the control signals CL3 in other output driving circuits are all at a low logic level (L). This operation method is to turn on the transistor T3 in the output driving circuit 240_0 when no refresh conflict occurs in all the pseudo-static random access memory chips 210_0 and 210_1, so as to pull down the strobe pins DQS_0 and DQS_1 to the ground voltage VSS, thereby preventing the strobe pins DQS_0 and DQS_1 from becoming a high impedance state.

[0042] In addition, during the period when the driving controller 230_0 receives the action command ACMD, the receiver 250_0 is in an enabled state. After the output driving circuit 240_0 outputs the corresponding conflict signal CF1_0 to the selection pin DQS_0, the receiver 250_0 can determine the delay time according to the conflict signal CF1_0.

[0043] Furthermore, since the selection pins of all the pseudo-static random access memory chips 210_0 and 210_1 are coupled to each other, all the pseudo-static random access memory chips 210_0 and 210_1 can be synchronously set to the same delay time. In the case that no refresh conflict occurs in all the pseudo-static random access memory chips 210_0 and 210_1, a shorter delay time can be synchronously set. In this way, under the architecture of the present invention, burst reading and writing across memory chips can be realized.

[0044] Also, as shown in Table 1, during a read operation, the receiver may be disabled. During a write operation, the output driver circuit is disabled and the receiver is enabled because a data mask signal may be generated using a strobe pin.

[0045] Figure 4 FIG. 3 is a circuit diagram of a memory system according to another embodiment of the present invention. The memory system 300 is suitable for an IO expansion type configuration. Figure 4 As shown, the memory system 300 includes a plurality of pseudo-static random access memory chips (eg, pseudo-static random access memory chips 310_0 and 310_1) and a memory controller 320. The number of the pseudo-static random access memory chips is not limited to this in the present invention.

[0046] like Figure 4 As shown, the pseudo-static random access memory chip 310_0 includes a strobe pin DQS_0, a data pin ADQ_0, a delay pin LTY_0, a driver controller 330_0, an output driver circuit 340_0, a receiver 350_0, and an output controller 360_0. The pseudo-static random access memory chip 310_1 includes a strobe pin DQS_1, a data pin ADQ_1, a delay pin LTY_1, a driver controller 330_1, an output driver circuit 340_1, a receiver 350_1, and an output controller 360_1. The strobe pin DQS_0 and the data pin ADQ_0 of the pseudo-static random access memory chip 310_0 are respectively coupled to the strobe pin DQS_C0 and the data pin ADQ_C0 of the memory controller 320. The strobe pin DQS_1 and the data pin ADQ_1 of the pseudo-SRAM chip 310_1 are respectively coupled to the strobe pin DQS_C1 and the data pin ADQ_C1 of the memory controller 320. The delay pin LTY_0 of the pseudo-SRAM chip 310_0 is coupled to the delay pins of all other pseudo-SRAM chips (for example, the delay pin LTY_1 of the pseudo-SRAM chip 310_1).

[0047] Taking the pseudo-SRAM chip 310_0 as an example, the driving controller 330_0 can receive the action command ACMD0 from the memory controller 320 through the data pin ADQ_0.

[0048] For example, the pseudo-static random access memory chip 310_0 may be a 256M-bit, 8IO pseudo-static random access memory chip. Different from the above-mentioned embodiment, since the memory controller 320 is coupled to the data pin ADQ_0 of the pseudo-static random access memory chip 310_0 and the data pin ADQ_1 of the static random access memory chip 310_1 via the data pin ADQ_C0 and the data pin ADQ_C1 respectively, when the pseudo-static random access memory chip 310_0 is to be selected, the memory controller 320 may send the action command ACMD0 to the pseudo-static random access memory chip 310_0 via the data pin ADQ_C0. In the IO-expanded multi-chip package, the memory controller 320 simultaneously sends the same command to all pseudo-static random access memory chips 310_0 and 310_1.

[0049] Next, when the PSRAM chip 310_0 is selected, the driving controller 330_0 may determine whether a refresh conflict occurs in the PSRAM chip 310_0 according to the time point and content of the received action command ACMD0, and generate the control signal CL2_0 accordingly.

[0050] The output driving circuit 340_0 is coupled to the delay pin LTY_0 and the driving controller 330_0. The output driving circuit 340_0 provides a conflict signal CF2_0 to the delay pin LTY_0 according to the control signal CL2_0.

[0051] The receiver 350_0 is coupled to the delay pin LTY_0. The receiver 350_0 can determine the delay time according to the conflict signal CF2_0 to delay the corresponding pseudo-static random access memory chip 310_0. In this embodiment, the receiver 350_0 can be a logic circuit including a counter and a plurality of logic gates, but the embodiment of the present invention is not limited thereto.

[0052] The output controller 360_0 is coupled to the receiver 350_0 and the strobe pin DQS_0. The output controller 360_0 provides a delay signal LT_0 to the strobe pin DQS_0 according to the determined delay time. In this way, the memory controller 320 can obtain the delay information of the pseudo-static random access memory chip 310_0 so as to properly control the pseudo-static random access memory chip 310_0. In this embodiment, the output controller 360_0 can be a logic circuit composed of a plurality of logic gates, but the embodiment of the present invention is not limited thereto.

[0053] In addition, in one embodiment, an off-chip driver (OCD) may be connected between the output controller 360_0 and the strobe pin DQS_0 to adjust the voltage of the strobe pin DQS_0 to compensate for the pull-up and pull-down resistor values ​​to ensure signal integrity and reliability.

[0054] The operation of the PSRAM chip 310_1 is substantially the same as that of the PSRAM chip 310_0 , so the operation of its actions and signals (including the action command ACMD1 , the control signal CL2_1 , the conflict signal CF2_1 and the delay signal LT_1 ) can refer to the operation of the PSRAM chip 310_0 .

[0055] The following example illustrates the detailed circuit structure and operation of the output driving circuit 340_0. Figure 5 The output driving circuit 340_0 is a schematic diagram showing the structure of another embodiment of the present invention. The output driving circuit 340_0 includes a transistor T4, a transistor T5 and a resistor R2. In this embodiment, the control signal CL2_0 includes sub-control signals CL4 and CL5, which are used to control the transistor T4 and the transistor T5 respectively.

[0056] exist Figure 5 In the embodiment, a first terminal of the transistor T4 receives a driving voltage VDD, a second terminal of the transistor T4 is coupled to the delay pin LTY_0, and a control terminal of the transistor T4 receives a sub-control signal CL4.

[0057] The first terminal of the transistor T5 is coupled to the second terminal of the transistor T4. The control terminal of the transistor T5 receives the sub-control signal CL5. The first terminal of the resistor R2 is coupled to the second terminal of the transistor T5, and the second terminal of the resistor R2 receives the ground voltage VSS.

[0058] like Figure 5 As shown, transistor T4 is a P-type transistor, and transistor T5 is an N-type transistor. The operation of control signals CL4 and CL5 is as follows:

[0059] Table 2

[0060]

[0061] In Table 2, H is a high logic level and L is a low logic level.

[0062] Please also refer to Figure 5As shown in Table 2, in the operation of the circuit, when the driving controller 330_0 receives the action command ACMD0 and determines that the corresponding pseudo-static random access memory chip 310_0 will not have a refresh conflict, the control signal CL4 is at a high logic level (H), and the control signal CL5 in the output driving circuit 340_0 is at a high logic level (H). At this time, the transistor T4 in the output driving circuit 340_0 is turned off, so the output driving circuit 340_0 will not drive the logic level of the delay pin LTY_0. In the case that no refresh conflict occurs in all pseudo-static random access memory chips 310_0 and 310_1, since only the transistor T5 in the output driving circuit 340_0 is turned on, the delay pin LTY_0 will be pulled down to the ground voltage VSS to output the corresponding conflict signal CF2_0 to the delay pin LTY_0.

[0063] On the other hand, when the driver controller 330_0 receives the action command ACMD0 and determines that the corresponding pseudo-static random access memory chip 310_0 will have a refresh conflict, the control signal CL4 is at a low logic level (L), and the control signal CL5 in the output driver circuit 340_0 is at a high logic level (H). At this time, the transistor T4 in the output driver circuit 340_0 is turned on, so the output driver circuit 340_0 pulls up the logic level of the delay pin LTY_0 to output the corresponding conflict signal CF2_0 to the delay pin LTY_0.

[0064] Through the above operation, among the multiple PSRAM chips (eg, PSRAM chips 310_0 and 310_1) of the present invention, the chip with refresh conflict can drive the delay pin to a high logic level, while the chip without refresh conflict will not drive the delay pin.

[0065] Moreover, such operation mode is not easy to generate bus fight on the pin. When the delay pin LYT_0 is driven to a high logic level, a DC current flows through the transistor T5 and the resistor R2. This current depends on the resistance value of the resistor R2. For example, when the resistor R2 is 10K ohms and VDD is 2.0 volts, the DC current through the transistor T5 is 200u amperes, which is less than the activated current of the pseudo-static random access memory chip.

[0066] As shown in Table 2, during the period when the driving controller 330_0 receives the action command ACMD0, no matter whether a refresh conflict occurs or not, only the control signal CL5 in the output driving circuit 340_0 is at a high logic level (H), and the control signals CL5 in other output driving circuits are at a low logic level (L). Such an operation method is to turn on the transistor T5 in the output driving circuit 340_0 when no refresh conflict occurs in all the pseudo-static random access memory chips 310_0 and 310_1, thereby pulling down the delay pins LYT_0 and LYT_1 to the ground voltage VSS, thereby preventing the delay pins LYT_0 and LYT_1 from becoming a high impedance state.

[0067] In addition, during the period when the driving controller 330_0 receives the action command ACMD0, the receiver 350_0 is in an enabled state. When the output driving circuit 340_0 outputs the corresponding conflict signal CF2_0 to the delay pin LYT_0, the receiver 350_0 can determine the delay time according to the conflict signal CF2_0.

[0068] Furthermore, since the delay pins of all the PSRAM chips 310_0 and 310_1 are coupled to each other, all the PSRAM chips 310_0 and 310_1 can be synchronously set to the same delay time. When no refresh conflict occurs in all the PSRAM chips 310_0 and 310_1, a shorter delay time can be synchronously set.

[0069] Please refer to the following Figure 6 , Figure 6 A flow chart showing an operation method of a memory system according to an embodiment of the present invention. The memory system of this embodiment includes a plurality of pseudo-static random access memory chips. In step S610, an action command is received. Next, in step S620, it is determined whether a refresh conflict will occur, and a conflict signal is generated accordingly. Finally, in step S630, the conflict signal is shared to all pseudo-static random access memory chips to synchronously perform the same delay. Figure 6 The implementation details of the steps of the operating method of the memory system are described in detail in the aforementioned multiple embodiments and multiple implementation methods, and will not be repeated here.

[0070] In summary, in the memory system of the present invention, all memory chips can share their own conflict information (conflict signals). Since the delay time of all memory chips is the same, a variable delay time mode can be used in a multi-chip package architecture to adjust the delay time in real time to increase the execution speed of the memory chip and reduce the difficulty of control and operation.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory system, comprising: A plurality of pseudo-static random access memory chips, the plurality of pseudo-static random access memory chips are coupled to each other, and when each of the plurality of pseudo-static random access memory chips receives an action command, it determines whether a refresh conflict will occur in itself, and generates a conflict signal accordingly; as well as A memory controller is coupled to the plurality of pseudo-static random access memory chips and controls the plurality of pseudo-static random access memory chips according to the conflict signal. wherein all the plurality of pseudo-static random access memory chips share their respective conflict signals to synchronously perform the same delay, Each of the plurality of pseudo-static random access memory chips comprises: A strobe pin coupled to the memory controller and strobe pins of all other pseudo-static random access memory chips; A data pin coupled to the memory controller and data pins of all other pseudo-static random access memory chips; A driving controller receives the action command from the memory controller through the data pin, determines whether the refresh conflict occurs in the pseudo-static random access memory chip according to the time point and content of the received action command, and generates a control signal accordingly; and The output driving circuit is coupled to the strobe pin and the driving controller, and provides the conflict signal to the strobe pin according to the control signal.

2. The memory system according to claim 1, wherein: The control signal includes a first sub-control signal, a second sub-control signal and a third sub-control signal, and the output drive circuit includes: A first transistor, a first terminal of which receives a driving voltage, a second terminal of which is coupled to the selection pin, and a control terminal of the first transistor receives the first sub-control signal; A second transistor, a first terminal of which is coupled to the second terminal of the first transistor, a second terminal of which receives a ground voltage, and a control terminal of the second transistor receives the second sub-control signal; A third transistor, a first terminal of which is coupled to the second terminal of the first transistor, and a control terminal of the third transistor receives the third sub-control signal; and A resistor has a first end coupled to the second end of the third transistor and a second end receiving the ground voltage.

3. The memory system according to claim 2, wherein: The first transistor is a P-type transistor, and the second transistor and the third transistor are N-type transistors.

4. The memory system according to claim 1, wherein: Each of the plurality of pseudo-static random access memory chips further comprises: The receiver is coupled to the selection pin and determines a delay time according to the conflict signal so as to delay the corresponding pseudo-static random access memory chip.

5. A memory system, comprising: A plurality of pseudo-static random access memory chips, the plurality of pseudo-static random access memory chips are coupled to each other, and when each of the plurality of pseudo-static random access memory chips receives an action command, it determines whether a refresh conflict will occur in itself, and generates a conflict signal accordingly; as well as A memory controller is coupled to the plurality of pseudo-static random access memory chips and controls the plurality of pseudo-static random access memory chips according to the conflict signal. wherein all the plurality of pseudo-static random access memory chips share their respective conflict signals to synchronously perform the same delay, Each of the plurality of pseudo-static random access memory chips comprises: A strobe pin coupled to the memory controller; A data pin coupled to the memory controller; A delay pin coupled to the delay pins of all other pseudo-static random access memory chips; A driving controller receives the action command from the memory controller through the data pin, determines whether the refresh conflict occurs in the pseudo-static random access memory chip according to the time point and content of the received action command, and generates a control signal accordingly; and The output driving circuit is coupled to the delay pin and the driving controller, and provides the conflict signal to the delay pin according to the control signal.

6. The memory system according to claim 5, characterized in that: The control signal includes a first sub-control signal and a second sub-control signal, and the output drive circuit includes: A first transistor, a first terminal of which receives a driving voltage, a second terminal of which is coupled to the delay pin, and a control terminal of the first transistor receives the first sub-control signal; a second transistor, a first terminal of which is coupled to the second terminal of the first transistor, and a control terminal of the second transistor receives the second sub-control signal; and A resistor has a first terminal coupled to the second terminal of the second transistor and a second terminal receiving a ground voltage.

7. The memory system according to claim 6, characterized in that: The first transistor is a P-type transistor, and the second transistor is an N-type transistor.

8. The memory system according to claim 5, characterized in that: Each of the plurality of pseudo-static random access memory chips further comprises: A receiver coupled to the delay pin, and determining a delay time according to the conflict signal; and The output controller is coupled to the receiver and the enable pin, and provides a delay signal to the enable pin according to the determined delay time.

9. An operating method of a memory system, the memory system comprising a plurality of pseudo-static random access memory chips, each of the plurality of pseudo-static random access memory chips comprising a strobe pin and a data pin, the strobe pin being coupled to the strobe pins of all other pseudo-static random access memory chips, the data pin being coupled to the data pins of all other pseudo-static random access memory chips, The operation method comprises: Receiving an action command via the data pin; Determine whether a refresh conflict will occur and generate a conflict signal accordingly; as well as Sharing the conflict signal to all the plurality of pseudo-static random access memory chips to synchronously perform the same delay, The step of determining whether the refresh conflict will occur and generating the conflict signal accordingly includes: Determining whether the refresh conflict will occur in the corresponding pseudo-static random access memory chip according to the time point and content of the received action command, and generating a control signal accordingly; and According to the control signal, the conflict signal is provided to the enable pin.

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