Signal conditioner device and signal conditioner method

Abstract

The present disclosure relates to a signal adjuster device and a signal adjustment method, wherein the signal adjuster device comprises a frequency adjustment circuit, a filter circuit and a power estimation circuit. The frequency adjustment circuit is used to receive a two-tone signal from a signal generator and generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is used to filter the first signal to generate a second signal. The power estimation circuit is used to detect the power of an intermodulation distortion signal component of the two-tone signal in the second signal, and adjust at least one of the first coefficient and the second coefficient according to the power to reduce the power.

Description

Technical Field

[0001] The present invention relates to a signal adjuster device, and more particularly to a signal adjuster device and a signal adjustment method for correcting the linearity of a signal generator. Background Art

[0002] In order to obtain a more reliable test result, the specification of the test instrument usually needs to be better than the specification of the circuit to be tested. However, with the development of technology, the specifications of integrated circuits are getting higher and higher, making the existing test instruments insufficient to verify the integrated circuits. In order to test whether the operation of the integrated circuit is correct, the existing test instruments need to be replaced with better test instruments. This will greatly increase the testing cost. Summary of the invention

[0003] In some embodiments, the signal adjuster device includes a frequency adjustment circuit, a filter circuit, and a power estimation circuit. The frequency adjustment circuit is used to receive a two-tone signal from a signal generator and generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is used to filter the first signal to generate a second signal. The power estimation circuit is used to detect the power of the intermodulation distortion signal component of the two-tone signal in the second signal, and adjust at least one of the first coefficient and the second coefficient according to the power to reduce the power.

[0004] In some embodiments, the signal adjustment method includes the following operations: receiving a dual-frequency signal from a signal generator and generating a first signal based on the dual-frequency signal, wherein the signal generator generates the dual-frequency signal based on a first coefficient and a second coefficient; filtering the first signal to generate a second signal; and detecting the power of an intermodulation distortion signal component of the dual-frequency signal in the second signal, and adjusting at least one of the first coefficient and the second coefficient based on the power to reduce the power.

[0005] The features, implementation and effects of the present invention are described in detail below with reference to the drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a signal conditioner device according to some embodiments of the present invention is drawn;

[0007] Figure 2 According to some embodiments of the present invention, Figure 1 A schematic diagram of the changing trends of multiple signal components in ; and

[0008] Figure 3 A flow chart of a signal adjustment method according to some embodiments of the present invention is drawn. DETAILED DESCRIPTION

[0009] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any of the words discussed herein in the context of the present invention are merely illustrative and should not limit the scope and meaning of the present invention. Similarly, the present invention is not limited to the various embodiments shown in this specification.

[0010] As used herein, "coupling" or "connection" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuit" may refer to a device that is composed of at least one transistor and / or at least one active and passive component connected in a certain manner to process signals.

[0011] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this document, the terms first, second, and third are used to describe and distinguish each component. Therefore, the first component in this document may also be referred to as the second component without departing from the intent of the present invention. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

[0012] Figure 1 A schematic diagram of a signal conditioner device 100 is drawn according to some embodiments of the present invention. In some embodiments, the signal conditioner device 100 can be used to correct a signal (for example, but not limited to, a two-tone signal ST) generated from a signal generator 100A to improve the linearity of the signal. In this way, the corrected signal can be used to test the circuit under test 100B to obtain a more accurate test result. In some embodiments, the signal conditioner device 100 is an external device independent of the circuit under test 100B. In some embodiments, the signal conditioner device 100 can be integrated into the circuit under test 100B. For example, the circuit under test 100B is a chip, and the signal conditioner device 100 can be a part of a test circuit in the chip. The above-mentioned application method of the signal conditioner device 100 is only used for example, and the present invention is not limited thereto.

[0013] The signal adjuster device 100 includes a frequency adjustment circuit 120, a filter circuit 140, and a power estimation circuit 160. In some embodiments, the signal generator 100A may be an arbitrary waveform generator, which may generate a dual-frequency signal ST according to data (e.g., Formula 2 described later) input by a user or an external device. In some embodiments, the dual-frequency signal ST may be used to test the linearity of the circuit under test 100B. Compared with a single-tone signal, a more accurate test result may be obtained by using the dual-frequency signal ST. The frequency adjustment circuit 120 receives the dual-frequency signal ST from the signal generator 100A and generates a signal SA according to the dual-frequency signal ST.

[0014] In some embodiments, the dual-frequency signal ST mainly includes a signal component S1 having a frequency f1 and a signal component S2 having a frequency f2. If the signal generator 100A is nonlinear, a nonlinear model (such as the equation 3 described later) can be used to derive that the dual-frequency signal ST also includes an intermodulation distortion (IMD3) signal component S I1 With the IMD3 signal component S I2 , where the IMD3 signal component S I2 The frequency of the IMD3 signal component S is 2×f2-f1. I1 The frequency of is 2×f1-f2. In some cases, if the above IMD3 signal component S I1 With the IMD3 signal component S I2 If the power of both is too high, the linearity of the dual-frequency signal ST will be reduced, resulting in the dual-frequency signal ST being insufficient as a test signal. To avoid the above situation, in some embodiments, the power estimation circuit 160 may respond to the IMD3 signal component S I2 (or IMD3 signal component S I1 ) to adjust at least one of the coefficients C1 and C2 to reduce the IMD3 signal component S I1 With the IMD3 signal component S I2 In this way, the linearity of the dual-frequency signal ST can be improved to obtain more accurate test results.

[0015] In some embodiments, the frequency adjustment circuit 120 is used to down-convert the dual-frequency signal ST to generate the signal SA. For example, the frequency adjustment circuit 120 may be a self-mixer circuit, which may modulate the dual-frequency signal ST according to the dual-frequency signal ST to generate the signal SA. In the dual-frequency signal ST, the IMD3 signal component S I1 The frequency can be expressed as f1-(f2-f1), and the IMD3 signal component S I2The frequency of can be expressed as f2+(f2-f1), where f2-f1 is the frequency offset between signal component S2 and signal component S1. I1 With the IMD3 signal component S I2 The frequency of each of the two frequency components S is positively correlated with the absolute frequency of the dual frequency signal ST (ie, frequency f1 or frequency f2) and the frequency difference. I2 It can be downconverted to the IMD3 signal component S3 in the signal SA. The IMD3 signal component S3 has a frequency of 2×(f2-f1), and this frequency is positively correlated only with the frequency difference and has nothing to do with the absolute frequency. If the IMD3 signal component S3 of the dual-frequency signal ST is directly detected I2 (or the IMD3 signal component S I1 ), the subsequent circuit (such as the analog-to-digital converter circuit 162) needs to have a higher sampling rate, which is not easy to implement in hardware. In some embodiments, by detecting the power of the down-converted IMD3 signal component S3, the sampling rate required by the subsequent circuit can be reduced.

[0016] For example, if the frequency f1 is 10 MHz and the frequency f2 is 12 MHz, the IMD3 signal component S 12 The frequency and IMD3 signal component S I1 The frequencies of the IMD3 signal component S3 associated with the dual-frequency signal ST in the signal SA are 14 MHZ and 8 MHZ respectively. After being processed by the frequency adjustment circuit 120, the frequency of the IMD3 signal component S3 associated with the dual-frequency signal ST in the signal SA is 4 MHZ. In this way, the sampling rate of the subsequent circuit can be reduced, so it is easier to implement in hardware. In other embodiments, the frequency adjustment circuit 120 can be implemented by an envelope detector circuit.

[0017] The filter circuit 140 is used to filter the signal SA to generate a signal SB. In some cases, the signal SA may introduce a larger DC offset due to the operation of the frequency adjustment circuit 120, causing the subsequent circuit (for example, the analog-to-digital converter circuit 162) to be oversaturated. To avoid this problem, the filter circuit 140 can filter out at least one signal component S4 (equivalent to the aforementioned DC offset) close to the DC frequency (i.e., 0 Hz) in the signal SA to generate the signal SB. In some embodiments, the signal SA may also introduce additional signal components of other frequencies due to the operation of the frequency adjustment circuit 120. In other words, the frequency of the at least one signal component S4 may further include additional signal components, wherein the frequency of the additional signal component is less than or equal to the aforementioned frequency difference f2-f1. In some embodiments, the filter circuit 140 can be implemented by a high-pass filter circuit or a band-pass filter circuit.

[0018] The power estimation circuit 160 is used to detect the power of the IMD3 signal component S3 associated with the dual-frequency signal ST in the signal SB, and adjust at least one of the coefficient C1 and the coefficient C2 according to the power of the IMD3 signal component S3. In some embodiments, the power estimation circuit 160 includes an analog-to-digital converter circuit 162 and a processing circuit 164. The analog-to-digital converter circuit 162 is used to convert the IMD3 signal component S3 into a digital code SC. The processing circuit 164 obtains the power of the IMD3 signal component S3 according to the digital code SC, and adjusts at least one of the coefficient C1 and the coefficient C2 according to the power of the IMD3 signal component S3, thereby reducing the power of the IMD3 signal component S3 (i.e., reducing the power of the IMD3 signal component S3). I1 And the IMD3 signal component S I2 In some embodiments, the processing circuit 164 may be a digital signal processing circuit including one or more digital logic circuits for executing Figure 3 Multiple operations in to adjust at least one of the coefficient C1 and the coefficient C2.

[0019] Referring to the following technical literature: K.Kato, F.Abe, K.Wakabayashi, T.Yamada, H. Kobayashi, O.Kobayashi, K.Niitsu "Low-IMD Two-Tone Signal Generation for ADC Testing", IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, Taipei, Taiwan, China (May 2012), the dual-frequency signal ST can be expressed as follows:

[0020] Formula 1:

[0021]

[0022] In some embodiments, further referring to the technical literature, x1(n) and x2(n) in the above formula 1 can be rewritten as the following formula 2:

[0023]

[0024] Wherein Ts is the sampling frequency of the signal generator 100A, the function related to the frequency f1 is used to define the signal component S1, the function related to the frequency f2 is used to define the signal component S2, A is the amplitude of the signal component S1 and the signal component S2, the coefficient C1 is used to set the phase of the signal component S1, and the coefficient C2 is used to set the phase of the signal component S2. In some embodiments, the initial value of the coefficient C1 and the initial value of the coefficient C2 can be set to 3, but the present invention is not limited thereto. In some embodiments, the user can input the above formula 2 to the signal generator 100A so that the signal generator 100A generates the dual-frequency signal ST according to the coefficient C1 and the coefficient C2.

[0025] In order to improve linearity, the above-mentioned document sets the two signal components in the dual-frequency signal to have a fixed phase angle. However, in actual applications, this setting method still cannot completely eliminate the influence of the IMD3 signal component. Compared with the above-mentioned document, in some embodiments of the present invention, by detecting the IMD3 signal component S3 to adjust the coefficient C1 and / or the coefficient C2, the IMD3 signal component S3 in the dual-frequency signal ST can be reduced according to the actual application environment. I1 With S I2 power to achieve optimal linearity.

[0026] Figure 2 According to some embodiments of the present invention, Figure 1 The signal component S in I2 And a schematic diagram of the variation trend of the signal component S3. If the signal generator 100A is nonlinear, the nonlinear model of the signal generator 100A can be expressed as follows:

[0027] ST=a1·x(n)+a3·x(n) 3 …3

[0028] Wherein, a1 is the coefficient of the first-order term and a3 is the coefficient of the third-order term. The aforementioned IMD3 signal component is related to the third-order term. In an experimental example, if Figure 2 As shown in the figure, when the coefficient a3 changes, the signal component S I2 The variation trend (i.e., line segment 210) is similar to the variation trend (i.e., line segment 215) of signal component S3. In other words, when adjusting coefficients C1 and C2, the power of signal component S3 can be detected (rather than directly detecting signal component S I2 ) to confirm whether the linearity of the dual-frequency signal ST is improved. As mentioned above, by using this detection method, the sampling rate can be reduced to facilitate hardware implementation.

[0029] Figure 3A flow chart of a signal adjustment method 300 is drawn according to some embodiments of the present invention. In operation S310, a dual-frequency signal ST is received from a signal generator 100A, and a signal SA is generated according to the dual-frequency signal ST, wherein the signal generator 100A generates the dual-frequency signal ST according to a coefficient C1 and a coefficient C2. In operation S320, the signal SA is filtered to generate a signal SB. In operation S330, the power of an IMD3 signal component S3 associated with the dual-frequency signal ST in the signal SB is detected, and the coefficient C1 and the coefficient C2 are adjusted according to the power of the IMD3 signal component S3 to reduce the power of the IMD3 signal component S3.

[0030] In detail, operation S330 includes a plurality of steps S31 to S34. In step S31, coefficient C1 and / or coefficient C2 are adjusted. In step S32, the power of IMD3 signal component S3 in signal SB is detected. In operation S33, it is confirmed whether the power of IMD3 signal component S3 is minimum. If yes, it means that the signal adjustment method 300 is completed. If no, step S34 is executed. In step S34, the adjustment direction of coefficient C1 and / or coefficient C2 is determined.

[0031] For example, in the initial operation, the power estimation circuit 160 may set the coefficient C1 and the coefficient C2 to initial values ​​and record the power of the IMD3 signal component S3. Then, the power estimation circuit 160 may fix the coefficient C1 and increase the coefficient C2 (i.e., step S31), and confirm whether the power of the adjusted IMD3 signal component S3 is smaller than the previous power of the IMD3 signal component S3 (i.e., steps S32 and S33). If yes, the power estimation circuit 160 may increase the coefficient C2 again (i.e., steps S34 and S31) and repeat the above steps S32 and S33 to find the minimum power of the IMD3 signal component S3. On the contrary, if the power of the adjusted IMD3 signal component S3 is not less than the previous power, the power estimation circuit 160 can change to a fixed coefficient C1 and reduce the coefficient C2 (i.e., step S34 and step S31), and confirm whether the power of the adjusted IMD3 signal component S3 is less than the previous power (i.e., step S32 and step S33) to find the minimum power of the IMD3 signal component S3. By recording the power of the IMD3 signal component S3 corresponding to a variety of combinations of coefficients C1 and coefficients C2, the power estimation circuit 160 can output the coefficients C1 and C2 that can minimize the power of the IMD3 signal component S3. Based on steps S31 to S34, it can be understood that in some embodiments, Figure 1 The power estimation circuit 160 may minimize the power of the IMD3 signal component S3 by recursively adjusting at least one of the coefficient C1 and the coefficient C2.

[0032] The above description only takes the adjustment coefficient C2 as an example, but the present invention is not limited thereto. In some embodiments, in order to find the minimum power, the power estimation circuit 160 may fix the value of the coefficient C2 after adjusting the coefficient C2, and start adjusting the coefficient C1 according to the same steps. In different embodiments, the power estimation circuit 160 may adjust the coefficient C1 and the coefficient C2 at the same time in step S31, or only adjust one of the coefficient C1 and the coefficient C2.

[0033] The above-mentioned multiple operations of the signal adjustment method 300 are only examples, and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present invention, the various operations under the signal adjustment method 300 can be appropriately added, replaced, omitted or performed in a different order. Alternatively, one or more operations under the signal adjustment method 300 can be performed simultaneously or partially simultaneously.

[0034] In an experimental example, compared to the method of using a fixed phase angle in the aforementioned related literature, after adjustment by the signal adjustment method 300 , the linearity of the dual-frequency signal ST can be improved by about 9.52 decibels (dB) on average.

[0035] In summary, through the signal conditioner device and signal conditioner method in some embodiments of the present invention, a circuit with a lower sampling rate can be used to detect the IMD3 signal component and dynamically adjust the coefficient input to the signal generator to improve the linearity of the output signal of the signal generator.

[0036] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person having ordinary knowledge in the technical field may make changes to the technical features of the present invention according to the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope defined by the claims of this specification.

[0037]

Explanation of symbols

[0038] 100: Signal Conditioner Device

[0039] 100A: Signal generator

[0040] 100B: Circuit under test

[0041] 120: Frequency adjustment circuit

[0042] 140: Filter circuit

[0043] 160: Power estimation circuit

[0044] 162: Analog-to-digital converter circuit

[0045] 164: Processing circuit

[0046] C1, C2: coefficients

[0047] f1, f2: frequency

[0048] S1, S2, S4: signal components

[0049] S I1 , S I2 , S3: intermodulation distortion signal component

[0050] SA, SB: signal

[0051] SC: Digital code

[0052] ST: Dual frequency signal

[0053] 210, 215: Line segment

[0054] 300: Signal adjustment method

[0055] S310, S320, S330: Operation

[0056] S31, S32, S33, S34: steps.

Claims

1. A signal conditioner device, comprising: A frequency adjustment circuit is used for receiving a dual-frequency signal from a signal generator and generating a first signal according to the dual-frequency signal, wherein the signal generator generates the dual-frequency signal according to a first coefficient and a second coefficient; a filter circuit, configured to filter the first signal to generate a second signal; and a power estimation circuit for detecting a power of an intermodulation distortion signal component associated with the dual-frequency signal in the second signal, and adjusting at least one of the first coefficient and the second coefficient according to the power to reduce the power; in, The dual-frequency signal includes a first signal component and a second signal component. The first signal component or the second signal component has an absolute frequency, and a frequency of the intermodulation distortion signal component is independent of the absolute frequency.

2. The signal conditioner device according to claim 1, wherein: The frequency adjustment circuit is used for down-converting the dual-frequency signal to generate the first signal.

3. The signal conditioner device according to claim 1, wherein: The frequency adjustment circuit is a self-mixer circuit.

4. The signal conditioner device according to claim 1, wherein: The filter circuit is used for filtering out at least one signal component close to a DC frequency in the first signal to generate the second signal.

5. The signal conditioner device according to claim 1, wherein: The dual-frequency signal includes a first signal component and a second signal component. The first coefficient is used to set a phase of the first signal component, and the second coefficient is used to set a phase of the second signal component.

6. The signal conditioner device according to claim 1, wherein: The dual-frequency signal includes a first signal component and a second signal component. There is a frequency difference between the first signal component and the second signal component, and a frequency of the intermodulation distortion signal component is positively correlated with the frequency difference.

7. The signal conditioner device according to claim 1, wherein: The power estimation circuit is used for recursively adjusting the first coefficient and the second coefficient to minimize the power of the intermodulation distortion signal component.

8. A signal adjustment method, comprising: Receive a dual-frequency signal from a signal generator, and generate a first signal according to the dual-frequency signal, wherein the signal generator generates the dual-frequency signal according to a first coefficient and a second coefficient; filtering the first signal to generate a second signal; and detecting a power of an intermodulation distortion signal component associated with the dual-frequency signal in the second signal, and adjusting at least one of the first coefficient and the second coefficient according to the power to reduce the power; in, The dual-frequency signal includes a first signal component and a second signal component. The first signal component or the second signal component has an absolute frequency, and a frequency of the intermodulation distortion signal component is independent of the absolute frequency.

9. The signal adjustment method according to claim 8, wherein: Receiving the dual-frequency signal from the signal generator and generating the first signal according to the dual-frequency signal comprises: The dual-frequency signal is down-converted to generate the first signal.

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