GaN substrate wafer and method for manufacturing the same

Abstract

The present invention provides a GaN substrate wafer that can be preferably used for manufacturing a nitride semiconductor device having a horizontal device structure and has improved productivity. The GaN substrate wafer is a GaN substrate wafer having a (0001) orientation, and has a first region provided on the N-polarity side and a second region having a minimum thickness provided on the Ga-polarity side with a regrowth interface therebetween. The minimum thickness of the second region is 20 μm or more, and in at least a part of the second region, the total concentration of compensating impurities is 1×10<supgt;17< / supgt> atoms / cm<supgt;3< / supgt> or more.

Description

Technical Field

[0001] The present invention relates to a substrate wafer formed of GaN (gallium nitride) and a method for manufacturing the same. The substrate wafer is a wafer used as a substrate when manufacturing a semiconductor device. Background Art

[0002] A GaN substrate wafer having a high resistance region formed locally only on the surface side has been proposed, wherein a GaN thick film having a region with a high concentration of transition metal atoms only on the upper portion is grown on a sapphire wafer by HVPE (Hydride Vapor Phase Epitaxy), and then the GaN thick film is peeled off from the sapphire wafer (Patent Document 1). Patent Document 1 states that GaN crystals that have been made highly resistive by impurity doping are prone to cracking, but a GaN substrate wafer manufactured by this method is not prone to cracking.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2012-232884 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] When manufacturing a GaN substrate wafer having a region with increased specific resistance only locally provided on the surface side by the method disclosed in Patent Document 1, it is necessary to grow a GaN thick film on a sapphire wafer by HVPE for each GaN substrate wafer produced.

[0008] Solutions to the problem

[0009] The present inventors have discovered that, by replacing the method disclosed in Patent Document 1 with that of growing a GaN layer doped with compensating impurities on a prefabricated GaN wafer having a low impurity concentration, it is possible to more efficiently produce GaN substrate wafers having a region with increased resistivity only locally on the surface side.

[0010] The present invention has been completed based on the above-mentioned concept, and its embodiments include the following.

[0011] [1] A GaN substrate wafer having a (0001) orientation,

[0012] The GaN substrate wafer has a first region disposed on the N polarity side and a second region having a minimum thickness disposed on the Ga polarity side across a regrown interface, wherein:

[0013] The minimum thickness of the second region is 20 μm or more.

[0014] In at least a portion of the second region, the total concentration of the compensating impurities is 1×10 17 atoms / cm 3 above.

[0015] [2] The GaN substrate wafer according to [1] above, wherein:

[0016] The first region satisfies one or more conditions selected from the following (a) to (c):

[0017] (a) Si concentration is 5×10 16 atoms / cm 3 above;

[0018] (b) O concentration is 3×10 16 atoms / cm 3 the following;

[0019] (c) H concentration is 1×10 17 atoms / cm 3 the following.

[0020] [3] The GaN substrate wafer according to [1] or [2] above, wherein:

[0021] In the first region, the total concentration of the compensating impurities is lower than the total concentration of the donor impurities.

[0022] [4] The GaN substrate wafer according to any one of [1] to [3] above, wherein:

[0023] In the first region, the total concentration of compensating impurities is less than 1×10 17 atoms / cm 3 .

[0024] [5] The GaN substrate wafer according to any one of [1] to [4] above, wherein:

[0025] In the first region, the concentration of impurity elements other than Si, O and H is independently 5×10 15 atoms / cm 3 the following.

[0026] [6] The GaN substrate wafer according to any one of [1] to [5] above, which satisfies any of the following conditions (1) to (3),

[0027] (1) having a diameter of 50 mm or more and 55 mm or less and a thickness of 250 μm or more and 450 μm or less,

[0028] (2) having a diameter of 100 mm or more and 105 mm or less and a thickness of 350 μm or more and 750 μm or less,

[0029] (3) Having a diameter of 150 mm or more and 155 mm or less and a thickness of 450 μm or more and 800 μm or less.

[0030] [7] The GaN substrate wafer according to any one of [1] to [6] above, wherein:

[0031] The second region has a main doping region including at least a main surface on the Ga polarity side, and the total concentration of the compensating impurities in the main doping region is 1×10 17 atoms / cm 3 above.

[0032] [8] The GaN substrate wafer according to [7] above, wherein:

[0033] The total concentration of compensating impurities in the main doping region is 1×10 18 atoms / cm 3 above.

[0034] [9] The GaN substrate wafer according to [7] or [8] above, wherein:

[0035] In the main doping region, the total concentration of the compensating impurities is more than twice the total concentration of the donor impurities.

[0036]

[10] The GaN substrate wafer according to any one of [7] to [9] above, wherein:

[0037] The main doping region contains one or more elements selected from carbon and transition metal elements.

[0038]

[11] The GaN substrate wafer according to any one of [7] to

[10] above, wherein:

[0039] The impurity contained in the main doping region at the highest concentration is Fe, Mn or C.

[0040]

[12] The GaN substrate wafer according to any one of [7] to

[11] above, wherein:

[0041] The main doping region is a region within a specific length from the main surface on the polar side of GaN, and the specific length is 20 μm or more.

[0042]

[13] The GaN substrate wafer according to any one of [7] to

[12] above, wherein:

[0043] In the main doping region, the total concentration of the compensating impurities along the c-axis direction varies within a range of ±25% from the central value.

[0044]

[14] The GaN substrate wafer according to

[12] or

[13] above, wherein:

[0045] The specific length is greater than 50 μm.

[0046]

[15] The GaN substrate wafer according to any one of [1]2 to

[14] above, wherein:

[0047] The specific length is greater than or equal to 50% of the minimum thickness of the second region.

[0048]

[16] The GaN substrate wafer according to any one of [1] to

[15] above, wherein:

[0049] The total concentration of compensating impurities in the second region is 5×10 19 atoms / cm 3 the following.

[0050]

[17] The GaN substrate wafer according to any one of [1] to

[16] above, wherein:

[0051] The minimum thickness of the second region is 300 μm or less.

[0052]

[18] The GaN substrate wafer according to any one of [1] to

[17] above, wherein:

[0053] The primary surface on the Ga polarity side is a flat surface.

[0054]

[19] The GaN substrate wafer according to

[18] above, wherein:

[0055] The regrown interface is inclined with respect to the primary surface on the Ga polar side.

[0056]

[20] The GaN substrate wafer according to

[19] above, wherein:

[0057] A thickness difference between one end and the other end of the second region in the direction in which the regrown interface is tilted is not more than 200 μm.

[0058]

[21] An epitaxial wafer comprising:

[0059] The GaN substrate wafer according to any one of [1] to

[20] , and

[0060] A nitride semiconductor layer is epitaxially grown on the main surface on the Ga polarity side of the GaN substrate wafer.

[0061]

[22] A method for manufacturing an epitaxial wafer, the method comprising:

[0062] A step of preparing a GaN substrate wafer according to any one of [1] to

[20] above; and

[0063] A step of growing a nitride semiconductor layer on the main surface on the Ga polarity side of the GaN substrate wafer.

[0064]

[23] A method for manufacturing a nitride semiconductor device, the method comprising:

[0065] A step of preparing a GaN substrate wafer according to any one of [1] to

[20] above;

[0066] A step of growing a nitride semiconductor layer on the main surface on the Ga polarity side of the GaN substrate wafer to obtain an epitaxial wafer; and

[0067] A step of removing the first region of the GaN substrate wafer from at least a portion of the epitaxial wafer.

[0068]

[24] A method for manufacturing a GaN substrate wafer, the method comprising:

[0069] A second step of growing a second GaN thick film having a (0001) orientation on the substrate by HVPE and then slicing the second GaN thick film to obtain a second c-plane GaN wafer; and

[0070] A third step is to grow a GaN film having a (0001) orientation and a thickness greater than 50 μm on the second c-plane GaN wafer by HVPE,

[0071] Furthermore, the GaN film is provided with a total concentration of 1×10 17 atoms / cm 3 The above part.

[0072]

[25] A method for manufacturing a GaN substrate wafer, the method comprising manufacturing a GaN substrate wafer having a region on the N polarity side and a region on the Ga polarity side sandwiching a regrown interface,

[0073] This method has:

[0074] (i) a first step of growing a first GaN thick film formed of unintentionally doped GaN and having a (0001) orientation on a seed crystal wafer by HPVE, and processing the first GaN thick film to obtain at least one first c-plane GaN thick film;

[0075] (ii) a second step of growing a second GaN thick film formed of GaN that is not intentionally doped and has a (0001) orientation on the first c-plane GaN wafer obtained in the first step by HVPE, and slicing a second c-plane GaN wafer from the second GaN thick film; and,

[0076] (iii) a third step of growing a GaN film having a thickness of more than 50 μm and a (0001) orientation on the second c-plane GaN wafer obtained in the second step by HVPE to obtain a stacked structure,

[0077] The GaN film grown in the third step has a total concentration of 1×10 17 atoms / cm 3 The above part.

[0078]

[26] The method for manufacturing a GaN substrate wafer according to

[25] above, wherein:

[0079] The GaN film has a thickness of 300 μm or less.

[0080]

[27] The method for manufacturing a GaN substrate wafer according to

[25] or

[26] above, wherein:

[0081] The GaN substrate wafer satisfies any of the following conditions (1) to (3),

[0082] (1) having a diameter of 50 mm or more and 55 mm or less and a thickness of 250 μm or more and 450 μm or less,

[0083] (2) having a diameter of 100 mm or more and 105 mm or less and a thickness of 350 μm or more and 750 μm or less,

[0084] (3) Having a diameter of 150 mm or more and 155 mm or less and a thickness of 450 μm or more and 800 μm or less.

[0085]

[28] The method for manufacturing a GaN substrate wafer according to any one of

[25] to

[27] above, wherein:

[0086] The GaN film has a region with a length of 20 μm or more in the c-axis direction, and a total concentration of compensating impurities in the region of 1×10 17 atoms / cm 3 The above specific doping regions.

[0087]

[29] The method for manufacturing a GaN substrate wafer according to

[28] above, wherein:

[0088] The total concentration of compensating impurities in the specific doping region is 1×10 18 atoms / cm 3 above.

[0089]

[30] The method for manufacturing a GaN substrate wafer according to

[28] or

[29] above, wherein:

[0090] In the specific doping region, the total concentration of the compensating impurities is more than twice the total concentration of the donor impurities.

[0091]

[31] The method for manufacturing a GaN substrate wafer according to any one of

[28] to

[30] above, wherein:

[0092] The variation of the total concentration of the compensating impurities in the specific doping region along the c-axis direction is within a range of ±25% from the central value.

[0093]

[32] A method for manufacturing a GaN substrate wafer according to any one of

[28] to

[31] above, wherein the length of the region is greater than 50% of the thickness of the GaN film.

[0094]

[33] A method for manufacturing a GaN substrate wafer according to any one of

[28] to

[32] above, wherein the length from the lower end of the specific doping region to the interface between the GaN film and the second c-plane GaN wafer is greater than 1 μm.

[0095]

[34] A method for manufacturing a GaN substrate wafer according to any one of

[28] to

[33] above, wherein the specific doping region contains one or more elements selected from carbon and transition metal elements.

[0096]

[35] A method for manufacturing a GaN substrate wafer according to any one of

[28] to

[34] above, wherein the impurity contained in the specific doping region at the highest concentration is Fe, Mn or C.

[0097]

[36] The method for manufacturing a GaN substrate wafer according to any one of

[24] to

[35] above, wherein the total concentration of the compensating impurities in the GaN film is 5×10 19 atoms / cm 3 the following.

[0098]

[37] A method for manufacturing a GaN substrate wafer according to any one of

[24] to

[36] above, wherein the method comprises a thinning step of thinning the stacked structure after the third step.

[0099]

[38] The method for manufacturing a GaN substrate wafer according to

[37] above, wherein:

[0100] The difference in thickness of the GaN film before and after the thinning step is 50 μm or more.

[0101]

[39] The method for manufacturing a GaN substrate wafer according to

[37] or

[38] above, wherein:

[0102] The difference in thickness of the GaN film before and after the thinning step is 200 μm or less.

[0103]

[40] A method for manufacturing a GaN substrate wafer according to any one of

[37] to

[39] above, wherein the crystal orientation deviation direction of the GaN substrate wafer is different from the crystal orientation deviation direction of the second c-plane GaN wafer.

[0104]

[41] A method for manufacturing a GaN substrate wafer according to any one of

[24] to

[40] above, wherein, before growing the GaN film in the third step, there is a flattening step for flattening the main surface on the Ga polarity side of the second c-plane GaN wafer sliced ​​from the second GaN film in the second step, and further a roughening step for roughening the main surface by etching.

[0105] Effects of the Invention

[0106] The present invention can provide a GaN substrate wafer and a method for manufacturing the same which can be preferably used for manufacturing a nitride semiconductor device having a horizontal device structure and has improved productivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0107] Figure 1 FIG. 1 is a perspective view showing a GaN substrate wafer according to an embodiment.

[0108] Figure 2 1 is a cross-sectional view showing a GaN substrate wafer according to an embodiment.

[0109] Figure 3 1 is a cross-sectional view showing a GaN substrate wafer according to an embodiment.

[0110] Figure 4 The present invention is a cross-sectional view for explaining the process of manufacturing a nitride semiconductor device using the GaN substrate wafer according to the embodiment.

[0111] Figure 5 The diagram is a cross-sectional view of the steps for explaining the method for manufacturing a GaN substrate wafer according to the embodiment.

[0112] Figure 6 The diagram is a cross-sectional view of the steps for explaining the method for manufacturing a GaN substrate wafer according to the embodiment.

[0113] Figure 7The diagram is a cross-sectional view of the steps for explaining the method for manufacturing a GaN substrate wafer according to the embodiment.

[0114] Figure 8 Schematic diagram showing the basic structure of an HVPE apparatus.

[0115] Explanation of symbols

[0116] 1 Seed wafer

[0117] 2 The first GaN thick film

[0118] 3 The first c-plane GaN wafer

[0119] 4 Second GaN thick film

[0120] 5 Second c-plane GaN wafer

[0121] 6 GaN film

[0122] 6a Specific doping area

[0123] 10 HVPE device

[0124] 11 Reactor

[0125] 12 Gallium Storage

[0126] 13 Base

[0127] 14 First Heater

[0128] 15 Second Heater

[0129] 100 GaN substrate wafer

[0130] 101 N polarity surface

[0131] 102 Ga polar surface

[0132] 103 Regrowth Interface

[0133] 110 First Area

[0134] 120 Second Area

[0135] 120a Main doping region

[0136] 200 Epitaxial Film

[0137] 210 Undoped GaN channel layer

[0138] 220 Undoped AlGaN carrier supply layer DETAILED DESCRIPTION

[0139] The following description of the components is an example (representative example) of the embodiment of the present invention, and the present invention is not limited to these contents unless exceeding the gist thereof.

[0140] In the present specification, when represented as "X to Y" (X and Y are arbitrary numbers), unless otherwise specified, it includes the meaning of "X or more and Y or less", and also includes the meaning of "preferably greater than X" and "preferably less than Y".

[0141] In addition, in this specification, the term “independently” used when describing two or more objects together means that the two or more objects may be the same or different.

[0142] 1.GaN substrate wafer

[0143] One embodiment of the present invention relates to a GaN substrate wafer.

[0144] The GaN substrate wafer of the embodiment is a GaN substrate wafer with a (0001) orientation, which has a first region disposed on the N polarity side and a second region with a minimum thickness disposed on the Ga polarity side sandwiching a regrown interface. The minimum thickness of the second region is 20 μm or more. In addition, in at least a portion of the second region, the total concentration of the compensating impurities is 1×10 17 atoms / cm 3 above.

[0145] Furthermore, the impurity concentration in the first region of the GaN substrate wafer preferably satisfies one or more of the following conditions (a) to (c):

[0146] (a) Si (silicon) concentration is 5×10 16 atoms / cm 3 above;

[0147] (b) O (oxygen) concentration is 3×10 16 atoms / cm 3 the following;

[0148] (c) H (hydrogen) concentration is 1×10 17 atoms / cm 3 the following.

[0149] It should be noted that, in this specification, “impurities” refer to components other than Ga element and N element contained in the GaN substrate.

[0150] A (0001)-oriented GaN wafer refers to a GaN wafer having a major surface (large surface) parallel or substantially parallel to the (0001) crystal plane, ie, the c-plane, and is also called a c-plane GaN wafer.

[0151] Figure 1 and Figure 2 An example of a GaN substrate wafer according to an embodiment is shown in FIG. Figure 1 For a stereogram, Figure 2 It is a cross-sectional view.

[0152] Figure 1 and Figure 2 The GaN substrate wafer 100 shown in FIG. 1 is a self-supporting substrate wafer composed only of GaN crystals, and one of its two main surfaces is an N polar surface 101 and the other is a Ga polar surface 102. The N polar surface 101 and the Ga polar surface 102 are parallel to each other.

[0153] The GaN substrate wafer 100 is oriented (0001), and the inclination of the Ga polar plane 102 relative to the (0001) crystal plane is 10 degrees or less, preferably 5 degrees or less, and more preferably 2.5 degrees or less. The inclination can be 0.2 degrees or more and less than 1 degree, 1 degree or more and 2.5 degrees or less.

[0154] The diameter of the GaN substrate wafer 100 is usually 45 mm or more, and may be 95 mm or more, or 145 mm or more, and is typically 50 to 55 mm (about 2 inches), 100 to 105 mm (about 4 inches), 150 to 155 mm (about 6 inches), etc.

[0155] The preferred range of the thickness of the GaN substrate wafer 100 varies depending on the diameter. When the diameter is about 2 inches, the thickness is preferably 250 μm or more, more preferably 300 μm or more, and preferably 450 μm or less, more preferably 400 μm or less. When the diameter is about 4 inches, the thickness is preferably 350 μm or more, more preferably 400 μm or more, and preferably 750 μm or less, more preferably 650 μm or less. When the diameter is about 6 inches, the thickness is preferably 450 μm or more, more preferably 550 μm or more, and preferably 800 μm or less, more preferably 700 μm or less.

[0156] As described above, the GaN substrate wafer 100 is generally disc-shaped, but in a modified example, the shape of the main surface may also be square, rectangular, hexagonal, octagonal, elliptical, etc., or may be an irregular shape. In the case of such a modified example, the above diameter may be alternatively interpreted as "the shortest length of a straight line passing through the center of gravity on the main surface".

[0157] The N-polar surface 101 of the GaN substrate wafer 100 is the “back surface” and may be mirror-polished or roughened or matte-finished.

[0158] The Ga polar surface 102 of the GaN substrate wafer 100 is the “surface”, and when the GaN substrate wafer 100 is used to manufacture a nitride semiconductor device, a nitride semiconductor layer is usually epitaxially grown on the Ga polar surface 102 .

[0159] The Ga polar surface 102 may be a surface that maintains the state after crystal growth (as-grown), but is usually flattened by processing. The processing performed to flatten the Ga polar surface 102 and make it a flat surface may include one or more selected from polishing and CMP (Chemical Mechanical Polishing). In addition to these processes, etching for the purpose of removing the damaged layer may also be performed. The roughness of the flat surface is not limited. For example, the root mean square (RMS) roughness of the Ga polar surface 102 measured by an atomic force microscope (AFM) is preferably less than 5nm, more preferably less than 2nm, further preferably less than 1nm, and may also be less than 0.5mm within the measurement range of 2μm×2μm.

[0160] The Ga polar surface 102 may be a surface formed by cutting, but is preferably a surface that is not cut but is only flattened by polishing, CMP, etching, or the like.

[0161] The GaN substrate wafer 100 has a regrown interface 103 between its two main surfaces, and has a first region 110 on the N polarity side and a second region 120 on the Ga polarity side sandwiching the regrown interface 103. "Regrowth interface" refers to a boundary surface generated when GaN crystal grows on any substrate, and the existence of the "regrowth interface" can be confirmed by, for example, scanning electron microscope cathode luminescence observation or fluorescence microscope observation of a cross section of the GaN substrate wafer.

[0162] The regrown interface 103 is preferably parallel to the Ga polar surface 102. When the regrown interface 103 is inclined relative to the Ga polar surface 102, the thickness of the second region 120 is usually the smallest at one end of the inclination direction and the largest at the other end. The difference between the thickness of the second region 120 at one end and the thickness at the other end is preferably not more than 200 μm.

[0163] In the manufacturing process of the nitride semiconductor device using the GaN substrate wafer 100, it is assumed that the first region 110 is finally removed. In other words, it is assumed that the nitride semiconductor device chip manufactured using the GaN substrate wafer 100 does not include a portion derived from the first region 110. If it is used in this way, there is no particular restriction on the electrical properties of the GaN crystal that becomes the first region 110.

[0164] Since the first region 110 is generally formed of GaN crystal grown by HVPE, the impurity concentration satisfies at least one condition selected from the following (a) to (c). In this specification, HVPE refers to hydride vapor phase epitaxy.

[0165] (a) Si concentration is 5×10 16 atoms / cm 3 above.

[0166] (b) O concentration is 3×10 16 atoms / cm 3 the following.

[0167] (c) H concentration is 1×10 17 atoms / cm 3 the following.

[0168] In GaN crystals grown by HVPE, the total concentration of compensating impurities is usually lower than the total concentration of donor impurities unless compensating impurities are intentionally doped. It should be noted that "intentional doping" refers to adding the target element as a raw material during the process of growing GaN crystals.

[0169] In addition, the total concentration of the compensating impurities in the first region is preferably less than 1×10 17 atoms / cm 3 .

[0170] The GaN crystal forming the first region 110 is preferably a GaN crystal that is not intentionally doped.

[0171] The second region 120 is grown by HVPE on the first region 110. The reason why the regrown interface 103 exists between the first region 110 and the second region 120 is that the process of growing the first region 110 and the process of growing the second region 120 are not continuous.

[0172] The minimum thickness of the second region 120 is 20 μm or more. The reason for this is that in the manufacturing process of the nitride semiconductor device chip using the GaN substrate wafer 100, after removing the first region 110 from the substrate wafer 100, the remaining second region 120 can function as a substrate supporting the structure of the semiconductor device chip. The minimum thickness refers to the thickness of the smallest portion.

[0173] The minimum thickness of the second region 120 is 50 μm or more, further 75 μm or more, further 100 μm or more, and further may be 150 μm or more.

[0174] The minimum thickness of the second region 120 is preferably 350 μm or less, more preferably 300 μm or less, and may be 250 μm or less, 200 μm or less, or the like.

[0175] When the Ga polar plane 102 and the regrown interface 103 are parallel and the thickness of the second region 120 is uniform, the thickness of the second region is considered to be the minimum thickness at all locations.

[0176] Preferably, the second region 120 at least includes the main surface on the Ga polar side, specifically, the region within a specific length L from the Ga polar surface 102 of the GaN substrate wafer 100 as the main doping region 120a. The second region 120 is at least such that the total concentration of the compensating impurities in the main doping region 120a reaches 1×10 17 atoms / cm 3 The above method was used for doping.

[0177] The total concentration of compensating impurities is the concentration obtained by adding the concentrations of all types of compensating impurities. In GaN crystals grown by HVPE, the total concentration of compensating impurities usually does not reach 1×10 17 atoms / cm 3 Therefore, the total concentration of compensating impurities can be increased to 1×10 17 atoms / cm 3 above.

[0178] The so-called compensating impurities in this specification refer to impurities that have the function of compensating n-type carriers in GaN crystals. Well-known compensating impurities are C (carbon) and transition metal elements. Among transition metal elements, Fe (iron) and Mn (manganese) are the representatives, and other known ones include Co (cobalt), Cr (chromium), V (vanadium), Ni (nickel), Cu (copper), etc.

[0179] The total concentration of the compensating impurities in the main doping region 120a may be 1×10 17 atoms / cm 3 More than and less than 2×10 17 atoms / cm 3 , 2×10 17 atoms / cm 3 More than and less than 5×10 17 atoms / cm 3 , 5×10 17 atoms / cm 3 More than and less than 1×10 18 atoms / cm 3 , 1×10 18 atoms / cm 3More than and less than 2×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 More than and less than 5×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 More than and less than 1×10 19 atoms / cm 3 , 1×10 19 atoms / cm 3 More than and less than 2×10 19 atoms / cm 3 , 2×10 19 atoms / cm 3 More than and less than 5×10 19 atoms / cm 3 wait.

[0180] In the main doping region 120a, the total concentration of the compensating impurities is preferably more than 2 times the total concentration of the donor impurities, more preferably more than 5 times, further preferably more than 10 times, and may be more than 50 times. In addition, the compensating impurities contained in the main doping region 120 at the highest concentration are preferably Fe, Mn or C.

[0181] In a preferred embodiment, the concentration of the compensating impurity added to the main doping region 120a is set to make the GaN crystal forming the main doping region 120a semi-insulating, that is, to make its room temperature resistivity 1×10 5 Ω·cm or more.

[0182] Elements that can act as donor impurities in GaN crystals include carbon group elements such as Si, Ge (germanium), Sn (tin), and oxygen group elements such as O, S (sulfur), Se (selenium), and Te (tellurium). Among them, Si and O can be present in GaN crystals grown by HVPE at an order of magnitude of 10 even if they are not intentionally added. 16 atoms / cm 3 In contrast, carbon group elements other than Si and oxygen group elements other than O do not exist in GaN crystals grown by HVPE at concentrations of 10 or more unless they are intentionally added. 15 atoms / cm 3 Contains above concentration.

[0183] The specific length L is at least 1 μm, preferably 20 μm or more, more preferably 25 μm or more, and further preferably 50 μm or more, and can be arbitrarily set within a range that does not exceed the minimum thickness of the second region 120 .

[0184] In the main doping region 120a, it is desirable that the variation of the specific resistance along the c-axis direction, which is the thickness direction of the GaN substrate wafer 100, is small. Therefore, the variation of the total concentration of the compensating impurities along the c-axis direction in the main doping region 120a is preferably within ±25% from the central value, more preferably within ±20%, further preferably within ±15%, and further preferably within ±10%.

[0185] In a preferred embodiment, the specific length L is set to a value greater than 50 μm so that in the manufacturing process of a nitride semiconductor device chip using a GaN substrate chip 100, when the second region 120 is partially removed from the GaN substrate chip 100 in addition to the first region 110 to expose the main doping region 120a, the GaN substrate formed only by the remaining main doping region 120a can still support the structure of the semiconductor device chip.

[0186] In this preferred embodiment, the specific length L may be 75 μm or more, 100 μm or more, further 150 μm or more, further 200 μm or more.

[0187] In this preferred embodiment, the specific length L is preferably 50% or more of the minimum thickness of the second region 120 , more preferably 75% or more, and even more preferably 90% or more.

[0188] In addition, the length from the lower end of the specific length L (one end on the N polar surface 101 side) to the regrown interface is preferably greater than 1 μm, more preferably greater than 5 μm, and further preferably greater than 10 μm. In addition, the length from the lower end to the interface is preferably less than 50 μm, more preferably less than 30 μm.

[0189] In order to avoid over-doping and thus significantly reduce the crystal quality, the total concentration of the compensating impurities in the second region 120 including the main doping region 120a may be 5×10 19 atoms / cm 3 Below, further can be 2×10 19 atoms / cm 3 Below, further can be 1×10 19 atoms / cm 3 the following.

[0190] In the lowermost portion of the second region 120 , ie, the portion adjacent to the first region 110 , the concentration of the same type of compensating impurities as the compensating impurities intentionally added in the main doping region 120 a may increase continuously or in stages as it moves away from the first region 110 .

[0191] Since the second region 120 is generally grown by HVPE, its impurity concentration satisfies one or more conditions selected from the following (a′) to (c′).

[0192] (a')Si concentration is 5×10 16 atoms / cm 3 above.

[0193] (b')O concentration is 3×10 16 atoms / cm 3 the following.

[0194] (c')H concentration is 1×10 17 atoms / cm 3 the following.

[0195] In one example, Figure 3 As shown, the regrown interface 103 may also be rough. For example, when the surface of the first region 110 is roughened by etching before the second region 120 is grown, the regrown interface 103 may be rough. When the direction from the first region 110 to the second region 120 perpendicular to the regrown interface 103 is set as the height direction, and the height difference between the highest point and the lowest point in the regrown interface is set as the roughness r of the regrown interface, the roughness r may be, for example, 0.3 μm or more and 12 μm or less.

[0196] In addition, although Figure 1 to Figure 3 Although not shown, the edge of the GaN substrate wafer 100 may also be chamfered. In addition, the GaN substrate wafer 100 may be provided with various marks as required, such as an orientation plane or notch for indicating the orientation of the crystal, an index flat for making the front and back surfaces easily distinguishable, and the like.

[0197] The GaN substrate wafer 100 can be preferably used for manufacturing nitride semiconductor devices with horizontal device structures such as GaN-HEMT. Nitride semiconductor devices refer to semiconductor devices in which the main part of the device structure is formed by nitride semiconductors. Nitride semiconductors are also called nitride III-V compound semiconductors, III-nitride compound semiconductors, GaN semiconductors, etc. In addition to GaN, they also include compounds in which part or all of the gallium of GaN is replaced by other elements of the boron group (B, Al, In) in the periodic table.

[0198] The horizontal device structure can also be adopted in electronic devices other than high electron mobility transistors (HEMTs) such as bipolar transistors, and light-emitting devices such as light-emitting diodes (LEDs) and laser diodes (LDs).

[0199] When GaN-HEMT is manufactured using the GaN substrate wafer 100, Figure 4 After a GaN substrate wafer 100 is prepared as shown in (a), on its Ga polar surface 102, as shown in Figure 4 As shown in (b), an epitaxial film 200 including at least an undoped GaN channel layer 210 and an undoped AlGaN carrier supply layer 220 is grown by, for example, metal organic vapor phase epitaxy (MOVPE), thereby forming an epitaxial wafer.

[0200] After performing semiconductor processes including etching, ion implantation, electrode formation, and protective film formation, the epitaxial wafer is divided into GaN-HEMT chips. However, in order to thin the epitaxial wafer before division, the epitaxial wafer is usually cut into pieces. Figure 4 As shown in (c), at least a portion of the first region 110 of the GaN substrate wafer 100 is removed by grinding, etching, or the like.

[0201] The thinning process may be performed so that a ring-shaped thick portion remains at the periphery of the epitaxial wafer. In other words, the first region 110 of the GaN substrate wafer 100 may be removed only at the portion other than the periphery of the epitaxial wafer.

[0202] Figure 4 In (c), the second region 120 is also partially removed from the GaN substrate wafer 100 so that the main doping region 120a is exposed on the N-polar surface side of the thinned epitaxial wafer. It should be noted that semiconductor devices using the GaN substrate wafer 100 are not limited to nitride semiconductor devices.

[0203] 2. Manufacturing method of GaN substrate wafer

[0204] Next, a method for manufacturing a GaN substrate wafer as another embodiment of the present invention is described. The manufacturing method described below is a preferred method for manufacturing the above-mentioned GaN substrate wafer. In addition, a preferred method of the GaN substrate wafer obtained by the manufacturing method of the GaN substrate wafer described below can include the above-mentioned GaN substrate wafer.

[0205] The GaN substrate wafer 100 of the embodiment can be preferably manufactured by the method described below. The method is suitable for manufacturing a GaN substrate wafer having an N polarity side region and a Ga polarity side region sandwiching a regrown interface, and is preferably a method for increasing the resistivity at least in a portion of the GaN polarity side, and the method has the following steps.

[0206] (ii') a second step of growing a second GaN thick film having a (0001) orientation on the substrate by HVPE and then slicing the second GaN thick film to obtain a second c-plane GaN wafer; and

[0207] (iii') a third step of growing a GaN film having a (0001) orientation and a thickness greater than 50 μm on the second c-plane GaN wafer by HVPE, wherein the GaN film has a region having a higher total concentration of donor impurities than that of the second c-plane GaN wafer.

[0208] Furthermore, it is preferable to adopt a process in which the first step is added as a process of manufacturing a substrate in the second step. Therefore, the first step described below is optional.

[0209] (i) A first step of growing a first GaN thick film composed of unintentionally doped GaN and having a (0001) orientation on a seed wafer by HPVE, and processing the first GaN thick film to obtain at least one first c-plane GaN thick film.

[0210] (ii) A second step of growing a second GaN thick film composed of unintentionally doped GaN and having a (0001) orientation on the first c-plane GaN wafer obtained in the first step by HVPE, and slicing a second c-plane GaN wafer from the second GaN thick film.

[0211] (iii) a third step of growing a GaN film having a thickness of more than 50 μm and a (0001) orientation on the second c-plane GaN wafer obtained in the second step by HVPE to obtain a stacked structure. The GaN film has a total concentration of 1×10 17 atoms / cm 3 The above part.

[0212] In this specification, “on a wafer” and “on the surface of a wafer” have the same meaning.

[0213] It should be noted that the structures and characteristics of the first c-plane GaN wafer obtained in the first step and the second GaN thick film obtained in the second step can be respectively applied to the structures and characteristics of the first region and the second region.

[0214] In the first step, prepare Figure 5 (a) shows a seed crystal wafer 1, on which a Figure 5As shown in (b), a first GaN thick film 2 formed of GaN that is not intentionally doped and has a (0001) orientation is grown by HVPE. Figure 5 As shown in (c), at least one first c-plane GaN wafer 3 is obtained by processing the first GaN thick film 2 .

[0215] An example of the seed wafer 1 is a c-plane sapphire wafer, which may preferably be a wafer having a peeling layer on the main surface. For example, after a GaN layer having a thickness of several hundred nm is grown on a c-plane sapphire wafer via a low-temperature buffer layer by MOVPE, and a Ti (titanium) layer having a thickness of several tens of nm is further formed on the GaN layer by vacuum evaporation, the wafer is annealed in a mixed gas of 80% H2 and 20% NH3 (ammonia) at, for example, 1060° C. for 30 minutes, thereby forming a c-plane sapphire wafer with a peeling layer.

[0216] The seed crystal wafer 1 may be a c-plane GaN wafer manufactured in another process.

[0217] The first GaN thick film 2 is processed to grow to a thickness sufficient to produce at least one self-supporting c-plane GaN wafer. In a preferred embodiment, the first GaN thick film 2 is grown to a thickness of several mm or more, and at least two first c-plane GaN wafers 3 are sliced ​​from the thick film.

[0218] Figure 6 (a) is a cross-sectional view showing a first c-plane GaN wafer 3 produced in the first step. However, it should be noted that the first c-plane GaN wafer 3 is not limited to those obtained in the first step.

[0219] In the second step, Figure 6 As shown in (b), a second GaN thick film formed of unintentionally doped GaN and having a (0001) orientation is grown on the Ga polar surface of the first c-plane GaN wafer 3 by HVPE, and then, as shown in Figure 6 As shown in (c), a second c-plane GaN wafer 5 is sliced ​​out from the second GaN thick film 4. By processing the second GaN thick film 4, the second GaN thick film 4 grows to a thickness that can produce at least one second c-plane GaN wafer 5. In a preferred embodiment, the second GaN thick film 4 is grown to a thickness of more than several mm, and at least two second c-plane GaN wafers 5 are sliced ​​out from the thick film.

[0220] Since the second GaN thick film 4 has weak n-type conductivity, a wire electrode electro-discharge machining device can be used for this slicing. The wire electrode electro-discharge machining device has a higher cutting speed than a free abrasive wire saw and is easier to operate. In addition, the cut loss when the GaN crystal is cut using the wire electrode electro-discharge machining device is less than that using a fixed abrasive wire saw.

[0221] like Figure 7 As shown in the cross-sectional view of (a), the second c-plane GaN wafer 5 has an N-polar plane and a Ga-polar plane parallel to each other as main surfaces.

[0222] In the case of manufacturing the above-mentioned GaN substrate wafer 100 of the embodiment, when slicing the second c-plane GaN wafer 5 from the second GaN thick film 4 in the second process, it is preferred to make the inclination angle (off-cut angle) and inclination direction (off-cut direction) of the Ga polar plane in the second c-plane GaN wafer 5 relative to the (0001) crystal plane the same as the off-cut angle and off-cut direction that the GaN substrate wafer 100 should have, but it is not necessary.

[0223] The crystal orientation deviation orientation that the GaN substrate wafer 100 should have varies depending on the requirements of the manufacturer of the semiconductor device using the GaN substrate wafer 100, but preparing the second c-plane GaN wafer 5 with various crystal orientation deviation orientations may lead to a decrease in the production efficiency of the GaN substrate wafer 100. It is also necessary to note that the optimal conditions for growing the GaN film 6 on the second c-plane GaN wafer 5 by HVPE in the subsequent third step may change depending on the crystal orientation deviation orientation of the second c-plane GaN wafer 5.

[0224] The initial thickness t of the second c-plane GaN wafer 5 5i The thickness of the GaN substrate wafer used to manufacture nitride semiconductor devices can also be thinner than that of the GaN substrate wafer generally used to manufacture nitride semiconductor devices. This is because, unlike the GaN substrate wafer that needs to undergo a semiconductor process consisting of multiple steps, the second c-plane GaN wafer 5 only needs to be free of damage until the subsequent third step.

[0225] For example, when the diameter of the second c-plane GaN wafer 5 is about 2 inches, its initial thickness t 5i It is preferably 300 μm or less, may be 250 μm or less, and may be 200 μm or less.

[0226] By reducing the initial thickness t of the second c-plane GaN wafer 5 5i , the number of second c-plane GaN wafers 5 sliced ​​from the second GaN thick film 4 can be increased.

[0227] In the third step, Figure 7 As shown in (b), a GaN wafer 5 having a Ga polar surface and a thickness of t is grown by HVPE on the Ga polar surface of the second c-plane GaN wafer 5. 6g The GaN film 6 with a thickness exceeding 50 μm and a (0001) orientation is grown to obtain a stacked structure. At this time, a regrown interface is formed between the second c-plane GaN wafer 5 and the GaN film 6 .

[0228] Typically, before growing the GaN film 6, the Ga polar surface of the second c-plane GaN wafer 5 is processed to be flat (flattening process) using appropriate techniques such as grinding, polishing, and CMP. However, in one example, the flattened Ga polar surface can also be processed into a rough surface by etching (roughening process) before the GaN film 6 is grown.

[0229] When HCl (hydrogen chloride) is used as the etching gas, the Ga polar surface of GaN can be roughened without using an etching mask. If an HCl supply line for etching is provided in the HVPE device for growing the GaN film 6, the Ga polar surface of the second c-plane GaN wafer 5 can also be roughened in the reactor of the HVPE device just before the GaN film 6 is grown.

[0230] Preferred etching conditions when HCl is used as the etching gas are as follows.

[0231] The HCl partial pressure is, for example, 0.002 to 0.05 atm.

[0232] The H2 partial pressure is, for example, 0.2 to 0.8 atm.

[0233] The partial pressure of NH3 is, for example, 0.01 to 0.05 atm. By introducing NH3, the Ga polar surface of GaN is roughened more uniformly.

[0234] The etching temperature is, for example, 900 to 1050°C.

[0235] The etching time is, for example, 1 to 60 minutes.

[0236] When the roughness of the Ga polar surface of the second c-plane GaN wafer 5 after etching is defined as the height difference between the highest point and the lowest point, the roughness may be, for example, 0.3 to 12 μm.

[0237] In etching using HCl, when conditions other than etching time are fixed, the roughness of the Ga polar surface of the second c-plane GaN wafer tends to increase with etching time.

[0238] When HCl is used as the etching gas, the etching time can be set so that the roughness of the Ga polar surface does not exceed 0.5 μm.

[0239] For example, when the Ga polar surface of the second c-plane GaN wafer 5 is etched under the conditions of HCl partial pressure of 0.01-0.02atm, H2 partial pressure of 0.05-0.08atm, NH3 partial pressure of 0.01-0.03atm, and temperature of 970-1000°C, the roughness of the Ga polar surface can be made less than 0.5μm by setting the etching time to less than 5 minutes.

[0240] In one example, after forming a patterned etching mask by a photolithography process, the Ga polar surface of the second c-plane GaN wafer 5 can be roughened by dry etching. Dot patterns and mesh patterns are typical examples of preferred patterns of etching masks. Dry etching can also be RIE (reactive ion etching) using Cl2 (chlorine) or chlorine-containing compounds as etching gas.

[0241] For the GaN film 6, the total concentration of the compensating impurities in at least a portion thereof is 1×10 17 atoms / cm 3 The above-mentioned doping method is used. The particularly preferred compensating impurities are Fe, Mn and C.

[0242] In a preferred embodiment, a specific doping region 6a may be provided in the GaN film 6. The specific doping region 6a is preferably a region with a length of 20 μm or more in the c-axis direction, and a total concentration of compensating impurities in the region of 1×10 17 atoms / cm 3 In other words, the length of this region means that the total concentration of the compensating impurities is 1×10 17 atoms / cm 3 The thickness of the above region (height in the thickness direction).

[0243] The region length of the specific doping region 6 a in the c-axis direction may be 25 μm or more, 50 μm or more, 75 μm or more, 100 μm or more, 150 μm or more, 200 μm or more, or the like.

[0244] The upper end of the specific doping region 6 a (the end on the

[0001] side) is preferably within 10 μm, more preferably within 5 μm, from the upper surface of the GaN film 6 , and may be the upper surface of the GaN film 6 .

[0245] The length from the lower end of the specific doping region 6a (one end on the [000-1] side) to the interface between the second c-plane GaN wafer 5 and the GaN film 6 is preferably greater than 1 μm, more preferably greater than 5 μm or greater than 10 μm. In addition, the length from the lower end to the interface is preferably less than 50 μm, more preferably less than 30 μm.

[0246] The region length of the specific doping region 6 a in the c-axis direction is more preferably 50% or more of the thickness of the GaN film 6 , more preferably 75% or more, and even more preferably 90% or more.

[0247] In the specific doping region 6a, the total concentration of the compensating impurities is at least 1×10 17 atoms / cm 3 , or 2×10 17 atoms / cm 3 Above, 5×10 17 atoms / cm 3 Above, 1×10 18 atoms / cm 3 Above, 2×10 18 atoms / cm 3 Above, 5×10 18 atoms / cm 3 above.

[0248] In the specific doping region 6 a , the total concentration of the compensating impurities is preferably 2 times or more, more preferably 5 times or more, further preferably 10 times or more, and may be 50 times or more of the total concentration of the donor impurities.

[0249] In the specific doping region 6a, the GaN crystal may be semi-insulating, that is, its room temperature resistivity may be 1×10 5 Ω·cm or more.

[0250] In the specific doping region 6a, it is desired that the specific resistance change along the c-axis direction is small. Therefore, the change of the total concentration of the compensating impurities along the c-axis direction in the specific doping region 6a is preferably within ±25% from the central value, more preferably within ±20%, further preferably within ±15%, and further preferably within ±10%.

[0251] In order to avoid a significant decrease in crystal quality due to over-doping, the total concentration of the compensating impurities in the GaN film 6 including the specific doping region 6a can be 5×10 19 atoms / cm 3 Below, further can be 2×10 19 atoms / cm 3 Below, further can be 1×10 19 atoms / cm 3 the following.

[0252] In the lowermost part of the GaN film 6 , i.e., the part adjacent to the second c-plane GaN wafer 5 , compensating impurities of the same type as those added to the specific doping region 6 a can be added, and their concentration can be continuously or stepwise increased as the distance from the second c-plane GaN wafer 5 increases.

[0253] The growth thickness t of the GaN film 6 6g The thickness can be set according to the designed thickness of the Ga polarity side region of the GaN substrate wafer to be manufactured. Specifically, it can be 20 μm or more, 50 μm or more, or more than 50 μm, or more than 75 μm, or more than 100 μm, or more than 150 μm, or less than 500 μm, or less than 350 μm, or less than 300 μm, or less than 250 μm, or less than 200 μm, or more.

[0254] When manufacturing the GaN substrate wafer 100, the growth thickness of the GaN film 6 is t 6g It may be the same as the designed thickness of the second region 120 in the GaN substrate wafer, but it is preferably greater than the designed thickness, so that the surface of the GaN film 6 can be flattened in the subsequent thinning process. Therefore, in order to ensure a processing margin for flattening, the growth thickness t of the GaN film 6 is 6g It is preferably 50 μm or more, more preferably 100 μm or more greater than the designed maximum thickness of the second region 120. A processing margin exceeding 200 μm is usually not required. In other words, the difference in thickness of the GaN film 6 before and after the thinning step is preferably 200 μm or less.

[0255] For example, when the growth thickness of the GaN film 6 is t 6g When the thickness is 50 μm or more greater than the designed maximum thickness of the second region 120 , the thickness of the GaN film 6 decreases by 50 μm or more in the subsequent thinning step. In other words, the difference in thickness of the GaN film 6 before and after the thinning step is 50 μm or more.

[0256] When manufacturing the GaN substrate wafer 100, even if the wafer has a large diameter, for example, even if the wafer has a diameter of 6 inches, the growth thickness t of the GaN film 6 can be reduced to 0. 6g Suppressed to 500 μm or less.

[0257] Due to the growth thickness t 6g The GaN film 6 can be formed in a short time because the size of the wafer can be very small. Therefore, there is no need to worry about NH4Cl (ammonium chloride) as a by-product clogging the exhaust system of the HVPE device, so that the GaN film 6 can be grown on multiple second c-plane GaN wafers 5 at one time. As a result, the total processing capacity of the third step can be extremely high.

[0258] In addition, the short time required to form the GaN film 6 can also help reduce the costs associated with cleaning and maintenance of the HVPE reactor. Generally, for an HVPE reactor, the shorter the time required for a single growth process, the slower the degradation progresses and the longer the service life.

[0259] After the third step, as required, Figure 7 As shown in (c), a thinning step is provided for thinning the layered structure obtained in the third step.

[0260] exist Figure 7 In (c), the thickness of the second c-plane GaN wafer 5 is increased from the initial thickness t 5i Reduced to the final thickness t 5f , and the thickness of the GaN film 6 increases from the initial thickness t 6i Reduced to the final thickness t 6f However, in the thinning step, only one of the second c-plane GaN wafer 5 and the GaN film 6 may be processed.

[0261] When manufacturing the GaN substrate wafer 100 according to the embodiment, in the thinning process, the thickness of the second c-plane GaN wafer 5 and the GaN film 6 can be reduced to match the designed thickness of the first region 110 and the second region 120 in the GaN substrate wafer, respectively.

[0262] When the crystal orientation deviation of the GaN substrate wafer 100 to be manufactured is the same as that of the second c-plane GaN wafer 5, the back side (N-polarity surface of the stacked structure) of the second c-plane GaN wafer 5 can be used as a reference for the surface orientation during thinning.

[0263] When the crystal orientation deviation orientation of the GaN substrate chip 100 to be manufactured is different from the crystal orientation deviation of the second c-plane GaN chip 5, that is, when at least one of the crystal orientation deviation angle and the crystal orientation deviation direction is different, the crystal orientation of the stacked structure can be confirmed by an X-ray diffraction device before thinning.

[0264] The processing technique used in the thinning step can be appropriately selected from grinding, lapping, CMP, dry etching, wet etching, and the like.

[0265] By using the manufacturing method described above, the GaN substrate wafer 100 of the embodiment can be produced with a high yield.

[0266] The reason for this is that there is no step of growing a GaN thick film that has been intentionally doped to a thickness of 1 mm or more by HVPE, and no step of slicing the GaN thick film grown in this way.

[0267] In the first and second steps, although HVPE can be used to grow GaN thick films to a thickness of millimeters, the first GaN thick film 2 and the second GaN thick film 4 grown in these steps are not intentionally doped, so it is not easy to produce morphological abnormalities or cracks during growth, and the frequency of breakage in the slices is also low.

[0268] On the other hand, the GaN film 6 grown in the third step may be provided with a 1×10 17 atoms / cm 3 The above concentration contains the portion of compensating impurities, but since the growth thickness of the GaN film 6 is less than 500 μm, it is not easy to produce morphological abnormalities or cracks during growth. In addition, the GaN film 6 does not need to be sliced. In other words, it is not necessary to perform slicing in the above-mentioned thinning process. In particular, the GaN film 6 formed in the third process is preferably subjected to the thinning process without slicing.

[0269] Furthermore, in the GaN substrate wafer obtained by the manufacturing method described above, the deviation of the crystal orientation in the main surface becomes extremely small.

[0270] The reason is that on the first c-plane GaN wafer 3 that is not intentionally doped, the warping of the second GaN thick film 4 that is homoepitaxially grown without intentional doping will become extremely small. Therefore, in the second c-plane GaN wafer 5 sliced ​​from the second GaN thick film 4, the deviation of the crystal orientation will become extremely small.

[0271] Below, refer to Figure 8 An example of an HVPE apparatus that can be used in the first step to the third step included in the above-mentioned production method will be described.

[0272] Figure 8 The HVPE apparatus 10 shown includes a hot wall reactor 11, a gallium reservoir 12 and a susceptor 13 disposed in the reactor, and a first heater 14 and a second heater 15 disposed outside the reactor. The first heater 14 and the second heater 15 each surround the reactor 11 in a ring shape.

[0273] The reactor 11 is a quartz tube chamber. The reactor 11 includes a first zone Z1 mainly heated by a first heater 14 and a second zone Z2 mainly heated by a second heater 15. E Connected to the reactor end on the second zone Z2 side.

[0274] The gallium storage 12 disposed in the first zone Z1 is a quartz container having a gas inlet and a gas outlet.

[0275] The susceptor 13 disposed in the second zone Z2 is formed of graphite, for example. The mechanism for rotating the susceptor 13 can be arbitrarily provided.

[0276] In order to grow GaN in the HVPE device 10, after placing a seed crystal on the susceptor 13, the reactor 11 is heated by the first heater 14 and the second heater 15, and NH3 (ammonia) diluted with a carrier gas is supplied to the second zone Z2 through the ammonia introduction pipe P1, and HCl (hydrogen chloride) diluted with a carrier gas is supplied to the gallium reservoir 12 through the hydrogen chloride introduction pipe P2. The HCl reacts with the metal gallium in the gallium reservoir 12, and the generated GaCl (gallium chloride) is transported to the second zone Z2 through the gallium chloride introduction pipe P3.

[0277] In the second zone Z2 , NH 3 reacts with GaCl, and the generated GaN crystallizes on the seed crystal placed on the base 13 .

[0278] When the grown GaN is intentionally doped, a doping gas diluted with a carrier gas is introduced into the second zone Z2 in the reactor 11 through the dopant introduction pipe P4.

[0279] The ammonia introduction pipe P1 , the hydrogen chloride introduction pipe P2 , the gallium chloride introduction pipe P3 , and the dopant introduction pipe P4 are formed of quartz at portions disposed in the reactor 11 .

[0280] As the carrier gas for diluting NH 3 , HCl and the doping gas, H 2 (hydrogen), N 2 (nitrogen), or a mixed gas of H 2 and N 2 can be preferably used.

[0281] Preferred conditions for growing GaN using the HVPE apparatus 10 are as follows.

[0282] The temperature of the gallium reservoir is, for example, 500 to 1000° C., preferably 700° C. or higher, and preferably 900° C. or lower.

[0283] The susceptor temperature is, for example, 900 to 1100° C., preferably 930° C. or higher, more preferably 950° C. or higher, and preferably 1050° C. or lower, more preferably 1020° C. or lower.

[0284] The ratio V / III of the NH 3 partial pressure to the GaCl partial pressure in the reactor is, for example, 1 to 20, preferably 2 or more, more preferably 3 or more, and preferably 10 or less.

[0285] If the V / III ratio is too large or too small, the morphology of the GaN growth surface may be degraded, and the degraded morphology of the growth surface may cause the crystal quality to deteriorate.

[0286] For certain impurities, the efficiency of their introduction into GaN crystals strongly depends on the crystal orientation of the growth surface. The uniformity of the concentration of the impurities inside the GaN crystal grown under the condition of poor growth surface morphology is reduced. This is caused by the presence of small facets of various orientations on the growth surface with poor morphology.

[0287] A typical example of an impurity whose introduction efficiency into GaN crystal varies significantly depending on the crystal orientation of the growth surface is O (oxygen). Since O is a donor impurity, a decrease in its concentration uniformity leads to a decrease in the uniformity of the resistivity.

[0288] In addition, the use of too low a V / III ratio will increase the nitrogen vacancy concentration of the grown GaN crystal. The effect of nitrogen vacancies on GaN crystals, GaN substrates using the GaN crystals, or nitride semiconductor devices formed on the GaN substrates is still unclear, but since nitrogen vacancies are point defects, it can be considered that the concentration should be as low as possible.

[0289] The growth rate of GaN is preferably 40 to 200 μm / h, and the product of the partial pressure of NH3 and the partial pressure of GaCl in the reactor can be used as a parameter to control the growth rate. Too high a growth rate will deteriorate the surface morphology of the grown GaN.

[0290] When doping the GaN film 6 in the third step, in order to prevent the morphology of the growth surface from being deteriorated, it is preferred that the supply rate of the doping gas be gradually increased to a given value over several minutes or tens of minutes from the start of supply.

[0291] For the same reason, it is preferable to start supplying the doping gas when the GaN film 6 has grown by at least several μm.

[0292] The method for making the GaN film 6 contain the compensating impurity is not limited, but a method of introducing a doping gas into an HVPE apparatus is generally used.

[0293] As the doping gas used for C doping, a hydrocarbon gas such as CH 4 (methane) can be used, for example.

[0294] The doping gas used for Fe doping can be, for example, vaporized ferric chloride. Ferric chloride vapor can be produced by contacting heated metallic iron with HCl under carrier gas circulation, or by reacting vaporized ferrocene (bis(cyclopentadienyl) iron) with HCl in a dopant introduction tube under carrier gas circulation. Here, ferrocene can also be replaced by other organic compounds containing iron.

[0295] As for the doping gas for Mn doping, for example, metal Mn may be placed in an introduction pipe, and a carrier gas or the like may be flowed therethrough while heating the pipe.

[0296] When other transition metal elements are added to GaN, vapor of the transition metal element or vapor of chloride of the transition metal element may be used as the doping gas.

[0297] Even when GaN grown using the HVPE apparatus 10 is not intentionally doped, it is possible that it contains O and Si at a concentration that can be detected by SIMS (Secondary Ion Mass Spectrometry). The Si source is quartz (SiO2) used for the reactor or the piping in the reactor, and the O source is either or both of the above quartz and the water remaining in or invading the reactor.

[0298] Figure 8 The components not shown in the figure are included. For the components arranged in the reactor 11, in addition to quartz and carbon, SiC (silicon carbide), SiN x Therefore, the concentration of impurity elements other than Si, O and H in GaN grown using the HVPE device 10 can be independently 5×10 15 atoms / cm 3 the following.

[0299] Example

[0300] The present invention will be described in more detail below with reference to the following examples, but the present invention is not limited to these examples, and various applications are possible without departing from the technical concept of the present invention.

[0301] [Example]

[0302] <Fabrication of the First c-plane GaN Wafer (First Step)>

[0303] First, a GaN seed crystal was placed on a susceptor of an HVPE device. As the GaN seed crystal, a GaN template substrate on sapphire produced by MOCVD (metal organic chemical vapor deposition) was used, with the c-plane side being the growth surface.

[0304] <Fabrication of Second c-plane GaN Wafer (Second Step)>

[0305] Next, N 2 , H 2 , and NH 3 were supplied into the reactor so that their partial pressures became 0.67 atm, 0.31 atm, and 0.02 atm, respectively, and the reactor was heated by a heater provided outside the reactor.

[0306] After the pedestal temperature reaches 1000 °C, keep the pedestal temperature constant to grow GaN. Set the temperature of the gallium reservoir to 900 °C. As the carrier gas supplied into the reactor during growth, 69 mol% is H2 and the rest is N2.

[0307] Supply GaCl and NH3 into the reactor in such a way that their respective partial pressures reach 7.9×10 -3 atm and 0.024 atm to grow a second GaN thick film without donor impurities to a thickness of about 2.5 mm. The growth rate of the second GaN thick film calculated from the thickness and growth time is about 40 μm / h.

[0308] Next, after slicing the GaN thick film parallel to the c-plane to obtain a wafer, planarize the Ga-polar surface of the wafer by grinding and then perform CMP finishing. Remove the slicing damage on the N-polar surface side of the wafer by etching. Further, fabricate a second c-plane GaN wafer with a thickness of 400 μm without donor impurities by dicing the wafer. The dislocation density of the obtained wafer is about 2×10 6 ~4×10 6 cm -2 .

[0309] It should be noted that if the thickness of the second GaN thick film is increased by extending the growth time, two or more second c-plane GaN wafers can be obtained.

[0310] <Fabrication of GaN Substrate Wafer (Third Process)>

[0311] Use the above-mentioned second c-plane GaN wafer as a seed crystal and set it on the pedestal of the HVPE device with the c-plane side as the growth surface.

[0312] Next, introduce N2 and NH3 into the reactor in such a way that their respective partial pressures reach 0.84 atm and 0.16 atm, and at the same time heat the inside of the reactor by a heater provided outside the reactor.

[0313] After the temperature of the gallium reservoir reaches 900 °C and the pedestal temperature reaches 1030 °C, keep the pedestal temperature constant and start the growth of GaN crystals by supplying GaCl and NH3 in such a way that their respective partial pressures reach 0.013 atm and 0.16 atm. Let the carrier gas supplied during growth be only N2.

[0314] Fe doping starts in the following way: 1 minute after the start of growth, start introducing into the dopant introduction tube provided with metallic Fe at 9.4×10 -4Atm, HCl was flowed in. The GaN film doped with Fe as a donor impurity was grown to a thickness of about 0.4 mm. The growth rate of the Fe-doped GaN crystal layer was 1.6 μm / min.

[0315] The entire surface of the GaN film was observed using a differential interference microscope, and it was confirmed that no surface defects such as grooves and cracks were present.

[0316] Assuming that the GaN film is grown to about 0.8 mm under the same growth conditions as above, grooves may sometimes be generated on the crystal surface due to the influence of abnormal drops caused by the degradation of the components of the device. Since the crystal planes that constitute the grooves will take in donor impurities such as oxygen and silicon that show conductivity at high concentrations, it may cause the problem of generating areas with different resistivity on the crystal surface. In addition, if compensating impurities are doped at high concentrations, the GaN film tends to generate stress, and it will become more significant as the growth thickness becomes thicker. The stress accumulated in the GaN film may cause defects such as dislocations and cracks. In this embodiment, it can be considered that the growth thickness of the GaN film (Fe-doped GaN crystal layer) is limited to about 0.4 mm, which is successful. When the growth thickness is thickened, the above-mentioned defects such as dislocations and cracks can be suppressed by reducing the doping concentration of compensating impurities, improving the device, and improving manufacturing conditions.

[0317] The surface of the GaN film grown to a thickness of about 0.4 mm was not sliced, but was finely processed by grinding and polishing the surface (one side of the GaN film) and the back side (one side of the second c-plane GaN wafer), respectively, to produce an Fe-doped GaN substrate wafer with an overall thickness of 400 μm and a diameter of about 50 mm.

[0318] The obtained GaN substrate wafer is a double-layer substrate having a regrown interface, a first region with a thickness of 100 μm on the N polarity side (equivalent to the second c-plane GaN wafer), and a second region with a thickness of 300 μm on the Ga polarity side (equivalent to the GaN film).

[0319] The impurity concentration of the Fe-doped GaN substrate wafer was measured by SIMS, and the Fe content was 6.4×10 18 atoms / cm 3 、Si is 1.9×10 16 atoms / cm 3 , O is 2.0×10 16 atoms / cm 3 , C is 7.1×10 15 atoms / cm 3 .

[0320] Five locations were appropriately selected on the surface of the Fe-doped GaN substrate wafer, and the dislocation density of each location was calculated based on the number of dark spots observed in a 100 μm × 100 μm square area under cathode luminescence. The result was approximately 2 × 10 6 ~3×10 6 cm -2 , which is equivalent to the dislocation density of the single crystal GaN (0001) substrate used as the seed crystal.

[0321] Evaluation of resistivity based on double ring method

[0322] The resistivity of the Fe-doped GaN substrate wafer was measured by the double ring method. The room temperature resistivity was 7×10 11 Ωcm.

[0323] The present invention has been described above in conjunction with specific embodiments, but each embodiment is shown as an example and is not intended to limit the scope of the present invention. The embodiments described in this specification may be modified in various ways without departing from the spirit of the invention, and may be combined with features described in conjunction with other embodiments within the scope of implementation.

Claims

1. A GaN substrate wafer having a (0001) orientation, The GaN substrate wafer has a first region disposed on the N polarity side and a second region having a minimum thickness disposed on the Ga polarity side across a regrown interface, wherein: In the first region, the total concentration of compensating impurities is less than 1×10 17 atoms / cm 3 , The minimum thickness of the second region is 20 μm or more. The minimum thickness of the second region is less than 350 μm. In at least a portion of the second region, the total concentration of the compensating impurities is 1×10 17 atoms / cm 3 above, The main surface on the Ga polar side is a flat surface, The GaN substrate wafer satisfies any of the following conditions (1) to (3), (1) having a diameter of 50 mm or more and 55 mm or less and a thickness of 250 μm or more and 450 μm or less, (2) having a diameter of 100 mm or more and 105 mm or less and a thickness of 350 μm or more and 750 μm or less, (3) Having a diameter of 150 mm or more and 155 mm or less and a thickness of 450 μm or more and 800 μm or less.

2. The GaN substrate wafer according to claim 1, wherein: The first region satisfies one or more conditions selected from the following (a) to (c): (a) Si concentration is 5×10 16 atoms / cm 3 above; (b) O concentration is 3×10 16 atoms / cm 3 the following; (c) H concentration is 1×10 17 atoms / cm 3 the following.

3. The GaN substrate wafer according to claim 1 or 2, wherein: In the first region, the total concentration of the compensating impurities is lower than the total concentration of the donor impurities.

4. The GaN substrate wafer according to claim 1 or 2, wherein: In the first region, the concentration of impurity elements other than Si, O and H is independently 5×10 15 atoms / cm 3 the following.

5. The GaN substrate wafer according to claim 1 or 2, wherein: The second region has a main doping region including at least a main surface on the Ga polarity side, and the total concentration of the compensating impurities in the main doping region is 1×10 17 atoms / cm 3 above.

6. The GaN substrate wafer according to claim 5, wherein: The total concentration of compensating impurities in the main doping region is 1×10 18 atoms / cm 3 above.

7. The GaN substrate wafer according to claim 5, wherein: In the main doping region, the total concentration of the compensating impurities is more than twice the total concentration of the donor impurities.

8. The GaN substrate wafer according to claim 5, wherein: The main doping region contains one or more elements selected from carbon and transition metal elements.

9. The GaN substrate wafer according to claim 5, wherein: The impurity contained in the main doping region at the highest concentration is Fe, Mn or C.

10. The GaN substrate wafer according to claim 5, wherein: The main doped region is a region within a specific length from the main surface on the Ga polarity side, and the specific length is 20 μm or more.

11. The GaN substrate wafer according to claim 5, wherein: In the main doping region, the total concentration of the compensating impurities along the c-axis direction varies within a range of ±25% from the central value.

12. The GaN substrate wafer according to claim 10, wherein: The specific length is greater than 50 μm.

13. The GaN substrate wafer according to claim 10, wherein: The specific length is greater than or equal to 50% of the minimum thickness of the second region.

14. The GaN substrate wafer according to claim 1 or 2, wherein: The total concentration of compensating impurities in the second region is 5×10 19 atoms / cm 3 the following.

15. The GaN substrate wafer according to claim 1 or 2, wherein: The minimum thickness of the second region is 300 μm or less.

16. The GaN substrate wafer according to claim 1 or 2, wherein: The second region satisfies the following condition (a'): (a')Si concentration is 5×10 16 atoms / cm 3 above.

17. The GaN substrate wafer according to claim 1 or 2, wherein: The regrown interface is inclined with respect to the primary surface on the Ga polar side.

18. The GaN substrate wafer according to claim 17, wherein: A thickness difference between one end and the other end of the second region in the direction in which the regrown interface is tilted is not more than 200 μm.

19. The GaN substrate wafer according to claim 1 or 2, wherein: The main surface on the Ga polar side is a flat surface having a root mean square (RMS) roughness of less than 5 nm within a measurement range of 2 μm×2 μm as measured by an atomic force microscope (AFM).

20. An epitaxial wafer comprising: The GaN substrate wafer according to any one of claims 1 to 19, and A nitride semiconductor layer is epitaxially grown on the main surface on the Ga polarity side of the GaN substrate wafer.

21. A method for manufacturing an epitaxial wafer, the method comprising: A step of preparing the GaN substrate wafer according to any one of claims 1 to 19; and A step of growing a nitride semiconductor layer on the main surface on the Ga polarity side of the GaN substrate wafer.

22. A method for manufacturing a nitride semiconductor device, the method comprising: A step of preparing a GaN substrate wafer according to any one of claims 1 to 19; A step of growing a nitride semiconductor layer on the main surface on the Ga polarity side of the GaN substrate wafer to obtain an epitaxial wafer; and A step of removing the first region of the GaN substrate wafer from at least a portion of the epitaxial wafer.

23. A method for manufacturing a GaN substrate wafer, the method comprising: A second step of growing a second GaN thick film having a (0001) orientation on the substrate by HVPE and then slicing the second GaN thick film to obtain a second c-plane GaN wafer; and A third step is to grow a GaN film having a (0001) orientation and a thickness greater than 50 μm on the second c-plane GaN wafer by HVPE, wherein: The GaN film has a region having a total concentration of donor impurities higher than that of the second c-plane GaN wafer, Furthermore, the GaN film is provided with a total concentration of 1×10 17 atoms / cm 3 The above part, The thickness of the GaN film is less than 350 μm. The GaN substrate wafer satisfies any of the following conditions (1) to (3), (1) having a diameter of 50 mm or more and 55 mm or less and a thickness of 250 μm or more and 450 μm or less, (2) having a diameter of 100 mm or more and 105 mm or less and a thickness of 350 μm or more and 750 μm or less, (3) Having a diameter of 150 mm or more and 155 mm or less and a thickness of 450 μm or more and 800 μm or less.

24. A method for manufacturing a GaN substrate wafer, the method comprising manufacturing a GaN substrate wafer having a region on an N-polarity side and a region on a Ga-polarity side sandwiching a regrown interface, This method has: (i) a first step of growing a first GaN thick film formed of unintentionally doped GaN and having a (0001) orientation on a seed crystal wafer by HPVE, and processing the first GaN thick film to obtain at least one first c-plane GaN thick film; (ii) a second step of growing a second GaN thick film formed of GaN that is not intentionally doped and has a (0001) orientation on the first c-plane GaN wafer obtained in the first step by HVPE, and slicing a second c-plane GaN wafer from the second GaN thick film; and, (iii) a third step of growing a GaN film having a thickness of more than 50 μm and a (0001) orientation on the second c-plane GaN wafer obtained in the second step by HVPE to obtain a stacked structure; and After the third step, a thinning step of thinning the stacked structure, in, In the GaN film grown in the third step, the total concentration of the compensating impurities is set to 1×10 17 atoms / cm 3 The above part, The thickness of the GaN film is less than 350 μm. The GaN substrate wafer satisfies any of the following conditions (1) to (3), (1) having a diameter of 50 mm or more and 55 mm or less and a thickness of 250 μm or more and 450 μm or less, (2) having a diameter of 100 mm or more and 105 mm or less and a thickness of 350 μm or more and 750 μm or less, (3) Having a diameter of 150 mm or more and 155 mm or less and a thickness of 450 μm or more and 800 μm or less.

25. The method for manufacturing a GaN substrate wafer according to claim 24, wherein: The GaN film has a thickness of 300 μm or less.

26. The method for manufacturing a GaN substrate wafer according to claim 24 or 25, wherein: The GaN film has a region with a length of 20 μm or more in the c-axis direction, and a total concentration of compensating impurities in the region of 1×10 17 atoms / cm 3 The above specific doping regions.

27. The method for manufacturing a GaN substrate wafer according to claim 26, wherein: The total concentration of compensating impurities in the specific doping region is 1×10 18 atoms / cm 3 above.

28. The method for manufacturing a GaN substrate wafer according to claim 26, wherein: In the specific doping region, the total concentration of the compensating impurities is more than twice the total concentration of the donor impurities.

29. The method for manufacturing a GaN substrate wafer according to claim 26, wherein: The variation of the total concentration of the compensating impurities in the specific doping region along the c-axis direction is within the range of ±25% from the central value.

30. The method for manufacturing a GaN substrate wafer according to claim 26, wherein: The length of the region is greater than or equal to 50% of the thickness of the GaN film.

31. The method for manufacturing a GaN substrate wafer according to claim 26, wherein: A length from a lower end of the specific doping region to an interface between the GaN film and the second c-plane GaN wafer is 1 μm or more.

32. The method for manufacturing a GaN substrate wafer according to claim 26, wherein: The specific doping region contains one or more elements selected from carbon and transition metal elements.

33. The method for manufacturing a GaN substrate wafer according to claim 26, wherein: The impurity contained in the specific doping region at the highest concentration is Fe, Mn or C.

34. The method for manufacturing a GaN substrate wafer according to claim 23 or 24, wherein: The total concentration of compensating impurities in the GaN film is 5×10 19 atoms / cm 3 the following.

35. The method for manufacturing a GaN substrate wafer according to claim 24, wherein: The difference in thickness of the GaN film before and after the thinning step is 50 μm or more.

36. The method for manufacturing a GaN substrate wafer according to claim 24, wherein: The difference in thickness of the GaN film before and after the thinning step is 200 μm or less.

37. The method for manufacturing a GaN substrate wafer according to claim 23 or 24, wherein: The crystal orientation deviation azimuth of the GaN substrate wafer is different from the crystal orientation deviation azimuth of the second c-plane GaN wafer.

38. The method for manufacturing a GaN substrate wafer according to claim 23 or 24, wherein: Before growing the GaN film in the third step, there is a planarizing step of planarizing the main surface on the Ga polarity side of the second c-plane GaN wafer sliced ​​from the second GaN film in the second step, and further a roughening step of roughening the main surface by etching.

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