Integrated circuit capable of quaternary logic operations based on two-bit transistor memory

Abstract

The present invention discloses an integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory, belonging to the technical field of integrated circuits, and includes three types of integrated circuits, namely, a NOT gate, a NAND gate, and a NOR gate. The three integrated circuits all use a two-bit transistor memory as a core component; the three integrated circuits can all complete corresponding quaternary logic (NOT, NAND, NOR) operations; the NOT gate circuit is composed of a resistor and a two-bit transistor memory in series; the NAND gate is composed of two two-bit transistor memories and a resistor in series in sequence; the NOR gate is composed of two two-bit transistor memories first connected in parallel and then connected in series with a resistor. The operating voltage of the two-bit transistor memory of the present invention is not higher than 15 volts, and the field effect mobility is greater than 5cm 2 / Vs, can double the information storage capacity of the memory. The three integrated circuits of the present invention can all perform quaternary logic operations, and are applied to construct a storage and computing integrated architecture, which can solve the von Neumann bottleneck problem.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an integrated circuit which is constructed by using a two-bit transistor memory and can realize quaternary logic operations. Background Art

[0002] Information storage and computational processing are two important links in the information industry. As a carrier of information storage, memory is one of the key components of the information industry. In the current information industry chain, each transistor memory unit that constitutes the memory is a single-bit memory, that is, a transistor memory unit only stores a binary code (0 or 1). Correspondingly, various integrated circuits that perform computational processing on information in the information industry chain also use binary logic operations. With the rapid development of photolithography technology, the size of transistors is gradually approaching its physical limit; accordingly, the information storage capacity of a single-layer storage array in a transistor memory also tends to the physical limit. Continuously increasing the information storage capacity has always been the goal and direction of memory development. In a single transistor memory unit, realizing multi-bit (two-bit, three-bit, four-bit...) information storage, that is, developing multi-bit transistor memory, can double the information storage capacity of the memory. Accordingly, constructing and developing integrated circuits based on multi-bit (ternary, quaternary,...) logic operations can further broaden the bandwidth and speed of information processing by integrated circuits.

[0003] In recent years, reports on multi-bit transistor memories have increased year by year. Several polymer electrets [Macromol. Rapid Commun. (2014) 35, 1039], two-dimensional semiconductor molybdenum disulfide nanosheets [Nanoscale. (2014) 6, 12315], metal lithium ion encapsulated fullerenes [Org. Electron. (2017) 45, 234] and other dielectric materials have been used as charge trapping media to prepare multi-bit transistor memories. However, these reported multi-bit transistor memories generally require very high erase / write voltages (80-200V), which is not conducive to their practical application. Therefore, significantly reducing the erase / write voltage of multi-bit transistor memories to a reasonable level is a prerequisite for promoting their practical application and industrialization.

[0004] On the other hand, the basic structural form followed by the development of modern computers is still the von Neumann architecture; its characteristic is that the data processor and memory are separated. As the size of transistors is further reduced, their working speed increases significantly; this leads to the data transfer time between the processor and the memory gradually becoming a bottleneck problem that restricts the overall computing speed of the computer, the so-called von Neumann bottleneck. Some researchers have proposed that the use of memristors to build a storage-computing integrated architecture can solve the von Neumann bottleneck. Transistor memory can also be used to build logic operation circuits to achieve a storage-computing integrated architecture, providing another option for fundamentally solving the bottleneck problem of the von Neumann architecture. Summary of the invention

[0005] In response to the problems of physical limit of storage capacity and von Neumann bottleneck of single-layer transistor memory array faced by the aforementioned prior art, the present invention provides an integrated circuit based on two-bit transistor memory and a preparation method thereof, which can perform quaternary logic operations while effectively improving storage density, laying a foundation for building storage and computing integration and solving the bottleneck problem of von Neumann architecture.

[0006] The present invention is achieved through the following technical solutions:

[0007] Integrated circuits capable of performing quaternary logic operations based on two-bit transistor memories are three types of integrated circuits, namely NOT gate, NAND gate, and NOR gate. The three integrated circuits all use two-bit transistor memories as core components; the three integrated circuits can all complete corresponding quaternary logic (NOT, NAND, NOR) operations; wherein the NOT gate circuit is composed of a resistor and a two-bit transistor memory in series; the NAND gate is composed of two two-bit transistor memories and a resistor in series in sequence; and the NOR gate is composed of two two-bit transistor memories first connected in parallel and then connected in series with a resistor.

[0008] Furthermore, the NOT gate circuit is composed of a two-bit transistor memory and a resistor in series; the source electrode of the two-bit transistor memory is grounded, the drain electrode is connected to one end of the resistor, and the other end of the resistor is connected to the working voltage; the gate electrode of the two-bit transistor memory serves as the input end, and the connection point between the drain electrode and the resistor serves as the output end;

[0009] The NAND gate circuit is composed of two two-bit transistor memories and a resistor connected in series in sequence, the two two-bit transistor memories are respectively a first memory and a second memory; the source electrode of the first memory is grounded, the drain electrode of the first memory is connected to the source electrode of the second memory, the drain electrode of the second memory is connected to one end of the resistor, and the other end of the resistor is connected to the working voltage; the gate electrodes of the first memory and the second memory are respectively set as two input terminals (named as input terminal A and input terminal B respectively); the drain electrode of the second memory is set as an output terminal;

[0010] The NOR gate circuit is composed of two two-bit transistor memories connected in parallel and then connected in series with a resistor; the two two-bit transistor memories are respectively a third memory and a fourth memory, the source electrodes of the third memory and the fourth memory are connected and then grounded, and the drain electrodes of the third memory and the fourth memory are connected; after the drain electrodes of the third memory and the fourth memory are connected, they are connected to one end of the resistor, and the connection point is used as the output end; the other end of the resistor is connected to the working voltage; the gate electrodes of the third memory and the fourth memory are respectively set as two input ends (named as input end A and input end B respectively).

[0011] Furthermore, the two-bit transistor memory is composed of a substrate 1, a gate electrode 2, a ferroelectric gate insulating layer 3, an ultra-thin film optimization layer 4, a semiconductor layer 5 and a source-drain electrode 6 from bottom to top; the material of the substrate 1 is one or more of glass, silicon, polyethylene terephthalate, polyethylene naphthalate, polyimide, polyether sulfone or paper; the material of the gate electrode 2 and the source-drain electrode 6 is one or more of indium tin oxide, silver, gold, copper or aluminum; the material of the ferroelectric gate insulating layer 3 is a copolymer of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene; the material of the ultra-thin film optimization layer 4 is one of tetradecane, polymethyl methacrylate, polystyrene, polyimide, polyvinyl alcohol or polyvinyl pyrrolidone; the material of the semiconductor layer 5 is a small molecule organic semiconductor or a polymer organic semiconductor layer.

[0012] Furthermore, the small molecule organic semiconductor is pentacene, copper phthalocyanine, zinc phthalocyanine, fullerene, fluorinated copper phthalocyanine, 6,13-bis(triisopropylsilyl side ethynyl), 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, 2,9-didecyl dinaphtho[2,3-b:2′,3′-f]thiophene[3,2-b]thiophene; the polymer organic semiconductor layer is 3-hexyl substituted polythiophene (P3HT), {[N,N′-bis(2-octyldodecane alcohol) naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl]-5,5′-(2,2′-bithiophene)} copolymer, (9,9-octylfluorene-benzothiadiazole) copolymer, 2,20-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrolo[3,4-c]pyrrole-1,4-diyl]bithiophene-5,50-diyl-alt-thiophen[3,2-b]thiophene-2,5-diyl.

[0013] Furthermore, the thickness of the ferroelectric gate insulating layer 3 is 100 to 1000 nanometers; the thickness of the ultra-thin film optimization layer 4 is 5 to 50 nanometers; and the thickness of the semiconductor layer 5 is 10 to 150 nanometers.

[0014] Furthermore, the method for preparing the two-bit transistor memory includes the following steps: using vapor deposition or solution method to sequentially prepare a gate electrode, a ferroelectric gate insulation layer, an ultra-thin film optimization layer, a semiconductor layer and a source-drain electrode on the surface of a substrate to obtain a two-bit transistor memory that can operate at a low voltage.

[0015] Furthermore, the preparation method of the two-bit transistor memory comprises the following specific steps:

[0016] Step 1: preparing a gate electrode on the substrate surface by vacuum thermal deposition;

[0017] Step 2: preparing a ferroelectric polymer solution, and preparing a ferroelectric gate insulating layer on the surface of the gate electrode obtained in step 1 by a solution method; then heat-treating the ferroelectric gate insulating layer to remove the residual solvent in the ferroelectric gate insulating layer; the heat treatment temperature is 100 to 140° C.; the time is 60 to 120 minutes; the mass concentration of the ferroelectric polymer solution is 2% to 15%;

[0018] Step 3: treating the prepared ferroelectric gate insulating layer with ultraviolet ozone for 5 to 60 minutes;

[0019] Step 4: preparing a solution for an ultra-thin film optimization layer, and preparing the ultra-thin film optimization layer on the surface of the ferroelectric gate insulation layer obtained in step 3 by a solution method;

[0020] Step 5: preparing a semiconductor layer on the surface of the ultra-thin film optimization layer obtained in step 4 by vacuum thermal deposition or solution method;

[0021] Step 6: Prepare source-drain electrodes on the surface of the semiconductor layer obtained in step 5 by vacuum thermal deposition to obtain a two-bit transistor memory.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. The three integrated circuits of the invention, namely, the NOT gate, the NAND gate, and the NOR gate, which are constructed based on the two-bit transistor memory, can all perform reliable quaternary logic operations and are applied to construct a storage and computing integrated architecture, which can essentially solve the von Neumann bottleneck problem;

[0024] 2. The two-bit transistor memory provided by the present invention has a significant low-voltage operating characteristic, and the required erasing voltage is no higher than 15V, which is significantly lower than the 40-200V erasing voltage required by similar memories in the prior art; its low-voltage operating characteristic can meet the requirements of practicality and industrialization.

[0025] 3. The present invention uses ultraviolet ozone treatment on the ferroelectric gate insulating layer to increase the surface energy of the ferroelectric gate insulating layer and improve the coverage of the ultra-thin film optimization layer. The ultra-thin film optimization layer can smooth the surface of the ferroelectric gate insulating layer, shield the body traps and surface traps of the ferroelectric gate insulating layer from the charge transfer in the semiconductor layer; improve the microstructure of the semiconductor film prepared subsequently, reduce the body traps of the semiconductor; and further reduce the operating voltage of the transistor memory and significantly improve the field effect mobility of the transistor memory.

[0026] 4. The field effect mobility of the two-bit transistor memory provided by the present invention is greater than 5 cm 2 / Vs, which is significantly higher than the 0.001-0.5cm reported by most similar memories. 2 / Vs, laying the foundation for improving other performance parameters of memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A circuit diagram of a NOT gate integrated circuit constructed based on a two-bit transistor memory provided by the present invention;

[0028] Figure 2 A circuit diagram of a NAND gate integrated circuit constructed based on a two-bit transistor memory provided by the present invention;

[0029] Figure 3 A circuit diagram of a NOR gate integrated circuit constructed for a two-bit transistor memory provided by the present invention;

[0030] Figure 4 A schematic diagram of the structure of a two-bit transistor memory capable of operating at a low voltage provided by the present invention;

[0031] In the figure: substrate 1, gate electrode 2, ferroelectric gate insulating layer 3, ultra-thin film optimization layer 4, semiconductor layer 5, source-drain electrode 6;

[0032] Figure 5 The current-voltage transfer characteristic curve of the two-bit transistor memory capable of operating at a low voltage in different gate voltage operating ranges provided by Embodiment 2 of the present invention;

[0033] Figure 6 The erase and write cycle characteristics of the two-bit transistor memory capable of operating at a low voltage in the two-bit (four) storage state provided by the second embodiment of the present invention;

[0034] Figure 7 The non-volatile characteristics of the two-bit transistor memory capable of operating at a low voltage provided in Embodiment 2 of the present invention, namely, the persistent storage retention characteristics of the two-bit transistor memory in the two-bit (four) storage states;

[0035] Figure 8The output voltage measured at the output end of the NOT gate integrated circuit constructed based on the two-bit transistor memory provided in Example 2 of the present invention under different input logic signals given at the input end;

[0036] Fig. 9 When the NAND gate integrated circuit constructed based on the two-bit transistor memory of Example 2 provided by the present invention performs a quaternary logic operation, under different input logic signals provided by the input terminal A and the input terminal B, the output voltage measured at the output terminal;

[0037] Fig.10 A truth table diagram of a quaternary logic operation performed by the NAND gate integrated circuit provided by the present invention;

[0038] Fig.11 When the NOR gate integrated circuit constructed based on the two-bit transistor memory of Example 2 provided by the present invention performs a quaternary logic operation, under different input logic signals provided by the input terminal A and the input terminal B, the output voltage measured at the output terminal;

[0039] Fig.12 A truth table diagram of a quaternary logic operation performed by the NOR gate integrated circuit provided by the present invention. DETAILED DESCRIPTION

[0040] The embodiments of the technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only used as examples and cannot be used to limit the protection scope of the present invention.

[0041] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0042] Example 1

[0043] The present invention provides an integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory.

[0044] In the present invention, the circuit diagram of the NOT gate integrated circuit capable of performing quaternary logic operations is as follows: Figure 1 As shown; wherein, a two-bit transistor memory is connected in series with a resistor.

[0045] In the present invention, the circuit diagram of the NAND gate integrated circuit capable of performing quaternary logic operations is as follows: Figure 2 As shown, two two-bit transistor memories are connected in series and then in series with a resistor.

[0046] In the present invention, the circuit diagram of the NOR gate integrated circuit capable of performing quaternary logic operations is as follows: Figure 3As shown, two two-bit transistor memories are connected in parallel and then connected in series with a resistor.

[0047] In the present invention, the structure of the two-bit transistor memory capable of operating at low voltage is as follows: Figure 4 As shown by Figure 4 It can be seen that the two-bit transistor memory capable of operating at low voltage provided by the present invention comprises, from bottom to top, a substrate 1, a gate electrode 2, a ferroelectric gate insulating layer 3, an ultra-thin film optimization layer 4, a semiconductor layer 5 and a source-drain electrode 6.

[0048] In the present invention, the material of the substrate includes one or more of glass, silicon, polyethylene naphthalate, polyethylene terephthalate, polyimide, polyethersulfone and paper.

[0049] In the present invention, the gate electrode and the source-drain electrode are preferably made of one or more of indium tin oxide, silver, gold, copper, and aluminum. The thickness of the gate electrode is preferably 20 to 150 nanometers. The thickness of the source-drain electrode is preferably 20 to 200 nanometers.

[0050] The material of the ferroelectric grid insulation layer is vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer; the thickness of the ferroelectric grid insulation layer is preferably 100 to 1000 nanometers.

[0051] The preferred thickness of the ultra-thin film optimization layer is 5 to 50 nanometers; its material includes one of tetratetradecane, polymethyl methacrylate, polystyrene, polyimide, polyvinyl alcohol and polyvinyl pyrrolidone.

[0052] The semiconductor layer can be a small molecule organic semiconductor (for example, pentacene, copper phthalocyanine, zinc phthalocyanine, fullerene, fluorinated copper phthalocyanine, 6,13-bis(triisopropylsilyl side ethynyl), 2,7-bisoctyl[1]benzothieno[3,2-b][1]benzothiophene, 2,9-didecyl dinaphtho[2,3-b:2′,3′-f]thiophene[3,2-b]thiophene, etc.), or a polymer organic semiconductor layer (for example, 3-hexyl substituted polythiophene (P3HT), {[N,N′-bis(2 -octyldodecanol)naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl]-5,5′-(2,2′-bithiophene)} copolymer, (9,9-octylfluorene-benzothiadiazole) copolymer, 2,20-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrolo[3,4-c]pyrrole-1,4-diyl]bithiophene-5,50-diyl-alt-thiophene[3,2-b]thiophene-2,5-diyl, etc.).

[0053] The thickness of the semiconductor layer is preferably 10 to 150 nanometers.

[0054] In the present invention, all substances are commercially available products.

[0055] The present invention also provides a method for preparing a two-bit transistor memory capable of operating at a low voltage as described in the above technical solution, comprising the following steps: using a vapor deposition or solution method (spin coating, scraping, drip coating) process preparation method, sequentially preparing a gate electrode, a ferroelectric gate insulating layer, an ultra-thin film optimization layer, a semiconductor layer and a source-drain electrode on the surface of a substrate to obtain a two-bit transistor memory capable of operating at a low voltage. In the present invention, the preparation method preferably comprises the following steps:

[0056] (1) preparing a gate electrode on the substrate surface by vacuum thermal deposition;

[0057] (2) preparing a ferroelectric polymer solution, and preparing a ferroelectric gate insulating layer on the surface of the gate electrode obtained in step (1) by a solution method (spin coating, scraping, drip coating); then heat treating the ferroelectric gate insulating layer to remove residual solvent in the ferroelectric gate insulating layer; the heat treatment temperature is preferably 100 to 140° C.; the time is preferably 60 to 120 minutes; the mass concentration of the ferroelectric polymer solution is preferably 2% to 15%; the thickness of the obtained ferroelectric gate insulating layer can be optimized and adjusted by adjusting the concentration of the solution and specific solution method process preparation parameters (spin coating, scraping or drip coating rate, solvent atmosphere, etc.);

[0058] (3) treating the prepared ferroelectric gate insulating layer with ultraviolet ozone, the treatment time is preferably 5 to 60 minutes;

[0059] (4) preparing a solution for an ultra-thin film optimization layer, and preparing the ultra-thin film optimization layer on the surface of the ferroelectric gate insulating layer obtained in step (3) by a solution method (spin coating, scraping, drip coating) process; by adjusting the concentration of the solution and specific solution method process parameters (spin coating, scraping or drip coating rate, solvent atmosphere, etc.), the thickness of the obtained ultra-thin film optimization layer can be optimized and adjusted;

[0060] (5) preparing a semiconductor layer on the surface of the ultra-thin film optimization layer obtained in step (4) by vacuum thermal deposition or solution method (spin coating, scraping coating, drop coating); the thickness of the obtained semiconductor layer can be optimized and adjusted by specific preparation parameters;

[0061] (6) preparing source-drain electrodes on the surface of the semiconductor layer obtained in step (5) by vacuum thermal deposition to obtain a two-bit transistor memory.

[0062] The present invention has no special requirements on the vacuum vapor deposition or solution process used in the preparation process of each layer of thin film, and the common methods used by those skilled in the art can be adopted.

[0063] Example 2

[0064] The technical solution of the two-bit transistor memory capable of operating at a low voltage in the present invention is described clearly and completely below in conjunction with the embodiments of the present invention.

[0065] A two-bit transistor memory capable of operating at low voltage, having a bottom gate structure, and consisting of a substrate, a gate electrode, a ferroelectric gate insulating layer, an ultra-thin film optimization layer, a semiconductor layer, and a source-drain electrode from bottom to top;

[0066] Among them, the substrate is a polyethylene naphthalate (PEN) flexible substrate; the gate electrode is aluminum with a thickness of 50 nanometers; the ferroelectric gate insulation layer is a copolymer of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene with a thickness of 650 nanometers; the ultra-thin film optimization layer is tetratetradecane with a thickness of 12 nanometers; the semiconductor layer is 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene with a thickness of 30 nanometers; the source-drain electrode is gold with a thickness of 50 nanometers.

[0067] The preparation process of the two-bit transistor memory capable of operating at low voltage is as follows:

[0068] Firstly, the substrate is placed in a multi-source organic molecule / metal vapor deposition system, and a vacuum thermal deposition process is adopted to prepare a gate electrode.

[0069] Then, the ferroelectric material vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer is dissolved in butyl acetate solvent to prepare a solution with a concentration of 8% (mass percentage), and then the prepared vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer solution is dripped on the gate electrode, and a layer of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer film is prepared as a ferroelectric gate insulating layer by a spin coating process. After that, the substrate prepared with the ferroelectric film is placed in an oven and heated at 120° C. for 100 minutes to remove the residual butyl acetate solvent.

[0070] The substrate with the ferroelectric gate insulating layer prepared was placed in a UV-ozone treatment system for UV-ozone treatment for 20 minutes.

[0071] Tetradecane was dissolved in n-heptane solvent to prepare a solution with a concentration of 0.05% (mass percentage), and then the prepared tetradecane solution was dropped on the ferroelectric gate insulating layer, and a layer of tetradecane film was prepared as an ultra-thin film optimization layer by a scraping process; the scraping rate was 5 mm / s.

[0072] The substrate with the ultra-thin film optimization layer prepared was placed in a multi-source organic molecule / metal vapor deposition system. A layer of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene thin film was grown on the surface of the ultra-thin film optimization layer using a vacuum thermal deposition process as a semiconductor layer. Next, a layer of gold thin film was grown on the surface of the semiconductor layer using a vacuum thermal deposition process as a source-drain electrode. The source-drain electrodes were patterned using a mask. The channel length and width of the prepared device were 100 microns and 1000 microns, respectively.

[0073] Example 3

[0074] A two-bit transistor memory capable of operating at low voltage has a bottom gate structure and is composed of a substrate, a gate electrode, a ferroelectric gate insulating layer, an ultra-thin film optimization layer, a semiconductor layer, and a source-drain electrode from bottom to top.

[0075] Among them, the substrate is glass covered with patterned indium tin oxide, which is purchased from the market; the gate electrode is indium tin oxide with a thickness of 120 nanometers; the ferroelectric gate insulating layer is a copolymer of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene with a thickness of 500 nanometers; the ultra-thin film optimization layer is polyvinyl pyrrolidone with a thickness of 20 nanometers; the semiconductor layer is 2,20-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrole[3,4-c]pyrrole-1,4-diyl]dithiophene-5,50-diyl-alt-thiophene[3,2-b]thiophene-2,5-diyl with a thickness of 50 nanometers; the source-drain electrode is copper with a thickness of 120 nanometers.

[0076] The preparation process of the two-bit transistor memory capable of operating at low voltage is as follows:

[0077] The glass substrate purchased from the market has been covered with patterned indium tin oxide as the gate electrode;

[0078] The ferroelectric material vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer is dissolved in 2-ethoxyethanol solvent to prepare a solution with a concentration of 5% (mass percentage), and then the prepared vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer solution is dripped on the gate electrode, and a layer of vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer film is prepared as a ferroelectric gate insulating layer by a spin coating process. Afterwards, the substrate prepared with the ferroelectric film is placed in an oven and heated at 130° C. for 100 minutes to remove the residual 2-ethoxyethanol solvent.

[0079] The substrate with the ferroelectric gate insulating layer prepared was placed in a UV-ozone treatment system for UV-ozone treatment for 40 minutes.

[0080] Polyvinyl pyrrolidone was dissolved in propylene glycol solvent to prepare a solution with a concentration of 0.5% (mass percentage), and then the prepared polyvinyl pyrrolidone solution was dropped on the ferroelectric gate insulating layer, and a layer of polyvinyl pyrrolidone film was prepared as an ultra-thin film optimization layer by spin coating process.

[0081] The polymer semiconductor 2,20-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrole[3,4-c]pyrrole-1,4-diyl]dithiophene-5,50-diyl-alt-thiophene[3,2-b]thiophene-2,5-diyl is dissolved in a chlorobenzene solvent to prepare a solution with a concentration of 0.5% (mass percentage); the prepared polymer semiconductor solution is then dropped on a ferroelectric gate insulating layer and a thin film is prepared by a spin coating process to serve as a semiconductor layer; the solution is placed in a glove box and heated at 100° C. for 20 minutes to remove residual chlorobenzene solvent.

[0082] The substrate with the semiconductor layer prepared was placed in a multi-source organic molecule / metal vapor deposition system, and a copper film was grown on the surface of the semiconductor layer as a source-drain electrode using a vacuum thermal deposition process. The source-drain electrode was patterned using a mask, and the channel length and width of the prepared device were 100 microns and 1000 microns respectively.

[0083] Performance Testing:

[0084] The electrical performance of the prepared two-bit transistor memory capable of operating at low voltage was tested using an Agilent B1500A semiconductor test analyzer. All tests were conducted in an atmospheric environment at room temperature.

[0085] The current-voltage transfer characteristics of the two-bit transistor memory capable of operating at low voltage provided by Embodiment 2 of the present invention in different gate voltage scanning ranges are as follows: Figure 5 As shown; the storage cycle characteristics of the two-bit transistor memory with low voltage operation provided in Example 2 obtained under different erase voltage operations with two-bit (four) storage characteristics are as follows Figure 6 As shown; the storage retention characteristics of the two-bit transistor memory with two-bit (four) storage characteristics provided by Example 2 that can operate at low voltage are as follows Figure 7 shown.

[0086] from Figures 5 to 7It can be seen that the two-bit transistor memory capable of low voltage operation provided by the present invention can obtain different storage windows and storage current ratios under different gate voltage scanning ranges; under the erase voltage operation of +15, -5, -10 and -15 volts, different four-level storage states are obtained, and the source-drain current in different storage states can be marked as quaternary storage 0 state, storage 1 state, storage 2 state and storage 3 state from small to large, and its four-level storage state can be well switched and maintained for a long time; within the actual measured storage cycle endurance of more than 200 cycles, the source-drain current representing the four-level storage states of 0, 1, 2 and 3 has no obvious attenuation; in the actual 40,000 seconds storage retention time test, the source-drain current representing the four-level storage states of 0, 1, 2 and 3 has no obvious attenuation, indicating that the device has good non-volatile storage characteristics. These data show that the two-bit transistor memory of the present invention has significant low voltage operation characteristics and excellent storage performance. Compared with other reported two-bit (multi-bit) transistor memories (working voltage is generally 40-200V), the two-bit transistor memory of the present invention obtains excellent two-bit storage function at a lower working voltage, and its working voltage meets the practical and industrial requirements of the memory; in addition, Figure 5 It is calculated that the field effect mobility of the two-bit transistor memory provided in Example 2 of the present application is greater than 5 cm 2 / Vs, which indicates that the field effect mobility of the two-bit transistor memory provided by the present application is relatively high.

[0087] The circuit connection method and performance test of the NOT gate integrated circuit are as follows:

[0088] The two-bit transistor memory capable of operating at a low voltage as described in Example 2 is connected in series with a resistor with a resistance value of 2 megohms, the source electrode is grounded, the drain electrode is connected to one end of the resistor, and the connection point is set as the output end; the other end of the resistor is connected to the operating voltage to form a non-gate integrated circuit, such as Figure 1 As shown. The working voltage is set to -10 volts, and the gate electrode of the two-bit transistor memory is set as the input terminal. The input voltages of 15, -5, -10, and -15 volts are input to the input terminal in sequence, corresponding to the quaternary input logic signals 0, 1, 2, and 3 respectively; at the output terminal, four different output voltages are measured in sequence, corresponding to the quaternary output logic signals 3, 2, 1, and 0 respectively. Figure 8 shown.

[0089] The connection method and performance test of the NAND gate integrated circuit are as follows:

[0090] The two two-bit transistor memories capable of operating at low voltage described in Example 2 (named as the first memory and the second memory, the same below) are connected in series; wherein the source electrode of the first memory is grounded, and the drain electrode of the first memory is connected to the source electrode of the second memory; then the two memories connected in series are connected in series with a resistor with a resistance of 2 megohms, and the drain electrode of the second memory is connected to one end of the resistor; the other end of the resistor is connected to the operating voltage; and a NAND gate integrated circuit is formed, such as Figure 2 As shown. The working voltage is set to -10 volts. The gate electrodes of the first memory and the second memory are set as input terminals A and B respectively; the drain electrode of the second memory is set as the output terminal. Input voltages of 15, -5, -10, and -15 volts are given at input terminals A and B in sequence according to the duration of time, corresponding to the quaternary input logic signals 0, 1, 2, and 3 respectively; at the output terminal, four different output voltages are measured in sequence according to the duration of time, and the measured output voltages correspond to the quaternary output logic signals 3, 2, 1, and 0 respectively from high to low, as shown in FIG. Fig. 9 shown. Fig.10 The truth table of the corresponding input terminal A, input terminal B and output terminal for quaternary logic operation in the NAND gate integrated circuit is given.

[0091] The connection method and performance test of the NOR gate integrated circuit are as follows:

[0092] The two two-bit transistor memories capable of operating at low voltage described in Example 2 are connected in parallel; wherein the source electrodes of the third memory and the fourth memory are connected and then grounded, and the drain electrodes of the third memory and the fourth memory are connected. The two parallel memories are connected in series with a resistor with a resistance value of 2 megohms, and the drain electrodes of the two memories are connected to one end of the resistor, and the connection point is used as the output terminal; the other end of the resistor is connected to the working voltage, and the working voltage is set to -10 volts. The gate electrodes of the third memory and the fourth memory are set as input terminals A and B respectively. The formed NOR gate integrated circuit is as follows: Figure 3 As shown. Input voltages of 15, -5, -10, and -15 volts are given at input terminals A and B in sequence according to the duration of time, corresponding to the input signals 0, 1, 2, and 3 of the quaternary logic operation respectively; four different output voltages are obtained at the output terminal in sequence according to the duration of time, and the measured output voltages correspond to the quaternary output logic signals 3, 2, 1, and 0 respectively from high to low, as shown. Fig.11 shown. Fig.12 The truth table of the corresponding input terminal A, input terminal B and output terminal for quaternary logic operation in the NOR gate integrated circuit is given.

[0093] It can be clearly seen from the test results that after the two-bit transistor memory and the resistor are connected according to the set NOT gate, NAND gate, or NOR gate integrated circuit, the corresponding quaternary NOT, NAND, or NOR logic operations can be stably performed. In the NOT gate, NAND gate, or NOR gate integrated circuit described in the present invention, the specific values ​​of the operating voltage and the resistor can be adjusted respectively, which will affect the specific voltage value obtained by the output terminal test, but will not affect the logic operation result.

[0094] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0095] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0096] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. An integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory, characterized in that: The three integrated circuits are respectively a NOT gate, a NAND gate, and a NOR gate; the three integrated circuits can all perform corresponding quaternary logic operations; wherein the NOT gate circuit is composed of a resistor and a two-bit transistor memory connected in series; the NAND gate is composed of two two-bit transistor memories and a resistor connected in series in sequence; the NOR gate is composed of two two-bit transistor memories connected in parallel and then connected in series with a resistor; The NOT gate circuit is composed of a two-bit transistor memory and a resistor in series; the source electrode of the two-bit transistor memory is grounded, the drain electrode is connected to one end of the resistor, and the other end of the resistor is connected to the working voltage; the gate electrode of the two-bit transistor memory is used as the input end, and the connection point of its drain electrode and the resistor is used as the output end; The NAND gate circuit is composed of two two-bit transistor memories and a resistor connected in series in sequence, the two two-bit transistor memories are respectively a first memory and a second memory; the source electrode of the first memory is grounded, the drain electrode of the first memory is connected to the source electrode of the second memory, the drain electrode of the second memory is connected to one end of the resistor, and the other end of the resistor is connected to the working voltage; the gate electrodes of the first memory and the second memory are respectively set as two input terminals; the drain electrode of the second memory is set as an output terminal; The NOR gate circuit is composed of two two-bit transistor memories connected in parallel and then connected in series with a resistor; the two two-bit transistor memories are respectively a third memory and a fourth memory, the source electrodes of the third memory and the fourth memory are connected and then grounded, and the drain electrodes of the third memory and the fourth memory are connected; after the drain electrodes of the third memory and the fourth memory are connected, they are connected to one end of the resistor, and the connection point is used as the output end; the other end of the resistor is connected to the working voltage; the gate electrodes of the third memory and the fourth memory are respectively set as two input ends.

2. The integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory as claimed in claim 1, characterized in that: The two-bit transistor memory is composed of a substrate (1), a gate electrode (2), a ferroelectric gate insulating layer (3), an ultra-thin film optimization layer (4), a semiconductor layer (5) and a source-drain electrode (6) from bottom to top; the material of the substrate (1) is one or more of glass, silicon, polyethylene terephthalate, polyethylene naphthalate, polyimide, polyethersulfone or paper; the material of the gate electrode (2) and the source-drain electrode (6) is one or more of indium tin oxide, silver, gold, copper or aluminum; the material of the ferroelectric gate insulating layer (3) is a vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer; the material of the ultra-thin film optimization layer (4) is one of tetradecane, polymethyl methacrylate, polystyrene, polyimide, polyvinyl alcohol or polyvinyl pyrrolidone; the material of the semiconductor layer (5) is a small molecule organic semiconductor or a polymer organic semiconductor layer.

3. The integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory as claimed in claim 2, characterized in that: The small molecule organic semiconductor is pentacene, copper phthalocyanine, zinc phthalocyanine, fullerene, fluorinated copper phthalocyanine, 6,13-bis(triisopropylsilyl side ethynyl), 2,7-bisoctyl[1]benzothieno[3,2-b][1]benzothiophene, 2,9-didecyl dinaphtho[2,3-b:2′,3′-f]thiophene[3,2-b]thiophene; the polymer organic semiconductor layer is 3-hexyl substituted polythiophene (P3HT), {[N,N′-bis(2-octyl dodecanol) Naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl]-5,5′-(2,2′-bithiophene)} copolymer, (9,9-octylfluorene-benzothiadiazole) copolymer, 2,20-[(2,5-bis(2-octyldodecyl)-3,6-dioxy-2,3,5,6-tetrahydropyrrolo[3,4-c]pyrrole-1,4-diyl]bithiophene-5,50-diyl-alt-thiophen[3,2-b]thiophene-2,5-diyl.

4. The integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory as claimed in claim 2, characterized in that: The thickness of the ferroelectric grid insulation layer (3) is 100-1000 nanometers; the thickness of the ultra-thin film optimization layer (4) is 5-50 nanometers; and the thickness of the semiconductor layer (5) is 10-150 nanometers.

5. The integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory as claimed in claim 2, characterized in that: The preparation method of the two-bit transistor memory comprises the following steps: using vapor deposition or solution method to sequentially prepare a gate electrode, a ferroelectric gate insulating layer, an ultra-thin film optimization layer, a semiconductor layer and a source-drain electrode on the surface of a substrate to obtain a two-bit transistor memory capable of operating at a low voltage.

6. The integrated circuit capable of performing quaternary logic operations based on a two-bit transistor memory as claimed in claim 2, characterized in that: The preparation method of the two-bit transistor memory comprises the following specific steps: Step 1: preparing a gate electrode on the substrate surface by vacuum thermal deposition; Step 2: preparing a ferroelectric polymer solution, and preparing a ferroelectric gate insulating layer on the surface of the gate electrode obtained in step 1 by a solution method; then heat-treating the ferroelectric gate insulating layer to remove the residual solvent in the ferroelectric gate insulating layer; the heat treatment temperature is 100 to 140° C.; the time is 60 to 120 minutes; the mass concentration of the ferroelectric polymer solution is 2% to 15%; Step 3: treating the prepared ferroelectric gate insulating layer with ultraviolet ozone for 5 to 60 minutes; Step 4: preparing a solution for an ultra-thin film optimization layer, and preparing the ultra-thin film optimization layer on the surface of the ferroelectric gate insulation layer obtained in step 3 by a solution method; Step 5: preparing a semiconductor layer on the surface of the ultra-thin film optimization layer obtained in step 4 by vacuum thermal deposition or solution method; Step 6: Prepare source-drain electrodes on the surface of the semiconductor layer obtained in step 5 by vacuum thermal deposition to obtain a two-bit transistor memory.

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