Dynamic voltage setting optimization during lifetime of memory device

Abstract

This application is about dynamic voltage setting optimization during the lifetime of a memory device. An initial level of a sense voltage is set based on one or more characteristics of a segment of a memory device. A count of operating cycles is set for the segment of the memory device. The sense voltage is changed relative to the initial level of the sense voltage in response to determining that a number of operating cycles performed on the segment of the memory device has reached the set count of operating cycles. The sense voltage is adjusted to a new level based on wear of the segment of the memory device during the number of operating cycles performed on the segment of the memory device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically to optimizing voltage settings based on changes in wear conditions of segments of memory devices in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] One aspect of the present disclosure provides a method comprising: setting an initial level of a sense voltage based on one or more characteristics of a segment of a memory device; setting a count of operational cycles for the segment of the memory device; in response to determining, by a processing device, that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, determining that the sense voltage needs to be adjusted relative to the initial level of the sense voltage; and adjusting the sense voltage to a new level based on wear of the segment of the memory device during which the number of operational cycles is performed on the segment of the memory device.

[0004] Another aspect of the present disclosure provides a system comprising: a memory device comprising a plurality of memory segments; and a processing device operably coupled to the plurality of memory segments to periodically perform, for each of the plurality of memory segments, a dynamic voltage optimization operation, the operation comprising: determining whether a number of operational cycles performed on a memory segment satisfies a cycle threshold criterion specific to the memory segment; in response to determining that the number of operational cycles satisfies the cycle threshold criterion, determining a bit error rate associated with the memory segment; determining whether the bit error rate satisfies an error threshold criterion specific to the memory segment; and in response to determining that the bit error rate satisfies the error threshold criterion, adjusting a level of a sense voltage applied to the memory segment.

[0005] Another aspect of the disclosure provides a non-transitory computer- readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: setting an initial level of a sense voltage based on one or more characteristics of a segment of a memory device; setting a count of operating cycles for the segment of the memory device; in response to determining, by the processing device, that a number of operating cycles performed on the segment of the memory device has reached the set count of operating cycles, determining that the sense voltage needs to be adjusted relative to the initial level of the sense voltage; and adjusting the sense voltage to a new level based on wear of the segment of the memory device during the number of operating cycles performed on the segment of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which:

[0007] Figure 1 An example computing system including a host system coupled with a memory sub-system according to some embodiments of the disclosure is described.

[0008] Figure 2 Variations in threshold voltage windows for which cycle counts are performed for individual segments of a memory device subjected to various temperatures according to some embodiments of the disclosure are described.

[0009] Figure 3A A single sense voltage for individual segments of a memory device for a fixed number of operating cycles according to some embodiments of the disclosure is described.

[0010] Figure 3B Different sense voltages for different segments of a memory device for a fixed number of operating cycles according to embodiments of the disclosure are described.

[0011] Figure 4 A flowchart of an example method of dynamic voltage optimization according to some embodiments of the disclosure is described.

[0012] Figure 5 A flowchart of an example method of optimal sense voltage search according to some embodiments of the disclosure is described.

[0013] Figure 6 Various possible voltage offset settings for two different write-to-read delay values according to some embodiments of the disclosure are described.

[0014] Figure 7 Selecting the correct voltage setting optimized for different write-to-read delay values according to some embodiments of the disclosure is illustrated.

[0015] Figure 8 A graph illustrating a bit error rate distribution in a sampled region of a memory segment is shown, in accordance with some embodiments of the application.

[0016] Figure 9 A block diagram of an example computer system in which embodiments of the application can operate is shown. DETAILED DESCRIPTION

[0017] Aspects of the application relate to dynamically optimizing voltage settings for memory cells in various segments of memory devices in a memory sub-system based on changes in wear conditions in the respective segments and based on characteristics of the memory cells of the memory segments. The memory sub-system can be a storage device, a memory module, or a mix of storage devices and memory modules. The following description is made in connection with Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. The term "segment" is used to encompass a grouping of one or more memory cells in a memory device based on some common characteristic, as will be described in detail below.

[0018] The memory sub-system can include high-density non-volatile memory devices, where the retention of data is required when no power is supplied to the memory device. One example of a non-volatile memory device is a NAND memory device. Another example is a three-dimensional cross-point ("3D cross-point") memory device that includes an array of non-volatile memory cells. The 3D cross-point memory device can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. The following description is made in connection with Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a collection of physical blocks. Each block is composed of a collection of pages. Each page is composed of a collection of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and has various logical states related to the number of bits stored. The logical states can be represented by binary values (e.g., "0" and "1") or combinations of such values.

[0019] Memory devices can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (also referred to below as bit lines (BL)) and rows (also referred to below as word lines (WL)). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. Hereinafter, a block refers to a unit of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks can be grouped together to form a plane of a memory device in order to allow concurrent operations on each plane. A 3D cross-point based memory device can be referred to as a "drive," which has multiple dies layered in multiple "slabs." A "segment" of a 3D cross-point memory device can thus mean one or more slabs, one or more dies, or one or more units that are not necessarily physically contiguous but have a common characteristic, e.g., have the same electrical distance (ED) to a word line (WL) and / or bit line (BL), as described in further detail below.

[0020] In conventional memory sub-systems, variations in temperature and / or process drift can adversely affect the reliability of a memory device. For example, excessive temperatures used for a heating process during assembly can cause crystallization of a region of a memory device over time (e.g., reset amorphous phase change memory in a memory cell). This crystallization can decrease the resistivity of the memory cell, which in turn decreases the threshold voltage of the memory cell. This decrease in threshold voltage can adversely affect reliability because high voltage levels can cause voltage level instability, causing a higher error rate of the memory device during the useful lifetime of the memory sub-system.

[0021] For example, during the useful lifetime of a memory device, a set state and a reset state of a memory cell can register a higher than expected voltage level relative to a predefined threshold voltage (V t ) read level. As such, a memory cell of a memory device in a state indicative of a set state (e.g., a lower voltage level associated with a bit value of'1 ') can be interpreted by a read operation as a higher voltage level that can indicate a reset state (e.g., a higher voltage level associated with a bit value of '0'). This in turn can cause a higher error rate due to a drift in the observed voltage level that can affect the representative voltage state of the affected memory cell. While a write operation is performed to program the memory cell to a set state, the voltage state of the memory cell in response to a read operation can be indicated differently due to voltage level drift.

[0022] Conventional memory sub-systems configured in this manner typically address the resulting reliability issues by performing specialized read or write operations on the memory device in repeated cycles to stabilize the voltage levels of the memory cells. During these "conditioning" cycles, voltage pulses are applied to the memory device to stabilize the voltage levels of the memory cells to predetermined set and reset voltage states separated by a demarcation voltage (Vdm), also referred to as a "sensing voltage" during the useful life of the memory device.

[0023] In conventional memory sub-systems, the same number of conditioning cycles are applied to all memory devices of the memory sub-system to obtain an initial level of the sensing voltage at the beginning of the useful life of the memory devices. In such instances, some memory devices can reach a stable voltage level with fewer conditioning cycles, while some memory devices can reach a stable voltage level with more conditioning cycles. Thus, applying a single number of conditioning cycles can "over-condition" or "under-condition" various memory devices within the memory sub-system. Over-conditioning can significantly shorten the life of that memory device due to excess wear even before the beginning of the useful life of the memory device. Conversely, under-conditioning a memory device can result in a higher bit error rate due to continued instability of the voltage levels during the useful life of the memory device.

[0024] Aspects of the present disclosure address the above and other deficiencies by selecting different sensing voltage levels for different segments of a memory device based on characteristics of the memory cells in the respective segments of the memory device and based on a current level of wear in the segments during the useful life of the segments. The characteristics of the memory cells in a particular segment of the memory device are indicative of an initial bit error rate for the respective segment. After a preset number of operational cycles (e.g., read cycles or write cycles), if the determined bit error rate does not satisfy an acceptable bit error rate associated with a stable voltage level, the sensing voltage is conditioned before proceeding to the next set of operational cycles. Read cycles constitute transferring data from the memory device to a host. Write cycles constitute transferring data from the host to the memory device. The dynamic voltage optimization scheme disclosed herein can adapt to current wear conditions due to the number of operational cycles and other characteristics of the media at a more granular level compared to the overall memory device level (also referred to as a drive level).

[0025] Advantages of the present disclosure include, but are not limited to, improved reliability of a memory device during its lifetime, which leads to superior data integrity. The dynamic voltage optimization process of the present disclosure reduces the impact of reliability and performance variations among various segments of a memory device due to external factors, such as temperature experienced by the segments, location of the segments in the memory device (e.g., which tier the segments belong to), and the like.

[0026] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the present disclosure is described. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of these.

[0027] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including memory and a processing device.

[0029] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 An example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0030] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more cache memories, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0031] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0033] Some examples of non-volatile memory devices (e.g., memory devices 130) include NAND-type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grided data access array. Additionally, in contrast to many flash-based memories, a cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without prior erasure of the non-volatile memory cell. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination of these. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0035] While 3D cross-point arrays of non-volatile memory cells, such as SLC, and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or NOR flash memory, as well as electrically erasable programmable read-only memory (EEPROM).

[0036] The memory sub-system controller 115 (or, for simplicity, the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory sub-system controller 115 can be a processing device that includes one or more processors (e.g., the processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0038] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the local memory 119 is illustrated as being internal to the memory sub-system controller 115, in some embodiments, the local memory 119 can be external to the memory sub-system controller 115. Figure 1 The example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, but in another embodiment of the application, the memory sub-system 110 does not include the memory sub-system controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0039] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA) namespace) and a physical address (e.g., physical block address) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from a host system into command instructions to access memory devices 130, as well as convert responses associated with memory devices 130 into information for host system 120.

[0040] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0041] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory devices 130 are managed memory devices that are raw memory devices combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] The memory sub-system 110 can additionally include a voltage optimization component 113, which can be used to facilitate operations for the memory device 130. The operations include transferring data from the host to the memory device during a write cycle, and transferring data from the memory device to the host during a read cycle. In some embodiments, the memory sub-system controller 115 includes at least a portion of the voltage optimization component 113. For example, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the voltage optimization component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the voltage optimization component 113 and is configured to perform the functionality described herein. Further details regarding the operations of the voltage optimization component 113 are described below.

[0043] Figure 2 The variation of threshold voltage window in which the cycle count is performed for individual segments of a memory device subjected to various temperature conditions is illustrated in accordance with some embodiments of the present disclosure. Generally, the threshold voltage window (i.e., the difference between the maximum value of the threshold voltage and the minimum value of the threshold voltage before the bit error rate becomes unacceptable) degrades as the operation cycle count increases. This degradation becomes more pronounced for memory segments subjected to high temperatures (curve 208) as compared to the same memory segments subjected to low temperatures (curve 204). At room temperature, the degradation of the threshold voltage window is between the degradation experienced at high temperatures and the degradation experienced at low temperatures, as shown by curve 206. Figure 2 The degradation of the threshold voltage window can further depend on the physical location of the memory segment in the memory device for the same temperature, for example. The degradation for a first segment at room temperature ("tier 0") (curve 202) is less pronounced as compared to the degradation for a second segment at room temperature ("tier 1") (curve 206). The initial level of the sensing voltage for a particular segment is selected based on the "pre-conditioning" that the cells of the memory segment have been subjected to prior to their useful life. Another characteristic that can be a factor in setting the initial sensing voltage is the variation in electrical distance (ED), i.e., the distance from the voltage source to the memory cells in the memory array. The voltage sources in the memory array are the word line (WL) and bit line (BL) drivers. The further a memory cell is from a driver, the greater the voltage drop between the expected voltage and the actual voltage, which can affect the characteristics of the memory device or its segments. ED can have a large impact on the reliability of the memory device. Lower write voltages can cause certain memory cells in the memory device to have a different threshold voltage distribution as compared to memory cells programmed with higher write voltages.

[0044] Figure 3A A single sense voltage (Vdm 310) applied to two segments of a memory device is illustrated. Curve 302 illustrates a threshold voltage distribution for a "set" phase for a first memory segment, and curve 304 illustrates a threshold voltage distribution for a "reset" phase for the same memory segment. An initial sense voltage (Vdm 310) is set to divide the set and reset phases of the first memory segment for a fixed number of cycles. However, for the same number of cycles, the single Vdm 310 can not unambiguously divide the set (curve 306) and reset (curve 308) phases of a second memory segment. Bits for the second memory segment within profile 312 are likely to be read as erroneous values due to the suboptimal Vdm 310 for the second memory segment.

[0045] Figure 3B Different sense voltages (Vdm#1 311 and Vdm#2 309) applied to different segments of a memory device for a fixed number of operating cycles according to embodiments of the present disclosure are illustrated. After the first and second segments of the memory device have been subjected to the same number or different numbers of operating cycles, Vdm#2 309 can be optimized for the set (curve 302) and reset (304) demarcations for the first segment of the memory device, while Vdm#1 311 can be optimized for the set (curve 306) and reset (curve 308) demarcations for the second segment of the memory device. This results in a slight shifting of the set and reset curves for each segment, requiring Figure 3A The initial sense voltage Vdm 310 shown in FIG. 3 is shifted by an offset voltage, as described below.

[0046] Figure 4 is a flow diagram of an example method 400 of dynamically optimizing a sense voltage in a memory segment according to some embodiments of the present disclosure. The method 400 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 can be performed by the voltage optimization component 113 of FIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. Figure 1 is a flow diagram of an example method 400 of dynamically optimizing a sense voltage in a memory segment according to some embodiments of the present disclosure. The method 400 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 can be performed by the voltage optimization component 113 of FIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0047] At operation 410, the voltage optimizer component 113 sets an initial level of the sense voltage based on one or more characteristics of the segment of the memory device. This process is sometimes referred to as voltage "trimming," in which one or more parameters for a read cycle or a write cycle for a particular segment are stored locally in the segment. Some of the trimming parameters can include parameters for the initial sense voltage level, e.g., pulse width, amplitude, and rate. The trimming parameters including the initial level of the sense voltage can vary from one segment to another in the memory device.

[0048] At operation 420, a processing device in the voltage optimizer component 113 or elsewhere in the memory sub-system controller 115 sets a count of operational cycles for a segment of the memory device. The "count" sets a threshold number of operational cycles after which the sense voltage is adjusted. This count can also vary from one segment to another. Typical values for the expected performance operational cycles of a segment belonging to a memory device can be 50k, 100k, 150, 200k, 500k, 1 million, etc. As an example, a memory device can be designed for a total of 200k operational cycles during its lifetime. The initial count can thus be set to 50k, and subsequently incremented by another 50k after the processing device adjusts the sense voltage according to operations 430 and 440 described below, until the total cycle count reaches 200k. It is noted that these illustrative numbers are non-limiting, and any other number of operational cycles can be used.

[0049] At operation 430, in response to determining that the number of operation cycles performed on the segment of the memory device has reached the set count of operation cycles, the processing device determines that the sense voltage needs to be adjusted relative to the initial level of the sense voltage. To change the Vdm, a number of Vdm offsets relative to the initial level of the Vdm can be stored in the memory segment based on the location of the memory segment in the memory device and / or other characteristics of the memory segment. Different offset values can be stored for different numbers of cycle counts. For example, a Vdm offset (0, 0, 1) can indicate an offset to be applied relative to the initial sense voltage after the cycle count reaches a first set point (e.g., a number of cycles N) for a first memory segment (e.g., tier 0) having a first ED value (e.g., ED0). A Vdm offset (0, 0, 2) can indicate an offset to be applied relative to the initial sense voltage after the cycle count reaches a second set point (e.g., 2N number of cycles) for the first memory segment (e.g., tier 0) having the first ED value (e.g., ED0). In the same manner, a Vdm offset (i, m, n) can indicate an offset to be applied relative to the initial sense voltage after the cycle count reaches an n-th set point (i.e., nxN number of cycles) for an i-th memory segment (e.g., tier i) having an m-th ED value (i.e., ED-m). The offset is relative to the initial sense voltage based on the location of the memory segment (e.g., tier 0 or tier 1) and other characteristics (e.g., ED1, ED2,... ED-m) of the memory segment. Figure 5 The search operation is described in more detail with respect to the flowchart of FIG. 4.

[0050] At operation 440, the voltage optimizer component 113 adjusts the sense voltage to a new level based on the wear of the segment of the memory device during the number of operation cycles performed on the segment of the memory device. As an example, if the cycle count is set to 50k, and the number of read / write operations reaches 50k, the initial Vdm is shifted to a new level of the sense voltage with the stored offset value in the memory segment for the current wear state of 50k cycles corresponding to the location of the memory segment (e.g., tier 0 or tier 1) and other characteristics (e.g., ED1, ED2,... ED-m).

[0051] Figure 5 is a flowchart of an example method 500 of optimal sense voltage search according to some embodiments of the present disclosure. The method 500 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 500 can be performed by a voltage optimizer component 113 coupled to a memory device 101. Figure 1by a processing device in firmware of a memory subsystem of the voltage optimization component 113. Although shown in a particular order or sequence, unless otherwise specified, the order or sequence can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. One or more processes can also be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. This operation can be performed periodically for each memory segment in the memory device.

[0052] At operation 510, the processing device sets a cycle count to have a predetermined value, e.g., N. Different values of N can be selected for different segments, and N can be a cycle threshold criterion specific to the corresponding memory segment. Until the N number of operation cycles are performed on a particular memory segment, the initial Vdm remains unchanged for all cycles (operation 515) for the memory segment. When the cycle count reaches the set point "N", the process moves to operation 520.

[0053] At operation 520, the processing device runs the optimal Vdm search algorithm. In one embodiment, this algorithm can be programmed as a background process to be run by the firmware of the memory controller. Relative to the initial Vdm, the algorithm searches for an optimal Vdm offset value that can be applied to the initial Vdm to achieve the optimal Vdm for the memory segment. Figure 8 The selection of the sampling region is described in more detail. The Vdm search algorithm can be based on determining a bit error rate associated with the memory segment. When the bit error rate meets an error threshold criterion specific to the memory segment, the need for adjusting the Vdm is established. The algorithm then searches for an optimal storage value of the Vdm offset, as described in operation 430 of method 400.

[0054] At operation 530, the processing device applies the optimal Vdm offset to the current value of the Vdm to raise or lower the Vdm level to a new adjusted value. This value is maintained until the next set point. The set point can be incremented to 2N or any arbitrary number of additional cycles to be performed on the memory segment, and operations 520 and 530 are repeated until the new set point is reached.

[0055] Figure 6 Various possible default voltage settings for two different write-to-read delay values at the die level (i.e., initial settings of the Vdm during fine-tuning optimization) are illustrated in accordance with some embodiments of the present application. Because the distance between the set and reset curves for the same segment with the same intrinsic characteristics can vary based on the write-to-read (W2R) delay time at the die level, the default Vdm can also be adjusted based on the write-to-read delay. In some embodiments, the default Vdm is set to the value of the Vdm at the reset point of the set and reset curves. In other embodiments, the default Vdm is set to the value of the Vdm at the set point of the set and reset curves. In yet other embodiments, the default Vdm is set to the average of the Vdm values at the set and reset points of the set and reset curves. Figure 6In particular, curves 602 and 604 indicate set and reset curves for a write-to-read delay value of 25 μβ, respectively, while curves 606 and 608 indicate set and reset curves for a write-to-read delay value of 1 second, respectively. As can be seen in Figure 6 In particular, curves 602 and 604 indicate set and reset curves for a write-to-read delay value of 25 μβ, respectively, while curves 606 and 608 indicate set and reset curves for a write-to-read delay value of 1 second, respectively. As can be seen in Figure 6 In particular, curves 602 and 604 indicate set and reset curves for a write-to-read delay value of 25 μβ, respectively, while curves 606 and 608 indicate set and reset curves for a write-to-read delay value of 1 second, respectively. As can be seen in

[0056] Figure 7 FIG. 7 illustrates selecting the correct voltage setting optimized for different write-to-read delay values, according to some embodiments of the application. The raw bit error rate (RBER) is plotted for each possible voltage setting (Setting #1, Setting #2, Setting #3, and Setting #4) for a particular die. Curve 702 corresponds to a W2r delay value of Is, while curve 704 corresponds to a W2r delay value of 25 μβ. While both curves 702 and 704 deviate from the ideal change in RBER with continuously changing Vdm, as shown by curve 706, in Figure 7 In particular, curves 602 and 604 indicate set and reset curves for a write-to-read delay value of 25 μβ, respectively, while curves 606 and 608 indicate set and reset curves for a write-to-read delay value of 1 second, respectively. As can be seen in

[0057] Figure 8 FIG. 8 illustrates a plot showing the distribution of bit error rates in a sample region of a memory segment, according to some embodiments of the application. For each memory segment, a plurality of memory cells having similar RBER values can be grouped together to apply a single Vdm. Memory cells having similar RBER do not have to be physically on the same die and can be distributed across multiple dies. For example, in Figure 8 In particular, curves 602 and 604 indicate set and reset curves for a write-to-read delay value of 25 μβ, respectively, while curves 606 and 608 indicate set and reset curves for a write-to-read delay value of 1 second, respectively. As can be seen in

[0058] Figure 9An example machine of a computer system 900 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. For example, the computer system 900 may correspond to a host system (e.g., Figure 1 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or can be used to perform operations of the controller (for example, to execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0059] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0060] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0061] The processing device 902 represents one or more general-purpose processing devices, e.g., a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 902 can also be one or more special-purpose processing devices, e.g., an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. The computer system 900 can further include a network interface device 908 to communicate over a network 920. The data storage device 918 can include a machine-readable storage medium 924 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions or software 926 embodying any one or more of the methods or functions described herein. The instructions 926 can also reside completely or at least partially within the main memory 904 and / or within the processing device 902 during execution by the computer system 900, the main memory 904 and the processing device 902 also constituting a machine-readable storage medium. The machine-readable storage medium 924, the data storage device 918, and / or the main memory 904 can correspond to Figure 1 the memory subsystem 110.

[0062] In one embodiment, the instructions 926 include instructions for implementing the functionality corresponding to a particular component, e.g., Figure 1 the voltage optimization component 113). Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated cache memories and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present invention. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid state memories, optical media, and magnetic media.

[0063] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0064] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated as otherwise, throughout the description, occurrences of terms such as "receiving" or "service" or "publishing" or the like are to be associated with the actions of a computer system or similar electronic computing device manipulating and transforming physical quantities represented as electrical or magnetic signals within the computer system's registers and memories into other physical quantities similarly represented as electrical or magnetic signals within other such information storage devices within the computer system or similar electronic computing devices.

[0065] The present application also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0066] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present application is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the application as described herein.

[0067] The application can be provided as a computer program product, or software, which can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present application. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium, etc.

[0068] In the foregoing specification, embodiments of the application have been described with reference to specific examples thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the application as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method of dynamically optimizing voltage settings in a memory device, comprising: setting an initial level of a sense voltage based on one or more characteristics of a segment of a memory device, wherein at least one of the one or more characteristics is obtained during fabrication of the segment; setting a count of operating cycles for the segment of the memory device; in response to determining, by a processing device, that a number of operating cycles performed on the segment of the memory device has reached the set count of operating cycles, determining that the sense voltage needs to be adjusted relative to the initial level of the sense voltage; and adjusting the sense voltage to a new level based on wear of the segment of the memory device during the number of operating cycles performed on the segment of the memory device.

2. The method of claim 1, wherein the one or more characteristics of the segment of the memory device comprise at least one of a physical location of the segment in the memory device, an electrical distance (ED), a temperature, or a process drift during fabrication.

3. The method of claim 1, further comprising: associating a threshold of a bit error rate with the segment of the memory device.

4. The method of claim 3, wherein the adjusting the sense voltage further comprises: determining a change in a value of the bit error rate of the segment of the memory device associated with the wear of the segment of the memory device; determining a voltage offset needed to bring the value of the bit error rate back to the threshold associated with the segment of the memory device; and applying the determined voltage offset to the initial level of the sense voltage to set the sense voltage to the new level.

5. The method of claim 4, further comprising: changing a write-to-read latency of the operating cycles; for each write-to-read latency, storing a plurality of levels of a sense voltage, each of the plurality of levels at an offset relative to an initial level of the sense voltage; and selecting the new level of the sense voltage from the plurality of levels.

6. The method of claim 1, further comprising: resetting the count of operating cycles to a higher value until reaching a maximum number of operating cycles that lasts a lifetime of the segment of the memory device.

7. The method of claim 1, wherein the method is performed by a background processing thread.

8. A memory system, comprising: a memory device comprising a plurality of memory segments; and a processing device operably coupled to the plurality of memory segments to periodically perform a dynamic voltage optimization operation for each of the plurality of memory segments, the operation comprising: determining whether a number of operating cycles performed on a memory segment meets a cycle threshold criterion specific to the memory segment; in response to determining that the number of operating cycles meets the cycle threshold criterion, determining a bit error rate associated with the memory segment; determining whether the bit error rate meets an error threshold criterion specific to the memory segment; and ​ adjusting a level of a sense voltage applied to the memory segment, wherein a default level of the sense voltage depends on one or more characteristics of the memory segment, wherein at least one of the one or more characteristics is obtained during manufacturing of the memory segment.

9. The memory system of claim 8, wherein the one or more characteristics comprise at least one of a physical location of the memory segment in the memory device, an electrical distance (ED), a temperature, or a process drift during manufacturing.

10. The memory system of claim 8, the dynamic voltage optimization operations further comprising: associating an applicable value of a bit error rate with the memory segment.

11. The memory system of claim 10, wherein the operations for adjusting the sense voltage further comprise: determining a change in the value of the bit error rate of the memory segment associated with wear-out of the memory segment; determining a voltage offset needed to bring the value of the bit error rate to a value that satisfies the error threshold criteria associated with the memory segment; and applying the determined voltage offset to an initial level of a sense voltage to set the sense voltage to a new level.

12. The memory system of claim 11, the dynamic voltage optimization operations further comprising: changing a write-to-read delay time of the operational cycle; for each write-to-read delay time, storing a plurality of levels of a sense voltage, each of the plurality of levels at an offset from an initial level of a sense voltage; and selecting the new level of a sense voltage from the stored plurality of levels.

13. The memory system of claim 8, the dynamic voltage optimization operations further comprising: resetting the cycle threshold criteria to a higher value until a maximum number of operational cycles is reached that lasts a lifetime of the memory segment.

14. The memory system of claim 8, wherein the bit error rate is represented by at least one of a raw bit error rate (RBER) or a failed bit count (FBC).

15. The memory system of claim 8, further comprising firmware that samples the memory device to determine the error threshold criteria associated with a memory segment.

16. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: setting an initial level of a sense voltage based on one or more characteristics of a segment of a memory device, wherein at least one of the one or more characteristics is obtained during manufacturing of the segment; setting a count of operational cycles for a segment of the memory device; in response to determining, by the processing device, that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, determining that adjustment of the sense voltage relative to the initial level of the sense voltage is needed; and adjusting the sense voltage to a new level based on wear of the segment of the memory device during the number of operational cycles performed on the segment of the memory device.

17. The non-transitory computer-readable medium of claim 16, wherein the one or more characteristics of the segment of the memory device comprise at least one of a physical location of the segment in the memory device, an electrical distance (ED), a temperature, or a process drift during manufacturing.

18. The non-transitory computer-readable medium of claim 16, the operations further comprising: associating a threshold of a bit error rate with the segment of the memory device.

19. The non-transitory computer-readable medium of claim 18, wherein the adjusting the sense voltage further comprises: determining a change in a value of the bit error rate of the segment of the memory device associated with wear of the segment of the memory device; determining a voltage offset needed to bring the value of the bit error rate back to the threshold associated with the segment of the memory device; and applying the determined voltage offset to an initial level of the sense voltage to set the sense voltage to the new level.

20. The non-transitory computer-readable medium of claim 19, the operations further comprising: changing a write-to-read latency of the operational cycles; for each write-to-read latency, storing a plurality of levels of sense voltage, each of the plurality of levels at an offset relative to an initial level of the sense voltage; and selecting the new level of sense voltage from the plurality of levels.

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