Group iii nitride laminate, semiconductor element, and method for manufacturing group iii nitride laminate

Abstract

A Group III nitride laminate, a semiconductor element, and a manufacturing method of a Group III nitride laminate. The object is to improve equipment characteristics. The means for solving the problem is as follows: having a base substrate, a first layer provided on the base substrate and formed of aluminum nitride, and a second layer provided on the first layer and formed of gallium nitride, the thickness of the first layer is greater than 100 nm and is 1 μm or less, the half-value width of (0002) diffraction based on X-ray rocking curve measurement is 250 seconds or less, and the half-value width of (10-12) diffraction based on X-ray rocking curve measurement is 500 seconds or less.

Description

TECHNICAL FIELD

[0001] The present application relates to a Group III nitride laminate, a semiconductor element, and a method for manufacturing a Group III nitride laminate. BACKGROUND

[0002] A Group III nitride-based high electron mobility transistor (HEMT) is widely used as a power amplifier for mobile phone base station applications (for example, Patent Document 1). The Group III nitride-based HEMT can greatly increase the electric power that can be input to each element, as compared with a Si-based device used in the past. Thus, the base station can be downsized, and the installation cost can be greatly reduced.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Laid-Open (JP-A) No. 2006-286741 SUMMARY

[0006] Problem to be solved by the invention

[0007] An object of the present application is to improve device characteristics.

[0008] Solution to the problem

[0009] According to one embodiment of the present application, there is provided a Group III nitride laminate, comprising:

[0010] a base substrate;

[0011] a first layer provided on the base substrate and formed of aluminum nitride; and

[0012] a second layer provided on the first layer and formed of gallium nitride,

[0013] the first layer has a thickness of greater than 100 nm and 1 μm or less, a half-value width of (0002) diffraction based on an X-ray rocking curve is 250 seconds or less, and a half-value width of (10-12) diffraction based on an X-ray rocking curve is 500 seconds or less.

[0014] According to another embodiment of the present application, there is provided a semiconductor element,

[0015] which has the second layer of the Group III nitride laminate according to the above embodiment as at least a part of an active layer.

[0016] According to another embodiment of the present application, there is provided a Group III nitride laminate, comprising:

[0017] a base substrate; and

[0018] a first layer provided on the aforementioned base substrate and formed of aluminum nitride,

[0019] the aforementioned first layer has a thickness of greater than 100 nm and 1 μm or less, a half-value width of (0002) diffraction based on X-ray rocking curve measurement is 250 seconds or less, and a half-value width of (10-12) diffraction based on X-ray rocking curve measurement is 500 seconds or less.

[0020] According to another aspect of the present application, there is provided a method for manufacturing a group III nitride laminate, including the steps of:

[0021] forming a first layer formed of aluminum nitride on a base substrate;

[0022] performing heat treatment of the aforementioned first layer in an atmosphere containing hydrogen; and

[0023] forming a second layer formed of gallium nitride on the aforementioned first layer,

[0024] in the step of forming the aforementioned first layer, the aforementioned first layer is formed in such a manner that:

[0025] the aforementioned first layer has a thickness of greater than 100 nm and 1 μm or less, a half-value width of (0002) diffraction based on X-ray rocking curve measurement is 250 seconds or less, and a half-value width of (10-12) diffraction based on X-ray rocking curve measurement is 500 seconds or less.

[0026] Effects of the invention

[0027] According to the present application, it is possible to improve device characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic cross-sectional view showing a group III nitride laminate according to a first embodiment of the present application.

[0029] Figure 2 is a schematic cross-sectional view showing a semiconductor element according to the first embodiment of the present application.

[0030] Figure 3 is a flowchart showing a method for manufacturing a group III nitride laminate and a method for manufacturing a semiconductor element according to the first embodiment of the present application.

[0031] Figure 4 is a schematic cross-sectional view showing a group III nitride laminate according to a second embodiment of the present application.

[0032] Figure 5is a graph showing the half-value width of each of the (0002) diffraction and the (10-12) diffraction of the AlN in Experiment 1 with respect to the thickness of the AlN layer.

[0033] Figure 6 is a graph showing the range of the thickness of the AlN layer and the thickness of the GaN layer when the half-value width of each of the (0002) diffraction and the (10-12) diffraction of the GaN in Experiment 2 satisfies a prescribed condition.

[0034] Figure 7A is a schematic cross-sectional view showing a semiconductor element of an embodiment of Experiment 3.

[0035] Figure 7B is a graph showing SIMS results of the embodiment of Experiment 3.

[0036] Figure 8A is a schematic cross-sectional view showing a semiconductor element of Comparative Example 1 of Experiment 3.

[0037] Figure 8B is a graph showing SIMS results of Comparative Example 1 of Experiment 3.

[0038] Figure 9A is a schematic cross-sectional view showing a semiconductor element of Comparative Example 2 of Experiment 3.

[0039] Figure 9B is a graph showing SIMS results of Comparative Example 2 of Experiment 3.

[0040] Figure 10A is a schematic cross-sectional view showing a semiconductor element of Comparative Example 3 of Experiment 3.

[0041] Figure 10B is a graph showing SIMS results of Comparative Example 3 of Experiment 3.

[0042] Figure 11A is a graph showing an example of the leakage current with respect to the gate voltage in a conventional semiconductor element.

[0043] Figure 11B is a graph showing the buffer leakage current with respect to the threshold voltage after stress application in Experiment 3.

[0044] Figure 12 is a graph showing the element lifetime with respect to the half-value width of the (10-12) diffraction of GaN in the electron transport layer in Experiment 4.

[0045] Reference Signs List

[0046] 1 Group III nitride layer stack (stack)

[0047] 2 Semiconductor element

[0048] 10 base substrate

[0049] 20 nucleus formation layer

[0050] 30 electron movement layer

[0051] 40 electric supply layer

[0052] 50 cap layer DETAILED DESCRIPTION

[0053] <Insights obtained by the present inventors>

[0054] First, the insights obtained by the present inventors will be described.

[0055] A Group III nitride-based HEMT has, for example, a prescribed base substrate, a first layer formed of aluminum nitride (AIN), a second layer formed of gallium nitride (GaN), and a third layer having a wide band gap. As a device characteristic of such a Group III nitride-based HEMT, high mobility, high reliability of the element, and low buffer leakage current are sought, for example.

[0056] However, a Group III nitride-based HEMT is difficult to optimize the device characteristics for the following reasons.

[0057] To obtain high mobility and high reliability, it is sought to reduce the dislocation density of the second layer formed of GaN. As a method thereof, a method can be considered in which the second layer is caused to grow three-dimensionally in an initial stage of growing the second layer on the first layer formed of AIN. In this method, dislocations are caused to converge with each other and disappear in the course of three-dimensional growth of the second layer. Thereby, the dislocation density of the second layer can be reduced. By reducing the dislocation density of the second layer, deterioration of the gate electrode can be suppressed, for example. As a result, high mobility and high reliability can be achieved. At this time, regarding the film thickness of the second layer, the film thickness for three-dimensional growth for sufficiently reducing the dislocation density and the film thickness thereafter for planarizing the second layer need to be about 1 μm or more.

[0058] However, in the method of causing the second layer to grow three-dimensionally, impurities such as oxygen (O) are mixed in by means of inclined crystal planes (facets) in the island-shaped crystal during the three-dimensional growth of the second layer. In the portion of the second layer into which O is mixed, O forms an n-type impurity (donor), and thus the free electron concentration locally increases. Therefore, the leakage current (also referred to as buffer leakage current) that flows through the region of the second layer on the first layer side (i.e., the region of the second layer in which three-dimensional growth occurs) increases. If the above-described buffer leakage current increases when the two-dimensional electron gas (2DEG) of the second layer is pinched off, the On / Off current ratio can decrease. Furthermore, in the case where the buffer leakage current is large, the operation of one element can affect the operation of the other element for a pair of elements that are adjacent to each other.

[0059] Note that, in the case where the three-dimensional growth of the second layer is suppressed and the flat second layer is grown to be thin, the dislocation density of the second layer cannot be sufficiently reduced. Therefore, the gate leak cannot be sufficiently suppressed. As a result, the reliability of the element as a HEMT can decrease.

[0060] On the other hand, in order to suppress the above-described buffer leakage current, a method of highly doping impurities such as iron (Fe) and carbon (C) that form deep levels in the vicinity of the interface between the first layer formed of AlN and the second layer formed of GaN can be considered.

[0061] However, in this method, as the impurities that form deep levels are charged and discharged, the pinch-off voltage changes with a large time constant, and a so-called hysteresis can occur. Therefore, the operating current can be unstable. Thus, there is a clear trade-off between the suppression of the above-described buffer leakage current and the stable operation achieved by suppressing hysteresis.

[0062] As described above, in the conventional group III nitride-based HEMT, it is difficult to achieve at least any one of high mobility, high reliability, and low buffer leakage current as device characteristics.

[0063] The present application is based on the above-described insight discovered by the present inventors and the like.

[0064] [Details of Embodiments of the Present Invention]

[0065] Next, one embodiment of the present application will be described below with reference to the drawings. Note that the present application is not limited to these examples, and all modifications shown in the claims and included in the equivalent meaning and range of the claims are included.

[0066] [First Embodiment of the Present Invention]

[0067] Hereinafter, a first embodiment of the present application will be described with reference to the drawings.

[0068] (1) Group III Nitride Layer Stack

[0069] Use Figure 1 The group III nitride layer stack (group III nitride layer stack substrate) according to the present embodiment will be described. Figure 1 is a schematic cross-sectional view showing the group III nitride layer stack according to the present embodiment.

[0070] Note that, hereinafter, in a crystal of a group III nitride semiconductor having a wurtzite structure or the like, a <0001> axis is referred to as a "c-axis", and a (0001) plane is referred to as a "c-plane". Note that, sometimes, the (0001) plane is referred to as a "+c-plane (group III element polarity plane)", and the (000-1) plane is referred to as a "-c-plane (nitrogen (N) polarity plane)". Further, a <1-100> axis (for example, a [1-100] axis) is referred to as an "m-axis", and a {1-100} plane is referred to as an "m-plane". Further, a <11-20> axis (for example, a [11-20] axis) is referred to as an "a-axis", and a {11-20} plane is referred to as an "a-plane".

[0071] As shown in FIG. 1, the group III nitride layer stack 1 (hereinafter also referred to as "layer stack 1") according to the present embodiment has, for example, a base substrate 10, a core formation layer (first layer) 20, an electron movement layer (second layer) 30, and an electron supply layer (third layer) 40. Note that, the layer stack 1 can further have a cladding layer (fourth layer) 50. However, as will be described later, the cladding layer 50 can not be provided. Figure 1

[0072] (Base Substrate)

[0073] The base substrate 10 is formed of, for example, silicon carbide (SiC) or sapphire (AI2O3). Here, the base substrate 10 is, for example, an SiC substrate. The polytype of the SiC substrate as the base substrate 10 is not particularly limited, and is, for example, 4H, 6H, or 3C. Further, the SiC substrate as the base substrate 10 is preferably semi-insulating.

[0074] The base substrate 10 has a base surface (main surface) 11. In the present embodiment, the lowest index crystal plane closest to the base surface 11 is, for example, a c-plane ((0001) plane, Si plane).

[0075] ​The c-axis of the base substrate 10 can be inclined with respect to the normal line of the base surface 11 at a prescribed off-angle. The magnitude of the off-angle of the base surface 11 is, for example, preferably greater than 0° and 1° or less, more preferably greater than 0° and 0.1° or less. The off-angle of the base surface 11 can have a distribution in the plane within the above range. Furthermore, the direction of inclination (off direction) of the off-angle of the base surface 11 is not limited, and can be, for example, the a-axis direction, or can also be the m-axis direction.

[0076] The base substrate 10 is preferably large in area, for example, in order to improve the productivity when manufacturing a semiconductor element. Specifically, the diameter of the base substrate 10 is, for example, 2 inches (50.8 mm) or more, preferably 4 inches (100 mm) or more, and more preferably 6 inches (150 mm) or more.

[0077] The thickness of the base substrate 10 is not particularly limited, and depends on the diameter of the base substrate 10. Specifically, the thickness of the base substrate 10 having a diameter of 2 inches is, for example, 300 μm or more and 500 μm or less (typically, 430 μm), the thickness of the base substrate 10 having a diameter of 4 inches is, for example, 400 μm or more and 1000 μm or less (typically, 500 μm), and the thickness of the base substrate 10 having a diameter of 6 inches is, for example, 400 μm or more and 1500 μm or less (typically, 600 μm).

[0078] Furthermore, the root mean square roughness RMs of the base surface 11 of the base substrate 10, which is measured using an atomic force microscope (AFM) for a 5 μm square region, is, for example, 1 nm or less, and is preferably 0.5 nm or less.

[0079] (Nucleus formation layer)

[0080] The nucleus formation layer 20 is configured, for example, in a manner such that a crystal nucleus for growing the electron movement layer 30 described later is generated. Specifically, the nucleus formation layer 20 is formed of, for example, AlN. Furthermore, the nucleus formation layer 20 is provided on the base substrate 10, for example. The nucleus formation layer 20 is formed, for example, by hetero-epitaxially growing a single crystal of AlN on the base surface 11 of the base substrate 10.

[0081] The nucleus formation layer 20 has a main surface 21. The "main surface 21" referred to here means a surface side (the main surfaces 31 and 41 described later also mean a surface side in the same manner as described above). In the present embodiment, the nucleus formation layer 20 is epitaxially grown on the base surface 11 formed of the c-plane of the base substrate 10, and thus the lowest index crystal plane closest to the main surface 21 of the nucleus formation layer 20 is, for example, the c-plane ((0001) plane, Al-plane).

[0082] The thickness of the nucleus formation layer 20 is, for example, greater than 100 nm and is 1 μm or less. In the related art, the thickness of the AlN layer as the nucleus formation layer 20 is set to 100 nm or less. Thus, impurities can possibly diffuse from the base substrate 10 to the electron transport layer 30 described later through the nucleus formation layer 20. Specifically, when the SiC substrate is used as the base substrate 10, diffusion of Si from the SiC substrate to the electron transport layer 30 is inevitable. Thus, in the related art, even in the case where three-dimensional growth of the electron transport layer 30 is not performed, as long as impurities such as iron (Fe) and carbon (C) which form deep energy levels are not doped at a high concentration in the vicinity of the interface between the nucleus formation layer 20 formed of AlN and the electron transport layer 30 formed of GaN, there is a problem that buffer leakage cannot be suppressed. In contrast, in the present embodiment, by setting the thickness of the nucleus formation layer 20 to be greater than 100 nm, diffusion of impurities from the base substrate 10 to the electron transport layer 30 through the nucleus formation layer 20 can be suppressed. Specifically, in the case where the base substrate 10 is the SiC substrate, diffusion of Si from the base substrate 10 to the electron transport layer 30 can be suppressed. Thus, even if impurities such as Fe and C which form deep energy levels are not doped at a high concentration in the vicinity of the interface between the nucleus formation layer 20 formed of AlN and the electron transport layer 30 formed of GaN, buffer leakage can be suppressed.

[0083] On the other hand, if the thickness of the nucleus formation layer 20 is greater than 1 μm, the laminate 1 can be warped or the nucleus formation layer 20 or the like can be cracked mainly due to a difference in linear expansion coefficient between the nucleus formation layer 20 and other layers. In contrast, in the present embodiment, by setting the thickness of the nucleus formation layer 20 to be 1 μm or less, warping of the laminate 1 and cracking of the nucleus formation layer 20 or the like caused by a difference in linear expansion coefficient between the nucleus formation layer 20 and other layers can be suppressed.

[0084] Further, when the half width (FWHM: Full Width at Half Maximum) of the prescribed crystal plane diffraction of AlN based on X-ray rocking curve measurement is plotted with respect to the thickness of the nucleus formation layer 20 obtained by the manufacturing method described later, the X-ray diffraction half width of AlN shows a tendency to be convex downward. Thus, if the thickness of the nucleus formation layer 20 is 100 nm or less, the X-ray diffraction half width of AlN can be large. In contrast, in the present embodiment, by setting the thickness of the nucleus formation layer 20 to be greater than 100 nm, an increase in the X-ray diffraction half width of AlN can be suppressed. That is, a decrease in the crystallinity of the nucleus formation layer 20 can be suppressed.

[0085] Further, the thickness of the nucleus formation layer 20 is preferably, for example, 200 nm or more and 700 nm or less, and more preferably 300 nm or more and 500 nm or less. By setting the thickness of the nucleus formation layer 20 within the above range, the X-ray diffraction half-value width of AlN can be further reduced. That is, the crystallinity of the nucleus formation layer 20 can be improved.

[0086] Specifically, when the thickness of the nucleus formation layer 20 is, for example, greater than 100 nm and 1 μm or less, the half-value width of (0002) diffraction of AlN measured based on an X-ray rocking curve is 250 seconds or less, and the half-value width of (10-12) diffraction of AlN measured based on an X-ray rocking curve is 500 seconds or less.

[0087] Further, when the thickness of the nucleus formation layer 20 is, for example, 200 nm or more and 700 nm or less, the half-value width of (0002) diffraction of AlN measured based on an X-ray rocking curve is 200 seconds or less, and the half-value width of (10-12) diffraction of AlN measured based on an X-ray rocking curve is 400 seconds or less.

[0088] Further, when the thickness of the nucleus formation layer 20 is, for example, 300 nm or more and 500 nm or less, the half-value width of (0002) diffraction measured based on an X-ray rocking curve is 180 seconds or less, and the half-value width of (10-12) diffraction measured based on an X-ray rocking curve is 380 seconds or less.

[0089] As such, by improving the crystallinity of the nucleus formation layer 20, even if three-dimensional growth is not introduced at the time of growth of the electron movement layer 30, the crystallinity of the electron movement layer 30 to be described later formed on the nucleus formation layer 20 can be improved.

[0090] For example, when the nucleus formation layer 20 is formed in high quality using the HVPE method or the like as in the present embodiment, the nucleus formation layer 20 has a strain in the direction along the substrate surface 11 (for example, the a-axis direction). The amount of strain in the a-axis direction of the nucleus formation layer 20 depends on, for example, the difference in linear expansion coefficient (and the difference in lattice constant) between the base substrate 10 and the nucleus formation layer 20.

[0091] Note that the "amount of strain in the a-axis direction" referred to here means, for example, the ratio of change in the a-axis length (lattice constant in the a-axis direction) of the crystal constituting a prescribed layer compared to the a-axis length of a bulk crystal having no strain. When the amount of strain is positive, it means that the crystal has tensile strain, and when the amount of strain is negative, it means that the crystal has compressive strain.

[0092] The amount of strain in the a-axis direction ε1 (%) of the nucleus formation layer 20 is, for example, calculated by the following formula (1).

[0093] ε1 = (a1 - a AlN ) / a AlN× 100... (1)

[0094] wherein a1 is the a-axis length of the AlN crystal constituting the nucleus formation layer 20, a AlN is the a-axis length of the bulk AlN crystal without strain.

[0095] Note that the strain amount ε1 (%) in the a-axis direction of the nucleus formation layer 20 can be found, for example, by the following steps. First, the diffraction angle of the (0002) plane of the nucleus formation layer 20 is measured by X-ray diffraction measurement (2θ-ω scan), and the c-axis length (lattice constant in the c-axis direction) of the nucleus formation layer 20, c1, is found. The c-axis length c1 of the nucleus formation layer 20, the Poisson's ratio v of AlN, and the strain amount ε1 in the a-axis direction of the nucleus formation layer 20 satisfy the following equation (2).

[0096] (c1-c AlN ) / c AlN = -2v / (1-v) x ε1... (2)

[0097] The Poisson's ratio v of AlN is assumed to be 0.2, and thus, based on the change in the c-axis length c1, the strain amount ε1 in the a-axis direction of the nucleus formation layer 20 can be found by the following equation (3).

[0098] ε1 = -2(c1-c AlN ) / c AlN ... (3)

[0099] Specifically, when the base substrate 10 is formed of SiC, the strain amount ε1 (%) in the a-axis direction of the nucleus formation layer 20 (at room temperature 27°C) is, for example, +0.1% or more and +0.5% or less. Note that since the strain amount is positive, it means that the AlN crystal constituting the nucleus formation layer 20 has tensile strain.

[0100] (Electron movement layer)

[0101] The electron movement layer 30 is configured, for example, as described later, to generate a two-dimensional electron gas (2DEG) in a region on the side of the electron supply layer 40 and to enable movement of electrons when the semiconductor element 2 is driven. Specifically, the electron movement layer 30 is formed of, for example, GaN. Further, the electron movement layer 30 is provided on, for example, the nucleus formation layer 20. The electron movement layer 30 is formed, for example, by hetero-epitaxial growth of a single crystal of GaN on the main face 21 of the nucleus formation layer 20.

[0102] The electron movement layer 30 has, for example, a main face 31. In the present embodiment, the low-index crystal face closest to the main face 31 of the electron movement layer 30 is, for example, the c-face ((0001) plane, Ga-face).

[0103] In the present embodiment, the thickness of the electron transport layer 30 is, for example, less than 1 μm. If the thickness of the electron transport layer 30 is 1 μm or more, warping of the laminate 1 can occur mainly due to the difference in the linear expansion coefficient between the electron transport layer 30 and other layers. Thus, pattern defects can occur at the time of photolithography. Further, GaN constituting the electron transport layer 30 is itself a slightly conductive material as in the prior art as long as it is not doped with Fe or C. Thus, if the thickness of the electron transport layer 30 is unnecessarily increased as in the case where the thickness of the electron transport layer 30 is 1 μm or more, the buffer leakage current can increase. In contrast, in the present embodiment, by setting the thickness of the electron transport layer 30 to be less than 1 μm, warping of the laminate 1 due to the difference in the linear expansion coefficient between the electron transport layer 30 and other layers can be suppressed. Thus, the photolithography accuracy can be improved. Further, in the present embodiment, by setting the thickness of the electron transport layer 30 to be less than 1 μm, the buffer leakage current due to the slight conductivity of GaN itself constituting the electron transport layer 30 can be suppressed.

[0104] Note that the lower limit of the thickness of the electron transport layer 30 is not limited. From the viewpoint of causing the electron transport layer 30 to generate a prescribed 2DEG, the thickness of the electron transport layer 30 is, for example, preferably 100 nm or more.

[0105] In the present embodiment, by improving the crystallinity of the nucleus formation layer 20 and introducing point defects to the main surface 21 of the nucleus formation layer 20 in the later-described heat treatment process S30, the strain of the electron transport layer 30 at the time of growing the electron transport layer 30 on the nucleus formation layer 20 can be relaxed. As a result, in the present embodiment, even if the electron transport layer 30 is not caused to grow three-dimensionally, a high-quality electron transport layer 30 can be grown.

[0106] Here, when the nucleus formation layer 20 is AlN and the electron transport layer 30 is GaN, a large lattice mismatch (about 2.5%) occurs between them, thereby causing strain (lattice strain). Thus, at the time of growing the electron transport layer 30, relaxation of the lattice strain caused by introduction of dislocations is unavoidable.

[0107] In the past, when a GaN layer was caused to grow three-dimensionally to obtain high-quality GaN, by causing dislocations generated at the GaN / AlN interface to converge with each other (by so-called annihilation), the threading dislocation density reaching the upper portion of the GaN layer could be reduced to about 10 8 cm -2 around. The GaN layer thus obtained was in a state where the lattice strain caused by the introduction of dislocations in the growth was relaxed, and thus was in a state of approximately no strain, in contrast to which, the GaN layer was in a state of exhibiting strain (thermal strain) caused by the difference in the thermal expansion coefficient at the time of cooling after the growth at room temperature.

[0108] On the other hand, in the past, when growing GaN layers on AlN layers without three-dimensional growth of the GaN layer, dislocations were introduced into the GaN layer, which mitigated the lattice strain, resulting in a strain-free GaN layer. In this case, the dislocation density of the GaN layer gradually decreased due to the aforementioned pair annihilation as the GaN growth thickness increased. However, the degree of reduction in dislocation density in this case was significantly lower than that when the GaN layer underwent three-dimensional growth. Specifically, when the GaN layer thickness was approximately 1–2 μm, there were 10-1 dislocations. 9 ~10 10 cm -2 Dislocations will remain on the surface of the GaN layer. The resulting GaN layer, due to the introduction of dislocations during growth, experiences lattice strain that is mitigated, resulting in a near-strain-free state. On the other hand, this GaN layer may exhibit thermal strain at room temperature due to the difference in thermal expansion coefficients generated during cooling after growth. However, since this GaN layer has a relatively large number of dislocations, some of the thermal strain is mitigated by the effect of these dislocations, resulting in a smaller residual strain.

[0109] In contrast, in this embodiment, by increasing the crystallinity of the AlN-formed nucleation layer 20 and introducing point defects into the main surface 21 of the nucleation layer 20 during the subsequent heat treatment step S30, lattice strain during the growth of the GaN-formed electron-mobile layer 30 can be suppressed. This suppresses the generation of dislocations at the interface between the electron-mobile layer 30 and the nucleation layer 20 (i.e., the GaN / AlN interface). As a result, although the lattice strain of the growing electron-mobile layer 30 is suppressed, the dislocation density of the electron-mobile layer 30 can still be achieved to 5 × 10⁻⁶ as described later. 8 cm -2 The following should be noted: The electron-mobile layer 30 obtained at this time is in a state of suppressed dislocation generation and near-strain-free during growth. In contrast, at room temperature, it exhibits a state of thermal strain caused by the difference in thermal expansion coefficients generated during the cooling process after growth.

[0110] It should be noted that the strain ε2 (%) in the a-axis direction of the electron mobile layer 30 is, for example, calculated by the following equation (4).

[0111] ε2=(a2-a GaN ) / a GaN ×100···(4)

[0112] Where a2 is the a-axis length of the GaN crystal constituting the electron mobility layer 30, a GaN The a-axis length is the length of the unstrained bulk GaN crystal.

[0113] When the substrate 10 of this embodiment is formed of SiC, the strain ε2 (%) of the electron mobility layer 30 in the a-axis direction (at room temperature of 27°C) is, for example, +0.05% or more and +0.3% or less.

[0114] In this embodiment, by mitigating the lattice strain of the electron-mobile layer 30 during its growth on the high-quality nucleation layer 20, the electron-mobile layer 30 exhibits high crystallinity even when it is thin. Specifically, even if the thickness of the electron-mobile layer 30 is within the aforementioned range, the half-width at half-maximum (WHM) of the (0002) diffraction of GaN, as measured by X-ray rocking curves, is 200 seconds or less, preferably 150 seconds or less, and the half-width at half-maximum (WHM) of the (10-12) diffraction of GaN, as measured by X-ray rocking curves, is 400 seconds or less, preferably 300 seconds or less, more preferably 200 seconds or less, and even more preferably 150 seconds or less.

[0115] In this embodiment, by mitigating the lattice strain of the electron-moving layer 30 during its growth on the high-quality nucleation layer 20, the dislocation density of the electron-moving layer 30 is reduced as described above, even without three-dimensional growth or excessively thick growth. Specifically, even if the thickness of the electron-moving layer 30 is within the aforementioned range, the dislocation density of the main surface 31 of the electron-moving layer 30 is, for example, 5 × 10⁻⁶. 8 cm -2 The following, preferably less than 1×10 8 cm -2 More preferably 7×10 7 cm -2 Therefore, gate leakage when driving semiconductor element 2 can be reduced. It should be noted that the dislocation density of the main surface 31 of the electron mobility layer 30 can be measured, for example, by multiphoton excitation microscopy.

[0116] It should be noted that, since a method without three-dimensional growth is used, the lower limit of the dislocation density on the principal surface 31 of the electron mobility layer 30 can be considered, for example, to be 1 × 10⁻⁶. 7 cm -2 .

[0117] In this embodiment, the electron-mobilizing layer 30 is not grown in three dimensions using the manufacturing method described later, but rather grown on the c-plane (lateral growth), thereby suppressing the incorporation of impurities such as O through the facets other than the c-plane. Specifically, the O concentration in the electron-mobilizing layer 30 is, for example, 1 × 10⁻⁶ throughout the entire electron-mobilizing layer 30. 16 cm -3 In this way, by suppressing the incorporation of O, which becomes an n-type impurity (donor), into the electron mobility layer 30, it is possible to suppress the increase in the concentration of free electrons in the electron mobility layer 30.

[0118] In this embodiment, when the base substrate 10 is a SiC substrate, the thickness of the core formation layer 20 is made greater than 100 nm, thereby suppressing diffusion of Si from the base substrate 10 to the electron transport layer 30. Specifically, the Si concentration in the electron transport layer 30 is, for example, 1 x 1019cm-3or less throughout the entire electron transport layer 30. 16 cm -3 -3or less throughout the entire electron transport layer 30. In this way, by suppressing incorporation of Si, which is an n-type impurity (donor), in the electron transport layer 30, it is possible to suppress an increase in the free electron concentration in the electron transport layer 30.

[0119] In this embodiment, as described above, by suppressing incorporation of Si and O, which are n-type impurities, in the electron transport layer 30, it is not necessary to dope impurities such as Fe and C, which form deep energy levels, into the electron transport layer 30 at a high concentration. Specifically, the Fe concentration and the C concentration in the electron transport layer 30 are, for example, 1 x 1019cm-3or less and 1 x 1019cm-3or less, respectively, throughout the entire electron transport layer 30. 16 cm -3 -3or less throughout the entire electron transport layer 30. In this way, at the time of driving of the semiconductor element 2, it is possible to suppress charging and discharging of impurities that form deep energy levels.

[0120] In this embodiment, by making the electron transport layer 30 undergo lateral growth using a manufacturing method described later, the electron transport layer 30 is made to have good surface flatness. Specifically, the root mean square roughness RMs of a 5 μm square region of the main surface 31 of the electron transport layer 30, which is measured using an atomic force microscope (AFM), is, for example, 1 nm or less, and preferably 0.5 nm or less.

[0121] (Electron supply layer)

[0122] The electron supply layer 40 is configured, for example, in such a manner that a 2DEG is generated in the electron transport layer 30. Specifically, the electron supply layer 40 is formed of a Group III nitride having a wider band gap than GaN that constitutes the electron transport layer 30 and a smaller lattice constant than the lattice constant of GaN. As the Group III nitride that constitutes the electron supply layer 40, for example, AlN, AlGaN, InAlN, or AlInGaN, having a composition formula of AlxGayIn1-x-yN (where 0 < x < 1, 0 < y < 1, and 0 < x + y < 1) can be cited. The electron supply layer 40 is, for example, provided on the electron transport layer 30. The electron supply layer 40 is formed, for example, by making a single crystal of the above-described Group III nitride undergo heteroepitaxial growth on the main surface 31 of the electron transport layer 30. x In y Ga 1-x-y N (where 0 < x < 1, 0 < y < 1, and 0 < x + y < 1). The electron supply layer 40 is, for example, provided on the electron transport layer 30. The electron supply layer 40 is formed, for example, by making a single crystal of the above-described Group III nitride undergo heteroepitaxial growth on the main surface 31 of the electron transport layer 30.

[0123] The electron supply layer 40 has a main surface 41. In the present embodiment, the low-index crystal plane closest to the main surface 41 of the electron supply layer 40 is, for example, a c-plane ((0001) plane, group III element polar plane).

[0124] The thickness of the electron supply layer 40 is, for example, 5 nm or more and 50 nm or less, and is preferably 10 nm or more and 30 nm or less. If the thickness of the electron supply layer 40 is less than 5 nm, the gate leakage current can become large. In contrast, by setting the thickness of the electron supply layer 40 to be 5 nm or more, the gate leakage current can be reduced. Further, by setting the thickness of the electron supply layer 40 to be 10 nm or more, the gate leakage current can be stably reduced. On the other hand, if the thickness of the electron supply layer 40 is more than 50 nm, the threshold voltage can become large and the switching characteristics can deteriorate. In contrast, by setting the thickness of the electron supply layer 40 to be 50 nm or less, the threshold voltage can be set to be equal to or less than a predetermined value, and the switching characteristics can be improved. By setting the thickness of the electron supply layer 40 to be 30 nm or less, the switching characteristics can be stably improved.

[0125] In the present embodiment, the electron supply layer 40 has good surface flatness similarly to the electron transport layer 30. Specifically, the root mean square roughness (RMS) of a 5 μm square region of the main surface 41 of the electron supply layer 40 measured using an atomic force microscope (AFM) is, for example, equal to the root mean square roughness (RMS) of the electron transport layer 30.

[0126] (Capping Layer)

[0127] The capping layer 50 is, for example, configured in such a manner that evaporation of Ga components or In components from the main surface 41 of the electron supply layer 40 is inhibited during cooling after growth. Specifically, the capping layer 50 is, for example, formed of GaN. The capping layer 50 is, for example, provided on the electron supply layer 40. The capping layer 50 can be formed, for example, by hetero-epitaxially growing a single crystal of GaN on the main surface 41 of the electron supply layer 40. By forming the capping layer 50 formed of GaN on the main surface 41 of the electron supply layer 40 as such, for example, in the case where the electron supply layer 40 is formed of AlGaN, evaporation of Ga selectively from the surface of the AlGaN can be inhibited during cooling after growth, and formation of an Al-rich AlGaN layer can be inhibited.

[0128] The thickness of the cover layer 50 is, for example, 1 nm or more and 10 nm or less, and preferably 2 nm or more and 5 nm or less. If the thickness of the cover layer 50 is less than 1 nm, it is difficult to suppress evaporation of the Ga component or the In component. In contrast, by setting the thickness of the cover layer 50 to 1 nm or more, and preferably 2 nm or more, evaporation of the Ga component or the In component can be stably suppressed. On the other hand, if the thickness of the cover layer 50 is more than 10 nm, the current component flowing through the cover layer 50 becomes significant when the semiconductor element 2 is manufactured, and it can hinder the operation of the device. In contrast, by setting the thickness of the cover layer 50 to 10 nm or less, and preferably 5 nm or less, the generation of the current component flowing through the cover layer 50 can be suppressed. Thus, the hindrance of the operation of the device caused by the cover layer 50 can be suppressed.

[0129] In the laminate 1 configured as described above, by thinning the thickness of the electron moving layer 30 as described above, the warpage of the laminate 1 can be reduced. Specifically, the warpage of the laminate 1 per 50.8 mm of length is, for example, 20 μm or less, and preferably 10 μm or less. Thus, the reduction in the photolithography precision caused by the warpage of the laminate 1 can be suppressed. As a result, the manufacturing yield of the semiconductor element 2 can be improved.

[0130] Note that the warpage of the laminate 1 is preferably as small as possible, and is, for example, 0 μm or more.

[0131] (2) Semiconductor Element

[0132] Next, the semiconductor element according to the present embodiment will be described using Figure 2 , for example. Figure 2 is a schematic cross-sectional view illustrating the semiconductor element according to the present embodiment.

[0133] As illustrated in Figure 2 , the semiconductor element 2 according to the present embodiment is manufactured using, for example, the laminate 1 described above, and is configured in the form of a HEMT. Specifically, the semiconductor element 2 has, for example, the base substrate 10, the core formation layer 20, the electron moving layer 30, the electron supply layer 40, the cover layer 50, the gate electrode 61, the source electrode 62, and the drain electrode 63. That is, the semiconductor element 2 has at least a part of the above-described electron moving layer 30 formed of GaN as an operation layer.

[0134] (Electrode)

[0135] The gate electrode 61 is provided on the electron supply layer 40. The gate electrode 61 can be in contact with the electron supply layer 40, or can be provided on the electron supply layer 40 with the cover layer 50 interposed therebetween, for example. The gate electrode 61 is formed of, for example, a multilayer structure of nickel (Ni) and gold (Au) (Ni / Au).

[0136] The source electrode 62 is provided on the electron supply layer 40, for example, with the cap layer 50 interposed therebetween. The source electrode 62 is disposed at a position separated from the gate electrode 61 by a prescribed distance. The source electrode 62 is formed of a multilayer structure of titanium (Ti) and aluminum (Al) (Ti / Al), for example.

[0137] The drain electrode 63 is provided on the electron supply layer 40, for example, with the cap layer 50 interposed therebetween. The drain electrode 63 is disposed at a position separated from the gate electrode 61 by a prescribed distance on the side opposite to the source electrode 62 with the gate electrode 61 interposed therebetween. The drain electrode 63 is formed of a multilayer structure of Ti and Al, similarly to the source electrode 62. Note that, of the source electrode 62 and the drain electrode 63, a multilayer structure of Ni and Au can be stacked on the multilayer structure of Ti and Al.

[0138] (3) Method for manufacturing group III nitride laminate and method for manufacturing semiconductor element

[0139] Next, the method for manufacturing a group III nitride laminate and the method for manufacturing a semiconductor element according to the present embodiment will be described using Figures 1-3 Figure 3 is a flowchart showing the method for manufacturing a group III nitride laminate and the method for manufacturing a semiconductor element according to the present embodiment.

[0140] The method for manufacturing a semiconductor element according to the present embodiment has, for example, a base substrate preparation step S10, a nucleus formation layer formation step S20, a heat treatment step S30, an electron movement layer formation step S40, an electron supply layer formation step S50, a cap layer formation step S60, and an electrode formation step S70.

[0141] (S10: Base substrate preparation step)

[0142] First, a base substrate 10 is prepared. As the base substrate 10, for example, a polytype 4H semi-insulating SiC substrate is prepared.

[0143] (S20: Nucleus formation layer formation step)

[0144] Next, a nucleus formation layer 20 formed of a single crystal of AlN is caused to hetero-epitaxially grow on the base surface 11 of the base substrate 10. The growth of the nucleus formation layer 20 is performed by a hydride vapor phase epitaxy (HVPE) method, for example.

[0145] ​As the Group III (Al) source gas, for example, aluminum monochloride (AlCl) gas or aluminum trichloride (AlCl3) gas is used. The AlCl gas or the AlCl3 gas can be generated by supplying hydrogen chloride (HCl) gas to metallic Al provided in the HVPE apparatus. As the N source gas, for example, ammonia (NH3) gas is used. These source gases can also be supplied after being mixed with a carrier gas obtained using hydrogen (H2) gas, nitrogen (N2) gas, or a mixture thereof.

[0146] At this time, in the present embodiment, the nucleus formation layer 20 is formed in a manner to improve the crystallinity of the nucleus formation layer 20.

[0147] For example, the nucleus formation layer 20 is formed in a manner such that the thickness of the nucleus formation layer 20 is greater than 100 nm and is 1 μm or less, and the half-value width of the (0002) diffraction of AlN measured based on an X-ray rocking curve is 250 seconds or less, and the half-value width of the (10-12) diffraction of AlN measured based on an X-ray rocking curve is 500 seconds or less.

[0148] Preferably, the nucleus formation layer 20 is formed in a manner such that, for example, the thickness of the nucleus formation layer 20 is 200 nm or more and 700 nm or less, and the half-value width of the (0002) diffraction of AlN measured based on an X-ray rocking curve is 200 seconds or less, and the half-value width of the (10-12) diffraction of AlN measured based on an X-ray rocking curve is 400 seconds or less.

[0149] More preferably, the nucleus formation layer 20 is formed in a manner such that, for example, the thickness of the nucleus formation layer 20 is 300 nm or more and 500 nm or less, and the half-value width of the (0002) diffraction of AlN measured based on an X-ray rocking curve is 180 seconds or less, and the half-value width of the (10-12) diffraction of AlN measured based on an X-ray rocking curve is 380 seconds or less.

[0150] As a method for forming such a high-quality nucleus formation layer 20, for example, the crystal growth conditions are controlled. As the crystal growth conditions, for example, at least any one of the growth temperature, the V / III ratio, the growth rate, and the growth pressure is appropriately controlled. Thereby, the high-quality nucleus formation layer 20 can be grown. Note that the "V / III ratio" referred to here means the ratio of the supply amount (partial pressure) of the Group V (N) source gas to the supply amount (partial pressure) of the Group III (Al) source gas.

[0151] Specifically, for example, the crystal growth conditions are set as follows.

[0152] Growth temperature: 900°C or more and 1300°C or less

[0153] V / III ratio: 0.2 or more and 200 or less

[0154] Growth rate: 0.5 nm / min or more and 3000 nm / min or less

[0155] Growth pressure: 0.9 atm or more and 1.3 atm or less

[0156] At this time, it is preferable to set the pressure at the time of crystal growth (growth pressure) to 0.9 atm or more and 1.3 atm or less around the atmospheric pressure as described above. By setting the growth pressure to 0.9 atm or more, that is, by growing at a higher pressure than when a reduced pressure growth device is used, a high-quality nucleus formation layer 20 can be easily grown. On the other hand, even if the growth pressure is made greater than 1.3 atm, there is nothing wrong from the viewpoint of crystal growth, but a growth device that withstands such high pressure needs a pressure-resistant structure, so from the viewpoint of manufacturing cost, it is preferable to set the growth pressure to 1.3 atm or less.

[0157] Note that at this time, in order to prevent the adhesion of AlN on the nozzle of a gas supply pipe for introducing various gases into the growth chamber of the HVPE device, HCl gas can be circulated. At this time, the ratio of the supply amount of HCl gas with respect to the supply amount of AlCl gas or AlCl3 gas is set to, for example, 0.1 or more and 100 or less.

[0158] Further, as a method for forming the high-quality nucleus formation layer 20 as described above, for example, heat treatment (annealing treatment) can be performed in an atmosphere containing N2 gas after the nucleus formation layer 20 is grown. At this time, for example, it is preferable to set the heat treatment temperature to, for example, 1400°C or more and 1700°C or less.

[0159] By controlling the crystal growth conditions as described above, the crystallinity of the nucleus formation layer 20 can be improved.

[0160] Note that when the crystallinity of the nucleus formation layer 20 obtained as in the present embodiment is high, at the time of cooling after the nucleus formation layer formation step S20 or at the time of cooling after the heat treatment step S30 described later, the nucleus formation layer 20 is stretched due to the difference in the linear expansion coefficient between the base substrate 10 and the nucleus formation layer 20. On the other hand, when the crystallinity of the nucleus formation layer 20 is low as in the past, that is, when the nucleus formation layer 20 contains a large amount of dislocations, thermal stress is relaxed due to the presence of dislocations, so the strain remaining around room temperature becomes small (less than +0.05%).

[0161] (S30: Heat treatment step)

[0162] Next, the nucleation layer 20 is subjected to heat treatment. This heat treatment step S30 is performed continuously in the same growth chamber of the HVPE apparatus after the nucleation layer formation step S20, for example, without lowering the temperature. Note that the heat treatment step S30 can also be performed in another apparatus after the nucleation layer formation step S20.

[0163] In the present embodiment, the heat treatment of the nucleation layer 20 is performed in an atmosphere containing H2 gas, for example. Note that the H2 gas can be mixed with a non-active gas such as N2 gas or argon (Ar gas) and then supplied.

[0164] By performing the heat treatment in an atmosphere containing H2 gas, the main surface 21 of the nucleation layer 20 can be modified so that the strain of the electron transport layer 30 grown on the main surface 21 of the nucleation layer 20 is relaxed. The mechanism of the strain relaxation of the electron transport layer 30 is not clear, but the following mechanism can be considered, for example. That is, in the heat treatment step S30, by containing H2 gas in the atmosphere, point defects are introduced into the AlN crystal constituting the nucleation layer 20. Specifically, N atoms in the AlN are bonded to H on the surface, form NH3, and are detached. Thus, a large number of N vacancies are formed in the AlN, which function as atomic-sized vacancies. As a result, it is considered that the strain of the electron transport layer 30 grown on the nucleation layer 20 can be relaxed.

[0165] At this time, it is preferable to perform the heat treatment of the nucleation layer 20 in an atmosphere substantially free of NH3 gas. The "substantially free of NH3 gas" referred to here means that the partial pressure of NH3 gas in the growth chamber is less than 1% with respect to the total pressure, for example. Specifically, this step is performed in such a manner that NH3 gas is not supplied to the growth chamber, for example. Here, when the heat treatment of the nucleation layer 20 is performed in an atmosphere containing NH3 gas, it is difficult to sufficiently introduce point defects into the AlN crystal constituting the nucleation layer 20. Thus, it can be impossible to sufficiently relax the strain of the electron transport layer 30 grown on the nucleation layer 20. In contrast, in the present embodiment, by performing the heat treatment of the nucleation layer 20 in an atmosphere substantially free of NH3 gas, it is possible to sufficiently introduce point defects into the AlN crystal constituting the nucleation layer 20.

[0166] Note that when the heat treatment step S30 is performed continuously in the same growth chamber of the HVPE apparatus after the nucleation layer formation step S20, the NH3 gas introduced in the nucleation layer formation step S20 can remain in the growth chamber. Therefore, before the heat treatment step S30 is performed, it is preferable to exhaust (or replace) the gas in the growth chamber.

[0167] Note that, as described above, it can be considered that, in the heat treatment step S30, N atoms in the AlN bond with H on the surface, form NH3, and are detached, but the NH3 generated by the detachment is extremely small. Therefore, the NH3 gas partial pressure in the growth chamber does not become 1% or more of the total pressure due to the detached NH3.

[0168] Further, at this time, it is preferable to set the heat treatment temperature to, for example, 900°C or higher and 1300°C or lower. If the heat treatment temperature is less than 900°C, the principal surface 21 of the nucleus formation layer 20 is difficult to be modified. In contrast, by setting the heat treatment temperature to 900°C or higher, the principal surface 21 of the nucleus formation layer 20 can be sufficiently modified. On the other hand, if the heat treatment temperature exceeds 1300°C, the principal surface 21 of the nucleus formation layer 20 can be decomposed. In contrast, by setting the heat treatment temperature to 1300°C or lower, decomposition of the principal surface 21 of the nucleus formation layer 20 can be suppressed.

[0169] Further, at this time, it is preferable to set the heat treatment time to, for example, 10 minutes or more and 120 minutes or less. If the heat treatment time is less than 10 minutes, the principal surface 21 of the nucleus formation layer 20 is difficult to be modified. In contrast, by setting the heat treatment time to 10 minutes or more, the principal surface 21 of the nucleus formation layer 20 can be sufficiently modified. On the other hand, if the heat treatment time exceeds 120 minutes, the flatness of the principal surface 21 of the nucleus formation layer 20 can be decreased. In contrast, by setting the heat treatment time to 120 minutes or less, decrease in the flatness of the principal surface 21 of the nucleus formation layer 20 can be suppressed.

[0170] Further, it is more preferable to set the heat treatment time to, for example, 30 minutes or more and 90 minutes or less, and most preferably to 60 minutes. By appropriately controlling the heat treatment time as such, the surface state of the principal surface 21 of the nucleus formation layer 20 can be maintained flat, and an appropriate amount of point defects can be introduced into the principal surface 21 of the nucleus formation layer 20. Thus, the crystallinity of the electron movement layer 30 formed on the nucleus formation layer 20 can be more stably improved.

[0171] (S40: Electron Movement Layer Formation Step)

[0172] Next, the electron movement layer 30 formed of a GaN single crystal is made to hetero-epitaxially grow on the principal surface 21 of the nucleus formation layer 20 on which the heat treatment has been performed. The growth of the electron movement layer 30 is performed by, for example, a metal organic vapor phase epitaxy (MOVPE) method.

[0173] As the Group III (Ga) source gas, for example, trimethylgallium (Ga(CH3)3, TMG) gas is used. As the N source gas, for example, NH3gas is used. These source gases can be supplied after being mixed with a carrier gas obtained using hydrogen (H2) gas, nitrogen (N2) gas, or a mixed gas thereof.

[0174] Note that in this embodiment, the base surface 11 of the base substrate 10 is covered with the nucleus formation layer 20 formed of AlN. Thus, it is possible to start the operation from the supply of NH3gas into the film formation chamber of the MOVPE device. As a result, it is possible to omit the pre-baking of the film formation chamber. The effect of this will be described later.

[0175] In this embodiment, as described above, by improving the crystallinity of the nucleus formation layer 20 in the nucleus formation layer formation step S20 and introducing point defects into the main surface 21 of the nucleus formation layer 20 in the heat treatment step S30, it is possible to relax the lattice strain of the electron transport layer 30 when the electron transport layer 30 is grown on the nucleus formation layer 20. Thus, it is possible to thin the thickness of the electron transport layer 30 and form the electron transport layer 30 having high crystallinity.

[0176] Specifically, for example, the electron transport layer 30 can be formed in such a manner that the thickness of the electron transport layer 30 is less than 1 μm, and the half-value width of (0002) diffraction of GaN measured based on an X-ray rocking curve becomes 200 seconds or less, and the half-value width of (10-12) diffraction of GaN measured based on an X-ray rocking curve becomes 400 seconds or less.

[0177] Further, in this embodiment, the electron transport layer 30 is not caused to grow three-dimensionally, but is caused to grow laterally (two-dimensionally). That is, in the electron transport layer 30, no facet other than the c-plane is generated, but the electron transport layer 30 is caused to grow with only the c-plane as a growth surface (laminar growth).

[0178] As the crystal growth conditions for causing the electron transport layer 30 to grow laterally, for example, at least any one of the growth temperature, the growth rate, and the growth pressure is appropriately controlled.

[0179] Specifically, the growth temperature of the electron transport layer 30 is set to be higher than the typical crystal growth temperature of GaN, for example, to be 1080°C or higher and 1200°C or lower, and preferably to be 1100°C or higher and 1150°C or lower.

[0180] Further, the growth rate in the electron transport layer formation step S40 is set to be, for example, 10 nm / minute or higher and 30 nm / minute or lower.

[0181] Further, the growth pressure in the electron transport layer formation step S40 is set to be, for example, 0.01 atm or higher and 0.5 atm or lower.

[0182] Note that, in the MOVPE method, even if C (carbon) is not intentionally introduced, C from the organic metal gas as the Group III raw material can be mixed into the growing film. However, in the present embodiment, by setting the V / III ratio in the electron transport layer forming step S40 to, for example, 3000 or more under the above conditions under which the electron transport layer 30 does not undergo three-dimensional growth, the mixing of C into the electron transport layer 30 can be made 1 x 10 16 cm -3 or less.

[0183] In the present embodiment, as described above, by relaxing the strain of the electron transport layer 30 grown on the high-quality nucleus formation layer 20, even if the electron transport layer 30 does not undergo three-dimensional growth and is not grown thick, the dislocation density of the electron transport layer 30 can be reduced. Specifically, for example, the electron transport layer 30 can be formed so that the thickness of the electron transport layer 30 is less than 1 μm and the dislocation density of the main surface 31 of the electron transport layer 30 is 5 x 10 8 cm -2 or less.

[0184] In the present embodiment, as described above, by not making the electron transport layer 30 undergo three-dimensional growth but making it undergo lateral growth, the mixing of impurities such as O via small faces other than the c-plane can be suppressed. Specifically, for example, the electron transport layer 30 can be formed so that the O concentration in the electron transport layer 30 is 1 x 10 16 cm -3 or less throughout the entire electron transport layer 30.

[0185] In the present embodiment, as described above, by suppressing the mixing of O and the like that become n-type impurities in the electron transport layer 30, Fe and C and the like that are impurities that form deep energy levels are not intentionally doped into the electron transport layer 30. Specifically, for example, the electron transport layer 30 can be formed so that the Fe concentration and the C concentration in the electron transport layer 30 are 1 x 10 16 cm -3 or less, respectively.

[0186] In the present embodiment, as described above, since the thickness of the electron transport layer 30 is thin, the growth rate can be slowed down, for example, to 30 nm / minute or less. Here, there is a tendency that the faster the growth rate, the more the amount of mixing of C into the growing film increases. Thus, in the present embodiment, by slowing down the growth rate as described above, a high-purity electron transport layer 30 can be easily obtained. That is, even if the MOVPE method is used, as described above, the C concentration can be easily made 1 x 10 16 cm -3The growth time is slightly longer, but the thickness of the electron transport layer 30 is thin, so the reduction in productivity can be suppressed.

[0187] (S50: Electron supply layer formation step)

[0188] Next, an electron supply layer 40 formed of a single crystal of a Group III nitride having a wider band gap than GaN that constitutes the electron transport layer 30 is grown heteroepitaxially on the main surface 31 of the electron transport layer 30. The growth of the electron supply layer 40 is performed by, for example, the MOVPE method. Therefore, the electron supply layer formation step S50 is preferably performed continuously in the growth chamber of the same MOVPE apparatus after the electron transport layer formation step S40, for example.

[0189] In the present embodiment, for example, the electron supply layer 40 formed of a single crystal of AlN, AlGaN, InAlN, or AlInGaN is grown.

[0190] Note that, as the Al source gas, for example, trimethylaluminum (Al(CH3)3, TMA) gas is used. As the In source gas, for example, trimethylindium (In(CH3)3, TMI) gas is used. As the other gases, the same gases as in the electron transport layer formation step S40 are used.

[0191] Further, the thickness of the electron supply layer 40 is set to be, for example, 5 nm or more and 50 nm or less.

[0192] (S60: Cap layer formation step)

[0193] Next, a cap layer 50 formed of GaN is grown on the main surface 41 of the electron supply layer 40.

[0194] The growth of the cap layer 50 is not particularly limited and is performed by, for example, the MOVPE method. At this time, the cap layer formation step S60 is also preferably performed continuously from the electron supply layer formation step S50.

[0195] The thickness of the cap layer 50 is set to be, for example, 1 nm or more and 10 nm or less.

[0196] The layered product 1 of the present embodiment is manufactured by the above operations.

[0197] (S70: Electrode formation step)

[0198] After the layered product 1 is manufactured, a gate electrode 61, a source electrode 62, and a drain electrode 63 are formed above the electron supply layer 40.

[0199] Specifically, by sequentially performing resist patterning, prescribed metal film formation, and peeling, a source electrode 62 and a drain electrode 63 formed of Ti / Al are formed in the prescribed region on the cover layer 50. Thereafter, the laminate 1 is subjected to heat treatment (for example, 650°C, 3 minutes) in an N2 atmosphere. Thus, the source electrode 62 and the drain electrode 63 are ohmically joined to the cover layer 50, respectively.

[0200] Next, resist patterning is performed in such a manner that the formation region of the lower gate electrode 61 becomes an opening in plan view, and the cover layer 50 in the formation region of the gate electrode 61 is etched with the resist film as a mask. As the etching method of the cover layer 50, for example, RIE (Reactive Ion Etching), inductively coupled plasma etching, or electrochemical etching can be used.

[0201] After the cover layer 50 in the prescribed region is etched, prescribed metal film formation and peeling are sequentially performed, whereby the gate electrode 61 is formed in the prescribed region of the electron supply layer 40. Thereafter, the laminate 1 is subjected to heat treatment (for example, 450°C, 10 minutes) in an N2 atmosphere.

[0202] As described above, after the gate electrode 61, the source electrode 62, and the drain electrode 63 are formed, the laminate 1 is cut, and divided into chips of a prescribed size.

[0203] The semiconductor element 2 of the present embodiment is manufactured by the above operations.

[0204] (4) Effects obtained by the present embodiment

[0205] According to the present embodiment, one or more of the effects shown below can be obtained.

[0206] (a) In the present embodiment, the thickness of the core formation layer 20 formed of AlN is greater than 100 nm and is 1 μm or less, the half-value width of the (0002) diffraction of AlN measured based on an X-ray rocking curve is 250 seconds or less, and the half-value width of the (10-12) diffraction of AlN measured based on an X-ray rocking curve is 500 seconds or less. In this way, by improving the crystallinity of the core formation layer 20, the crystallinity of the electron movement layer 30 formed on the core formation layer 20 can be improved. As a result, the characteristics of the semiconductor element 2 can be improved.

[0207] (b) In this embodiment, by increasing the crystallinity of the nucleus formation layer 20 and introducing point defects into the main surface 21 of the nucleus formation layer 20 in the heat treatment step S30, the strain of the electron transport layer 30 grown on the nucleus formation layer 20 can be relaxed. That is, by growing the electron transport layer 30 on the main surface 21 of the nucleus formation layer 20 having high crystallinity, the electron transport layer 30 can be grown in a state where the crystal axes (c-axes) are uniform. Further, by introducing point defects into the main surface 21 of the nucleus formation layer 20 in the heat treatment step S30, the region where the point defects are introduced in the nucleus formation layer 20 can function as a stress buffer region that relaxes the stress generated between the nucleus formation layer 20 and the electron transport layer 30. As a result, the strain of the electron transport layer 30 can be relaxed.

[0208] (c) In this embodiment, by relaxing the strain of the electron transport layer 30 grown on the high-quality nucleus formation layer 20, the crystallinity of the electron transport layer 30 can be improved even if the thickness of the electron transport layer 30 is thin. Specifically, the thickness of the electron transport layer 30 is less than 1 μm, the half-value width of (0002) diffraction of GaN measured based on an X-ray rocking curve is 200 seconds or less, and the half-value width of (10-12) diffraction of GaN measured based on an X-ray rocking curve is 400 seconds or less. In this way, by improving the crystallinity of the electron transport layer 30, the mobility of the electron transport layer 30 can be improved, and the degradation of the gate electrode can be suppressed, and the reliability of the element can be improved.

[0209] (d) In this embodiment, by relaxing the strain of the electron transport layer 30 grown on the high-quality nucleus formation layer 20, the dislocation density of the electron transport layer 30 can be reduced even if the electron transport layer 30 does not undergo three-dimensional growth and is not grown thick. Specifically, even if the thickness of the electron transport layer 30 is within the above range, the dislocation density of the main surface 31 of the electron transport layer 30 can be 5 x 10 8 cm -2 or less. Thus, the degradation of the gate electrode when the semiconductor element 2 is driven can be suppressed. As a result, the reliability of the semiconductor element 2 as a HEMT can be improved.

[0210] (e) In this embodiment, by not causing the electron transport layer 30 to undergo three-dimensional growth but causing it to undergo lateral growth, the mixing of impurities such as O through small faces other than the c-plane can be suppressed.

[0211] Specifically, the O concentration in the electron transport layer 30 can be set to 1 x 10 16 cm -3 or less throughout the entire electron transport layer 30.

[0212] Further, in the present embodiment, by setting the thickness of the nucleus formation layer 20 to be greater than 100 nm, diffusion of impurities from the base substrate 10 to the electron transport layer 30 through the nucleus formation layer 20 can be suppressed. Specifically, when the base substrate 10 is a SiC substrate, diffusion of Si from the base substrate 10 to the electron transport layer 30 can be suppressed. Thus, the Si concentration in the electron transport layer 30 can be set to 1 x 1018cm-3or less throughout the entire electron transport layer 30. 16 cm -3 Hereinafter.

[0213] As such, by suppressing the incorporation of Si and O, which are n-type impurities, in the electron transport layer 30, the increase in the free electron concentration in the electron transport layer 30 can be suppressed. By suppressing the increase in the free electron concentration in the electron transport layer 30, the increase in the buffer leakage current can be suppressed. By suppressing the increase in the buffer leakage current when pinching the 2DEG of the second layer, the decrease in the On / Off current ratio can be suppressed. Further, by suppressing the increase in the buffer leakage current, the leakage current between elements can be suppressed, and the operation interference between adjacent elements can be suppressed.

[0214] (f) In the present embodiment, by suppressing the incorporation of Si and O, which are n-type impurities, in the electron transport layer 30, it is not necessary to dope impurities such as Fe and C, which form deep energy levels, into the electron transport layer 30 at a high concentration. Specifically, the Fe concentration and the C concentration in the electron transport layer 30 are 1 x 1018cm-3or less, respectively. 16 cm -3 Hereinafter. Thus, the charging and discharging of impurities that form deep energy levels can be suppressed at the time of driving the semiconductor element 2. That is, the generation of hysteresis accompanying the charging and discharging of impurities can be suppressed. As a result, the semiconductor element 2 can be caused to operate stably.

[0215] As such, in the present embodiment, stable operation achieved by suppressing the buffer leakage current and suppressing hysteresis can be both achieved.

[0216] (g) In the present embodiment, the base surface 11 of the base substrate 10 is covered with the nucleus formation layer 20 formed of AlN at the start of the electron transport layer formation process S40. Thus, in the electron transport layer formation process S40, the operation of supplying NH3 gas into the film formation chamber of the vapor phase epitaxy apparatus can be started. That is, even if the operation of supplying NH3 gas is started, the base surface 11 of the base substrate 10 formed of SiC can be suppressed from being deteriorated into silicon nitride (SiN) that hinders the crystal growth of Group III nitride.

[0217] By starting the operation from the supply of NH3 gas into the film formation chamber, it is possible to deteriorate Ga adhering in the growth device into GaN, to suppress the vaporization of the Ga, and to suppress the adhesion of Ga to the base surface 11 of the base substrate 10. In other words, it is possible to omit the preheating of the film formation chamber of the vapor phase epitaxy device for removing Ga adhering in the growth device. As a result, it is possible to greatly shorten the manufacturing time of the laminate 1 and to greatly improve the productivity of the laminate 1.

[0218] <Second Embodiment of the Invention>

[0219] Next, the second embodiment of the present invention will be described.

[0220] In the above first embodiment, the case where the laminate 1 has at least the electron transport layer 30 on the nucleus formation layer 20 was described, but the present invention is not limited to this case. The constitution of the laminate 1 can be changed as in the following embodiments.

[0221] Hereinafter, only the elements different from those of the above embodiments will be described, the same symbols will be attached to the elements substantially the same as those described in the above embodiments, and the description thereof will be omitted.

[0222] (1) Group III Nitride Laminate

[0223] Use Figure 4 of the Group III Nitride Laminate Described in the Embodiment. Figure 4 is a schematic cross-sectional view showing the Group III Nitride Laminate described in the Embodiment.

[0224] As shown in Figure 4 , the laminate 1 of the present embodiment has, for example, the base substrate 10 and the nucleus formation layer 20. In other words, the laminate 1 of the present embodiment is the same as the laminate 1 of the first embodiment except that it does not have the electron transport layer 30, the electron supply layer 40, and the cap layer 50.

[0225] The nucleus formation layer 20 has high crystallinity as with the nucleus formation layer 20 of the above first embodiment. That is, the nucleus formation layer 20 has, for example, a thickness of more than 100 nm and 1 μm or less, a half-value width of (0002) diffraction of AlN based on X-ray rocking curve measurement of 250 seconds or less, and a half-value width of (10-12) diffraction of AlN based on X-ray rocking curve measurement of 500 seconds or less.

[0226] The nucleus formation layer 20 has, for example, a main surface 21 for forming the electron movement layer 30 formed of GaN. The main surface 21 of the nucleus formation layer 20 is subjected to, for example, a heat treatment process S30 to introduce point defects. That is, the main surface 21 of the nucleus formation layer 20 is capable of growing the electron movement layer 30 in a manner in which the strain of the electron movement layer 30 is relaxed.

[0227] That is, the main surface 21 of the nucleus formation layer 20 is configured in a manner in which the electron movement layer 30 having high crystallinity can be grown even if the thickness of the electron movement layer 30 is thin. Specifically, the main surface 21 of the nucleus formation layer 20 is configured, for example, in a manner in which the electron movement layer 30 can be grown in a manner in which the thickness of the electron movement layer 30 is less than 1 μm and the half-value width of (0002) diffraction measured based on an X-ray rocking curve is 200 seconds or less and the half-value width of (10-12) diffraction measured based on the X-ray rocking curve is 400 seconds or less.

[0228] Further, the main surface 21 of the nucleus formation layer 20 is configured in a manner in which the electron movement layer 30 can be grown in a manner in which the dislocation density is lowered even if the thickness of the electron movement layer 30 is thin. Specifically, the main surface 21 of the nucleus formation layer 20 is configured, for example, in a manner in which the electron movement layer 30 can be grown in a manner in which the thickness of the electron movement layer 30 is less than 1 μm and the dislocation density of the main surface 31 of the electron movement layer 30 is 5 x 10 8 cm -2 The electron movement layer 30 is grown in the following manner.

[0229] (2) Effects obtained by the present embodiment

[0230] In the present embodiment, even if the laminate 1 having only the base substrate 10 and the nucleus formation layer 20 is provided to the manufacturer of the semiconductor element 2 by the manufacturer who manufactures the laminate 1, the manufacturer of the semiconductor element 2 can easily grow the electron movement layer 30 and the like having high quality. As a result, the semiconductor element 2 having good device characteristics can be easily manufactured.

[0231] <Other Embodiments>

[0232] The embodiments of the present application are specifically described above. However, the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present application. Note that the "above-described embodiments" include the first embodiment and the second embodiment.

[0233] In the above embodiment, the case where the base substrate 10 is a SiC substrate is described, but the base substrate 10 can be a sapphire substrate. Even in this case, by the above manufacturing method, the strain of the electron moving layer 30 can be relaxed. However, in this case, the strain amount of each layer is different from that of the above embodiment. Specifically, the strain amount ε1 (%) in the a-axis direction of the nucleus formation layer 20 is, for example, -0.5% or more and -0.1% or less (i.e., compressive strain). The strain amount ε2 (%) in the a-axis direction of the electron moving layer 30 is, for example, -0.2% or more and +0.2% or less.

[0234] In the above embodiment, the case where the covering layer 50 is provided is described, but the covering layer 50 can not be provided.

[0235] In the above embodiment, the case where the covering layer 50 is provided is described, but the covering layer 50 can not be provided.

[0236] In the above embodiment, the case where the semiconductor element 2 is configured in the so-called MES gate (Metal-Semiconductor) type in which the semiconductor layer such as the electron supply layer 40 is in direct contact with the gate electrode 61 is described, but the semiconductor element 2 can be configured in the so-called MIS gate (Metal-Insulator-Semiconductor) type in which an insulating layer formed of silicon oxide (SiO2), aluminum oxide (Al2O3), or the like is interposed between the semiconductor layer such as the electron supply layer 40 and the gate electrode 61.

[0237] In the above embodiment, the case where the growth of the nucleus formation layer 20 is performed by the HVPE method is described, but the growth of the nucleus formation layer 20 can be performed by the MOVPE method.

[0238] In the above embodiment, the case where the growth of the electron moving layer 30 is performed by the MOVPE method is described, but the growth of the electron moving layer 30 can be performed by the HVPE method.

[0239] In the above embodiment, the case where the nucleation layer formation step S20 and the heat treatment step S30 are performed in the HVPE apparatus, and then the electron transport layer formation step S40 is performed in another MOVPE apparatus is described, but the present application is not limited to this case. As a modification, the nucleation layer 20 may, for example, have a first AlN layer and a second AlN layer, and the nucleation layer formation step S20 may, for example, have a first AlN layer formation step and a second AlN layer formation step. Here, as in the above embodiment, in particular, when the nucleation layer formation step S20 and the heat treatment step S30 are performed in different apparatuses from the electron transport layer formation step S40, there is a concern that impurities will adhere to the main surface 21 of the nucleation layer 20 before the electron transport layer 30 is formed. In contrast, in the above modification, by dividing the nucleation layer formation step S20 into the first AlN layer formation step and the second AlN layer formation step, it is possible to first perform the first AlN layer formation step in the HVPE apparatus, and then perform the second AlN layer formation step, the heat treatment step S30, and the electron transport layer formation step S40 in the same MOVPE apparatus. Thus, it is possible to suppress the adhesion of impurities to the main surface of the second AlN layer before the electron transport layer 30 is formed, and it is possible to suppress the contamination of the electron transport layer 30. Note that the thickness of the second AlN layer in the modification is, for example, 10 nm or more and 200 nm or less.

[0240] Embodiment

[0241] Hereinafter, various experimental results for verifying the effects of the present application will be described.

[0242] (1) Experiment 1 (1-1) Production of Group III Nitride Layer Stack

[0243] A plurality of stacks in which the thickness of the nucleation layer was different were produced under the following conditions.

[0244] [Production Conditions for Stacks] (Substrate)

[0245] Material: SiC (semi-insulating)

[0246] Diameter: 2 inches

[0247] Thickness: 400 μm

[0248] Low-index crystal plane closest to the substrate surface: c-plane (no pattern processing of the substrate surface was performed)

[0249] Polytype: 4H (nucleation layer)

[0250] Material: AlN

[0251] Growth method: HVPE method

[0252] Growth temperature: 1020°C

[0253] Growth stress: 0.987 atm (100 kPa)

[0254] AlCl partial pressure: 0.8 kPa

[0255] V / III ratio: 50

[0256] Growth rate: 100 nm / min

[0257] Thickness: Varies within the range of approximately 100nm and above, but below 1400nm.

[0258] (Heat treatment process)

[0259] Atmosphere: H2 gas (partial pressure of NH3 gas relative to total pressure is less than 1%)

[0260] Heat treatment temperature: 1220℃

[0261] Heat treatment time: 60 minutes

[0262] (1-2) Evaluation (X-ray swing curve measurement)

[0263] The X-ray rocking curves of AlN (0002) diffraction and AlN (10-12) diffraction were measured for the laminates of Experiment 1 above. The half-width at half maximum (FWHM) of AlN (0002) diffraction and the half-width at half maximum (FWHM) of AlN (10-12) diffraction were then determined.

[0264] (1-3) Results

[0265] use Figure 5 The results of the X-ray rocking curve measurement in Experiment 1 are explained. Figure 5 This is a graph showing the half-widths of the (0002) diffraction and (10-12) diffraction of AlN in Experiment 1 relative to the thickness of the AlN layer.

[0266] like Figure 5 As shown, when plotting the half-widths of the (0002) diffraction and (10-12) diffraction of AlN based on X-ray rocking curves relative to the thickness of the AlN layer as the nucleation layer obtained by the above manufacturing method, the half-widths of the X-ray diffraction of AlN show a tendency to bulge downwards.

[0267] It can be confirmed that when the thickness of the AlN layer, which serves as the nucleation layer, is greater than 100 nm and less than 1 μm, the half-width of the (0002) diffraction of AlN, as measured by X-ray rocking curve, is less than 250 seconds, and the half-width of the (10-12) diffraction of AlN, as measured by X-ray rocking curve, is less than 500 seconds.

[0268] It was confirmed that when the thickness of the AlN layer as the nucleus formation layer was 200 nm or more and 700 nm or less, the half value width of (0002) diffraction of AlN measured based on X-ray rocking curve was 200 seconds or less, and the half value width of (10-12) diffraction of AlN measured based on X-ray rocking curve was 400 seconds or less.

[0269] It was confirmed that when the thickness of the AlN layer as the nucleus formation layer was 300 nm or more and 500 nm or less, the half value width of (0002) diffraction measured based on X-ray rocking curve was 180 seconds or less, and the half value width of (10-12) diffraction measured based on X-ray rocking curve was 380 seconds or less.

[0270] (2) Experiment 2 (2-1) Production of Group III Nitride Laminate

[0271] Using the laminate of Experiment 1, in Experiment 2, a plurality of laminates in which the thickness of the nucleus formation layer and the thickness of the electron movement layer were different were produced under the following conditions.

[0272] [Production conditions of laminate] (substrate, nucleus formation layer, and heat treatment conditions)

[0273] The same as Experiment 1.

[0274] (Electron movement layer)

[0275] Material: GaN

[0276] Growth method: MOVPE method

[0277] Growth conditions: The following lateral growth conditions

[0278] Growth temperature: 1120°C

[0279] Growth pressure: 0.4 atm

[0280] TMG flow rate: 50 sccm

[0281] V / III ratio: 5000

[0282] Growth rate: 20 nm / minute

[0283] Note that there was no intentional impurity doping.

[0284] Thickness: Changed in the range of about 100 nm or more and 2800 nm or less.

[0285] (2-2) Evaluation (X-ray rocking curve measurement)

[0286] The X-ray rocking curves of GaN (0002) diffraction and GaN (10-12) diffraction were measured for the laminates in Experiment 2 above. The half-width at half maximum (FWHM) of GaN (0002) diffraction and GaN (10-12) diffraction were then determined.

[0287] (Observations based on multiphoton excitation microscopy)

[0288] Using multiphoton excitation microscopy, the main face of the electron supply layer was observed in a stack in which the thickness of the nucleation layer formed by AlN was set to be greater than 100 nm and less than 1 μm, and the thickness of the electron supply layer formed by GaN was set to be greater than 100 nm and less than 1 μm.

[0289] (2-3) Results (X-ray rocking curve determination)

[0290] use Figure 6 The results of the X-ray rocking curve measurement in Experiment 2 are explained. Figure 6 This is a graph showing the range of AlN layer thickness and GaN layer thickness when the half-widths of GaN's (0002) diffraction and (10-12) diffraction meet the specified conditions in Experiment 2. Figure 6 In the diagram, within the range enclosed by solid lines, the outermost range represents the range where the half-width of GaN's (0002) diffraction is less than 200 seconds and the half-width of GaN's (10⁻¹²) diffraction is less than 400 seconds. The middle range represents the range where the half-width of GaN's (0002) diffraction is less than 200 seconds and the half-width of GaN's (10⁻¹²) diffraction is less than 300 seconds. The innermost range represents the range where the half-width of GaN's (0002) diffraction is less than 150 seconds and the half-width of GaN's (10⁻¹²) diffraction is less than 150 seconds.

[0291] like Figure 6 As shown, when the thickness of the GaN layer, which serves as the electron mobility layer, is a specified value, the X-ray diffraction half-width of GaN depends on the thickness of the AlN layer, which serves as the nucleation layer. That is, it can be confirmed that as the thickness of the AlN layer approaches the thickness at which the X-ray diffraction half-width of AlN becomes minimal, the crystallinity of the GaN layer increases.

[0292] Further, it was confirmed that when the thickness of the GaN layer as the electron moving layer was about 2600 nm or less, the half-value width of the (0002) diffraction of GaN measured based on the X-ray rocking curve became 200 seconds or less and the half-value width of the (10-12) diffraction of GaN measured based on the X-ray rocking curve became 400 seconds or less in the GaN layer as the electron moving layer, when the thickness of the AlN layer as the core forming layer was about 300 nm at which the half-value width of the X-ray diffraction of AlN became extremely small.

[0293] From these results, it was confirmed that if the thickness of the AlN layer as the core forming layer was optimized in a manner in which the crystallinity of AlN was increased, the electron moving layer could be grown in such a manner that the thickness of the GaN layer as the electron moving layer was less than 1 μm and the half-value width of the (0002) diffraction of GaN measured based on the X-ray rocking curve became 200 seconds or less and the half-value width of the (10-12) diffraction of GaN measured based on the X-ray rocking curve became 400 seconds or less.

[0294] (dislocation density)

[0295] From the results of observation using the multiphoton excitation microscope, it was confirmed that in a laminate in which the thickness of the core forming layer formed of AlN was set to be greater than 100 nm and 1 μm or less and the thickness of the electron supply layer formed of GaN was set to be 100 nm or more and less than 1 μm, the dislocation density of the main surface of the electron supply layer was 5 x 10 8 cm -2 or less.

[0296] (3) Experiment 3 (3-1) Production of Semiconductor Element

[0297] In Experiment 3, the semiconductor elements of the examples and Comparative Examples 1 to 3 were produced under the following conditions.

[0298] Hereinafter, the structures of the semiconductor elements of the examples and Comparative Examples 1 to 3 will be described using Figure 7A , Figure 8A , Figure 9A , and Figure 10A . Figure 7A , Figure 8A , Figure 9A , and Figure 10A are schematic cross-sectional views showing the semiconductor elements of the examples and Comparative Examples 1 to 3 of Experiment 3. Note that the scales of the above drawings are not unified.

[0299] [Production Conditions of Semiconductor Element of Example] (Base Substrate, Core Forming Layer, Heat Treatment Conditions, and Electron Moving Layer)

[0300] The same as in Experiment 2.

[0301] That is, the growth conditions of the electron transport layer are set to be undoped and to cause lateral growth.

[0302] wherein,

[0303] Thickness of the nucleation layer (AlN layer): 300 nm

[0304] Thickness of the electron transport layer (GaN layer): 400 nm (electron supply layer)

[0305] Composition: Al 0.25 Ga 0.75 N

[0306] Growth method: MOVPE method

[0307] Thickness: 25 nm (capping layer)

[0308] Material: GaN

[0309] Growth method: MOVPE method

[0310] Thickness: 2.5 nm (electrode)

[0311] Gate electrode: Ni / Au, formed so as to contact the electron supply layer.

[0312] Source electrode and drain electrode: Ti / Al, formed so as to contact the capping layer.

[0313] The gate length was set to 10 μm, the gate width was set to 100 μm, the gate-source distance was set to 5 μm, and the gate-drain distance was set to 5 μm. In addition, the length of the source electrode and the length of the drain electrode were each set to 100 μm. Note that the interval between the source electrode of one element and the drain electrode of the other element was set to 50 μm in adjacent elements.

[0314] (Element separation)

[0315] In the laminate, etching was performed so as to surround the periphery of each semiconductor element region, to a depth of 200 nm from the surface side and a width of 10 μm, so as to separate a plurality of semiconductor elements in the plane from each other.

[0316] [Production conditions of the semiconductor element of Comparative Example 1] (Base substrate)

[0317] The same as in the example.

[0318] (Conditions of each layer)

[0319] Growth method of all layers: MOVPE method

[0320] Thickness of the nucleation layer (AlN layer): 10 nm

[0321] Thickness of the electron mobility layer (undoped GaN layer): 1500 nm

[0322] It should be noted that the electron mobility layer is initially grown in three dimensions.

[0323] Electronic supply layer (AI) 0.25 Ga 0.75 The thickness of the N-layer is 25 nm (same as in the example).

[0324] Thickness of the capping layer (GaN layer): 2.5 μm (same as in the example)

[0325] Each electrode: Same as in the embodiment.

[0326] [Fabrication conditions of semiconductor devices in Comparative Example 2] (substrate)

[0327] Same as the example.

[0328] (Conditions for each level)

[0329] Growth method for all layers: MOVPE method

[0330] Thickness of the nucleation layer (AlN layer): 10 nm

[0331] Thickness of the semi-insulating layer (C-doped GaN layer): 1000 nm

[0332] Thickness of the electron mobility layer (undoped GaN layer): 500 nm

[0333] It should be noted that the electron mobility layer is initially grown in three dimensions.

[0334] Electron supply layer (AI) 0.25 Ga 0.75 The thickness of the N-layer is 25 nm (same as in the example).

[0335] Thickness of the capping layer (GaN layer): 2.5 μm (same as in the example)

[0336] Each electrode: Same as in the embodiment.

[0337] It should be noted that in the growth process of the semi-insulating layer (C-doped GaN layer), the V / III ratio is set to approximately 2000. This allows C to be doped into the semi-insulating layer.

[0338] [Fabrication conditions of semiconductor devices in Comparative Example 3] (substrate)

[0339] Same as the example.

[0340] (Conditions for each level)

[0341] Growth method for all layers: MOVPE method

[0342] Thickness of the nucleation layer (AlN layer): 10 nm

[0343] Thickness of the semi-insulating layer (Fe-doped GaN layer): 800 nm

[0344] Thickness of the electron mobility layer (undoped GaN layer): 700 nm

[0345] It should be noted that the electron mobility layer is initially grown in three dimensions.

[0346] Electron supply layer (AI) 0.25 Ga 0.75 The thickness of the N-layer is 25 nm (same as in the example).

[0347] Thickness of the capping layer (GaN layer): 2.5 μm (same as in the example)

[0348] Each electrode: Same as in the embodiment.

[0349] (3-2) Evaluation (Secondary Ion Mass Spectrometry (SIMS))

[0350] SIMS was performed on the surface side of the semiconductor element in each of the Examples and Comparative Examples 1 to 3.

[0351] (Device characteristic: threshold voltage variation)

[0352] For the semiconductor devices of each of the embodiments and Comparative Examples 1 to 3, the drain-source voltage V ds With a voltage of 50V as the initial characteristic, the following measurements were taken relative to the gate voltage V. g Leakage current I d Find the leakage current I d Gate voltage V during rise g Threshold voltage V th Next, the gate voltage V... g Setting it to -5V creates a state that pinches off 2DEG, and the drain-source voltage V ds Stress was applied to each semiconductor element under conditions of 50V and an application time of 30 seconds. After stress application, the results were measured relative to the gate voltage V under the same conditions as the initial characteristic measurement. g Leakage current I d Calculate the gate voltage V after applying stress. g Threshold voltage V th '.

[0353] Here, use Figure 11AThe device characteristics in the example of the conventional semiconductor element will be described. Figure 11A is a graph showing an example of the leakage current with respect to the gate voltage in the conventional semiconductor element. Figure 11A In the table, "Before" indicates the characteristics before the stress is applied, and "After" indicates the characteristics after the stress is applied.

[0354] As shown in Figure 11A , in the conventional semiconductor element, the impurities mixed into a part of the active layer are charged and discharged due to the application of the stress, and thus the threshold voltage of the gate voltage after the stress is applied can fluctuate.

[0355] Thus, for each of the semiconductor elements of the example, Comparative Example 1 to Comparative Example 3, the threshold voltage V th before the stress is applied and the threshold voltage V th after the stress is applied, which are found based on the above operation, are used to find the threshold voltage fluctuation AV g (= V th ' - V th ) of the gate voltage V th .

[0356] (Device characteristics: buffer leakage current)

[0357] In each of the example, Comparative Example 1 to Comparative Example 3, 100 V is applied between the source electrode of one of the adjacent elements and the drain electrode of the other element (with a gap of 50 μm), and the buffer leakage current between the elements is measured. In this case, the unetched region within 1 semiconductor element region is conducted by the two-dimensional electron gas (2DEG), and thus the buffer leakage current is measured in a region having a length corresponding to the length of each of the source electrode and the drain electrode, 100 μm, and an etched width of 10 μm.

[0358] (3-3) Results (SIMS)

[0359] The results of the SIMS of Experiment 3 will be described using Figure 7B , Figure 8B , Figure 9B , and Figure 10B . Figure 7B , Figure 8B , Figure 9B , and Figure 10B are graphs showing the SIMS results of the example, Comparative Example 1, Comparative Example 2, and Comparative Example 3 of Experiment 3, respectively.

[0360] As shown in Figure 8B , in Comparative Example 1, the concentration of the impurities in the un-doped GaN layer as the electron movement layer on the side of the base substrate is greater than 1 x 1018 16 cm -3Si was detected at a concentration. As described above, in Comparative Example 1, an AlN layer with a relatively thin thickness (10 nm), which is a prior art material, was used as the nucleation layer. Therefore, it can be assumed that Si diffuses from the SiC substrate, which serves as the substrate, and that the Si concentration on the substrate side without the GaN layer is greater than 1 × 10⁻⁶. 16 cm -3 Furthermore, in Comparative Example 1, the GaN crystal was grown in three dimensions at the beginning of the growth of the undoped GaN layer. Therefore, O was incorporated through the small facets other than the c-plane, resulting in an O concentration of approximately 1 × 10⁻⁶ on the undoped GaN substrate side. 17 cm -3 O was detected at a concentration of [missing information]. Furthermore, in Comparative Example 1, O was uniformly distributed along the depth direction in the undoped GaN layer at a concentration of approximately 6 × 10 [missing information]. 15 cm -3 The concentration of C was detected.

[0361] like Figure 9B As shown, in Comparative Example 2, similar to Comparative Example 1, the AlN layer, which serves as the nucleation layer, is thinner. Si diffuses from the SiC substrate, which serves as the base substrate. Therefore, on the substrate side of the C-doped GaN layer, which serves as the semi-insulating layer, the diffusion rate is greater than 1 × 10⁻⁶. 16 cm -3 Si was detected at a concentration of [missing information]. Furthermore, in Comparative Example 2, the GaN crystal was grown in three dimensions at the initial stage of the growth of the C-doped GaN layer, which served as a semi-insulating layer. Therefore, O was incorporated through small facets other than the c-plane. Consequently, the concentration of O on the substrate side of the semi-insulating layer was approximately 1 × 10 [missing information]. 17 cm -3 The concentration of O was detected. On the other hand, in Comparative Example 2, C was doped in the semi-insulating layer. Therefore, in a manner that compensates for at least a portion of the Si and O mixed into the semi-insulating layer, the concentration was greater than 8 × 10⁻⁶. 16 cm -3 The concentration of C was detected.

[0362] like Figure 10B As shown, in Comparative Example 3, similar to Comparative Example 1, the AlN layer, which serves as the nucleation layer, is thinner, and Si diffuses from the SiC substrate, which serves as the substrate. Therefore, on the substrate side of the Fe-doped GaN layer, which serves as the semi-insulating layer, the Si diffusion rate is greater than 1 × 10⁻⁶. 16 cm -3 Si was detected at a concentration of [missing information]. Furthermore, in Comparative Example 3, the GaN crystal was three-dimensionally grown at the initial stage of the growth of the Fe-doped GaN layer, which served as a semi-insulating layer. Therefore, O was incorporated through small facets other than the c-plane. Consequently, the concentration of O on the substrate side of the semi-insulating layer was approximately 1 × 10 [missing information]. 17 cm -3The concentration of O was detected. On the other hand, in Comparative Example 3, Fe was doped in the semi-insulating layer, thus, in a manner that sufficiently compensates for the Si and O mixed into the opposing semi-insulating layer, the concentration was greater than 1 × 10⁻⁶. 18 cm -3 Fe was detected at a concentration.

[0363] In contrast, such as Figure 7B As shown, in this embodiment, by setting the thickness of the AlN layer, which serves as the nucleation layer, to be greater than 100 nm, the diffusion of Si from the SiC substrate, which serves as the base substrate, to the electron mobility layer can be suppressed. Therefore, it can be confirmed that, in this embodiment, the Si concentration in the electron mobility layer can be made to be 1 × 10⁻⁶ throughout the entire electron mobility layer. 16 cm -3 the following.

[0364] Furthermore, in this embodiment, by growing the electron-mobilizing layer laterally instead of in a three-dimensional manner, the incorporation of impurities such as O through small facets other than the c-facet can be suppressed. Therefore, it can be confirmed that, in this embodiment, the O concentration in the electron-mobilizing layer can be made to be 1 × 10⁻⁶ throughout the entire electron-mobilizing layer. 16 cm -3 the following.

[0365] Furthermore, in this embodiment, there was no intentional doping of impurities such as Fe and C into the electron mobility layer. Therefore, it can be confirmed that, in this embodiment, the Fe concentration and C concentration in the electron mobility layer can be made to be 1×10⁻⁶. 16 cm -3 the following.

[0366] (Equipment characteristics)

[0367] use Figure 11B The results regarding the equipment characteristics of Experiment 3 will be explained. Figure 11B This graph shows the variation of the buffer leakage current relative to the threshold voltage after stress was applied in Experiment 3. It should be noted that... Figure 11B In this study, the value of the buffer leakage current is recorded as the current per unit length of the source / drain electrodes used in the measurement.

[0368] like Figure 11B As shown, in Comparative Examples 2 and 3, since the Fe or C forming the deep energy level becomes charged, the threshold voltage change ΔV after stress is applied is... th The leakage current increases. On the other hand, in Comparative Examples 2 and 3, Fe or C compensates for Si and O, which are n-type impurities on the substrate side, thus reducing the buffer leakage current.

[0369] On the other hand, in Comparative Example 1, the buffer leakage current becomes large due to the mixing of Si and O as n-type impurities from the side of the base substrate. On the other hand, in Comparative Example 1, the buffer leakage current becomes large, and thus it is difficult for the impurities in the electron transport layer to be charged, and the threshold voltage variation ΔV th after the application of stress becomes small.

[0370] From the above results, it is confirmed that in the HEMT of the conventional structure like Comparative Examples 1 to 3, it is difficult to achieve both the suppression of the buffer leakage current and the stable operation achieved by suppressing the threshold voltage variation ΔV th after the application of stress.

[0371] On the other hand, in the embodiments, by setting the thickness of the AlN layer as the core formation layer to be greater than 100 nm, it is possible to suppress the diffusion of Si as an n-type impurity from the SiC substrate as the base substrate to the electron transport layer. Further, in the embodiments, by not causing the electron transport layer to grow three-dimensionally, but to grow laterally, it is possible to suppress the mixing of impurities such as O as an n-type impurity. From this, it is confirmed that in the embodiments, the buffer leakage current becomes small. Further, in the embodiments, there is no intentional doping of impurities such as Fe and C. From this, it is confirmed that in the embodiments, the threshold voltage variation ΔV th after the application of stress becomes small.

[0372] From the above results, it is confirmed that in the embodiments, it is possible to achieve both the suppression of the buffer leakage current and the stable operation achieved by suppressing the threshold voltage variation ΔV th after the application of stress.

[0373] (4) Experiment 4 (4-1) Production of Semiconductor Element

[0374] In Experiment 4, a semiconductor element equivalent to the embodiments of Experiment 3 was produced under the following conditions.

[0375] [Production Conditions of Semiconductor Element]

[0376] According to the same procedure as in Experiment 3, a semiconductor element was produced, except that the crystallinity of GaN in the electron transport layer was changed. Figure 6

[0377] (4-2) Evaluation (X-ray Diffraction Measurement)

[0378] The X-ray diffraction measurement of (10-12) diffraction of GaN in the electron transport layer was performed for the semiconductor elements of Experiment 4 described above, respectively. As a result, the half-value width of (10-12) diffraction of GaN in the electron transport layer was found.

[0379] (Device Characteristics: Element Life)

[0380] ​For the semiconductor element of Experiment 4, the temperature was set to 150°C, the gate voltage V g was set to -2 V, the drain-source voltage V ds was set to 50 V, and the semiconductor element was driven. Thereafter, the gate current (gate leakage current) I g was measured from a value less than 1 x 10 -8 A / mm to a value exceeding 1 x 10 -4 A / mm. The time at which the gate leakage current exceeded 1 x 10

[0381] (4-3) Results

[0382] The results of Experiment 4 will be described using Figure 12 . Figure 12 is a graph showing the element lifetime of Experiment 4 with respect to the half width of the (10-12) diffraction of GaN in the electron transport layer.

[0383] As shown in Figure 12 , a tendency was shown in which the element lifetime monotonically increased as the half width of the (10-12) diffraction of GaN in the electron transport layer of the semiconductor element became smaller (as the left side of the graph was approached, i.e., as the crystallinity improved). In other words, it was confirmed that by improving the crystallinity of the nucleus formation layer and improving the crystallinity of the electron transport layer formed on the nucleus formation layer, the element lifetime could be extended. Specifically, it was confirmed that by setting the half width of the (10-12) diffraction of GaN in the electron transport layer to 400 seconds or less, the element lifetime under the above driving conditions could be made to exceed 10,000 hours, which corresponds to a practically tolerable lifetime as a semiconductor element.

[0384] <Preferred Embodiment of the Invention>

[0385] Hereinafter, a preferred embodiment of the present invention will be described.

[0386] (Note 1)

[0387] A Group III nitride laminate having:

[0388] a base substrate;

[0389] a first layer provided on the aforementioned base substrate and formed of aluminum nitride; and

[0390] a second layer provided on the aforementioned first layer and formed of gallium nitride,

[0391] The first layer has a thickness of more than 100 nm and 1 μm or less, a half-value width of (0002) diffraction of 250 seconds or less as measured by an X-ray rocking curve, and a half-value width of (10-12) diffraction of 500 seconds or less as measured by an X-ray rocking curve.

[0392] (Paragraph 2)

[0393] The Group III nitride laminate according to Paragraph 1, wherein the second layer has a thickness of less than 1 μm,

[0394] The main surface of the second layer has a dislocation density of 5 x 10 8 cm -2 or less.

[0395] (Paragraph 3)

[0396] The Group III nitride laminate according to any one of Paragraphs 1 to 2, wherein the second layer has a thickness of less than 1 μm, a half-value width of (0002) diffraction of 200 seconds or less as measured by an X-ray rocking curve, and a half-value width of (10-12) diffraction of 400 seconds or less as measured by an X-ray rocking curve.

[0397] (Paragraph 4)

[0398] The Group III nitride laminate according to any one of Paragraphs 1 to 3, wherein the oxygen concentration in the second layer is 1 x 10 16 cm -3 or less throughout the entirety of the second layer.

[0399] (Paragraph 5)

[0400] The Group III nitride laminate according to any one of Paragraphs 1 to 4, wherein the silicon concentration in the second layer is 1 x 10 16 cm -3 or less throughout the entirety of the second layer.

[0401] (Paragraph 6)

[0402] The Group III nitride laminate according to any one of Paragraphs 1 to 5, wherein the iron concentration and the carbon concentration in the second layer are each 1 x 10 16 cm -3 or less.

[0403] (Paragraph 7)

[0404] The Group III nitride laminate according to any one of the following Notes 1 to 6, wherein the first layer has a thickness of 200 nm or more and 700 nm or less, a half-value width of (0002) diffraction measured based on an X-ray rocking curve is 200 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve is 400 seconds or less.

[0405] (Note 8)

[0406] The Group III nitride laminate according to any one of the following Notes 1 to 7, wherein the first layer has a thickness of 300 nm or more and 500 nm or less, a half-value width of (0002) diffraction measured based on an X-ray rocking curve is 180 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve is 380 seconds or less.

[0407] (Note 9)

[0408] The Group III nitride laminate according to any one of the following Notes 1 to 8, wherein the base substrate is formed of silicon carbide or sapphire.

[0409] (Note 10)

[0410] The Group III nitride laminate according to any one of the following Notes 1 to 9, further comprising a third layer provided on the second layer, the third layer being formed of a Group III nitride having a wider band gap than gallium nitride.

[0411] (Note 11)

[0412] A semiconductor element having, as at least a part of an operation layer, the second layer of the Group III nitride laminate according to any one of the following Notes 1 to 10.

[0413] (Note 12)

[0414] A Group III nitride laminate having:

[0415] a base substrate; and

[0416] a first layer provided on the base substrate and formed of aluminum nitride,

[0417] the first layer has a thickness of more than 100 nm and 1 μm or less, a half-value width of (0002) diffraction measured based on an X-ray rocking curve is 250 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve is 500 seconds or less.

[0418] (Note 13)

[0419] The Group III nitride laminate according to the supplementary note 12, wherein the first layer has a main surface for forming the second layer formed of gallium nitride,

[0420] The main surface of the first layer is configured in such a manner that the second layer is grown in such a manner that the thickness of the second layer is less than 1 μm, and the dislocation density of the main surface of the second layer is 5 x 1010 / cm2or less. 8 cm -2 The second layer is grown in the following manner.

[0421] (Supplementary Note 14)

[0422] The Group III nitride laminate according to the supplementary note 12 or 13, wherein the first layer has a main surface for forming the second layer formed of gallium nitride,

[0423] The main surface of the first layer is configured in such a manner that the second layer is grown in such a manner that the thickness of the second layer is less than 1 μm, and the half-value width of (0002) diffraction determined based on an X-ray rocking curve is 200 seconds or less, and the half-value width of (10-12) diffraction determined based on an X-ray rocking curve is 400 seconds or less.

[0424] (Supplementary Note 15)

[0425] A method for manufacturing a Group III nitride laminate, comprising the following steps:

[0426] a step of forming a first layer formed of aluminum nitride on a base substrate;

[0427] a step of performing heat treatment of the first layer in an atmosphere containing hydrogen; and

[0428] a step of forming a second layer formed of gallium nitride on the first layer,

[0429] In the step of forming the first layer, the first layer is formed in the following manner:

[0430] The thickness of the first layer is made greater than 100 nm and 1 μm or less, and the half-value width of (0002) diffraction determined based on an X-ray rocking curve is made 250 seconds or less, and the half-value width of (10-12) diffraction determined based on an X-ray rocking curve is made 500 seconds or less.

Claims

1. A Group III nitride laminate, comprising: a base substrate; a first layer provided on the base substrate and formed of aluminum nitride; and a second layer provided on the first layer and formed of gallium nitride, the first layer having a thickness of greater than 100 nm and 1 μm or less, a half-value width of (0002) diffraction measured based on an X-ray rocking curve of 250 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve of 500 seconds or less, the second layer having a thickness of less than 1 μm, a half-value width of (0002) diffraction measured based on an X-ray rocking curve of 200 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve of 400 seconds or less. The first layer has a thickness of 200 nm or more and 700 nm or less, a half-value width of (0002) diffraction measured based on an X-ray rocking curve of 200 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve of 400 seconds or less.

7. The Group III nitride laminate according to claim 1 or 2, further comprising a third layer provided on the second layer, the third layer being formed of a Group III nitride having a wider band gap than gallium nitride.

8. A semiconductor element comprising, as at least a portion of an active layer, the second layer possessed by the Group III nitride laminate according to any one of claims 1 to 7.

9. A Group III nitride laminate, comprising: a base substrate; and a first layer provided on the base substrate and formed of aluminum nitride, the first layer having a thickness of greater than 100 nm and 1 μm or less, a half-value width of (0002) diffraction measured based on an X-ray rocking curve of 250 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve of 500 seconds or less, the first layer having an upper surface for forming a second layer formed of gallium nitride.

10. A method of manufacturing a Group III nitride laminate, comprising the steps of: a step of forming a first layer formed of aluminum nitride on a base substrate; a step of performing heat treatment of the first layer in an atmosphere containing hydrogen; and a step of forming a second layer formed of gallium nitride on the first layer, the second layer having a thickness of less than 1 μm, the first layer being formed in the step of forming the first layer in such a manner that the first layer has a thickness of greater than 100 nm and 1 μm or less, and a half-value width of (0002) diffraction measured based on an X-ray rocking curve of 250 seconds or less, and a half-value width of (10-12) diffraction measured based on an X-ray rocking curve of 500 seconds or less. The dislocation density of the main surface of the second layer is 5 x 1010 8 cm -2 below.

2. The Group III nitride layer stack of claim 1, wherein, ​ 3. The Group III nitride layer stack of claim 1 or 2, wherein, The oxygen concentration in the second layer is 1 x 10 16 cm -3 below throughout the entirety of the second layer.

4. The Group III nitride layer stack of claim 1 or 2, wherein, Throughout the entirety of the second layer, the concentration of silicon in the second layer is 1 x 10 16 cm -3 below.

5. The Group III nitride layer stack of claim 1 or 2, wherein, The iron concentration and the carbon concentration in the second layer are 1 x 10 16 cm -3 below, respectively.

6. The Group III nitride layer stack of claim 1 or 2, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ The upper surface of the first layer is configured in such a manner that the thickness of the second layer is less than 1 μm, and the dislocation density of the main surface of the second layer is 5 x 1010 / cm2or less. 8 cm -2 The second layer is grown in the following manner. ​ ​ ​ ​ ​ The dislocation density of the main surface of the second layer is 5 x 1010 8 cm -2 Hereinafter, ​ ​

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