Back-gate modulation device and preparation method thereof, memory, and logic device

Abstract

The present invention provides a back-gate modulation device and its preparation method, memory, and logic device, wherein the back-gate modulation device may include but is not limited to a silicon substrate, an ONO layer, a single-crystal silicon layer, a gate, a first sidewall, a second sidewall, a first source and drain, and a second source and drain. The ONO layer fills a cavity formed on the silicon substrate, the single-crystal silicon layer is formed on the ONO layer, the gate is formed on the single-crystal silicon layer, the first sidewall surrounds the sidewall of the gate and is disposed on the single-crystal silicon layer, the second sidewall surrounds the sidewall of the first sidewall and is disposed on the single-crystal silicon layer; the first source and drain are disposed on the silicon substrate, on one side of the single-crystal silicon layer; and the second source and drain are disposed on the silicon substrate, on the other side of the single-crystal silicon layer. The present invention can flexibly control the thickness of the single-crystal silicon layer and the ONO structure by adjusting the thickness of the sacrificial layer and the substrate according to actual needs, thereby maximizing the performance of the back-gate modulation device and effectively reducing device cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices. More specifically, the present invention can provide a back-gate modulation device and a preparation method thereof, a memory, and a logic device. Background Art

[0002] With the continuous development of integrated circuit technology, the requirements for the structural design of semiconductor devices are becoming increasingly stringent due to factors such as device integration, performance, and cost. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices have the advantages of simple processing, good compatibility, low power consumption, and strong scalability. FDSOI (Fully Depleted Silicon-On-Insulator) technology is often combined with SONOS technology to produce low-power, high-performance semiconductor devices.

[0003] However, due to the limitations of existing SONOS device processes and structural designs, the thickness of the SONOS key device layer cannot be flexibly adjusted according to actual conditions, which affects the performance of the semiconductor device and increases the device processing cost. Summary of the Invention

[0004] To address the problems of the prior art in being unable to flexibly adjust the thickness of SONOS key device layers and being high in cost, one or more embodiments of the present invention provide a back-gate modulation device and a preparation method thereof, a memory, and a logic device.

[0005] To achieve the above technical objectives, the present invention provides a back-gate modulation device, which may include but is not limited to a silicon substrate, an ONO layer, a single crystal silicon layer, a gate, a first side wall, a second side wall, a first source and drain, and a second source and drain.

[0006] The ONO layer is filled in the cavity formed on the silicon substrate.

[0007] A single crystal silicon layer is formed on the ONO layer.

[0008] A gate is formed on the single crystal silicon layer.

[0009] The first sidewall spacer surrounds the sidewall of the gate and is disposed on the single crystal silicon layer.

[0010] The second sidewall surrounds the sidewall of the first sidewall and is disposed on the single crystal silicon layer.

[0011] The first source and drain are arranged on the silicon substrate and located beside the single crystal silicon layer.

[0012] The second source and drain are arranged on the silicon substrate and located on the other side of the single crystal silicon layer.

[0013] Furthermore, the back-gate modulation device also includes a shallow trench isolation structure.

[0014] A shallow trench isolation structure is formed in the silicon substrate. The first source and drain electrodes and the second source and drain electrodes are both arranged in a silicon substrate region surrounded by the shallow trench isolation structure.

[0015] Furthermore, the ONO layer includes a tunneling oxide layer, a nitride layer and a blocking oxide layer arranged in sequence; wherein the blocking oxide layer is arranged on the silicon substrate.

[0016] Furthermore, the first sidewall spacer is a silicon nitride layer, and the second sidewall spacer is a silicon oxide layer.

[0017] Furthermore, the gate is composed of a floating gate structure.

[0018] Furthermore, the gate is composed of polysilicon and silicon oxynitride.

[0019] In order to achieve the above technical objectives, the present invention further provides a memory, which may include but is not limited to the back-gate modulation device described in the embodiments of the present invention.

[0020] In order to achieve the above technical objectives, the present invention provides a logic device, which includes the back gate modulation device described in the embodiment of the present invention.

[0021] To achieve the above technical objectives, the present invention can also provide a method for preparing a back-gate modulation device, which may include but is not limited to one or more of the following steps.

[0022] A silicon substrate is provided.

[0023] A shallow trench isolation structure is formed in the silicon substrate.

[0024] A sacrificial layer is epitaxially grown on the surface of the silicon substrate surrounded by the shallow trench isolation structure, and a single crystal silicon layer is formed on the sacrificial layer.

[0025] A gate is formed on the single crystal silicon layer, and a first spacer is formed on a sidewall of the gate and a second spacer is formed on a sidewall of the first spacer.

[0026] The sacrificial layer is exposed by sequentially vertically etching the single crystal silicon layer and the sacrificial layer.

[0027] A cavity is formed by etching away the sacrificial layer, and the silicon substrate and the single crystal silicon layer are exposed.

[0028] An ONO layer is formed in the cavity between the silicon substrate and the single crystal silicon layer.

[0029] A first source and a drain electrode and a second source and a drain electrode are formed in the silicon substrate region surrounded by the shallow trench isolation structure.

[0030] Furthermore, in an embodiment of the present invention, forming an ONO layer in the cavity between the silicon substrate and the single crystal silicon layer includes:

[0031] growing a tunneling oxide layer on the surface of the exposed single crystal silicon layer and growing a barrier oxide layer on the surface of the exposed silicon substrate;

[0032] A nitride layer is filled between the tunnel oxide layer and the blocking oxide layer.

[0033] The beneficial effects of the present invention are as follows: compared with the prior art, the present invention can flexibly control the thickness of the single crystal silicon layer (top silicon) and the ONO structure through the thickness of the sacrificial layer (epitaxial SiGe) and the substrate (Si) according to actual needs, and the device structure is more flexible, thereby maximizing the performance of the back gate modulation device. The memory device produced based on the present invention can effectively improve the storage window, realize multi-bit storage, and has the advantages of high service life. The logic device produced based on the present invention can achieve the equivalent effect of different back gate voltages and has the advantages of low energy consumption. In addition, the present invention can greatly reduce the cost of manufacturing the SON structure based on single crystal silicon wafers, for example, it can reduce the cost by about 80% compared to SOI wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic cross-sectional structure diagram of a silicon substrate provided in one or more embodiments of the present invention is shown.

[0035] Figure 2 A schematic diagram is shown after a shallow trench isolation (STI) structure is fabricated on a silicon substrate in one or more embodiments of the present invention.

[0036] Figure 3 A schematic diagram of the device structure after forming a sacrificial layer and a single crystal silicon layer in one or more embodiments of the present invention is shown.

[0037] Figure 4 A schematic diagram of the device structure after the gate and double sidewalls are formed in one or more embodiments of the present invention is shown.

[0038] Figure 5 A schematic diagram of the device structure after vertical etching of the single crystal silicon layer and the sacrificial layer in one or more embodiments of the present invention is shown.

[0039] Figure 6 A schematic diagram of the device structure after a cavity is formed by etching away the sacrificial layer in one or more embodiments of the present invention is shown.

[0040] Figure 7 A schematic diagram of the device structure after an ONO layer is formed at the cavity position in one or more embodiments of the present invention is shown.

[0041] Figure 8 A schematic diagram of the device structure after forming the first source and drain and the second source and drain in one or more embodiments of the present invention is shown.

[0042] In the figure,

[0043] 100. Silicon substrate.

[0044] 200. Shallow trench isolation structure.

[0045] 300. Sacrificial layer.

[0046] 400. Single crystal silicon layer.

[0047] 500. Gate.

[0048] 600. First side wall (black filled part in the figure).

[0049] 700. Second side wall.

[0050] 800. Tunneling oxide layer. 801. Nitride layer. 802. Barrier oxide layer.

[0051] 900. First source and drain. 901. Second source and drain. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0053] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0054] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0055] like Figures 1 to 8 As shown, one or more embodiments of the present invention can provide a method for preparing a back-gate modulation device to manufacture the back-gate modulation device provided by the present invention and solve one or more problems existing in the prior art, which are specifically described as follows.

[0056] like Figure 1 As shown, a cleaned silicon substrate 100 is provided. The embodiment of the present invention can use the silicon substrate 100 formed by a single crystal silicon wafer (specifically a bulk silicon wafer) to manufacture a back-gate modulation device, which can effectively reduce costs, for example, reducing the cost by about 80% compared to SOI wafers.

[0057] like Figure 2 As shown, the embodiment of the present invention can form a shallow trench isolation (STI) structure 200 in a silicon substrate 100. It should be understood that the specific process of the shallow trench isolation process can be selected according to specific circumstances, and the embodiment of the present invention will not be described in detail.

[0058] like Figure 3 As shown, in an embodiment of the present invention, a sacrificial layer 300 can be grown epitaxially (Epi, Epitaxy) on the surface of a silicon substrate 100 surrounded by a shallow trench isolation structure 200, and a single crystal silicon layer 400 can be formed on the sacrificial layer 300. The sacrificial layer 300 in this embodiment is specifically a SiGe (silicon germanium) layer, that is, in this step, a layer of SiGe is epitaxially grown on the Si surface. The thickness of the SiGe can be determined by reverse deduction based on the thickness of the subsequently formed ONO layer. For example, the thickness of the ONO layer is the same as the thickness of the SiGe. Then, a layer of single crystal silicon can be grown on the outside. The thickness of the single crystal silicon takes into account the loss of RTO (Rapid Thermal Oxidation) or HTO (High Temperature Oxidation) in the subsequent steps.

[0059] like Figure 4As shown, a gate 500 and a double sidewall spacer structure are formed on a single crystal silicon layer 400. Specifically, a first sidewall spacer 600 is formed on the sidewall of the gate 500, and a second sidewall spacer 700 is formed on the sidewall of the first sidewall spacer 600. In the embodiment of the present invention, the first sidewall spacer 600 is a silicon nitride layer, and the second sidewall spacer 700 is a silicon oxide layer. When the back-gate modulation device in the embodiment of the present invention is used in a memory, the gate 500 is composed of a floating gate structure (Floating Gate). When the back-gate modulation device in the embodiment of the present invention is used in a logic device, the gate 500 can be composed of polysilicon (Poly) and silicon oxynitride (SiON).

[0060] Taking the formation of a floating gate structure as an example, the present invention sequentially performs high-temperature oxidation (HTO), SiN deposition, high-temperature oxidation (HTO), and rapid thermal processing (RTP), followed by LDD (lightly doped drain) treatment, and finally forms silicon nitride and silicon oxide sidewalls. It should be understood that the specific implementation process for forming the sidewalls can be selected as needed and will not be detailed in detail in the present embodiment.

[0061] like Figure 5 As shown, the sacrificial layer 300 is exposed by sequentially vertically etching the single crystal silicon layer 400 and the sacrificial layer 300. In this embodiment, the source and drain regions are vertically etched to form corresponding grooves and expose the side surfaces of the sacrificial layer 300 (SiGe). The vertical etching can be performed using a dry etching method.

[0062] like Figure 6 As shown, the cavity is formed by etching away the sacrificial layer 300, and the silicon substrate 100 and the single crystal silicon layer 400 are exposed. In the present invention, the process of etching the sacrificial layer 300 can be specifically implemented by wet etching, that is, etching away the SiGe layer. It should be understood that due to Figure 6 This is a cross-sectional view of the device structure. The cavity of this embodiment is indicated by the dotted line in the figure. In the actual structure, there is support for the upper related structure in other directions, and it is not a suspended structure.

[0063] like Figure 7 As shown, an ONO layer is formed in the cavity between the silicon substrate 100 and the single crystal silicon layer 400. It can be seen that the present invention provides a SON (Silicon On Nothing) back-gate modulation device based on bulk silicon wafer manufacturing, specifically, a SON condition exists during the manufacturing process.

[0064] The ONO (Oxide-Nitride-Oxide) layer specifically includes a tunneling oxide layer 800, a nitride layer 801, and a blocking oxide layer 802. In an embodiment of the present invention, the formation of the ONO layer in the cavity between the silicon substrate and the single crystal silicon layer 400 may include: growing a tunneling oxide layer 800 on the surface of the exposed single crystal silicon layer 400 and growing a blocking oxide layer 802 on the surface of the exposed silicon substrate 100. Specifically, oxide (Oxide) can be grown on the lower surface of the single crystal silicon layer 400 at the cavity and the upper surface of the silicon substrate 100 by rapid thermal oxidation (RTO) or high temperature oxidation (HTO); and filling the nitride layer 801 between the tunneling oxide layer 800 and the blocking oxide layer 802. In an embodiment of the present invention, SiN is specifically deposited and filled to form the ONO layer, thereby completing the processing of the SONOS structure.

[0065] like Figure 8 As shown, source and drain electrodes are epitaxially grown on the exposed silicon substrate 100. In the embodiment of the present invention, a first source and drain electrode 900 and a second source and drain electrode 901 are formed in the silicon substrate 100 region surrounded by the shallow trench isolation structure 200, thereby realizing basic transistor structure fabrication.

[0066] Based on the same inventive concept as the device preparation method provided by the present invention, one or more embodiments of the present invention can also provide a back-gate modulation device. The back-gate modulation device in the present invention may specifically include but is not limited to a silicon substrate 100, a shallow trench isolation structure 200, an ONO layer, a single crystal silicon layer 400, a gate 500, a first side wall 600, a second side wall 700, a first source and drain 900, and a second source and drain 901.

[0067] The shallow trench isolation structure 200 is formed in a silicon substrate 100, which is a substrate formed based on a single crystal silicon (Si) wafer. The shallow trench isolation structure 200 is also known as an STI (Shallow Trench Isolation) structure and can be formed of an insulating material such as silicon oxide.

[0068] The ONO layer is formed by filling the silicon substrate 100. The ONO layer in the embodiment of the present invention includes a tunneling oxide layer 800, a nitride layer 801 and a blocking oxide layer 802 arranged in sequence; wherein, in the embodiment of the present invention, the blocking oxide layer 802 is arranged on the silicon substrate 100, the nitride layer 801 is arranged on the oxide layer 802, and the tunneling oxide layer 800 is arranged on the nitride layer 801 to form an oxide (Oxide) - nitride (Nitride) - oxide (Oxide) layer.

[0069] The single crystal silicon layer 400 is formed on the ONO layer, specifically on the tunnel oxide layer 800. The silicon substrate 100, the ONO layer and the single crystal silicon layer 400 in the present invention together form a SONOS structure.

[0070] The gate 500 is formed on the single crystal silicon layer 400. In some embodiments of the present invention, the gate 500 is composed of a floating gate structure for use in a memory device. In this case, the floating gate structure acts as a positive gate, which is connected to the word line, and the data "01" and "00" are stored by word line writing. In addition, the SONOS structure of the present invention acts as a back gate, which is connected to the bit line, and the data "11" and "10" are stored by bit line writing. It can be seen that the present invention can effectively widen the range of the offset voltage (Vt Shift) and increase the storage window to obtain more storage bits. Specifically, it can achieve the purpose of dual-bit storage data writing. The comparison of the dual-bit storage writing method proposed by this patent with conventional technology is shown in the following table.

[0071]

[0072]

[0073] In other embodiments of the present invention, the gate 500 is composed of polysilicon and silicon oxynitride, and the back gate modulation device of this structural form can be used for logic devices. In this case, the SONOS structure can be used as the back gate, and the back gate is connected to the bit line to write "1" or "0" or not write through the bit line. Specifically, due to the quantum well structure of the SONOS structure energy band provided by the embodiment of the present invention, it has a good storage effect, and different back gate information can be written in a pulsed manner to achieve the equivalent effect of different back gate voltages (body bias). In addition, the back gate is in a 0V state for most of the time, and there is no need for a higher voltage input of about 2V, avoiding the problem of leakage in all directions of the substrate caused by continuous application of the back gate voltage and the problem of causing parasitic coupling effects, and has the advantages of low energy consumption. As shown in the table below, this patent proposes a method to replace the conventional SOI back bias.

[0074]

[0075] The first spacer 600 surrounds the sidewalls of the gate 500 and is disposed on the single crystal silicon layer 400. In the embodiment of the present invention, the first spacer 600 is a silicon nitride layer.

[0076] The second sidewall spacer 700 surrounds the sidewall of the first sidewall spacer 600 and is disposed on the single crystal silicon layer 400 . The second sidewall spacer 700 is a silicon oxide layer.

[0077] In the embodiment of the present invention, the first source-drain electrode 900 and the second source-drain electrode 901 can be respectively disposed on both sides of the single crystal silicon layer 400. Specifically, the first source-drain electrode 900 is disposed on the silicon substrate 100 and is located on one side of the single crystal silicon layer 400. The second source-drain electrode 901 is disposed on the silicon substrate 100 and is located on the other side of the single crystal silicon layer 400. It should be understood that in the present invention, when the first source-drain electrode 900 is a source electrode, the second source-drain electrode 901 is a drain electrode, or when the second source-drain electrode 901 is a source electrode, the first source-drain electrode 900 is a drain electrode.

[0078] In the embodiment of the present invention, the first source and drain electrodes 900 and the second source and drain electrodes 901 are both disposed in the silicon substrate 100 region surrounded by the shallow trench isolation structure 200 .

[0079] The present invention can also provide a memory, which can specifically include the back gate modulation device in the embodiment of the present invention. The memory is a storage device, which is a device that can store a large amount of binary information. It is used to store a large amount of data during the operation of computers and other digital systems, and is an indispensable component of computers and digital systems. The present invention helps to significantly improve the access speed and storage capacity of the memory device to meet the requirements of computers and other digital systems for operating speed and large-scale data processing. The memory device includes a plurality of memory cells (MemoryCell), each memory cell includes the back gate modulation device provided by the embodiment of the present invention; the memory provided by the present invention can be FlashMemory (flash memory).

[0080] The present invention can also provide a logic device (Logic), which may include the back gate modulation device in the embodiment of the present invention.

[0081] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0082] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0083] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0084] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0085] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A method for preparing a back-gate modulation device, characterized in that: include: providing a silicon substrate; forming a shallow trench isolation structure in the silicon substrate; epitaxially growing a sacrificial layer on the surface of the silicon substrate surrounded by the shallow trench isolation structure, and forming a single crystal silicon layer on the sacrificial layer; forming a gate on the single crystal silicon layer, and forming a first sidewall spacer on the sidewall of the gate and a second sidewall spacer on the sidewall of the first sidewall spacer; exposing the sacrificial layer by sequentially vertically etching the single crystal silicon layer and the sacrificial layer; forming a cavity by etching away the sacrificial layer, and exposing the silicon substrate and the single crystal silicon layer; forming an ONO layer in the cavity between the silicon substrate and the single crystal silicon layer; A first source and a drain electrode and a second source and a drain electrode are formed in the silicon substrate region surrounded by the shallow trench isolation structure.

2. The method for preparing a back-gate modulation device according to claim 1, wherein: Forming an ONO layer in the cavity between the silicon substrate and the single crystal silicon layer comprises: growing a tunneling oxide layer on the surface of the exposed single crystal silicon layer and growing a barrier oxide layer on the surface of the exposed silicon substrate; A nitride layer is filled between the tunnel oxide layer and the blocking oxide layer.

3. A back-gate modulation device, characterized in that: The back-gate modulation device is manufactured according to the method for manufacturing a back-gate modulation device according to claim 1 or 2, comprising: Silicon substrate; An ONO layer is filled in the cavity formed on the silicon substrate; a single crystal silicon layer formed on the ONO layer; a gate formed on the single crystal silicon layer; A first spacer surrounds the sidewall of the gate and is disposed on the single crystal silicon layer; a second sidewall spacer, surrounding the sidewall of the first sidewall spacer and disposed on the single crystal silicon layer; A first source and drain electrode is provided on the silicon substrate and is located beside the single crystal silicon layer; A second source and drain electrode is provided on the silicon substrate and is located on the other side of the single crystal silicon layer; An ONO layer is also included between the first source and drain electrodes and the second source and drain electrodes; the ONO layer includes a tunneling oxide layer, a nitride layer and a blocking oxide layer arranged in sequence; wherein the blocking oxide layer is arranged on the upper surface of the silicon substrate and contacts the upper surface of the silicon substrate.

4. The back-gate modulation device according to claim 3, wherein: Also includes: A shallow trench isolation structure is formed in the silicon substrate; The first source and drain and the second source and drain are both arranged in the silicon substrate region surrounded by the shallow trench isolation structure.

5. The back gate modulation device according to claim 3 or 4, characterized in that: The first sidewall spacer is a silicon nitride layer. The second sidewall spacer is a silicon oxide layer.

6. The back gate modulation device according to claim 3 or 4, characterized in that: The gate is composed of a floating gate structure.

7. The back gate modulation device according to claim 3 or 4, characterized in that: The gate is composed of polysilicon and silicon oxynitride.

8. A memory, characterized in that: The memory comprises the back gate modulation device according to any one of claims 3 to 6.

9. A logic device, characterized in that: The logic device includes the back gate modulation device according to any one of claims 3 to 5 and 7.

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