Power supply modulator

Abstract

A power modulator is provided. The power modulator includes: a multi-output voltage regulator (MOVR) configured to output a plurality of voltages in a discrete level envelope tracking mode (DLETM), the plurality of voltages having mutually different levels corresponding to reference output voltage signals; a switching regulator configured to output a switching regulator voltage, the output voltage depending on a selected voltage among the plurality of voltages and the switching regulator voltage in the DLETM, and the output voltage depending on the switching regulator voltage in the average power tracking mode; a switching regulator controller configured to sense an output current of the MOVR to obtain a sensed value, and to control the switching regulator based on the sensed value in the DLETM; a switch array including a plurality of switches corresponding to the plurality of voltages, respectively, and configured to selectively connect the selected voltage to a power amplifier by performing a switching operation; and a switch controller configured to control the switching operation.

Description

[0001] This application is based on and claims the benefit of Korean Patent Application No. 10-2020-0079516 filed on June 29, 2020, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0149587 filed on November 10, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The inventive concept relates to a power supply modulator with improved power efficiency and a wireless communication device including the same. Background Art

[0003] In wireless communication devices (such as smart phones, tablets and Internet of Things (IoT) devices), Wideband Code Division Multiple Access (WCDMA) (3G), Long Term Evolution (LTE), Advanced LTE (4G) or New Radio (NR) (5G) technology is used for high-speed communication. However, with the development of communication technology, a high peak-to-average power ratio (PAPR) of transmitted / received signals and a high bandwidth are used, and therefore, the efficiency of the power amplifier is reduced. In particular, when the power supply of the power amplifier at the transmitting end is connected to a battery, the efficiency reduction of the power amplifier is significant. Therefore, average power tracking (APT) technology or envelope tracking (ET) technology is used to improve the power efficiency of the power amplifier under high PAPR and high bandwidth. A chip or component that supports APT technology and ET technology is called a power modulator (SM). Summary of the Invention

[0004] The inventive concept provides a power modulator having improved power efficiency and a wireless communication device including the same.

[0005] According to one aspect of the inventive concept, a power supply modulator is provided, wherein the power supply modulator is configured to be driven in a tracking mode and provide an output voltage to a power amplifier, wherein the tracking mode is an average power tracking mode or a discrete level envelope tracking mode, and the power supply modulator includes: a multi-output voltage regulator, configured to output a plurality of voltages in the discrete level envelope tracking mode, wherein the plurality of voltages have different levels from each other, and the different levels correspond to a plurality of reference output voltage signals respectively; a switching regulator, configured to output a switching regulator voltage, wherein the output voltage depends on a selected voltage among the plurality of voltages and the switching regulator voltage in the discrete level envelope tracking mode, and the output voltage depends on the switching regulator voltage in the average power tracking mode; and a switching regulator controller, configured to: sense the multi-output voltage; an output current of the voltage regulator to obtain a sensed value, and controlling the switching regulator based on the sensed value in a discrete level envelope tracking mode; a switch array comprising a plurality of switches corresponding to the plurality of voltages, the switch array being configured to selectively connect the selected voltage to the power amplifier by performing a switching operation; a discrete level controller being configured to generate a level control signal based on the digital envelope signal; the switch controller being configured to control the switching operation of the switch array based on the level control signal; and a main controller being configured to: generate the plurality of reference output voltage signals, determine a tracking mode from among an average power tracking mode and a discrete level envelope tracking mode, and control at least one of the multi-output voltage regulator, the switch controller, the switching regulator controller and the discrete level controller based on the tracking mode.

[0006] According to one aspect of the inventive concept, a power modulator is provided, which is configured to be driven in a tracking mode and provide an output voltage to a power amplifier, the tracking mode being an average power tracking mode or a discrete level envelope tracking mode, the power modulator comprising: a multi-output voltage regulator, configured to output a plurality of voltages in the discrete level envelope tracking mode, the plurality of voltages having levels different from each other, and the different levels respectively corresponding to a plurality of reference output voltage signals; a switching regulator, configured to output a switching regulator voltage, the output voltage depending on a selected voltage among the plurality of voltages and the switching regulator voltage in the discrete level envelope tracking mode, the output voltage depending on the switching regulator voltage in the average power tracking mode; a switching regulator controller, configured to sense an output current of the multi-output voltage regulator to obtain a sensed value, and control the switching regulator based on the sensed value in the discrete level envelope tracking mode; a switch array comprising a plurality of switches , a switch array is configured to selectively connect a selected voltage to a power amplifier by performing a switching operation, wherein a first switch among the plurality of switches is connected to a ground voltage, and a subset of switches among the plurality of switches is connected to a multi-output voltage regulator to respectively correspond to the plurality of voltages, the switch subset not including the first switch; a discrete level controller is configured to generate a level control signal based on a digital envelope signal; a switch controller is configured to control the switching operation of the switch array based on the level control signal; a coupling capacitor has one end connected to the switch array and the other end connected to the power amplifier; and a main controller is configured to: generate the plurality of reference output voltage signals, generate a target voltage signal for the coupling capacitor, determine a tracking mode from among an average power tracking mode and a discrete level envelope tracking mode, and control at least one of the multi-output voltage regulator, the switch controller, the switching regulator controller and the discrete level controller based on the tracking mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of a wireless communication device according to an embodiment of the inventive concept;

[0009] Figure 2 It shows Figure 1 A block diagram of the signal processing operation of a digital transmit processor is shown in;

[0010] Figure 3 is a block diagram of a wireless communication device according to an embodiment of the inventive concept;

[0011] Figure 4is a circuit diagram illustrating a first example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept;

[0012] Figure 5 It shows Figure 4 A diagram of an example of a multiple output voltage regulator;

[0013] Figure 6 It shows Figure 4 A diagram of another example of a multi-output voltage regulator;

[0014] Figure 7 It shows Figure 4 A diagram of another example of a multi-output voltage regulator;

[0015] Figure 8 is a graph showing waveform characteristics of an output voltage according to a tracking mode;

[0016] Figure 9 is a graph showing an output voltage generation mechanism in envelope tracking mode;

[0017] Figure 10 It shows Figure 4 Graph showing average power tracking (APT) mode operation of a power supply modulator;

[0018] Figure 11 It shows Figure 4 Schematic diagram of discrete level envelope tracking (DL-ET) mode operation of a power supply modulator;

[0019] Figure 12 It shows Figure 4 Schematic diagram of continuous level envelope tracking (CL-ET) mode operation of a power supply modulator;

[0020] Figure 13 is a circuit diagram illustrating a second example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept;

[0021] Figure 14 It shows Figure 13 A diagram of the APT mode operation of the power supply modulator;

[0022] Figure 15 It shows Figure 13 Schematic diagram of DL-ET mode operation of the power modulator;

[0023] Figure 16 is a circuit diagram illustrating a third example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept;

[0024] Figure 17is a circuit diagram illustrating a fourth example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept;

[0025] Figure 18 is a circuit diagram illustrating a fifth example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept;

[0026] Figure 19 It shows Figure 18 A diagram of an example of a multiple output voltage regulator;

[0027] Figure 20 It shows Figure 18 A diagram of another example of a multi-output voltage regulator;

[0028] Figure 21 It shows Figure 18 A diagram of another example of a multi-output voltage regulator;

[0029] Figure 22 is a diagram illustrating a mechanism for increasing the output voltage of a multi-output voltage regulator by a coupling capacitor;

[0030] Figure 23 It shows Figure 18 A diagram of the APT mode operation of the power supply modulator;

[0031] Figure 24 It shows Figure 18 Schematic diagram of DL-ET mode operation of the power modulator;

[0032] Figure 25 It shows Figure 18 Schematic diagram of CL-ET mode operation of the power supply modulator;

[0033] Figure 26 is a circuit diagram illustrating a sixth example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept;

[0034] Figure 27 It shows Figure 26 A diagram of the APT mode operation of the power supply modulator;

[0035] Figure 28 It shows Figure 26 Schematic diagram of DL-ET mode operation of the power modulator;

[0036] Figure 29 is a circuit diagram illustrating a seventh example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept;

[0037] Figure 30is a circuit diagram illustrating an eighth example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept; and

[0038] Figure 31 is a block diagram of a mobile terminal to which a wireless communication device is applied according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0039] The inventive concept will now be described more fully with reference to the accompanying drawings, in which embodiments of the inventive concept are shown.

[0040] The advantages and features of the inventive concept and the methods for achieving the advantages and features will become clear with reference to the embodiments and drawings described in detail below. However, the inventive concept is not limited to the embodiments shown below, but can be implemented in various forms that are different from each other and can be used interchangeably. In addition, the embodiments are provided so that the inventive concept will be thorough and complete and will fully convey the scope of the inventive concept to those of ordinary skill in the art. In addition, specific components described only in some embodiments of the inventive concept can be used in other embodiments. The same reference numerals in the drawings represent the same elements.

[0041] When an element is described as being "connected to" or "coupled to" another element, the element is directly connected to or coupled to the other element, or another element is interposed therebetween. On the other hand, when an element is described as being "directly connected to" or "directly coupled to" another element, no other element is interposed therebetween. Like reference numerals in the drawings denote like elements. When items are described using the conjunction "and / or," the description should be understood to include any and all combinations of one or more of the listed items.

[0042] Although terms such as "first," "second," etc. may be used to describe various elements, components, and / or parts, such elements, components, and / or parts are not limited by the above terms. The above terms are only used to distinguish one element, component, or part from another element, component, or part. Within the inventive concept, a first element, first component, or first part may be a second element, second component, or second part.

[0043] The terms used in this specification are only used to describe specific embodiments and are not intended to limit the inventive concept. Unless the expression has a significantly different meaning in the context, the expression used in the singular includes the expression of the plural number. In this specification, it will be understood that terms (such as "include" and / or "comprising") are intended to indicate the presence of components, operations and / or elements disclosed in the specification, and are not intended to exclude the possibility that one or more other operations and / or elements may exist or may be added.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used as the meanings commonly understood by those skilled in the art to which this disclosure pertains. In addition, unless specifically defined otherwise, terms defined in general dictionaries are not ideally or excessively interpreted.

[0045] Figure 1 is a block diagram of a wireless communication device 1 according to an embodiment of the inventive concept. Figure 2 It shows Figure 1 A block diagram of the signal processing operation of the digital transmit processor 110 is shown in FIG.

[0046] Reference Figure 1 , a wireless communication device 1 according to an embodiment of the inventive concept may include a modem 100 , a radio frequency integrated circuit (RFIC) 200 , a power modulator 300 , a duplexer 400 , a power amplifier PA and / or an antenna ANT.

[0047] The modem 100 may include a digital transmission processor 110 , a digital reception processor 120 , a plurality of digital-to-analog converters (eg, a first DAC DAC1 and a second DAC DAC2 ), an analog-to-digital converter ADC, and / or a mobile industry processor interface (MIPI) 130 .

[0048] The modem 100 may process the baseband signal BB_T (e.g., including an I signal and a Q signal) including information to be transmitted by the digital transmission processor 110 according to a specific communication method. Furthermore, the modem 100 may process the baseband signal BB_R received by the digital reception processor 120 according to a specific communication method. For example, the modem 100 may process a signal to be transmitted or a signal to be received according to a communication method such as orthogonal frequency division multiplexing (OFDM), orthogonal frequency division multiple access (OFDMA), wideband code multiple access (WCDMA), high-speed packet access (HSPA+), etc. Furthermore, the modem 100 may process the baseband signal BB_T or BB_R according to various types of communication methods (e.g., various communication methods that apply a technique for modulating or demodulating the magnitude and / or frequency of the baseband signal BB_T or BB_R).

[0049] The modem 100 may extract the envelope of the baseband signal BB_T through the digital transmission processor 110 and generate a digital envelope signal D_ENV based on the extracted envelope. Here, the extracted envelope may correspond to the amplitude component of the baseband signal BB_T (for example, the magnitude of the I signal and the Q signal). In addition, the modem 100 may generate a digital envelope signal D_ENV based on the digital transmission processor 110. Figure 31 The average power signal D_REF is generated by using an average power tracking table (eg, APT table) in the memory 2200 in the memory.

[0050] For reference, the APT table may store information about the expected power supply voltage of the power amplifier PA according to the expected output power (or transmission power) of the antenna ANT, and may also store information about an average power signal corresponding to the expected power supply voltage of the power amplifier PA. Therefore, when the expected output power of the antenna ANT is determined, the modem 100 may generate an average power signal D_REF using the APT table and provide the generated average power signal D_REF as a reference voltage signal to the power modulator 300.

[0051] Here, refer to Figure 2 , which shows the detailed signal processing operation of the digital transmission processor 110.

[0052] In detail, in addition to the above-mentioned baseband signal processing operations, envelope extraction operations and digital envelope signal generation operations, the digital transmission processor 110 can also perform various operations by (for example, including) crest factor reduction (CFR) 111, shaping function (SF) 112, digital predistortion (DPD) 113, DELAY1 114, DELAY2 115, etc.

[0053] CFR 111 can reduce the peak-to-average power ratio (PAPR) of a communication signal (e.g., baseband signal BB_T). Furthermore, to improve the efficiency and linearity of the power amplifier (PA), SF 112 can transform the digital envelope signal D_ENV, and DPD 113 can compensate for and linearize the distortion of the power amplifier (PA) in the digital domain. Furthermore, DELAY1 114 can correct for the delay of the digital envelope signal D_ENV, and DELAY2 115 can correct for the delay of the baseband signal BB_T.

[0054] The digital transmission processor 110 having such a structure can output a digital envelope signal D_ENV and a baseband signal BB_T.

[0055] The digital envelope signal D_ENV is converted into an analog envelope signal A_ENV by the first digital-to-analog converter DAC1 and provided to the power modulator 300, or is directly provided to the power modulator 300 without digital-to-analog conversion. In addition, the digital envelope signal D_ENV can be provided to the power modulator 300 via MIPI 130. In addition, the baseband signal BB_T can be converted into a transmit signal TX by the second digital-to-analog converter DAC2 and provided to the transmit circuit TXC.

[0056] although Figure 2 Although not shown in the figure, the digital transmission processor 110 may also include internal components for processing the above operations (eg, baseband signal processing, envelope extraction, digital envelope signal generation, etc.). Figure 2The internal components of the digital transmission processor 110 shown in FIG. 1 are merely examples, but the embodiment is not limited thereto.

[0057] Refer again Figure 1 , the modem 100 can perform digital-to-analog conversion on each of the digital envelope signal D_ENV and the baseband signal BB_T by using the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 therein to generate an analog envelope signal A_ENV and a transmission signal TX as analog signals. In addition, the average power signal D_REF output from the modem 100 can be a digital signal. Therefore, the average power signal D_REF can be provided to the digital-to-analog converter included in the power modulator 300 via MIPI 130 and can be converted into an analog signal (e.g., a reference voltage signal) by the digital-to-analog converter included in the power modulator 300. For reference, the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 can operate at a relatively higher speed than the digital-to-analog converter included in the power modulator 300.

[0058] The inventive concept is not limited thereto, and the modem 100 may convert the average power signal D_REF into an analog signal through a digital-to-analog converter therein and output the analog signal. In this case, the modem 100 may provide the average power signal converted into an analog signal to the power modulator 300 as a reference voltage signal.

[0059] However, for convenience of explanation, a case in which the modem 100 provides the average power signal D_REF to the digital-to-analog converter included in the power modulator 300 via the MIPI 130 will be mainly described as an example.

[0060] For reference, the transmission signal TX and the analog envelope signal A_ENV may be differential signals each including a positive signal and a negative signal.

[0061] The modem 100 may receive a reception signal RX as an analog signal from the RFIC 200. Furthermore, the modem 100 may perform analog-to-digital conversion on the reception signal RX through an analog-to-digital converter ADC therein to extract a baseband signal BB_R as a digital signal. Here, the reception signal RX may be a differential signal including a positive signal and a negative signal.

[0062] The RFIC 200 may generate a radio frequency (RF) input signal RF_IN by performing frequency up-conversion on a transmission signal TX, or may generate a reception signal RX by performing frequency down-conversion on an RF reception signal RF_R.

[0063] In detail, the RFIC 200 may include a transmission circuit TXC for up-conversion, a reception circuit RXC for down-conversion, and / or a local oscillator LO.

[0064] Here, the transmitting circuit TXC may include a first analog baseband filter ABF1, a first mixer MX1 and / or an amplifier 210. For example, the first analog baseband filter ABF1 may include a low-pass filter.

[0065] The first analog baseband filter ABF1 can filter the transmit signal TX received from the modem 100 and provide it to the first mixer MX1. In addition, the first mixer MX1 can perform up-conversion to convert the frequency of the transmit signal TX from the baseband to a high frequency band using a frequency signal provided by the local oscillator LO. After the up-conversion, the transmit signal TX can be provided as an RF input signal RF_IN to the amplifier 210, and the amplifier 210 can perform a primary power amplification on the RF input signal RF_IN and provide it to the power amplifier PA.

[0066] The power amplifier PA can receive a power supply voltage (e.g., a dynamically variable output voltage) from the power modulator 300 and, based on the received power supply voltage, can amplify the power of the RF input signal RF_IN twice to generate an RF output signal RF_OUT. Furthermore, the power amplifier PA can provide the generated RF output signal RF_OUT to the duplexer 400.

[0067] The receiving circuit RXC may include a second analog baseband filter ABF2, a second mixer MX2 and / or a low noise amplifier 220. For example, the second analog baseband filter ABF2 may include a low-pass filter.

[0068] The low-noise amplifier 220 can amplify the RF receive signal RF_R received from the duplexer 400. Furthermore, the second mixer MX2 can down-convert the frequency of the RF receive signal RF_R from a high-frequency baseband to a baseband frequency using a frequency signal provided by the local oscillator LO. After down-conversion, the RF receive signal RF_R can be provided as a receive signal RX to the second analog baseband filter ABF2. The second analog baseband filter ABF2 can filter the receive signal RX and provide the filtered receive signal RX to the modem 100.

[0069] For reference, wireless communication device 1 can transmit and receive signals across multiple frequency bands using carrier aggregation (CA) technology. Furthermore, to this end, wireless communication device 1 may further include multiple power amplifiers for amplifying the power of multiple RF input signals corresponding to multiple carriers. However, in the embodiments of the inventive concept, for ease of explanation, a case where a single power amplifier PA is included will be described below as an example.

[0070] The power modulator 300 may generate an output voltage whose level changes dynamically based on the digital envelope signal D_ENV, the analog envelope signal A_ENV, and the average power signal D_REF, and may provide the output voltage as a power voltage to the power amplifier PA.

[0071] Specifically, the power modulator 300 can receive an average power signal D_REF, a digital envelope signal D_ENV, and an analog envelope signal A_ENV from the modem 100. Furthermore, based on the received average power signal D_REF, the digital envelope signal D_ENV, and the analog envelope signal A_ENV, the power modulator 300 can be driven in any one of the tracking modes: average power tracking (APT), discrete level envelope tracking (DL-ET), and continuous level envelope tracking (CL-ET), and generate a dynamically variable output voltage. Furthermore, the power modulator 300 can provide the generated output voltage as a power supply voltage to the power amplifier PA.

[0072] Here, when driven in the CL-ET mode, the power modulator 300 may receive the analog envelope signal A_ENV from the modem 100, and when driven in the DL-ET mode, the power modulator 300 may receive the digital envelope signal D_ENV from the modem 100. In addition, when the average power signal in the internal register (not shown) in the modem 100 is updated, the power modulator 300 may receive the average power signal D_REF from the modem 100.

[0073] For reference, when a power supply voltage having a fixed level is applied to the power amplifier PA, the power efficiency of the power amplifier PA is reduced. Therefore, for efficient power management of the power amplifier PA, the power amplifier PA may modulate an input voltage (e.g., a power supply provided from a battery or the like (e.g., an analog envelope signal A_ENV)) based on at least one of the digital envelope signal D_ENV, the analog envelope signal A_ENV, and the average power signal D_REF. Figure 4 VIN)), and the modulated voltage can be provided to the power amplifier PA as a power supply voltage.

[0074] The power modulator 300 according to an embodiment of the inventive concept may be driven in any one of three tracking modes (APT mode, CL-ET mode, and DL-ET mode) by considering power conversion efficiency and performance of the power modulator 300 .

[0075] Specifically, the power modulator 300 according to an embodiment of the inventive concept can separately include a switching regulator that supplies a current of a low-frequency component and a multi-output voltage regulator that supplies a current of a high-frequency component. Therefore, when driven in the DL-ET mode, the power modulator 300 according to an embodiment of the inventive concept can reduce the magnitude of the current flowing through the switch array, thereby reducing the heat loss (e.g., power loss) caused by the resistance components of the switch and reducing the size of the switch array.

[0076] In addition, the power supply modulator 300 according to an embodiment of the inventive concept may include a coupling capacitor located between the multi-output voltage regulator and the power amplifier PA. Therefore, in the power supply modulator 300, since the maximum output voltage of the multi-output voltage regulator (as used herein, the maximum output voltage or the maximum voltage level may refer to the upper limit output voltage and / or the upper limit voltage level, respectively) can be reduced, power efficiency can be improved and operating costs can be reduced. In addition, in the power supply modulator 300 according to an embodiment of the inventive concept, when the number of output voltages of the multi-output voltage regulator is reduced by the coupling capacitor, the number of output capacitors and switches connected to the multi-output voltage regulator can also be reduced.

[0077] On the other hand, in a power supply modulator of the related art, when any one of a plurality of voltages having levels different from each other generated by a multi-output voltage regulator is provided to a power amplifier PA as an output voltage (e.g., output current) via a switch, heat loss (e.g., power loss) occurs due to a resistance component of the switch when the output current passes through the switch.

[0078] In addition, to address the above challenges, as the size of a switch (eg, the size of a transistor) increases, the gate capacitance of the switch also increases, and thus, the power loss generated by charging and discharging the gate capacitor of the switch also increases.

[0079] In addition, a multi-output voltage regulator is used to generate and supply multiple voltages having different levels from each other (eg, a wide range of voltages to be generated and supplied), a voltage having a high output is difficult to generate and supply, and a large number of output capacitors and switches are used.

[0080] However, in the case of the power supply modulator 300 according to an embodiment of the inventive concept, as described above, the current of the low-frequency component (e.g., the current of the high output) is supplied by the switching regulator, and the current of the high-frequency component (e.g., the current of the low output) can be supplied by the multi-output voltage regulator. Therefore, compared with the prior art, the magnitude of the current flowing through the switch (e.g., the current output from the multi-output voltage regulator and passing through the switch) is reduced, and compared with the prior art, the heat loss (e.g., power loss) caused by the resistance component of the switch can also be reduced.

[0081] In addition, in the power supply modulator 300 according to the embodiment of the inventive concept, since the heat loss (e.g., power loss) caused by the resistance component of the switch is reduced without increasing the size of the switch, the size of the switch array can be reduced compared to the prior art. In addition, in the power supply modulator 300 according to the embodiment of the inventive concept, as the heat loss (e.g., power loss) caused by the resistance component of the switch is reduced, power efficiency can also be improved.

[0082] In addition, in the case of the power supply modulator 300 according to an embodiment of the inventive concept, the maximum output voltage and the number of output voltages of the multi-output voltage regulator can be reduced by the coupling capacitor. Therefore, compared with the prior art, the power supply modulator 300 according to the embodiment of the inventive concept is easier to generate and supply a high output voltage (because the voltage range to be generated and supplied is narrower than that of the prior art), and the number of output capacitors and switches is also reduced, so that power efficiency can be improved and operating costs can be reduced.

[0083] A more detailed description of the power supply modulator 300 will be given below.

[0084] The duplexer 400 may be connected to the antenna ANT and separate the transmit frequency from the receive frequency. Specifically, the duplexer 400 may separate the RF output signal RF_OUT received from the power amplifier PA for each frequency band and provide the RF output signal RF_OUT to the corresponding antenna ANT. In addition, the duplexer 400 may provide an external signal received from the antenna ANT to the low noise amplifier 220 of the receiving circuit RXC. For example, the duplexer 400 may include a front-end module (FEMiD) with an integrated duplexer.

[0085] The antenna ANT may transmit the RF output signal RF_OUT divided by the duplexer 400 to the outside, or may provide the RF reception signal RF_R received from the outside to the duplexer 400. For example, the antenna ANT may include an array antenna, but is not limited thereto.

[0086] For reference, the modem 100, the power modulator 300, the RFIC 200, the power amplifier PA, and / or the duplexer 400 may be implemented separately as an integrated circuit (IC), a chip, or a module. Furthermore, the modem 100, the power modulator 300, the RFIC 200, the power amplifier PA, and / or the duplexer 400 may be mounted together on a printed circuit board (PCB). However, the inventive concept is not limited thereto, and in an embodiment, at least some of the modem 100, the power modulator 300, the RFIC 200, the power amplifier PA, and the duplexer 400 may be implemented as a single communication chip.

[0087] in addition, Figure 1 The wireless communication device 1 shown in FIG may be included in a wireless communication system using a cellular network (such as NR, LTE, Advanced LTE, etc.), or may be included in a wireless local area network (WLAN) system (such as Wireless Fidelity (WiFi)) or any other wireless communication system. For reference, Figure 1 The structure of the wireless communication device 1 shown in FIG. 1 is merely an example, and the embodiment is not limited thereto, and various configurations may be made according to a communication protocol or a communication method.

[0088] Figure 3 is a block diagram of a wireless communication device 2 according to an embodiment of the inventive concept.

[0089] In addition to the contents related to the digital envelope signal D_ENV and the analog envelope signal A_ENV, the wireless communication device 2 has the following contents: Figure 1 The wireless communication device 1 has the same structure, function, effect, etc. or similar structure, function, effect, etc., and the differences will be mainly described below.

[0090] Reference Figure 3 , the wireless communication device 2 according to an embodiment of the inventive concept may include a modem 100 , an RFIC 200 , a power modulator 300 , a duplexer 400 , a power amplifier PA and / or an antenna ANT.

[0091] The modem 100 may process the baseband signal BB_T through the first digital transmission processor 110 according to a predetermined communication method, or alternatively, according to a given communication method. In addition, the modem 100 may provide the processed baseband signal BB_T to the RFIC 200 through the digital interface DI. In addition, the modem 100 may extract the envelope of the baseband signal BB_T through the first digital transmission processor 110 and generate the average power signal D_REF based on the extracted envelope.

[0092] Here, the average power signal D_REF may be provided to the power modulator 300 as a reference voltage signal. That is, the average power signal D_REF output from the modem 100 may be a digital signal. Therefore, the average power signal D_REF may be provided to the digital-to-analog converter included in the power modulator 300 via the MIPI 130 and may be converted into an analog signal (e.g., a reference voltage signal) by the digital-to-analog converter included in the power modulator 300. For reference, the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 included in the RFIC 200 may operate at a relatively higher speed than the digital-to-analog converter included in the power modulator 300.

[0093] The RFIC 200 may receive a baseband signal BB_T from the modem 100 via the digital interface DI, and the baseband signal BB_T may be provided to the second digital transmit processor 205 within the RFIC 200. The second digital transmit processor 205 may extract an envelope of the baseband signal BB_T and generate and output a digital envelope signal D_ENV based on the extracted envelope. For reference, the second digital transmit processor 205 may output the baseband signal BB_T received via the digital interface DI.

[0094] The digital envelope signal D_ENV and the baseband signal BB_T output from the second digital transmit processor 205 can be provided to the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 within the RFIC 200, respectively. The first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 can perform digital-to-analog conversion on the digital envelope signal D_ENV and the baseband signal BB_T and generate an analog envelope signal A_ENV and a transmit signal TX as analog signals. The digital envelope signal D_ENV output from the second digital transmit processor 205 can be directly provided to the power supply modulator 300 without passing through the digital-to-analog converter.

[0095] The RFIC 200 may generate an RF input signal RF_IN by performing up-conversion on the transmission signal TX through the transmission circuit TXC, and may provide a digital envelope signal D_ENV and an analog envelope signal A_ENV to the power modulator 300 .

[0096] The power modulator 300 may generate a voltage whose level dynamically changes based on the digital envelope signal D_ENV, the analog envelope signal A_ENV, and the average power signal D_REF, and may provide the voltage as a power supply voltage to the power amplifier PA.

[0097] Specifically, the power modulator 300 may receive an average power signal D_REF from the modem 100 and may receive a digital envelope signal D_ENV and an analog envelope signal A_ENV from the RFIC 200. Furthermore, the power modulator 300 may be driven in any one of three tracking modes (APT mode, CL-ET mode, and DL-ET mode) based on the received average power signal D_REF, digital envelope signal D_ENV, and analog envelope signal A_ENV, and generate a dynamically variable output voltage. Furthermore, the power modulator 300 may supply the generated output voltage as a power supply voltage to the power amplifier PA.

[0098] Here, when driving in the CL-ET mode, the power modulator 300 can receive the analog envelope signal A_ENV from the RFIC 200, and when driving in the DL-ET mode, the power modulator 300 can receive the digital envelope signal D_ENV from the RFIC 200. In addition, when the average power signal in the internal register (not shown) in the modem 100 is updated, the power modulator 300 can receive the average power signal D_REF from the modem 100. The power modulator 300 can receive each of the average power signal D_REF, the digital envelope signal D_ENV, and the analog envelope signal A_ENV at times other than the above-mentioned times. However, in the embodiments of the inventive concept, for ease of explanation, the case where the power modulator 300 receives each of the average power signal D_REF, the digital envelope signal D_ENV, and the analog envelope signal A_ENV at the above-mentioned times is described as an example.

[0099] As a reference, Figure 3 The structure of the wireless communication device 2 shown in FIG. 1 is merely an example, and the embodiment is not limited thereto, and various configurations may be made according to the communication protocol or the communication method.

[0100] As described above, each of the wireless communication devices 1 and 2 according to the embodiment of the inventive concept has the above-mentioned structure and characteristics, and hereinafter, referring to Figures 4 to 12 , a first example of the power modulator 300 included in the wireless communication devices 1 and 2 according to an embodiment of the inventive concept will be described.

[0101] Figure 4 is a circuit diagram illustrating a first example of a power modulator included in a wireless communication device according to an embodiment of the inventive concept. Figure 5 It shows Figure 4 FIG. 1 is a diagram of an example of a multiple-output voltage regulator 310 . Figure 6 It shows Figure 4 FIG. 1 is a diagram of another example of a multiple-output voltage regulator 310 . Figure 7 It shows Figure 4 FIG. 1 is a diagram of another example of a multiple-output voltage regulator 310 . Figure 8 is a graph showing waveform characteristics of the output voltage according to the tracking mode. Figure 9 is a graph showing the output voltage generation mechanism in envelope tracking mode. Figure 10 It shows Figure 4 FIG. 1 is a diagram illustrating the APT mode operation of the power supply modulator 300 - 1 . Figure 11 It shows Figure 4 FIG. 3 is a diagram illustrating the DL-ET mode operation of the power supply modulator 300 - 1 . Figure 12 It shows Figure 4 FIG. 3 is a diagram illustrating the CL-ET mode operation of the power supply modulator 300 - 1 .

[0102] For reference, in the following, for ease of explanation, it is assumed that the power supply modulator 300-1 is implemented as Figure 1 The power supply modulator 300 of the wireless communication device 1 shown in FIG. Figure 1 describe Figure 4 .

[0103] Reference Figure 4 , a first example of a power modulator 300 according to an embodiment of the inventive concept (i.e., power modulator 300-1) may include a multi-output voltage regulator 310, a switching regulator 330, a linear regulator LA, a switching regulator controller 350, a main controller 360, a switch array 370, a switch controller 380 and / or a discrete level controller 390.

[0104] For reference, each component may include a component-specific controller (e.g., switching regulator controller 350) therein or externally, and each dedicated controller may be controlled by main controller 360. In addition, there may be a controller that integrates and controls at least two components, and the corresponding controllers may be controlled by main controller 360.

[0105] However, for ease of explanation, only dedicated controllers of some components will be described in detail below.

[0106] In order to generate the output voltage VET_APT together with the switching regulator 330 in the DL-ET mode, the multi-output voltage regulator 310 can output a plurality of voltages V1 to VN (where N is a natural number of two or greater) having different levels from each other to correspond to a plurality of reference output voltage signals VREF1 to VREFN (where N is a natural number of two or greater). In addition, the multi-output voltage regulator 310 can be controlled by the main controller 360.

[0107] That is, when the multi-output voltage regulator 310 is connected in parallel with the switching regulator 330, the multi-output voltage regulator 310 can generate the output voltage VET_APT by operating in parallel with the switching regulator 330 in the DL-ET mode. In addition, the multi-output voltage regulator 310 can generate and output a plurality of voltages V1 to VN having different levels from each other by raising or lowering an input voltage (e.g., a power source VIN provided from a battery, etc.) based on a plurality of reference output voltage signals VREF1 to VREFN.

[0108] Here, a plurality of reference output voltage signals VREF1 to VREFN may be received from the main controller 360. For reference, the modem 100 may calculate a reference output voltage value based on the output power of the power amplifier PA and provide the calculated reference output voltage value to the main controller 360. In addition, the main controller 360 may generate a plurality of reference output voltage signals VREF1 to VREFN based on the received reference output voltage value and provide the plurality of reference output voltage signals VREF1 to VREFN to at least one of the multi-output voltage regulator 310 and the switching regulator controller 350.

[0109] In addition, the connection between the multi-output voltage regulator 310 and the power amplifier PA can be selectively connected and disconnected by the switch array 370. That is, through the switching operation of the switch array 370, at least one voltage among the plurality of voltages V1 to VN having different levels from each other generated and output from the multi-output voltage regulator 310 (for example, V1 to VN are generated and output in a time-division method) can be selected, and the selected voltage can be provided to the power amplifier PA.

[0110] In addition, the output terminal of the multi-output voltage regulator 310 may include a plurality of capacitors C1 to CN (where N is a natural number of two or greater) corresponding to a plurality of voltages V1 to VN having different levels from each other, and the connection between the plurality of capacitors C1 to CN and the power amplifier PA may be individually switched on and off by a plurality of switches S1 to SN (where N is a natural number of two or greater). The plurality of capacitors C1 to CN may be provided outside the multi-output voltage regulator 310 rather than inside. However, for ease of explanation, in the embodiment of the inventive concept, the case where the plurality of capacitors C1 to CN are included in the multi-output voltage regulator 310 is described as an example.

[0111] Reference Figures 5 to 7 , various implementation examples of the multi-output voltage regulator 310 (eg, the multi-output voltage regulators 310 - 1 to 310 - 3 ) are shown.

[0112] First, refer to Figure 5, the multi-output voltage regulator 310 - 1 may include, for example, a plurality of single output voltage regulators SOVR1 to SOVRN (where N is a natural number of two or greater) that respectively output a plurality of voltages V1 to VN having different levels from each other.

[0113] Here, each of the plurality of single output voltage regulators SOVR1 to SOVRN may include, for example, a switching regulator such as a buck converter and a boost converter, or may include a switched capacitor direct current (DC)-DC converter, a low dropout regulator (LDO), or the like.

[0114] Furthermore, in the plurality of single output voltage regulators SOVR1 to SOVRN, there may be a controller for each of the single output voltage regulators individually, or there may be one common controller.

[0115] Then, refer to Figure 6 , the multiple-output voltage regulator 310 - 2 may include, for example, a single-inductor multiple-output (SIMO) DC-DC converter or a SIMO buck-boost converter.

[0116] In detail, Figure 6 The multi-output voltage regulator 310 - 2 may be a structure that supplies the output current of a switching regulator (SR) in a SIMO DC-DC converter or a SIMO buck-boost converter to each output terminal through a single inductor L′ in a time-division method.

[0117] Furthermore, SIMO controller 312 may monitor the difference between each of the plurality of output voltages V1 to VN and each of the plurality of reference output voltage signals VREF1 to VREFN corresponding to each of the plurality of output voltages V1 to VN, and may determine, based on the monitoring result, which switch to turn on among switches S1M, S2M, ..., SNM connected to inductor L' and each of the plurality of output voltages V1 to VN. Simultaneously or concurrently, SIMO controller 312 may determine switch input SW_SIMO of the SR connected to one side of inductor L' based on information about the difference between each of the plurality of output voltages V1 to VN and each of the plurality of reference output voltage signals VREF1 to VREFN corresponding to each of the plurality of output voltages V1 to VN.

[0118] For reference, in an embodiment of the inventive concept, since the output current IHF of the multi-output voltage regulator 310 is not large (i.e., most of the output current IET_APT is supplied by the switching regulator 330 (e.g., ILF)), the multi-output voltage regulator 310 is suitable for applying a SIMO DC-DC converter or a SIMO buck-boost converter that supplies outputs in a time-division method. In addition, the SIMO DC-DC converter can operate in both the buck mode and the buck-boost mode.

[0119] Finally, refer to Figure 7 The multi-output voltage regulator 310-3 may include, for example, a boost converter (including converters of VIN, L, SN, SP) and a plurality of LDOs LDO1 to LDO(N-1) (where N is a natural number of two or greater), the boost converter generating a voltage with a highest level (e.g., V1) among a plurality of voltages V1 to VN having voltages different from one another, and the plurality of LDOs LDO1 to LDO(N-1) generating the remaining voltages (or referred to as a voltage subset) V2 to VN among the plurality of voltages V1 to VN having voltages different from one another by using the voltage with the highest level generated by the boost converter as an input.

[0120] In addition, the boost converter controller 314 can monitor the difference between the output voltage V1 of the boost converter (e.g., the voltage with the highest level) and the reference output voltage signal VREF1 corresponding to the output voltage V1 of the boost converter, and determine the switch to be turned on among the switches SN and SP based on the monitoring result.

[0121] As described above, the multi-output voltage regulator 310 may be implemented in various forms. The multi-output voltage regulator 310 may include a structure different from the above structure, and a detailed description thereof will be omitted.

[0122] Return to reference Figure 4 The linear regulator LA may operate in the CL-ET mode to generate an output voltage VET_APT based on an analog envelope signal A_ENV received from the outside. In addition, the linear regulator LA may be controlled by the main controller 360 .

[0123] In detail, the linear regulator LA may receive the analog envelope signal A_ENV from the modem 100 and may amplify and output the analog envelope signal A_ENV. Therefore, the linear regulator LA may operate in parallel with the switching regulator 330 in the CL-ET mode to generate the output voltage VET_APT.

[0124] In addition, despite Figure 4Although not shown in the figure, the linear regulator LA can receive an input voltage (e.g., a power source provided from a battery or the like) as a power supply voltage, or can receive a power supply voltage from a separate voltage regulator. In addition, the linear regulator LA can also receive any one of a plurality of voltages V1 to VN having different levels output from the multi-output voltage regulator 310 as a power supply voltage.

[0125] In addition, the linear regulator LA may be connected in parallel with the switching regulator 330 and may be implemented as a linear amplifier, for example. Figure 4 As shown in , the linear regulator LA may be implemented as a differential amplifier and may receive the positive signal ENV_P and the negative signal ENV_N of the analog envelope signal A_ENV through the positive terminal + and the negative terminal −, respectively.

[0126] In addition, despite Figure 4 Although not shown in the figure, the output of the linear regulator LA can be fed back to the negative terminal - of the linear regulator LA through a feedback unit (not shown), and the output level of the linear regulator LA can be adjusted to a desired level. That is, the feedback unit can adjust the output level of the linear regulator LA to a desired level by making the voltage output from the linear regulator LA and the power supply voltage input to the linear regulator LA have a linear relationship.

[0127] In addition, although Figure 4 Although not shown, noise can be removed from the analog envelope signal A_ENV input to the linear regulator LA by a noise removal unit (not shown). Specifically, the noise removal unit can remove noise from the analog envelope signal A_ENV provided to the linear regulator LA and provide the noise-removed analog envelope signal A_ENV to the linear regulator LA. For reference, the noise removal unit can include, for example, a low-pass filter or an input buffer. Here, the low-pass filter can have characteristics that enable a specific gain value while removing high-frequency noise from the image signal or frequency band of the digital-to-analog converter. Furthermore, although the noise removal performance is not as good as that of a low-pass filter, the input buffer can have characteristics that enable broadband operation due to its wide coverage bandwidth.

[0128] The switching regulator 330 can operate with the multi-output voltage regulator 310 to generate the output voltage VET_APT in the DT-EL mode, and can operate with the linear regulator LA to generate the output voltage VET_APT in the CL-ET mode. Furthermore, the switching regulator 330 can operate in the APT mode to generate the output voltage VET_APT. Furthermore, the switching regulator 330 can be controlled by a switching regulator controller 350.

[0129] Specifically, the switching regulator 330 can operate in parallel with the multi-output voltage regulator 310 in the DL-ET mode, and can operate in parallel with the linear regulator LA in the CL-ET mode. That is, in the DL-ET mode or the CL-ET mode, the switching regulator 330 can increase or decrease the output voltage VET_APT by controlling the on or off of the switch therein based on the switching regulator control signal SRC received from the switching regulator controller 350.

[0130] Here, in the DL-ET mode or the CL-ET mode, the switching regulator control signal SRC provided to the switching regulator 330 may be generated based on the output of the compensation comparator CCP in the switching regulator controller 350 .

[0131] In addition, in the DL-ET mode, the sum current IET_APT of the output current ILF of the switching regulator 330 and the output current IHF of the multi-output voltage regulator 310 can be provided to the power amplifier PA. In this case, the output current ILF of the switching regulator 330 can be controlled based on the switching regulator control signal SRC so that the average value of the output current IHF of the multi-output voltage regulator 310 is approximately zero.

[0132] For reference, the output current ILF of the switching regulator 330 may include a current with a low frequency component (eg, a frequency less than 1 MHz), and the output current IHF of the multi-output voltage regulator 310 may include a current with a high frequency component (eg, a frequency greater than 1 MHz).

[0133] On the other hand, in the CL-ET mode, the sum current IET_APT of the output current ILF of the switching regulator 330 and the output current IHF of the linear regulator LA may be provided to the power amplifier PA. In this case, the output current ILF of the switching regulator 330 may be controlled based on the switching regulator control signal SRC so that the average value of the output current IHF of the linear regulator LA is approximately zero.

[0134] For reference, the output current ILF of the switching regulator 330 may include a current of a low-frequency component (eg, a frequency less than 1 MHz), and the output current IHF of the linear regulator LA may include a current of a high-frequency component (eg, a frequency greater than 1 MHz).

[0135] The voltage VSR output from the switching regulator 330 may be provided to the power amplifier PA through the inductor L as an output voltage VET_APT.

[0136] Here, the inductor L may be a power inductor of the switching regulator 330. Therefore, the inductor L may be connected to the output terminal of the switching regulator 330 and support a continuous current waveform.

[0137] For reference, the inductor L may not be included in the switching regulator 330. That is, the inductor L may be provided outside the switching regulator 330. However, for convenience of explanation, in the embodiment of the inventive concept, a case where the inductor L is included in the switching regulator 330 is described as an example.

[0138] In the APT mode, the switching regulator 330 can independently regulate an input voltage (e.g., a power source VIN provided from a battery, etc.) to a target level based on a switching regulator control signal SRC received from the switching regulator controller 350. In addition, the switching regulator 330 can provide the regulated voltage VSR as an output voltage VET_APT to the power amplifier PA.

[0139] Here, in the APT mode, the switching regulator control signal SRC provided to the switching regulator 330 may be generated based on the output of the output comparator OCP in the switching regulator controller 350 .

[0140] For reference, the switching regulator 330 may include, for example, a two-phase hybrid buck-boost converter, but is not limited thereto. That is, the switching regulator 330 may include a buck converter, a boost converter, a buck-boost converter, a Cuk converter, or another DC-DC converter.

[0141] Furthermore, unlike the above description, in the DL-ET mode, the switching regulator 330 and the linear regulator LA can operate together to generate the output voltage VET_APT, and in the CL-ET mode, the switching regulator 330 and the multi-output voltage regulator 310 can operate together to generate the output voltage VET_APT. Furthermore, all of the switching regulator 330, the linear regulator LA, and the multi-output voltage regulator 310 can operate together to generate the output voltage VET_APT. Furthermore, in each of the DL-ET mode, the CL-ET mode, and the APT mode, a driving agent other than the driving agent described herein can operate.

[0142] However, for ease of explanation, in the embodiments of the inventive concept, the cases where the switching regulator 330 and the multi-output voltage regulator 310 operate together in the DL-ET mode, the switching regulator 330 and the linear regulator LA operate together in the CL-ET mode, and the switching regulator 330 operates in the APT mode are described as examples.

[0143] The switching regulator controller 350 can selectively sense the output current of the multi-output voltage regulator 310 and / or the output current of the linear regulator LA according to the tracking mode, and can control the switching regulator 330 based on the sensed value SV. In addition, the switching regulator controller 350 can be controlled by the main controller 360.

[0144] In detail, the switching regulator controller 350 may include a feedback loop FL, a plurality of transconductance operational amplifiers (OTAs) OTA1 to OTAN (where N is a natural number of two or greater), a first multiplexer MUX1, a second multiplexer MUX2, a summer ADD, a compensation comparator CCP, a digital-to-analog converter DAC, and / or an output comparator OCP.

[0145] The feedback loop FL may obtain (eg, sense) the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA.

[0146] That is, in the DL-ET mode, the feedback loop FL can sense the output current IHF of the multi-output voltage regulator 310 and provide the sensed value SV to the summer ADD. Conversely, in the CL-ET mode, the feedback loop FL can sense the output current IHF of the linear regulator LA and provide the sensed value SV to the summer ADD.

[0147] For reference, IHF may refer to the output current of the multi-output voltage regulator 310 in the DL-ET mode, and may refer to the output current of the linear regulator LA in the CL-ET mode. SV may refer to the sensed value of the output current of the multi-output voltage regulator 310 in the DL-ET mode, and may refer to the sensed value of the output current of the linear regulator LA in the CL-ET mode. Here, the sensed value SV may be, for example, a current value or a voltage value, but is not limited thereto.

[0148] The plurality of OTAs OTA1 to OTAN may output difference values by respectively comparing a plurality of voltages V1 to VN having levels different from each other with a plurality of reference output voltage signals VREF1 to VREFN.

[0149] That is to say, although Figure 4Although not shown in the figure, the plurality of OTAs OTA1 to OTAN may receive information about the plurality of voltages V1 to VN having different levels from each other output from the multi-output voltage regulator 310, and may receive information about the plurality of reference output voltage signals VREF1 to VREFN from the main controller 360. Therefore, the plurality of OTAs OTA1 to OTAN may respectively compare the voltage having a specific level with a specific reference output voltage signal corresponding to the voltage having the specific level, and output a difference DV between the voltage having the specific level and the specific reference output voltage signal corresponding to the voltage having the specific level based on the comparison result.

[0150] For example, the first OTA OTA1 may compare the first voltage V1 having the first level with the first reference output voltage signal VREF1 and output a difference between the first voltage V1 having the first level and the first reference output voltage signal VREF1 based on the comparison result.

[0151] For reference, the difference value DV output from the OTA may be a current value or a voltage value proportional to the difference between the voltage of each level and a reference output voltage signal corresponding to the voltage of each level, but is not limited thereto.

[0152] The first multiplexer MUX1 may select and output one difference value DV among the difference values DV output from the plurality of OTAs OTA1 to OTAN based on the level control signal ENV_LV received from the discrete level controller 390 .

[0153] That is, the first multiplexer MUX1 can receive the level control signal ENV_LV from the discrete level controller 390 and select and output one of the difference values DV output from the plurality of OTAs OTA1 to OTAN based on the level control signal ENV_LV received from the discrete level controller 390. Furthermore, the output difference DV can be provided to the summer ADD. Furthermore, the first multiplexer MUX1 can operate in the DL-ET mode as described above under the control of the main controller 360.

[0154] According to the tracking mode, the summer ADD may sum the difference value DV output from the first multiplexer MUX1 and the sensed value SV of the output current IHF of the multi-output voltage regulator 310 sensed by the feedback loop FL and output the summed value as the compensation value CV, or may output the sensed value SV of the output current IHF of the linear regulator LA sensed by the feedback loop FL as the compensation value CV.

[0155] That is, in the DL-ET mode, the summer ADD may sum the difference value DV output from the first multiplexer MUX1 with the sensed value SV of the output current IHF of the multi-output voltage regulator 310 sensed by the feedback loop FL, and output the summed value as the compensation value CV. Conversely, in the CL-ET mode, the summer ADD may output the sensed value SV of the output current IHF of the linear regulator LA sensed by the feedback loop FL as the compensation value CV. Furthermore, the compensation value CV output from the summer ADD may be provided to the compensation comparator CCP.

[0156] For reference, the compensation value CV output from the summer ADD may be in the form of, for example, a current value or a voltage value, but is not limited thereto.

[0157] The compensation comparator CCP may compare the compensation value CV output from the summer ADD with a reference value.

[0158] That is, the compensation comparator CCP can receive the compensation value CV output from the summer ADD through the positive terminal + and receive the reference value through the negative terminal -. In addition, the compensation comparator CCP can output the comparison result between the received compensation value CV and the reference value to the second multiplexer MUX2.

[0159] In more detail, when the compensation value CV is greater than the reference value, the compensation comparator CCP can output a high-level signal (e.g., "1"), and when the compensation value CV is less than the reference value, the compensation comparator CCP can output a low-level signal (e.g., "0").

[0160] As a reference, the negative terminal - may be grounded, and in this case the reference value may be zero.

[0161] The digital-to-analog converter DAC may convert the average power signal D_REF received from the outside into a reference voltage signal A_REF.

[0162] That is, the digital-to-analog converter DAC may receive the average power signal D_REF from the modem 100 via the MIPI 130 and may convert the received average power signal D_REF into a reference voltage signal A_REF and output the reference voltage signal A_REF to the output comparator OCP.

[0163] The output comparator OCP may compare the reference voltage signal A_REF converted by the digital-to-analog converter DAC with the output voltage VET_APT.

[0164] That is, the output comparator OCP can receive the reference voltage signal A_REF converted by the digital-to-analog converter DAC through the positive terminal +, and can receive the output voltage VET_APT through the negative terminal -. In addition, the output comparator OCP can output the comparison result between the received reference voltage signal A_REF and the output voltage VET_APT to the second multiplexer MUX2.

[0165] The second multiplexer MUX2 may output one of the output of the compensation comparator CCP and the output of the output comparator OCP to the switching regulator 330 as the switching regulator control signal SRC.

[0166] That is, in the APT mode, the second multiplexer MUX2 can output the output of the output comparator OCP as the switching regulator control signal SRC to the switching regulator 330, and in the ET mode (for example, the DL-ET mode or the CL-ET mode), the second multiplexer MUX2 can output the output of the compensation comparator CCP as the switching regulator control signal SRC to the switching regulator 330.

[0167] For reference, in the DL-ET mode, the switching regulator 330 may output an output current ILF based on the switching regulator control signal SRC received from the second multiplexer MUX2. Furthermore, the output current ILF may charge and discharge a capacitor (e.g., C1) connected to the switch (e.g., S1) through a turned-on switch (e.g., S1) among the plurality of switches S1 to SN.

[0168] As described above, the switching regulator controller 350 can selectively sense one of the output currents of the multi-output voltage regulator 310 and / or the linear regulator LA based on the above structure and characteristics, and can control the switching regulator 330 based on the sensed value SV.

[0169] As a reference, although Figure 4 Although not shown in FIG, the switching regulator controller 350 may sense factors other than the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA, and may control the switching regulator 330 based on the corresponding sensed values. That is, the feedback loop FL may sense factors other than the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA, and may provide the sensed values to the summer ADD. When the feedback loop FL senses different factors, the feedback loop FL may sense factors other than the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA, and may provide the sensed values to the summer ADD. Figure 4 The feedback loop can be configured with different paths than the path shown.

[0170] For example, switching regulator controller 350 may sense the following factors.

[0171] 1) The internal current of the multi-output voltage regulator 310 (eg, flowing through the internal inductor (eg, Figure 6 the current flowing through the internal LDOs (e.g., LDO1 to LDO(N-1)), or the current flowing through the capacitors (e.g., C1 to CN);

[0172] 2) current applied to the multi-output voltage regulator 310 from an input voltage (eg, a power source provided from a battery, etc.; VIN); and / or

[0173] 3) The internal voltage of the multi-output voltage regulator 310 (eg, the internal switch (eg, Figure 6 The voltage of the switch S1M to SNM), the internal LDO (for example, Figure 7 The gate voltage of LDO1 to LDO(N-1)).

[0174] However, for ease of explanation, in an embodiment of the inventive concept, a case is described as an example in which the switching regulator controller 350 selectively senses one of the output currents of the multi-output voltage regulator 310 and / or the output current of the linear regulator LA, and controls the switching regulator 330 based on the sensed value SV.

[0175] The switch array 370 may include a plurality of switches S1 to SN (where N is a natural number of two or greater) corresponding to the plurality of voltages V1 to VN having different levels output from the multi-output voltage regulator 310. Furthermore, switching operations of the plurality of switches S1 to SN in the switch array 370 may be controlled by a switch control signal SW provided from the switch controller 380. Thus, the switch array 370 may select one of the plurality of voltages V1 to VN having different levels based on the switch control signal SW and provide the selected voltage to the power amplifier PA.

[0176] The discrete level controller 390 may generate a level control signal ENV_LV including a plurality of pieces of envelope level information based on a digital envelope signal D_ENV received from the outside.

[0177] In detail, the discrete level controller 390 may receive the digital envelope signal D_ENV from the modem 100, and generate and output a level control signal ENV_LV including a plurality of pieces of envelope level information based on the digital envelope signal D_ENV received from the modem 100. In addition, the level control signal ENV_LV output from the discrete level controller 390 may be provided to the switch controller 380 and the switching regulator controller 350 (e.g., the first multiplexer MUX1).

[0178] The switch controller 380 may receive the level control signal ENV_LV from the discrete level controller 390 and control the switching operation of the plurality of switches S1 to SN based on the level control signal ENV_LV received from the discrete level controller 390. That is, the switch controller 380 may generate the switch control signal SW for controlling the switching operation of the switch array 370 and provide the generated switch control signal SW to the switch array 370. In addition, the switch controller 380 may be controlled by the main controller 360.

[0179] In detail, in the DL-ET mode, the switch controller 380 may control a switching operation of the switch array 370 to select a voltage to be supplied to the power amplifier PA from among a plurality of voltages V1 to VN having levels different from each other.

[0180] Furthermore, in the APT mode, the switch controller 380 may control at least one of the plurality of switches S1 to SN to connect a capacitor corresponding to the controlled switch among the plurality of capacitors C1 to CN to the power amplifier PA.

[0181] This is because in the APT mode, a decoupling capacitor connected to the output voltage VET_APT is used.

[0182] Therefore, in the APT mode, the switch controller 380 may control the switch array 370 to connect at least one capacitor among the plurality of capacitors C1 to CN of the multi-output voltage regulator 310 to the power amplifier PA. In addition, the capacitor connected to the power amplifier PA may be used as a decoupling capacitor.

[0183] The main controller 360 may generate a plurality of reference output voltage signals VREF1 to VREFN to provide the plurality of reference output voltage signals VREF1 to VREFN to at least one of the multi-output voltage regulator 310 and the switching regulator controller 350. In addition, the main controller 360 may determine a tracking mode and control at least one of the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390 based on the determined tracking mode.

[0184] In detail, the main controller 360 can communicate with the host controller 360 via MIPI ( Figure 1 130) receives the tracking mode determination signal from the modem 100 and determines the tracking mode of the power modulator 300-1.

[0185] Therefore, when the tracking mode is determined to be the DL-ET mode, the main controller 360 may control the parallel operation of the multi-output voltage regulator 310 and the switching regulator 330. In this case, the multi-output voltage regulator 310 and the switching regulator 330 may jointly generate a modulation voltage according to the DL-ET mode and provide the generated modulation voltage to the power amplifier PA as the output voltage VET_APT.

[0186] Subsequently, when the tracking mode is determined to be the CL-ET mode, the main controller 360 may control the parallel operation of the linear regulator LA and the switching regulator 330. In this case, the linear regulator LA and the switching regulator 330 may jointly generate a modulation voltage according to the CL-ET mode and provide the generated modulation voltage to the power amplifier PA as the output voltage VET_APT.

[0187] Finally, when the tracking mode is determined to be the APT mode, the main controller 360 may control the output voltage generation operation of the switching regulator 330. In this case, the switching regulator 330 may generate a modulation voltage according to the APT mode and provide the generated modulation voltage to the power amplifier PA as the output voltage VET_APT.

[0188] In the APT mode, the switch controller 380 may control the switching operation of the switch array 370 to activate some of the plurality of capacitors C1 to CN as decoupling capacitors.

[0189] The main controller 360 can receive various signals (e.g., various control signals (such as output voltage level signals, etc.)) other than the tracking mode determination signal from the modem 100 via the MIPI 130, and control components (such as the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390) based on the received various signals.

[0190] As a reference, in Figure 4 , the main controller 360 is shown as controlling at least one of the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390, but is not limited thereto. That is, the main controller 360 may control the operation of components other than the above components.

[0191] However, for ease of explanation, in the embodiments of the inventive concept, a case where the main controller 360 controls at least one of the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350 and the discrete level controller 390 is described as an example.

[0192] In addition to the above components, the power supply modulator 300 - 1 may further include an additional capacitor (not shown), an oscillator (not shown), a bandgap reference circuit (not shown), and the like.

[0193] Specifically, an additional capacitor may be connected near the output terminal of power supply modulator 300-1 to remove parasitic capacitance and high-frequency noise that may be present in the circuit of power supply modulator 300-1. Furthermore, an oscillator is a circuit employed when an n-channel metal oxide semiconductor (NMOS) structure (e.g., a gate-boosted NMOS structure) is used to improve the characteristics of the plurality of switches S1 to SN. Furthermore, a bandgap reference circuit is a circuit that supplies a reference voltage or current used when each component operates, and is largely unaffected by changes in operation, voltage, or temperature.

[0194] As described above, the power modulator 300-1 can have the above-mentioned structure and characteristics. In addition, based on the structure and characteristics, the power modulator 300-1 can be driven in any one of the tracking modes of the DL-ET mode, the CL-ET mode, and / or the APT mode, and provide the output voltage VET_APT to the power amplifier PA.

[0195] Therefore, refer to Figure 8 , shows the waveform characteristics of the output voltage according to the tracking mode.

[0196] In detail, Figure 8 An output voltage waveform APT (whose voltage is V′) according to the APT mode, an output voltage waveform DL-ET according to the DL-ET mode, and an output voltage waveform CL-ET according to the CL-ET mode are shown.

[0197] Here, the APT mode is a mode in which a modulation voltage that varies based on the peak level of the envelope RF_OUT_ENV of the RF output signal RF_OUT at a specific time interval (eg, a transmission time interval (TTI)) is applied to the power amplifier ( Figure 1 In addition, the CL-ET mode is a tracking mode in which a modulation voltage that follows the level of the envelope RF_OUT_ENV of the RF output signal RF_OUT is applied instantaneously or rapidly to the power amplifier ( Figure 1 In addition, the DL-ET mode is a tracking mode in which a modulation voltage following the level of the envelope RF_OUT_ENV of the RF output signal RF_OUT is applied to the power amplifier ( Figure 1 A tracking mode of the PA) is configured in which the modulation voltage is limited to a plurality of voltages having levels different from each other generated by the multi-output voltage regulator 310.

[0198] For reference, the envelope RF_OUT_ENV of the RF output signal RF_OUT may be generated based on the amplitude (magnitude) of the RF output signal RF_OUT.

[0199] Then, Figure 9 3 shows a mechanism by which the power modulator 300 - 1 generates the output voltage VET_APT in the ET mode (DL-ET mode or CL-ET mode).

[0200] Reference Figure 4 and Figure 9 In the ET mode (DL-ET mode or CL-ET mode), the switching regulator 330 may supply the output current ILF of the low-frequency component based on the switching regulator control signal SRC.

[0201] In detail, when the magnitude of the output current ILF of the switching regulator 330 is smaller than the magnitude of the output current ILF to be supplied to the power amplifier ( Figure 1 PA) and the magnitude of the current IET_APT, the multi-output voltage regulator 310 and / or the linear regulator LA can provide the power amplifier ( Figure 1 For reference, when the switching regulator control signal SRC is a low-level signal, the output current ILF of the switching regulator 330 may be smaller than that of the power amplifier ( Figure 1 PA) expected and current IET_APT size.

[0202] On the contrary, when the magnitude of the output current ILF of the switching regulator 330 is greater than that to be supplied to the power amplifier ( Figure 1 When the magnitude of the output current I ET_APT of the PA) is greater than that of the output current I ET_APT of the PA), the multi-output voltage regulator 310 or the linear regulator LA may absorb the overcurrent (for example, the output current I HF of the high frequency component). For reference, when the switching regulator control signal S RC is a high level signal, the magnitude of the output current I LF of the switching regulator 330 may be greater than that of the power amplifier ( Figure 1 PA) expected and current IET_APT size.

[0203] As described above, the power modulator 300-1 according to an embodiment of the inventive concept may generate a modulation voltage that varies according to any one of the tracking modes of the APT mode, the DL-ET mode, and / or the CL-ET mode to provide the generated modulation voltage as a power voltage to the power amplifier ( Figure 1 PA).

[0204] In addition, based on the above characteristics, as the power amplifier ( Figure 1The RF output signal RF_OUT of the PA) and the modulation voltage of the power modulator 300-1 (for example, will be provided to the power amplifier ( Figure 1 By reducing the voltage difference between the output voltages VET_APT of the PA), energy waste can be minimized or reduced, and the battery life can be improved.

[0205] In the power amplifier ( Figure 1 In the case of the power efficiency of the power supply modulator 300-1, the power efficiency in the ET mode (DL-ET mode or CL-ET mode) is greater than the power efficiency in the APT mode. Conversely, in the case of the power efficiency of the power supply modulator 300-1, the power efficiency in the APT mode is greater than the power efficiency in the ET mode (DL-ET mode or CL-ET mode).

[0206] As a reference, the power efficiency of the entire system (e.g. Figure 1 The efficiency of the wireless communication device 1) can be compared with the power efficiency of the power modulator 300-1 and the power amplifier (eg, Figure 1 is proportional to the power efficiency of the PA).

[0207] Therefore, in the high power region, the power level of the RF output signal RF_OUT (more specifically, the antenna ( Figure 1 The transmission power of the ANT) is high, and the power efficiency of the entire system can be greater in the ET mode (DL-ET mode or CL-ET mode) than in the APT mode. On the contrary, in the low power area, the power level of the RF output signal RF_OUT (more specifically, the antenna ( Figure 1 The transmission power of ANT) is low, and the power efficiency of the entire system can be greater in APT mode than in ET mode (DL-ET mode or CL-ET mode).

[0208] Therefore, the power modulator 300-1 can be configured to provide a power supply according to the antenna ( Figure 1 The transmit power TX power of ANT) is selectively driven in any one tracking mode of ET mode (DL-ET mode or CL-ET mode) and / or APT mode.

[0209] For reference, the CL-ET mode is achieved by using the linear regulator LA to track the RF output signal ( Figure 1 Therefore, the CL-ET mode can accurately track the RF output signal (RF_OUT) by Figure 1 When the output voltage VET_APT is generated by using the envelope RF_OUT_ENV of the linear regulator RF_OUT), excellent power conversion efficiency is achieved. However, the bandwidth of the output voltage VET_APT may be limited by the bandwidth of the linear regulator LA.

[0210] In contrast, the DL-ET mode tracks the RF output signal ( Figure 1 The envelope of RF_OUT) RF_OUT_ENV will be supplied to the power amplifier ( Figure 1 The output voltage VET_APT of the PA) is limited to a method in which a plurality of voltages V1 to VN having different levels from each other can be generated by the multi-output voltage regulator 310. Therefore, in the DL-ET mode, the output voltage VET_APT is different from the RF output signal ( Figure 1 A voltage difference may occur between the envelope RF_OUT_ENV of the output voltage (RF_OUT) and the output voltage (RF_OUT_ENV), resulting in lower power conversion efficiency than in CL-ET mode. However, in DL-ET mode, the power efficiency of the power modulator can be greater than that in CL-ET mode. In addition, in DL-ET mode, since the linear regulator LA is not used, the bandwidth of the output voltage VET_ATP can be greater than that in CL-ET mode.

[0211] For reference, the channel bandwidth used or to be used in NR (5G) may exceed the bandwidth limit of the linear regulator LA. Therefore, in NR (5G), the CL-ET mode using the linear regulator LA may be difficult to implement. However, in the DL-ET mode, since the output of the multi-output voltage regulator 310 is provided to the power amplifier (e.g., one of S1 to SN) through the switch (e.g., S1 to SN) (e.g., the output of the multi-output voltage regulator 310 does not pass through the linear regulator LA) Figure 1 PA), so the above bandwidth-related challenges can be solved.

[0212] Therefore, the main controller 360 may determine any one tracking mode of the DL-ET mode and the CL-ET mode in a direction that may improve the power efficiency of the entire system by considering the above situation.

[0213] As described above, since the power modulator 300-1 is driven in the APT mode or the ET mode (DL-ET mode or CL-ET mode) based on the above principle and generates the output voltage VET_APT, hereinafter, reference is made to Figures 10 to 12 , the operation of the power supply modulator 300 - 1 according to the tracking mode will be described.

[0214] As a reference, in Figures 10 to 12 The portion indicated by the bold line in each of the drawings may represent an operation activation path in the corresponding drawing.

[0215] First, refer to Figure 10 , shows the operation of the power supply modulator 300 - 1 in the APT mode.

[0216] The main controller 360 may receive an APT mode determination signal from the modem 100 and determine the APT mode of the power modulator 300 - 1 based on the APT mode determination signal.

[0217] In this case, the main controller 360 may control the switching regulator controller 350 based on the determined tracking mode, and the switching regulator controller 350 may control the switching regulator 330 based on the control of the main controller 360 .

[0218] Therefore, the switching regulator 330 can generate a modulation voltage (or a regulation voltage VSR) according to the APT mode, and provide the generated modulation voltage VSR as an output voltage VET_APT to the power amplifier ( Figure 1 PA).

[0219] In more detail, in order to generate the modulation voltage VSR according to the APT mode, the digital-to-analog converter DAC of the switching regulator controller 350 may receive the average power signal D_REF from the modem 100 and convert the average power signal D_REF received from the modem 100 into a reference voltage signal A_REF. The digital-to-analog converter DAC may provide the converted reference voltage signal A_REF to the output comparator OCP, and the output comparator OCP may compare the output voltage VET_APT with the reference voltage signal A_REF. In addition, the output comparator OCP may output the comparison result to the second multiplexer MUX2, and the second multiplexer MUX2 may output the output of the output comparator OCP as the switching regulator control signal SRC to the switching regulator 330. The switching regulator 330 may generate the modulation voltage VSR according to the APT mode based on the switching regulator control signal SRC received from the second multiplexer MUX2, and supply the generated modulation voltage VSR as the output voltage VET_APT to the power amplifier ( Figure 1 PA).

[0220] For reference, in the embodiment of the inventive concept, a method of controlling the output voltage VET_APT by using the output comparator OCP in the APT mode (e.g., a hysteresis (bang-bang) control method) is shown, but it is not limited thereto. That is, in the embodiment of the inventive concept, a method of controlling the output voltage VET_APT by using a compensator instead of a comparator in the APT mode (e.g., a voltage mode control method) can be used. However, for ease of explanation, in the embodiment of the inventive concept, a case where the method of controlling the output voltage VET_APT based on the output comparator OCP in the APT mode is used is described as an example.

[0221] Furthermore, the main controller 360 may control the switch controller 380 based on the determined tracking mode, and the switch controller 380 may control the switch array 370 based on the control of the main controller 360 .

[0222] In more detail, the switch controller 380 may control switching operations of some of the plurality of switches S1 to SN based on control of the main controller 360. Consequently, the switch array 370 may turn on switches corresponding to capacitors to be used as decoupling capacitors among the plurality of capacitors C1 to CN of the multi-output voltage regulator 310. Furthermore, the selected capacitors may be connected to the power amplifier PA via the turned-on switches and used as decoupling capacitors in the APT mode.

[0223] As a reference, although not in Figure 10 , but a separate capacitor (not shown) may be further included at the output terminal of the power supply modulator 300-1. In this case, the capacitor connected to the output terminal of the power supply modulator 300-1 may be used as a decoupling capacitor in the APT mode.

[0224] In addition, although Figure 10 Although not shown in FIG, the multi-output voltage regulator 310 may also generate a modulation voltage according to the APT mode based on the control of the main controller 360.

[0225] However, for convenience of explanation, in the embodiment of the inventive concept, a case where some of the plurality of capacitors C1 to CN of the multi-output voltage regulator 310 are used as decoupling capacitors and the switching regulator 330 generates and outputs the output voltage VET_APT is described as an example.

[0226] Then, refer to Figure 11 , shows the operation of the power modulator 300 - 1 in the DL-ET mode.

[0227] The main controller 360 may receive a DL-ET mode determination signal from the modem 100 and determine the DL-ET mode of the power modulator 300 - 1 based on the DL-ET mode determination signal.

[0228] In this case, the main controller 360 can control the multi-output voltage regulator 310, the switching regulator controller 350, the switch controller 380, and the discrete level controller 390 based on the determined tracking mode. In addition, the switching regulator controller 350 can control the switching regulator 330, and the switch controller 380 can control the switch array 370. Therefore, the switching regulator 330 and the multi-output voltage regulator 310 can generate a modulation voltage together according to the DL-ET mode and provide the generated modulation voltage as the output voltage VET_APT to the power amplifier ( Figure 1 PA).

[0229] In more detail, the multi-output voltage regulator 310 can receive a plurality of reference output voltage signals VREF1 to VREFN from the main controller 360, and generate and output a plurality of voltages V1 to VN having different levels from each other by raising or lowering an input voltage (e.g., a power source VIN provided from a battery, etc.) based on the plurality of reference output voltage signals VREF1 to VREFN received from the main controller 360.

[0230] The discrete level controller 390 may receive the digital envelope signal D_ENV from the modem 100 and generate a level control signal ENV_LV including a plurality of envelope level information based on the received digital envelope signal D_ENV. In addition, the discrete level controller 390 may provide the generated level control signal ENV_LV to the switch controller 380 and the first multiplexer MUX1.

[0231] The switch controller 380 may receive a level control signal ENV_LV from the discrete level controller 390 and control switching operations of the plurality of switches S1 to SN based on the level control signal ENV_LV received from the discrete level controller 390. That is, the switch controller 380 may control the switching operation of the switch array 370 to select a voltage to be provided to the power amplifier PA from among the plurality of voltages V1 to VN having different levels from each other.

[0232] Therefore, a switch (e.g., S1) selected from among the plurality of switches S1 to SN by the switch control signal SW may be turned on, and a voltage (e.g., V1) having a specific level corresponding to the switch may be provided to the power amplifier ( Figure 1 PA).

[0233] For reference, the power amplifier ( Figure 1 The output current IHF of the multi-output voltage regulator 310 (PA) may be sensed by the feedback loop FL of the switching regulator controller 350, and the sensed value SV may be provided to the summer ADD.

[0234] The plurality of OTAs OTA1 to OTAN of the switching regulator controller 350 may receive information about the plurality of voltages V1 to VN having different levels from each other, output from the multi-output voltage regulator 310, and may receive information about the plurality of reference output voltage signals VREF1 to VREFN from the main controller 360. Furthermore, the plurality of OTAs OTA1 to OTAN may respectively compare a voltage having a specific level (e.g., V1) with a specific reference output voltage signal (e.g., VREF1) corresponding to the voltage having the specific level, and output a difference between the voltage having the specific level and the specific reference output voltage signal corresponding to the voltage having the specific level based on the comparison result.

[0235] The first multiplexer MUX1 may receive a level control signal ENV_LV from the discrete level controller 390 and select and output one of the difference values DV output from the plurality of OTAs OTA1 to OTAN based on the level control signal ENV_LV received from the discrete level controller 390. In addition, the first multiplexer MUX1 may provide the selected difference value DV to the summer ADD.

[0236] The summer ADD may sum the difference value DV output from the first multiplexer MUX1 with the sensed value SV of the output current IHF of the multi-output voltage regulator 310 sensed by the feedback loop FL, and output the summed value as the compensation value CV. In addition, the compensation value CV output from the summer ADD may be provided to the compensation comparator CCP.

[0237] The compensation comparator CCP can receive the compensation value CV output from the summer ADD through the positive terminal + and receive the reference value through the negative terminal -. In addition, the compensation comparator CCP can output a comparison result between the received compensation value CV and the reference value to the second multiplexer MUX2.

[0238] In the DL-ET mode, the second multiplexer MUX2 may output the output of the compensation comparator CCP to the switching regulator 330 as the switching regulator control signal SRC.

[0239] The switching regulator 330 may generate a modulation voltage VSR according to the DL-ET mode based on the switching regulator control signal SRC received from the second multiplexer MUX2, and supply the generated modulation voltage VSR to the power amplifier ( Figure 1 PA).

[0240] For reference, the output current ILF of the switching regulator 330 output based on the switching regulator control signal SRC can be combined with the output current IHF of the multi-output voltage regulator 310 to form the output current IET_APT of the power amplifier ( Figure 1 PA).

[0241] Finally, refer to Figure 12 , shows the operation of the power supply modulator 300 - 1 in the CL-ET mode.

[0242] The main controller 360 may receive a CL-ET mode determination signal from the modem 100 and determine the CL-ET mode of the power modulator 300 - 1 based on the CL-ET mode determination signal.

[0243] In this case, the main controller 360 may control the linear regulator LA and the switching regulator controller 350 based on the determined tracking mode. In addition, the switching regulator controller 350 may control the switching regulator 330. Therefore, the switching regulator 330 and the linear regulator LA may generate a modulation voltage together according to the CL-ET mode and provide the generated modulation voltage as the output voltage VET_APT to the power amplifier ( Figure 1 PA).

[0244] In more detail, the linear regulator LA may receive the analog envelope signal A_ENV from the modem 100 and output the analog envelope signal A_ENV received from the modem 100 to output the output current IHF. In addition, the output current IHF output from the linear regulator LA may be provided to the power amplifier ( Figure 1 PA).

[0245] For reference, the output current IHF of the linear regulator LA may be sensed by the feedback loop FL of the switching regulator controller 350 , and the sensed value SV may be provided to the summer ADD.

[0246] The summer ADD in the switching regulator controller 350 may output the sensed value SV of the output current IHF of the linear regulator LA sensed by the feedback loop FL as the compensation value CV. In addition, the compensation value CV output from the summer ADD may be provided to the compensation comparator CCP.

[0247] The compensation comparator CCP can receive the compensation value CV output from the summer ADD through the positive terminal + and receive the reference value through the negative terminal -. In addition, the compensation comparator CCP can output a comparison result between the received compensation value CV and the reference value to the second multiplexer MUX2.

[0248] In the CL-ET mode, the second multiplexer MUX2 may output the output of the compensation comparator CCP to the switching regulator 330 as the switching regulator control signal SRC.

[0249] The switching regulator 330 may generate a modulation voltage VSR according to the CL-ET mode based on the switching regulator control signal SRC received from the second multiplexer MUX2, and provide the generated modulation voltage VSR to the power amplifier ( Figure 1 PA).

[0250] For reference, the output current ILF of the switching regulator 330 output based on the switching regulator control signal SRC can be combined with the output current IHF of the linear regulator LA to form the output current IET_APT of the power amplifier ( Figure 1 PA).

[0251] As described above, since the power supply modulator 300-1 operates according to the APT mode, the DL-ET mode, or the CL-ET mode based on the above principle, hereinafter, reference is made to Figures 13 to 15 , a second example of a power supply modulator according to an embodiment of the inventive concept will be described.

[0252] Figure 13 is a circuit diagram illustrating a second example of the power modulator 300 - 2 included in the wireless communication device according to an embodiment of the inventive concept. Figure 14 It shows Figure 13 FIG. 1 is a diagram illustrating the APT mode operation of the power supply modulator 300 - 2 . Figure 15 It shows Figure 13 FIG. 1 is a diagram illustrating the DL_ET mode operation of the power supply modulator 300 - 2 .

[0253] In the following, for the convenience of explanation, it is assumed that the power supply modulator 300-2 is implemented as Figure 1 The power supply modulator 300 of the wireless communication device 1 shown in FIG. Figure 1 describe Figure 13 In addition, since the power supply modulator 300-2 is Figure 4 The power supply modulator 300 - 1 is the same or similar except for some structures and mechanisms, so the following will mainly describe the differences.

[0254] Reference Figure 13 , a second example of the power modulator 300 according to an embodiment of the inventive concept (i.e., power modulator 300-2) may include a multi-output voltage regulator 310, a switching regulator 330, a switching regulator controller 350, a main controller 360, a switch array 370, a switch controller 380 and / or a discrete level controller 390.

[0255] In detail, with Figure 4 The power supply modulator 300-1 is different, Figure 13 The power supply modulator 300 - 2 may not include the linear regulator LA.

[0256] Therefore, the power modulator 300 - 2 can operate in the DL-ET mode or the APT mode, but will not operate in the CL-ET mode.

[0257] First, the switching regulator 330 may operate together with the multi-output voltage regulator 310 in the DL-ET mode to generate the output voltage VET_APT, and the switching regulator 330 may operate in the APT mode to generate the output voltage VET_APT.

[0258] Furthermore, in the DL-ET mode, the switching regulator controller 350 may sense the output current IHF of the multi-output voltage regulator 310 and control the switching regulator 330 based on the sensed value SV.

[0259] In detail, in the DL-ET mode, the feedback loop FL of the switching regulator controller 350 may sense the output current IHF of the multi-output voltage regulator 310 and provide the sensed value SV to the summer ADD.

[0260] In addition, in the APT mode, the second multiplexer MUX2 of the switching regulator controller 350 can output the output of the output comparator OCP as the switching regulator control signal SRC to the switching regulator 330, and in the DL-ET mode, the second multiplexer MUX2 of the switching regulator controller 350 can output the output of the compensation comparator CCP as the switching regulator control signal SRC to the switching regulator 330.

[0261] The main controller 360 may generate a plurality of reference output voltage signals VREF1 to VREFN and provide the plurality of reference output voltage signals VREF1 to VREFN to at least one of the multi-output voltage regulator 310 and the switching regulator controller 350. In addition, the main controller 360 may determine a tracking mode and control at least one of the multi-output voltage regulator 310, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390 according to the determined tracking mode.

[0262] The main controller 360 can be connected via MIPI ( Figure 1 130) receives various signals (e.g., various control signals (such as output voltage level signals, etc.)) other than the tracking mode determination signal from the modem 100, and controls components (such as the multi-output voltage regulator 310, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390) based on the received various signals.

[0263] As a reference, in Figure 13, the main controller 360 is shown as controlling at least one of the multi-output voltage regulator 310, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390, but is not limited thereto. That is, the main controller 360 may control the operation of components other than the above components.

[0264] However, for convenience of explanation, in the embodiment of the inventive concept, a case where the main controller 360 controls at least one of the multi-output voltage regulator 310 , the switch controller 380 , the switching regulator controller 350 , and the discrete level controller 390 is described as an example.

[0265] As described above, since the power supply modulator 300-2 has the above structure and characteristics, it is Figure 4 Compared with the power modulator 300-1, the circuit area and manufacturing cost of the power modulator 300-2 can be reduced. In addition, based on the structure and characteristics, the power modulator 300-2 can be driven in either the DL-ET mode or the APT mode and provide the output voltage VET_APT to the power amplifier PA.

[0266] As a reference, Figure 14 and Figure 15 Shown respectively according to Figure 13 The operation activation paths of the APT mode and the DL-ET mode of the power supply modulator 300 - 2 .

[0267] However, due to Figure 14 The power supply modulator 300-2 operates in APT mode with Figure 10 The operations are the same or similar to those described in Figure 15 The power supply modulator 300-2 operates in DL-ET mode with Figure 11 The operations described in are the same or similar, so their detailed description will be omitted.

[0268] As described above, since the power supply modulator 300-2 operates according to the APT mode or the DL-ET mode based on the above principle, reference will be made to the following. Figure 16 A third example of the power supply modulator according to an embodiment of the inventive concept is described.

[0269] Figure 16 is a circuit diagram illustrating a third example of the power modulator 300 - 3 included in the wireless communication device according to an embodiment of the inventive concept.

[0270] For reference, in the following, for ease of explanation, it is assumed that the power supply modulator 300-3 is implemented as Figure 1 The power modulator 300 of the wireless communication device 1 is shown in FIG. In addition, since the power modulator 300-3 is connected to the power modulator 300-3, Figure 4The power supply modulator 300 - 1 is the same or similar except for some structures and mechanisms, so the following will mainly describe the differences.

[0271] Reference Figure 16 The third example of the power modulator 300 according to an embodiment of the inventive concept (i.e., the power modulator 300-3) may include a multi-output voltage regulator 310, a first switching regulator 330 and a second switching regulator 333, a first linear regulator LA1 and a second linear regulator LA2, a first switching regulator controller 350 and a second switching regulator controller 353, a main controller 360, a first switch array 370 and a second switch array 373, a first switch controller 380 and a second switch controller 383, and a first discrete level controller 390 and a second discrete level controller 393. According to an embodiment, the first switching regulator controller 350 and the second switching regulator controller 353 may each be combined with Figure 4 The switching regulator controller 350 discussed is the same or similar.

[0272] In detail, Figure 16 The power supply modulator 300-3 can provide the first output voltage VET_APT1 and the second output voltage VET_APT2 to multiple power amplifiers (when there is Figure 1 power amplifier PA; for example, a first power amplifier and a second power amplifier).

[0273] Therefore, in Figure 16 In the case of the power supply modulator 300-3, with Figure 1 Compared to the power supply modulator 300 - 1 , the number of each of the switching regulator, the linear regulator, the switching regulator controller, the switch array, the switch controller, and the discrete level controller may be greater than one.

[0274] In addition, due to Figure 16 Power supply modulator 300-3 ratio Figure 4 The power modulator 300-1 receives more signals, so the power modulator 300-3 can receive more signals from the modem ( Figure 1 100) receives the first and second average power signals D_REF1 and D_REF2, the first and second analog envelope signals A_ENV1 and A_ENV2, and the first and second digital envelope signals D_ENV1 and D_ENV2.

[0275] In addition, Figure 16In the power supply modulator 300-3, since the multiple capacitors C1 to CN of the multi-output voltage regulator 310 are connected to both sides of the first power amplifier and the second power amplifier, the multiple capacitors C1 to CN of the multi-output voltage regulator 310 can be shared for generating each of the first output voltage VET_APT1 and the second output voltage VET_APT2. Therefore, the main controller 360 can jointly generate multiple reference output voltage signals VREF1 to VREFN for each of the first output voltage VET_APT1 and the second output voltage VET_APT2, and provide the multiple reference output voltage signals VREF1 to VREFN to the multi-output voltage regulator 310 and the first and second switching regulator controllers 350 and 353.

[0276] As described above, in an embodiment of the inventive concept, even in the case where multiple power supply voltages are generated for multiple power amplifiers, the increase in circuit area can be minimized or reduced because the number of output capacitors occupying most of the circuit area is the same or similar to the case where the power supply voltage is generated for a single power amplifier.

[0277] For ease of explanation, it is assumed that the first linear regulator LA1, the first switching regulator 330, the first switching regulator controller 350, the first switch array 370, the first discrete level controller 390 and the first switch controller 380 form a first modulation circuit, and the second linear regulator LA2, the second switching regulator 333, the second switching regulator controller 353, the second switch array 373, the second discrete level controller 393 and the second switch controller 383 form a second modulation circuit, and a brief description of each component of the power modulator 300-3 is as follows.

[0278] The first modulation circuit may include a first linear regulator LA1 and a first switching regulator 330, wherein the first linear regulator LA1 operates in a CL-ET mode to Figure 1The first modulation circuit 100 receives a first analog envelope signal A_ENV1 and generates a first output voltage VET_APT1. The first switching regulator 330 operates in conjunction with the multi-output voltage regulator 310 in the DL-ET mode to generate the first output voltage VET_APT1. The first switching regulator 330 operates in conjunction with the first linear regulator LA1 in the CL-ET mode to generate the first output voltage VET_APT1. The first switching regulator 330 also operates in the APT mode to generate the first output voltage VET_APT1. Furthermore, the first modulation circuit 100 may include a first switching regulator controller 350 that selectively senses either an output current IHF1 of the multi-output voltage regulator 310 or an output current IHF1 of the first linear regulator LA1, and controls the first switching regulator 330 based on the sensed value SV1. In addition, the first modulation circuit may include a first switch array 370, which includes a plurality of switches S1 to SN respectively corresponding to the plurality of voltages V1 to VN having different levels output from the multi-output voltage regulator 310, and selects one of the plurality of voltages V1 to VN having different levels and provides the one of the plurality of voltages V1 to VN having different levels to the first power amplifier. In addition, the first modulation circuit may include a first discrete level controller 390 and a first switch controller 380, the first discrete level controller 390 selecting a discrete level controller based on the output voltage from the modem ( Figure 1 The first digital envelope signal D_ENV1 provided by 100) generates a first level control signal ENV_LV1 including multiple envelope level information, and the first switch controller 380 receives the first level control signal ENV_LV1 from the first discrete level controller 390, and controls the switching operations of multiple switches S1 to SN based on the first level control signal ENV_LV1 received from the first discrete level controller 390.

[0279] The second modulation circuit may include a second linear regulator LA2 and a second switching regulator 333, wherein the second linear regulator LA2 operates in a CL-ET mode to Figure 1The second modulation circuit may include a second switching regulator controller 353 that selectively senses either the output current IHF2 of the multi-output voltage regulator 310 or the output current IHF2 of the second linear regulator LA2 and controls the second switching regulator 333 based on the sensed value SV2. The second modulation circuit may also include a second switch array 373 including a plurality of switches S1′ to SN′ corresponding to the plurality of voltages V1 to VN having different levels output from the multi-output voltage regulator 310, and selecting and providing one of the plurality of voltages V1 to VN having different levels to the second power amplifier. Furthermore, the second modulation circuit may include a second discrete level controller 393 and a second switch controller 383, which generates a second level control signal ENV_LV2 including a plurality of pieces of envelope level information based on the second digital envelope signal D_ENV2 provided from the modem 100, and a second switch controller 383, which receives the second level control signal ENV_LV2 from the second discrete level controller 393 and controls switching operations of the plurality of switches S1′ to SN′ based on the second level control signal ENV_LV2 received from the second discrete level controller 393.

[0280] The multi-output voltage regulator 310 can output a plurality of voltages V1 to VN having different levels from each other to correspond to a plurality of reference output voltage signals VREF1 to VREFN, respectively, to generate a first output voltage VET_APT1 or a second output voltage VET_APT2 in the DL-ET mode. That is, the multi-output voltage regulator 310 can operate in parallel with the switching regulator operating in the DL-ET mode among the first switching regulator 330 and the second switching regulator 333.

[0281] The main controller 360 can generate a plurality of reference output voltage signals VREF1 to VREFN and provide the plurality of reference output voltage signals VREF1 to VREFN to the multi-output voltage regulator 310 and at least one of the first switching regulator controller 350 and the second switching regulator controller 353. Furthermore, the main controller 360 can determine a tracking mode for each of the first and second power amplifiers. In other words, the main controller 360 can determine a different tracking mode for each of the first and second power amplifiers, or can determine the same or similar tracking mode for each of the first and second power amplifiers. Furthermore, the main controller 360 can control at least one of the first and second linear regulators LA1 and LA2, the first and second switch controllers 380 and 383, the first and second switching regulator controllers 350 and 353, the first and second discrete level controllers 390 and 393, and the multi-output voltage regulator 310 based on the determined tracking mode.

[0282] Each component may include a component-specific controller (e.g., first switching regulator controller 350 and second switching regulator controller 353) therein or externally, and each dedicated controller may be controlled by main controller 360. In addition, there may be a controller that integrates and controls at least two components, and the corresponding controllers may be controlled by main controller 360.

[0283] As described above, based on the above structure and characteristics, the power modulator 300-3 can be driven in at least one tracking mode among the DL-ET mode, the CL-ET mode and the APT mode to Figure 4 The power modulator 300 - 1 is based on the same principle or a similar principle to provide the first output voltage VET_APT1 and the second output voltage VET_APT2 to the first power amplifier and the second power amplifier, respectively.

[0284] For reference, the power supply modulator 300-3 is shown as including components that are bilaterally symmetrical with respect to the multi-output voltage regulator 310. However, Figure 16The power supply modulator 300-3 may include components that are asymmetrical on both sides relative to the multi-output voltage regulator 310. For example, two of each of the linear regulator, switching regulator, switching regulator controller, switch array, switch controller, and discrete level controller may be provided on the left side of the figure, but as shown on the right side of the figure, one of each of the linear regulator, switching regulator, switching regulator controller, switch array, switch controller, and discrete level controller may be provided. However, for ease of explanation, a case where the power supply modulator 300-3 includes components that are symmetrical on both sides relative to the multi-output voltage regulator 310 will be described as an example. Figure 16 In the figure, reference numerals IET_APT1, ILF1, VSR1, SRC1, A_REF1, CV1, DV1, SW1, ENV_P1, ENV_N1 and reference numerals IET_APT2, ILF2, VSR2, SRC2, A_REF2, CV2, DV2, SW2, ENV_P2, ENV_N2 are respectively Figure 4 The reference symbols IET_APT, ILF, VSR, SRC, A_REF, CV, DV, SW, ENV_P, ENV_N shown in are similar.

[0285] Figure 17 is a circuit diagram illustrating a fourth example of the power modulator 300 - 4 included in the wireless communication device according to an embodiment of the inventive concept.

[0286] For reference, in the following, for ease of explanation, it is assumed that the power supply modulator 300-4 is implemented as Figure 1 The power modulator 300 of the wireless communication device 1 is shown in FIG. In addition, since the power modulator 300-4 is connected to the power modulator 300-4, Figure 13 The power supply modulator 300 - 2 is the same or similar except for some structures and mechanisms, so the following will mainly describe the differences.

[0287] Reference Figure 17 , a fourth example of the power modulator 300 according to an embodiment of the inventive concept (i.e., power modulator 300-4) may include a multi-output voltage regulator 310, a first switch regulator 330 and a second switch regulator 333, a first switch regulator controller 350 and a second switch regulator controller 353, a main controller 360, a first switch array 370 and a second switch array 373, a first switch controller 380 and a second switch controller 383, and / or a first discrete level controller 390 and a second discrete level controller 393.

[0288] In detail, Figure 17 The power supply modulator 300-4 can supply the first output voltage VET_APT1 and the second output voltage VET_APT2 to multiple power amplifiers (when there is Figure 1 power amplifier PA; for example, a first power amplifier and a second power amplifier).

[0289] Therefore, in Figure 17 In the case of the power supply modulator 300-4, with Figure 13 Compared to the power supply modulator 300 - 2 , the number of each of the switching regulator, the switching regulator controller, the switch array, the switch controller, and the discrete level controller may be greater than one.

[0290] In addition, due to Figure 17 Power supply modulator 300-4 ratio Figure 13 The power modulator 300-2 receives more signals, so the power modulator 300-4 can receive more signals from the modem ( Figure 1 100) receives the first and second average power signals D_REF1 and D_REF2, the first and second analog envelope signals A_ENV1 and A_ENV2, and the first and second digital envelope signals D_ENV1 and D_ENV2.

[0291] In addition, Figure 17 In power supply modulator 300-4, since multiple capacitors C1 to CN of multi-output voltage regulator 310 are connected to both sides of the first power amplifier and the second power amplifier, multiple capacitors C1 to CN of multi-output voltage regulator 310 can be shared for generating each of first output voltage VET_APT1 and second output voltage VET_APT2. Therefore, main controller 360 can jointly generate multiple reference output voltage signals VREF1 to VREFN for each of first output voltage VET_APT1 and second output voltage VET_APT2, and provide the multiple reference output voltage signals VREF1 to VREFN to multi-output voltage regulator 310 and first and second switching regulator controllers 350 and 353.

[0292] As described above, in an embodiment of the inventive concept, even in the case where multiple power supply voltages are generated for multiple power amplifiers, the increase in circuit area can be minimized or reduced because the number of output capacitors occupying most of the circuit area is the same or similar to the case where the power supply voltage is generated for a single power amplifier.

[0293] For ease of explanation, it is assumed that the first switching regulator 330, the first switching regulator controller 350, the first switch array 370, the first discrete level controller 390, and the first switch controller 380 form a first modulation circuit, and the second switching regulator 333, the second switching regulator controller 353, the second switch array 373, the second discrete level controller 393 and the second switch controller 383 form a second modulation circuit, and a brief description of each component of the power modulator 300-4 is as follows.

[0294] The first modulation circuit may include a first switching regulator 330 that operates in DL-ET mode with the multi-output voltage regulator 310 to generate a first output voltage VET_APT1, and the first switching regulator 330 operates in APT mode to generate the first output voltage VET_APT1. Furthermore, the first modulation circuit may include a first switching regulator controller 350 and a first switch array 370, wherein the first switching regulator controller 350 senses the output current of the multi-output voltage regulator 310 and controls the first switching regulator 330 based on the sensed value SV1, and the first switch array 370 includes a plurality of switches S1 to SN that respectively correspond to a plurality of voltages V1 to VN having different levels output from the multi-output voltage regulator 310, selects one of the plurality of voltages V1 to VN having different levels, and provides the one of the plurality of voltages V1 to VN having different levels to the first power amplifier. Furthermore, the first modulation circuit may include a first discrete level controller 390 and a first switch controller 380, wherein the first discrete level controller 390 controls the output current of the multi-output voltage regulator 310 based on the output current of the multi-output voltage regulator 310 and controls the first switching regulator 330 based on the sensed value SV1. Figure 1 The first digital envelope signal D_ENV1 provided by 100) generates a first level control signal ENV_LV1 including multiple envelope level information, and the first switch controller 380 receives the first level control signal ENV_LV1 from the first discrete level controller 390, and controls the switching operations of multiple switches S1 to SN based on the first level control signal ENV_LV1 received from the first discrete level controller 390.

[0295] The second modulation circuit may include a second switching regulator 333 that operates in conjunction with the multi-output voltage regulator 310 in the DL-ET mode to generate a second output voltage VET_APT2, and the second switching regulator 333 operates in the APT mode to generate the second output voltage VET_APT2. Furthermore, the second modulation circuit may include a second switching regulator controller 353 and a second switch array 373, wherein the second switching regulator controller 353 senses the output current of the multi-output voltage regulator 310 and controls the second switching regulator 333 based on the sensed value SV2, and the second switch array 373 includes a plurality of switches S1' to SN' that respectively correspond to the plurality of voltages V1 to VN having different levels output from the multi-output voltage regulator 310, and selects one of the plurality of voltages V1 to VN having different levels and provides the one of the plurality of voltages V1 to VN having different levels to the second power amplifier. Furthermore, the second modulation circuit may include a second discrete level controller 393 and a second switch controller 383, wherein the second discrete level controller 393 controls the output current of the multi-output voltage regulator 310 based on the output current of the multi-output voltage regulator 310. Figure 1 The second digital envelope signal D_ENV2 provided by 100) generates a second level control signal ENV_LV2 including multiple envelope level information, and the second switch controller 383 receives the second level control signal ENV_LV2 from the second discrete level controller 393, and controls the switching operations of multiple switches S1' to SN' based on the second level control signal ENV_LV2 received from the second discrete level controller 393.

[0296] The multi-output voltage regulator 310 can output a plurality of voltages V1 to VN having different levels from each other to correspond to a plurality of reference output voltage signals VREF1 to VREFN, respectively, to generate a first output voltage VET_APT1 or a second output voltage VET_APT2 in the DL-ET mode. That is, the multi-output voltage regulator 310 can operate in parallel with the switching regulator operating in the DL-ET mode among the first switching regulator 330 and the second switching regulator 333.

[0297] The main controller 360 may generate a plurality of reference output voltage signals VREF1 to VREFN and provide the plurality of reference output voltage signals VREF1 to VREFN to the multi-output voltage regulator 310 and at least one of the first switching regulator controller 350 and the second switching regulator controller 353. Furthermore, the main controller 360 may determine a tracking mode for each of the first and second power amplifiers. In other words, the main controller 360 may determine a different tracking mode for each of the first and second power amplifiers, or may determine the same or similar tracking mode for each of the first and second power amplifiers. Furthermore, the main controller 360 may control at least one of the first and second switch controllers 380 and 383, the first and second switching regulator controllers 350 and 353, the first and second discrete level controllers 390 and 393, and the multi-output voltage regulator 310 based on the determined tracking mode.

[0298] Each component may include a component-specific controller (e.g., first switching regulator controller 350 and second switching regulator controller 353) therein or externally, and each dedicated controller may be controlled by main controller 360. In addition, there may be a controller that integrates and controls at least two components, and the corresponding controllers may be controlled by main controller 360.

[0299] As described above, based on the above structure and characteristics, the power modulator 300-4 can be driven in at least one tracking mode of the DL-ET mode and the APT mode to Figure 13 The power modulator 300 - 2 is based on the same principle or a similar principle, and provides a first output voltage VET_APT1 and a second output voltage VET_APT2 to the first power amplifier and the second power amplifier, respectively.

[0300] For reference, the power supply modulator 300-4 is shown as including components that are bilaterally symmetrical with respect to the multi-output voltage regulator 310. However, Figure 17 The power supply modulator 300-4 may include components that are asymmetrical relative to the multi-output voltage regulator 310. For example, as shown, the linear regulator may not be provided on the left side of the figure, but may be provided on the right side of the figure. However, for ease of explanation, the case where the power supply modulator 300-4 includes components that are symmetrical relative to the multi-output voltage regulator 310 will be described as an example.

[0301] As described above, since the power modulator 300-4 is driven in at least one tracking mode among the DL-ET mode, the CL-ET mode, and the APT mode based on the above principle, hereinafter, referring to Figure 18, a fifth example of a power supply modulator according to an embodiment of the inventive concept will be described.

[0302] Figure 18 is a circuit diagram illustrating a fifth example of the power modulator 300 - 5 included in the wireless communication device according to an embodiment of the inventive concept. Figure 19 It shows Figure 18 FIG. 1 is a diagram of an example of a multiple-output voltage regulator 310 . Figure 20 It shows Figure 18 FIG. 1 is a diagram of another example of a multiple-output voltage regulator 310 . Figure 21 It shows Figure 18 FIG. 1 is a diagram of another example of a multiple-output voltage regulator 310 . Figure 22 is a diagram illustrating a mechanism of increasing the output voltage of a multi-output voltage regulator by a coupling capacitor. Figure 23 It shows Figure 18 FIG. 5 is a diagram illustrating the APT mode operation of the power supply modulator 300 - 5 . Figure 24 It shows Figure 18 FIG. 5 is a diagram illustrating the DL-ET mode operation of the power supply modulator 300 - 5 . Figure 25 It shows Figure 18 FIG. 5 is a diagram illustrating the CL-ET mode operation of the power supply modulator 300 - 5 .

[0303] For reference, in the following, for ease of explanation, it is assumed that the power supply modulator 300-5 is implemented as Figure 1 The power supply modulator 300 of the wireless communication device 1 shown in FIG. Figure 1 describe Figure 18 .

[0304] Reference Figure 18 , a fifth example of the power modulator 300 according to an embodiment of the inventive concept (i.e., power modulator 300-5) may include a multi-output voltage regulator 310, a switching regulator 330, a linear regulator LA, a switching regulator controller 350, a main controller 360, a switch array 370, a switch controller 380, a discrete level controller 390 and / or a coupling capacitor CAC.

[0305] For reference, each component may include a component-specific controller (e.g., switching regulator controller 350) therein or externally, and each dedicated controller may be controlled by main controller 360. In addition, there may be a controller that integrates and controls at least two components, and the corresponding controllers may be controlled by main controller 360.

[0306] However, for ease of explanation, only dedicated controllers of some components will be described in detail below.

[0307] To generate the output voltage VET_APT together with the switching regulator 330 in the DL-ET mode, the multi-output voltage regulator 310 can output a plurality of voltages V1 to VN-1 (or referred to as switch subsets) having different levels from one another (where N is a natural number of two or greater) to correspond to a plurality of reference output voltage signals VREF1 to VREFN-1 (where N is a natural number of two or greater). In addition, the multi-output voltage regulator 310 can be controlled by the main controller 360.

[0308] That is, when the multi-output voltage regulator 310 is connected in parallel with the switching regulator 330, the multi-output voltage regulator 310 can generate the output voltage VET_APT by operating in parallel with the switching regulator 330 in the DL-ET mode. In addition, the multi-output voltage regulator 310 can generate and output a plurality of voltages V1 to VN-1 having different levels from each other by raising or lowering an input voltage (e.g., a power source VIN provided from a battery, etc.) based on a plurality of reference output voltage signals VREF1 to VREFN-1.

[0309] Here, the plurality of reference output voltage signals VREF1 to VREFN-1 may be received from the main controller 360. For reference, the modem 100 may calculate a reference output voltage value based on the output power of the power amplifier PA and provide the calculated reference output voltage value to the main controller 360. In addition, the main controller 360 may generate the plurality of reference output voltage signals VREF1 to VREFN-1 based on the received reference output voltage value and provide the plurality of reference output voltage signals VREF1 to VREFN-1 to the multi-output voltage regulator 310.

[0310] In addition, the connection between the multi-output voltage regulator 310 and the power amplifier PA can be selectively connected and disconnected by the switch array 370. That is, through the switching operation of the switch array 370, at least one voltage among the multiple voltages V1 to VN-1 having different levels from each other generated and output from the multi-output voltage regulator 310 (for example, V1 to VN-1 are generated and output in a time-division method) can be selected. In addition, the selected voltage can be added to the voltage VAC of the coupling capacitor CAC described below to be provided to the power amplifier PA.

[0311] In addition, the output end of the multi-output voltage regulator 310 may include a plurality of capacitors C1 to CN-1 (where N is a natural number of two or greater) corresponding to a plurality of voltages V1 to VN-1 having different levels from each other. In addition, the connection between the plurality of capacitors C1 to CN-1 and the power amplifier PA can be individually turned on or off by a plurality of switches S1 to SN-1 (where N is a natural number of two or greater) in the switch array 370, and SN is grounded (or connected to the ground voltage GND). The plurality of capacitors C1 to CN-1 may be provided outside the multi-output voltage regulator 310 rather than inside. However, for ease of explanation, in the embodiments of the inventive concept, the case where the plurality of capacitors C1 to CN-1 are included in the multi-output voltage regulator 310 will be described as an example.

[0312] Reference Figures 19 to 21 , various implementation examples of the multi-output voltage regulator 310 (ie, the multi-output voltage regulators 310 - 4 to 310 - 6 ) are shown.

[0313] First, refer to Figure 19 , the multi-output voltage regulator 310 - 4 may include, for example, a plurality of single output voltage regulators SOVR1 to SOVRN-1 (where N is a natural number of two or greater) that respectively output a plurality of voltages V1 to VN-1 having different levels from each other.

[0314] Here, the plurality of single output voltage regulators SOVR1 to SOVRN- 1 may include, for example, switching regulators such as a buck converter and a boost converter, or may include a switched capacitor DC-DC converter, an LDO, or the like.

[0315] Furthermore, in the plurality of single output voltage regulators SOVR1 to SOVRN- 1 , there may be a controller for each of the single output voltage regulators individually, or there may be one common controller.

[0316] Then, refer to Figure 20 , the multi-output voltage regulator 310 - 5 may include, for example, a SIMO DC-DC converter or a SIMO buck-boost converter.

[0317] In detail, Figure 20 The multi-output voltage regulator 310 - 5 may be a structure that supplies the output current of the SR in the SIMO DC-DC converter or the SIMO buck-boost converter to each output terminal through a single inductor L′ in a time-division method.

[0318] Furthermore, SIMO controller 312 may monitor the difference between each of the plurality of output voltages V1 to VN-1 and each of the plurality of reference output voltage signals VREF1 to VREFN-1 corresponding to each of the plurality of output voltages V1 to VN-1, and may determine, based on the monitoring result, which switch to turn on from among switches SM1, SM2, ..., SM(N-1) connected to inductor L' and each of the plurality of output voltages V1 to VN-1. Simultaneously or concurrently, SIMO controller 312 may determine switch input SW_SIMO of the SR connected to one side of inductor L' based on information about the difference between each of the plurality of output voltages V1 to VN-1 and each of the plurality of reference output voltage signals VREF1 to VREFN-1 corresponding to each of the plurality of output voltages V1 to VN-1.

[0319] For reference, in an embodiment of the inventive concept, since the magnitude of the output current IHF of the multi-output voltage regulator 310 is not large (i.e., most of the output current IET_APT is supplied by the switching regulator 330 (e.g., ILF)), the multi-output voltage regulator 310 is suitable for applying a SIMO DC-DC converter or a SIMO buck-boost converter that supplies outputs in a time-division method. In addition, the SIMO DC-DC converter can operate in both the buck mode and the buck-boost mode.

[0320] Finally, refer to Figure 21 The multi-output voltage regulator 310-6 may include, for example, a boost converter (including converters of VIN, L, SN, SP) and a plurality of LDOs LDO1 to LDO(N-2) (where N is a natural number of two or greater), the boost converter generating a voltage having a highest level (e.g., V1) among a plurality of voltages V1 to VN-1 having voltages different from one another, and the plurality of LDOs LDO1 to LDO(N-2) generating the remaining voltages V2 to VN-1 among the plurality of voltages V1 to VN-1 having levels different from one another by using the voltage having the highest level generated by the boost converter as an input.

[0321] In addition, the boost converter controller 314 can monitor the difference between the output voltage V1 of the boost converter (e.g., the voltage with the highest level) and the reference output voltage signal VREF1 corresponding to the output voltage V1 of the boost converter, and determine the switch to be turned on among the switches SN and SP based on the monitoring result.

[0322] As described above, the multi-output voltage regulator 310 may be implemented in various forms. The multi-output voltage regulator 310 may include a structure different from the above structure, and a detailed description thereof will be omitted.

[0323] Return to reference Figure 18 The linear regulator LA may operate in the CL-ET mode to generate an output voltage VET_APT based on an analog envelope signal A_ENV received from the outside. In addition, the linear regulator LA may be controlled by the main controller 360 .

[0324] In detail, the linear regulator LA may receive the analog envelope signal A_ENV from the modem 100 and may amplify and output the analog envelope signal A_ENV. Therefore, the linear regulator LA may operate in parallel with the switching regulator 330 in the CL mode to generate the output voltage VET_APT.

[0325] In addition, although not Figure 18 , the linear regulator LA may receive an input voltage (e.g., a power source provided from a battery or the like) as a power supply voltage, or may receive a power supply voltage from a separate voltage regulator. Furthermore, the linear regulator LA may receive any one of a plurality of voltages V1 to VN-1 having different levels output from the multi-output voltage regulator 310 as a power supply voltage.

[0326] In addition, the linear regulator LA can be connected in parallel with the switching regulator 330 and can be implemented as, for example, a linear amplifier. Figure 18 As shown in , the linear regulator LA may be implemented as a differential amplifier and may receive the positive signal ENV_P and the negative signal ENV_N of the analog envelope signal A_ENV through the positive terminal + and the negative terminal −, respectively.

[0327] In addition, despite Figure 18 Although not shown, when the output of the linear regulator LA is fed back to the negative terminal of the linear regulator LA through a feedback unit (not shown), the output level of the linear regulator LA can be adjusted to a desired level based on the feedback result. In other words, the feedback unit can adjust the output level of the linear regulator LA to a desired level by making the voltage output from the linear regulator LA and the power supply voltage input to the linear regulator LA have a linear relationship.

[0328] In addition, despite Figure 18Although not shown, noise can be removed from the analog envelope signal A_ENV input to the linear regulator LA by a noise removal unit (not shown). Specifically, the noise removal unit can remove noise from the analog envelope signal A_ENV provided to the linear regulator LA and provide the noise-removed analog envelope signal A_ENV to the linear regulator LA. For reference, the noise removal unit can include, for example, a low-pass filter or an input buffer. Here, the low-pass filter can have characteristics that enable a specific gain value while removing high-frequency noise from the image signal or frequency band of the digital-to-analog converter. Furthermore, although the noise removal performance is not as good as that of a low-pass filter, the input buffer can have characteristics that enable broadband operation due to its wide coverage bandwidth.

[0329] The switching regulator 330 can operate in DL-EL mode with the multi-output voltage regulator 310 to generate the output voltage VET_APT, and can operate in CL-ET mode with the linear regulator LA to generate the output voltage VET_APT. Furthermore, the switching regulator 330 can operate in APT mode to generate the output voltage VET_APT. Furthermore, the switching regulator 330 can be controlled by a switching regulator controller 350.

[0330] Specifically, the switching regulator 330 can operate in parallel with the multi-output voltage regulator 310 in the DL-ET mode, and can operate in parallel with the linear regulator LA in the CL-ET mode. That is, in the DL-ET mode or the CL-ET mode, the switching regulator 330 can increase or decrease the output voltage VET_APT by controlling the on or off of the switch therein based on the switching regulator control signal SRC provided by the switching regulator controller 350.

[0331] Here, in the DL-ET mode or the CL-ET mode, the switching regulator control signal SRC provided to the switching regulator 330 may be generated based on the output of the compensation comparator CCP in the switching regulator controller 350 .

[0332] In addition, in the DL-ET mode, the sum current IET_APT of the output current ILF of the switching regulator 330 and the output current IHF of the multi-output voltage regulator 310 can be provided to the power amplifier PA. In this case, the output current ILF of the switching regulator 330 can be controlled based on the switching regulator control signal SRC so that the average value of the compensation value CV (e.g., the sum of the sensed value SV of the output current IHF and the difference value DV output from the OTA) output from the summer ADD in the switching regulator controller 350 to be described below is approximately zero.

[0333] For reference, the output current ILF of the switching regulator 330 may include a current with a low frequency component (eg, a frequency less than 1 MHz), and the output current IHF of the multi-output voltage regulator 310 may include a current with a high frequency component (eg, a frequency greater than 1 MHz).

[0334] On the other hand, in the CL-ET mode, the sum current IET_APT of the output current ILF of the switching regulator 330 and the output current IHF of the linear regulator LA can be provided to the power amplifier PA. In this case, the output current ILF of the switching regulator 330 can be controlled based on the switching regulator control signal SRC so that the average value of the compensation value CV (e.g., the sum of the sensed value SV of the output current IHF and the difference value DV output from the OTA) output from the summer ADD in the switching regulator controller 350 to be described below is approximately zero.

[0335] For reference, the output current ILF of the switching regulator 330 may include a current of a low-frequency component (eg, a frequency less than 1 MHz), and the output current IHF of the linear regulator LA may include a current of a high-frequency component (eg, a frequency greater than 1 MHz).

[0336] The voltage VSR output from the switching regulator 330 may be provided to the power amplifier PA through the inductor L as an output voltage VET_APT.

[0337] Here, the inductor L may be a power inductor of the switching regulator 330. Therefore, the inductor L may be connected to the output terminal of the switching regulator 330 and support a continuous current waveform.

[0338] For reference, the inductor L may not be included in the switching regulator 330. That is, the inductor L may be provided outside the switching regulator 330. However, for convenience of explanation, in the embodiment of the inventive concept, a case where the inductor L is included in the switching regulator 330 is described as an example.

[0339] In the APT mode, the switching regulator 330 can independently regulate an input voltage (e.g., power VIN provided from a battery) to a target level based on a switching regulator control signal SRC received from the switching regulator controller 350. Furthermore, the switching regulator 330 can provide the regulated voltage VSR as an output voltage VET_APT to the power amplifier PA.

[0340] Here, in the APT mode, the switching regulator control signal SRC provided to the switching regulator 330 may be generated based on the output of the output comparator OCP in the switching regulator controller 350 .

[0341] For reference, the switching regulator 330 may include, for example, a two-phase hybrid buck-boost converter, but is not limited thereto. That is, the switching regulator 330 may include a buck converter, a boost converter, a buck-boost converter, a Cook converter, or another DC-DC converter. Furthermore, the input voltage VIN supplied to the multi-output voltage regulator 310 may be a different input voltage than the input voltage VIN supplied to the multi-output voltage regulator 310. However, in the embodiments of the inventive concept, for ease of explanation, the case where the two input voltages are the same input voltage or similar input voltages will be described.

[0342] Furthermore, unlike the above description, in the DL-ET mode, the switching regulator 330 and the linear regulator LA can operate together to generate the output voltage VET_APT, and in the CL-ET mode, the switching regulator 330 and the multi-output voltage regulator 310 can operate together to generate the output voltage VET_APT. Furthermore, all of the switching regulator 330, the linear regulator LA, and the multi-output voltage regulator 310 can operate together to generate the output voltage VET_APT. Furthermore, in each of the DL-ET mode, the CL-ET mode, and the APT mode, a driver other than the driver described herein can operate.

[0343] However, for ease of explanation, in the embodiments of the inventive concept, the cases where the switching regulator 330 and the multi-output voltage regulator 310 operate together in the DL-ET mode, the switching regulator 330 and the linear regulator LA operate together in the CL-ET mode, and the switching regulator 330 operates in the APT mode are described as examples.

[0344] Switching regulator controller 350 can selectively sense one of the output current of multi-output voltage regulator 310 and / or the output current IHF of linear regulator LA according to the tracking mode, and can control switching regulator 330 based on the sensed value SV. In addition, switching regulator controller 350 can be controlled by main controller 360.

[0345] In detail, the switching regulator controller 350 may include a feedback loop FL, an OTA, a multiplexer MUX, a summer ADD, a compensation comparator CCP, a digital-to-analog converter DAC, and an output comparator OCP.

[0346] The feedback loop FL may sense the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA.

[0347] That is, in the DL-ET mode, the feedback loop FL can sense the output current IHF of the multi-output voltage regulator 310 and provide the sensed value SV to the summer ADD. Conversely, in the CL-ET mode, the feedback loop FL can sense the output current IHF of the linear regulator LA and provide the sensed value SV to the summer ADD.

[0348] For reference, IHF may refer to the output current of the multi-output voltage regulator 310 in the DL-ET mode, and may refer to the output current of the linear regulator LA in the CL-ET mode. SV may refer to the sensed value of the output current of the multi-output voltage regulator 310 in the DL-ET mode, and may refer to the sensed value of the output current of the linear regulator LA in the CL-ET mode. Here, the sensed value SV may be, for example, a current value or a voltage value, but is not limited thereto.

[0349] The OTA may output a difference value DV by comparing the voltage VAC of the coupling capacitor CAC with the target voltage signal VCCMIN of the coupling capacitor CAC.

[0350] That is, the OTA can receive a target voltage signal VCCMIN of the coupling capacitor CAC from the main controller 360. Therefore, the OTA can receive the target voltage signal VCCMIN from the main controller 360 via the positive terminal + and can receive the voltage VAC of the coupling capacitor CAC via the negative terminal -. Therefore, the OTA can compare the target voltage signal VCCMIN with the voltage VAC of the coupling capacitor CAC and output a difference DV between the target voltage signal VCCMIN and the voltage VAC of the coupling capacitor CAC based on the comparison result.

[0351] For reference, an amplifier (not shown) that changes the voltage VAC of the coupling capacitor CAC into a single-ended voltage may be provided in the power modulator 300-5. In addition, the amplifier may provide the voltage VAC of the coupling capacitor CAC to the negative terminal - of the OTA.

[0352] In addition, the difference value DV output from the OTA may be a current value or a voltage value corresponding to the difference between the voltage VAC across the coupling capacitor CAC and a target voltage (voltage value indicated by VCCMIN).

[0353] For reference, the target voltage signal VCCMIN of the coupling capacitor CAC may be adjusted by the modem 100. That is, the modem 100 may calculate the target voltage value of the coupling capacitor CAC and provide the calculated target voltage value to the main controller 360. In addition, the main controller 360 may generate a target voltage signal VCCMIN based on the received target voltage value and provide the generated target voltage signal VCCMIN to the OTA of the switching regulator controller 350.

[0354] According to the tracking mode, the summer ADD may sum the difference value DV output from the OTA with the sensed value SV of the output current IHF of the multi-output voltage regulator 310 sensed by the feedback loop FL, or sum the difference value DV output from the OTA with the sensed value SV of the output current IHF of the linear regulator LA sensed by the feedback loop FL, and output the summed value as the compensation value CV.

[0355] That is, in the DL-ET mode, the summer ADD may sum the difference value DV output from the OTA with the sensed value SV of the output current IHF of the multi-output voltage regulator 310 sensed by the feedback loop FL, and output the summed value as the compensation value CV. Conversely, in the CL-ET mode, the summer ADD may sum the difference value output from the OTA with the sensed value SV of the output current IHF of the linear regulator LA sensed by the feedback loop FL, and output the summed value as the compensation value CV. Furthermore, the compensation value CV output from the summer ADD may be provided to the compensation comparator CCP.

[0356] For reference, the compensation value CV output from the summer ADD may be in the form of a current value or a voltage value, but is not limited thereto.

[0357] The compensation comparator CCP may compare the compensation value CV output from the summer ADD with a reference value.

[0358] That is, the compensation comparator CCP can receive the compensation value CV output from the summer ADD through the positive terminal + and receive the reference value through the negative terminal -. In addition, the compensation comparator CCP can output the comparison result between the received compensation value CV and the reference value to the multiplexer MUX.

[0359] In more detail, when the compensation value CV is greater than the reference value, the compensation comparator CCP can output a high-level signal (e.g., "1"), and when the compensation value CV is less than the reference value, the compensation comparator CCP can output a low-level signal (e.g., "0").

[0360] As a reference, the negative terminal - may be grounded, and in this case the reference value may be zero.

[0361] The digital-to-analog converter DAC may convert the average power signal D_REF received from the outside into a reference voltage signal A_REF.

[0362] That is, the digital-to-analog converter DAC may receive the average power signal D_REF from the modem 100 via the MIPI 130 and may convert the received average power signal D_REF into a reference voltage signal A_REF and output the reference voltage signal A_REF to the output comparator OCP.

[0363] The output comparator OCP may compare the reference voltage signal A_REF converted by the digital-to-analog converter DAC with the output voltage VET_APT.

[0364] That is, the output comparator OCP can receive the reference voltage signal A_REF converted by the digital-to-analog converter DAC through the positive terminal +, and can receive the output voltage VET_APT through the negative terminal -. In addition, the output comparator OCP can output the comparison result between the received reference voltage signal A_REF and the output voltage VET_APT to the multiplexer MUX.

[0365] For reference, the output terminal of the power modulator 300-5 can be connected to the negative terminal - of the output comparator OCP and the power amplifier PA. In this case, the output voltage VET_APT generated by the power modulator 300-5 can be directly provided to the negative terminal - of the output comparator OCP. In addition, a connection circuit (not shown; for example, a circuit including a resistor and a capacitor) that connects the output terminal of the power modulator 300-5 to the negative terminal - of the output comparator OCP can be included in the power modulator 300-5. In this case, the connection circuit can reduce the level of the output voltage VET_APT generated and output by the power modulator 300-5 and then provide the reduced output voltage VET_APT to the negative terminal - of the output comparator OCP.

[0366] The multiplexer MUX may output one of the output of the compensation comparator CCP and the output of the output comparator OCP to the switching regulator 330 as the switching regulator control signal SRC.

[0367] That is, in the APT mode, the multiplexer MUX can output the output of the output comparator OCP as the switching regulator control signal SRC to the switching regulator 330, and in the ET mode (for example, the DL-ET mode or the CL-ET mode), the multiplexer MUX can output the output of the compensation comparator CCP as the switching regulator control signal SRC to the switching regulator 330.

[0368] For reference, when the output of the compensation comparator CCP is a high-level signal, the switching regulator control signal SRC may also be a high-level signal. Furthermore, when the switching regulator 330 receives a high-level signal as the switching regulator control signal SRC, the output current ILF outputted from the switching regulator 330 may be increased. Conversely, when the output of the compensation comparator CCP is a low-level signal, the switching regulator control signal SRC may also be a low-level signal. Furthermore, when the switching regulator 330 receives a low-level signal as the switching regulator control signal SRC, the output current ILF outputted from the switching regulator 330 may be decreased.

[0369] That is, through the above ILF increase and decrease mechanism, the current value of the output current ILF can be adjusted so that the average value of the compensation value CV is approximately zero, and the voltage VAC of the coupling capacitor CAC can be maintained at the voltage level of the target voltage signal VCCMIN. In addition, through such a maintenance process, the level difference between the output voltage VET_APT of the power supply modulator 300-5 and the voltage VHF according to the output current IHF (for example, the output voltage of the multi-output voltage regulator 310) can be maintained at the level of the voltage VAC of the coupling capacitor CAC.

[0370] As described above, in embodiments of the inventive concept, since VHF is lower than VET_APT by VAC, when the power modulator 300-5 outputs VET_APT at a specific level, the output voltage VHF of the multi-output voltage regulator 310 can be lower by VAC than the output voltage VHF of the prior art, and the level of the input voltage VIN of the multi-output voltage regulator 310 can also be lower than the level of the input voltage VIN of the prior art. In addition, in embodiments of the inventive concept, since the maximum values (e.g., upper limits) of the output voltage of the switch array 370 and the output voltage of the linear regulator LA can be lowered by the above-described mechanism, the switch array 370 and the linear regulator LA can include elements having a lower voltage resistance than the prior art.

[0371] That is, in the case of the power supply modulator 300-5 according to an embodiment of the inventive concept, since the power supply can be supplied to the power amplifier (eg, Figure 1 The PA) supplies a high output voltage VET_APT, and the switch array 370 and the linear regulator LA include elements having a lower withstand voltage than that of the related art, so power efficiency can be improved compared to the related art.

[0372] For reference, in the DL-ET mode, the switching regulator 330 can output the output current ILF based on the switching regulator control signal SRC received from the multiplexer MUX. In addition, when the level of the output current ILF is increased or decreased based on the switching regulator control signal SRC, the average value of the output current IHF output from the multi-output voltage regulator 310 can be approximately zero. In addition, since the average value of the output current IHF is approximately zero, the level of the voltage output from the multi-output voltage regulator 310 is also reduced. In this case, the size of the switching element used in the multi-output voltage regulator 310 can be large. Therefore, in an embodiment of the inventive concept, the size of the switching element used in the multi-output voltage regulator 310 can be reduced compared to the prior art, and thus, the power conversion efficiency of the multi-output voltage regulator 310 can be improved.

[0373] As described above, the switching regulator controller 350 may selectively sense one of the output current of the multi-output voltage regulator 310 and the output current of the linear regulator LA based on the above structure and characteristics, and may control the switching regulator 330 based on the sensed value SV.

[0374] As a reference, although Figure 18 Although not shown in FIG, the switching regulator controller 350 may sense factors other than the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA, and may control the switching regulator 330 based on the corresponding sensed values. That is, the feedback loop FL may sense factors other than the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA, and may provide the sensed values to the summer ADD. When the feedback loop FL senses different factors, the feedback loop FL may sense factors other than the output current of the multi-output voltage regulator 310 or the output current of the linear regulator LA, and may provide the sensed values to the summer ADD. Figure 18 The feedback loops of different paths can be configured as shown in FIG.

[0375] For example, switching regulator controller 350 may sense the following factors.

[0376] 1) The internal current of the multi-output voltage regulator 310 (eg, flowing through the internal inductor (eg, Figure 20 L'), the current flowing through the internal LDO (for example, Figure 21 the current flowing through the capacitor (e.g., C1 to CN-1);

[0377] 2) the current applied to the multi-output voltage regulator 310 from the input voltage (ie, power source provided from a battery, etc.; VIN); and / or

[0378] 3) The internal voltage of the multi-output voltage regulator 310 (eg, the internal switch voltage (eg, Figure 20Switch voltage of switch SM1 to SM(N-1)), internal LDO (e.g. Figure 21 The gate voltage of LDO1 to LDO(N-2)) and so on.

[0379] However, for ease of explanation, in the embodiment of the inventive concept, a case is described as an example where the switching regulator controller 350 selectively senses one of the output current of the multi-output voltage regulator 310 and the output current of the linear regulator LA and controls the switching regulator 330 based on the sensed value SV.

[0380] The switch array 370 may include a plurality of switches S1 to SN (where N is a natural number of two or greater). Furthermore, any one switch SN of the plurality of switches S1 to SN may be connected to the ground voltage GND, and the remaining switches S1 to SN-1 of the plurality of switches S1 to SN may be connected to the multi-output voltage regulator 310 to respectively correspond to the plurality of voltages V1 to VN-1 having different levels output from the multi-output voltage regulator 310. Furthermore, the switching operations of the plurality of switches S1 to SN in the switch array 370 may be controlled by a switch control signal SW provided from the switch controller 380. Thus, the switch array 370 may select one of the plurality of voltages V1 to VN-1 having different levels and the ground voltage GND (e.g., 0V) based on the switch control signal SW, and provide the selected voltage to the power amplifier PA.

[0381] The discrete level controller 390 may generate a level control signal ENV_LV including a plurality of pieces of envelope level information based on a digital envelope signal D_ENV received from the outside.

[0382] In detail, the discrete level controller 390 may receive the digital envelope signal D_ENV from the modem 100 and generate and output a level control signal ENV_LV including a plurality of pieces of envelope level information based on the digital envelope signal D_ENV received from the modem 100. In addition, the level control signal ENV_LV output from the discrete level controller 390 may be provided to the switch controller 380.

[0383] The switch controller 380 may receive the level control signal ENV_LV from the discrete level controller 390 and control the switching operation of the plurality of switches S1 to SN based on the level control signal ENV_LV received from the discrete level controller 390. That is, the switch controller 380 may generate the switch control signal SW for controlling the switching operation of the switch array 370 and provide the generated switch control signal SW to the switch array 370. In addition, the switch controller 380 may be controlled by the main controller 360.

[0384] In detail, in the DL-ET mode, the switch controller 380 may control a switching operation of the switch array 370 to select a voltage to be supplied to the power amplifier PA from among a plurality of voltages V1 to VN-1 having different levels from each other and the ground voltage GND.

[0385] Furthermore, in the APT mode, the switch controller 380 may connect the ground voltage GND to the coupling capacitor CAC by controlling the switch SN connected to the ground voltage GND among the plurality of switches S1 to SN.

[0386] Therefore, in the APT mode, the coupling capacitor CAC can be used as a decoupling capacitor connected to the output voltage VET_APT. A separate capacitor (not shown) may be additionally connected to the output terminal of the power modulator 300-5, and in this case, in the APT mode, the separate capacitor additionally connected to the output terminal of the power modulator 300-5 can be used as a decoupling capacitor.

[0387] However, in an embodiment of the inventive concept, for convenience of explanation, a case where the coupling capacitor CAC is used as a decoupling capacitor in the APT mode will be described as an example.

[0388] The coupling capacitor CAC may be connected between the multi-output voltage regulator 310 and the output terminal of the power modulator 300-5. In addition, the coupling capacitor CAC may be, for example, an AC coupling capacitor, but is not limited thereto.

[0389] In detail, in the case of the coupling capacitor CAC, one end of the coupling capacitor CAC may be connected to the linear regulator LA and the switch array 370, and the other end of the coupling capacitor CAC may be connected to the power amplifier PA. Figure 18 As shown in , the other end of the coupling capacitor CAC may be connected to the inductor L of the switching regulator 330 and the output end of the power modulator 300 - 5 (the output end of the output voltage VET_APT), and therefore, the coupling capacitor CAC may be included in the power modulator 300 - 5.

[0390] The coupling capacitor CAC may be included outside the power modulator 300 - 5 , but in an embodiment of the inventive concept, for convenience of explanation, a case in which the coupling capacitor CAC is included in the power modulator 300 - 5 will be described as an example.

[0391] The maximum output voltage (e.g., maximum or highest level voltage) of the multi-output voltage regulator 310 and the number of output voltages can be reduced by the presence of the coupling capacitor CAC. In addition, since the coupling capacitor CAC can be used as a decoupling capacitor in the APT mode, it will be described in detail below.

[0392] The main controller 360 may generate a plurality of reference output voltage signals VREF1 to VREFN-1 and provide the plurality of reference output voltage signals VREF1 to VREFN-1 to the multi-output voltage regulator 310. In addition, the main controller 360 may generate a target voltage signal VCCMIN for the coupling capacitor CAC and provide the target voltage signal VCCMIN for the coupling capacitor CAC to the switching regulator controller 350. Furthermore, the main controller 360 may determine a tracking mode and control at least one of the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390 based on the determined tracking mode.

[0393] In detail, the main controller 360 can communicate with the host controller 360 via MIPI ( Figure 1 130 ) receives a tracking mode determination signal from the modem 100 and may determine the tracking mode of the power modulator 300 - 5 based on the tracking mode determination signal received from the modem 100 .

[0394] Therefore, when the tracking mode is determined to be the DL-ET mode, the main controller 360 may control the parallel operation of the multi-output voltage regulator 310 and the switching regulator 330. In this case, the multi-output voltage regulator 310 and the switching regulator 330 may jointly generate a modulation voltage according to the DL-ET mode and provide the generated modulation voltage to the power amplifier PA.

[0395] Subsequently, when the tracking mode is determined to be the CL-ET mode, the main controller 360 may control the parallel operation of the linear regulator LA and the switching regulator 330. In this case, the linear regulator LA and the switching regulator 330 may jointly generate a modulation voltage according to the CL-ET mode and provide the generated modulation voltage to the power amplifier PA.

[0396] Finally, when the tracking mode is determined to be the APT mode, the main controller 360 may control the output voltage generation operation of the switching regulator 330. In this case, the switching regulator 330 may generate a modulation voltage according to the APT mode and provide the generated modulation voltage to the power amplifier PA as the output voltage VET_APT.

[0397] In the APT mode, the switch controller 380 may control the switching operation of the switch array 370 to activate the coupling capacitor CAC as a decoupling capacitor.

[0398] The main controller 360 can receive various signals (e.g., various control signals (such as output voltage level signals, etc.)) other than the tracking mode determination signal from the modem 100 via the MIPI 130, and control components (such as the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390) based on the received various signals.

[0399] As a reference, in Figure 18 , the main controller 360 is shown as controlling at least one of the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390, but is not limited thereto. That is, the main controller 360 may control the operation of components other than the above components.

[0400] However, for ease of explanation, in the embodiments of the inventive concept, a case where the main controller 360 controls at least one of the multi-output voltage regulator 310, the linear regulator LA, the switch controller 380, the switching regulator controller 350 and the discrete level controller 390 is described as an example.

[0401] In addition to the above components, the power supply modulator 300 - 5 may further include an additional capacitor (not shown), an oscillator (not shown), a bandgap reference circuit (not shown), and the like.

[0402] Specifically, an additional capacitor may be connected near the output terminal of power supply modulator 300-5 to remove parasitic capacitance and high-frequency noise that may be present in the circuit of power supply modulator 300-5. Furthermore, an oscillator is a circuit that may be desirable when using an NMOS structure (e.g., a gate-boosted NMOS structure) to improve the characteristics of multiple switches S1 to SN. Furthermore, a bandgap reference circuit is a circuit that supplies a reference voltage or current that is desired when each component operates, and is largely unaffected by changes in operation, voltage, or temperature.

[0403] As described above, the power modulator 300-5 may have the above structure and characteristics. In addition, based on the structure and characteristics, the power modulator 300-5 may be driven in any one of the tracking modes of the DL-ET mode, the CL-ET mode, and the APT mode, and provide the output voltage VET_APT to the power amplifier PA.

[0404] Here, reference will be made to the above-described Figure 8 To describe the waveform characteristics of the output voltage according to the tracking mode.

[0405] In detail, the APT mode is a mode in which a modulation voltage that varies based on the peak level of the envelope RF_OUT_ENV of the RF output signal RF_OUT at a specific time interval (eg, TTI) is applied to the power amplifier ( Figure 1 In addition, the CL-ET mode is a tracking mode in which a modulation voltage that follows the level of the envelope RF_OUT_ENV of the RF output signal RF_OUT is applied instantaneously or rapidly to the power amplifier ( Figure 1 In addition, the DL-ET mode is a tracking mode in which a modulation voltage following the level of the envelope RF_OUT_ENV of the RF output signal RF_OUT is applied to the power amplifier ( Figure 1 A tracking mode of the PA) is provided, wherein the modulation voltage is limited to the sum voltage of one of a plurality of voltages having levels different from each other generated by the multi-output voltage regulator 310 and the voltage VAC of the coupling capacitor CAC, or is limited to the voltage VAC of the coupling capacitor CAC.

[0406] For reference, the envelope RF_OUT_ENV of the RF output signal RF_OUT may be generated based on the amplitude (magnitude) of the RF output signal RF_OUT.

[0407] The mechanism of the power modulator 300-5 generating the output voltage VET_APT in the ET mode (DL-ET mode or CL-ET mode) is similar to that of the power modulator 300-5. Figure 9 The above descriptions are the same or similar, so their detailed descriptions will be omitted.

[0408] As described above, the power modulator 300-5 may generate a modulation voltage that varies according to one tracking mode among the APT mode, the DL-ET mode, and the CL-ET mode, to provide the generated modulation voltage as a power voltage to the power amplifier ( Figure 1 PA).

[0409] In addition, based on the above characteristics, as the power amplifier ( Figure 1 The RF output signal RF_OUT of the PA) is connected to the modulation voltage of the power modulator 300-5 (for example, the modulation voltage provided to the power amplifier ( Figure 1 The voltage difference between the output voltages VET_APT of the PA) is reduced, energy waste can be minimized or reduced, and the battery life can be improved.

[0410] In the power amplifier ( Figure 1In the case of the power efficiency of the PA (for example, a PA with a power supply), the power efficiency in the ET mode (DL-ET mode or CL-ET mode) is greater than the power efficiency in the APT mode. Conversely, in the case of the power efficiency of the power supply modulator 300-5, the power efficiency in the APT mode is greater than the power efficiency in the ET mode (DL-ET mode or CL-ET mode).

[0411] As a reference, the power efficiency of the entire system (e.g. Figure 1 The efficiency of the wireless communication device 1) can be compared with the power efficiency of the power modulator 300-5 and the power amplifier (e.g., Figure 1 is proportional to the power efficiency of the PA).

[0412] Therefore, in the high power region, the power level of the RF output signal RF_OUT (more specifically, the antenna ( Figure 1 The transmission power of the ANT) is high, and the power efficiency of the entire system can be greater in the ET mode (DL-ET mode or CL-ET mode) than in the APT mode. On the contrary, in the low power area, the power level of the RF output signal RF_OUT (more specifically, the antenna ( Figure 1 The transmission power of ANT) is low, and the power efficiency of the entire system can be greater in APT mode than in ET mode (DL-ET mode or CL-ET mode).

[0413] Therefore, the power modulator 300-5 can be configured to provide a power supply according to the antenna ( Figure 1 The transmit power TX power of ANT) is selectively driven in any one of the ET mode (DL-ET mode or CL-ET mode) and the APT mode.

[0414] For reference, the CL-ET mode is achieved by using the linear regulator LA to track the RF output signal ( Figure 1 Therefore, the CL-ET mode can accurately track the RF output signal (RF_OUT) by Figure 1 When the output voltage VET_APT is generated by using the envelope RF_OUT_ENV of the linear regulator RF_OUT), excellent power conversion efficiency is achieved. However, the bandwidth of the output voltage VET_APT may be limited by the bandwidth of the linear regulator LA.

[0415] In contrast, the DL-ET mode tracks the RF output signal ( Figure 1 The envelope of RF_OUT) RF_OUT_ENV will be supplied to the power amplifier ( Figure 1The output voltage VET_APT of the PA) is limited to a method in which a plurality of voltages V1 to VN-1 having different levels from each other can be generated by the multi-output voltage regulator 310. Therefore, in the DL-ET mode, the output voltage VET_APT is different from the RF output signal ( Figure 1 A voltage difference may occur between the envelope RF_OUT_ENV of the output voltage (RF_OUT) and the output voltage (RF_OUT_ENV), resulting in lower power conversion efficiency than in CL-ET mode. However, in DL-ET mode, the power efficiency of the power modulator can be greater than that in CL-ET mode. In addition, in DL-ET mode, since the linear regulator LA is not used, the bandwidth of the output voltage VET_ATP can be greater than that in CL-ET mode.

[0416] For reference, the channel bandwidth used or to be used in NR (5G) may exceed the bandwidth limit of the linear regulator LA. Therefore, in NR (5G), the CL-ET mode using the linear regulator LA may be difficult to implement. However, in the DL-ET mode, since the output of the multi-output voltage regulator 310 is provided to the power amplifier (e.g., one of the switches S1 to SN-1) (e.g., the output of the multi-output voltage regulator 310 does not pass through the linear regulator LA) through the switch (e.g., S1 to SN-1), the output of the multi-output voltage regulator 310 is provided to the power amplifier (e.g., Figure 1 PA), so the above bandwidth-related challenges can be solved.

[0417] Therefore, the main controller 360 may determine any one tracking mode of the DL-ET mode and the CL-ET mode in a direction that may improve the power efficiency of the entire system by considering the above situation.

[0418] exist Figure 22 , a mechanism is shown in which the output voltage of the multi-output voltage regulator 310 is boosted by the coupling capacitor CAC in the power supply modulator 300 - 5 .

[0419] Reference Figure 18 and Figure 22 , shows an operation of generating the output voltage VET_APT by summing the output voltage VHF (V1 to VN-1) of the multi-output voltage regulator 310 and the voltage VAC of the coupling capacitor CAC. That is, Figure 22 The difference between the two voltages VHF and VET_APT due to the voltage VAC of the coupling capacitor CAC is shown in FIG.

[0420] For reference, as described above, in the DL-ET mode, the output current ILF of the switching regulator 330 may be controlled based on the switching regulator control signal SRC such that the average value of the output current IHF of the multi-output voltage regulator 310 is approximately zero.

[0421] More specifically, the switching regulator control signal SRC can be adjusted so that the average value of the compensation value CV (e.g., the sum of the sensed value SV of the output current IHF and the difference value DV output from the OTA) output from the summer ADD in the switching regulator controller 350 is approximately zero. Furthermore, as described above, the magnitude of the output current ILF of the switching regulator 330 can be adjusted by the adjusted switching regulator control signal SRC. Furthermore, through the magnitude adjustment operation of the output current ILF of the switching regulator 330, the average value of the output current IHF of the multi-output voltage regulator 310 is approximately zero, and the voltage VAC of the coupling capacitor CAC can be maintained at the voltage level of the target voltage signal VCCMIN.

[0422] That is, the voltage VAC of the coupling capacitor CAC may be regulated to a target voltage value indicated by the target voltage signal VCCMIN through the above-described approximate operation performed by the switching regulator controller 350 .

[0423] In addition, in the DL-ET mode, when the switch SN connected to the ground voltage GND among the switches of the switch array 370 is turned on (e.g., closed), the voltage VAC of the coupling capacitor CAC can reach the minimum voltage level of the output voltage VET_APT in the DL-ET mode (as used herein, the minimum voltage level can also be referred to as the lower limit voltage level). Therefore, when the main controller 360 adjusts the target voltage signal VCCMIN in the DL-ET mode, the minimum voltage level of the output voltage VET_APT can also be adjusted.

[0424] Based on this principle, refer to Figure 22 , the minimum voltage level of the output voltage VET_APT may be VAC, and the maximum voltage level of the output voltage VET_APT may be V1+VAC obtained by summing the maximum voltage value V1 of the multi-output voltage regulator 310 with VAC. In addition, although the maximum voltage level of the multi-output voltage regulator 310 is V1, the voltage level of V1 may be increased by the coupling capacitor CAC, and the maximum voltage level of the output voltage VET_APT may be V1+VAC, which is VAC greater than V1.

[0425] In addition, even when the coupling capacitor CAC is connected to the ground voltage GND via the switch SN of the switch array 370 instead of the multi-output voltage regulator 310, the output voltage VET_APT having the VAC level as the minimum voltage level can be supplied to the power amplifier PA. That is, even when the connection between the multi-output voltage regulator 310 and the output terminal of the power supply modulator 300-5 is disconnected by the switch array 370, the output voltage VET_APT can be supplied to the power amplifier PA. Therefore, in an embodiment of the inventive concept, the number of output voltages of the multi-output voltage regulator 310 can be one less than the total number of output voltages VHF that can be used to generate the output voltage VET_APT (for example, one output voltage of the multi-output voltage regulator 310 used to generate the output voltage VET_APT having the minimum voltage level).

[0426] As described above, since the power modulator 300-5 is driven to the APT mode or the ET mode (DL-ET mode or CL-ET mode) to generate the output voltage VET_APT based on the above principle, hereinafter, referring to Figures 23 to 25 , the operation of the power supply modulator 300 - 5 according to the tracking mode will be described.

[0427] As a reference, in Figures 23 to 25 In each of , the portion indicated by the bold line may represent an operation activation path in the corresponding drawing.

[0428] First, refer to Figure 23 , shows the operation of the power supply modulator 300 - 5 in the APT mode.

[0429] The main controller 360 may receive an APT mode determination signal from the modem 100 and determine the APT mode of the power modulator 300 - 5 based on the APT mode determination signal received from the modem 100 .

[0430] In this case, the main controller 360 may control the switching regulator controller 350 based on the determined tracking mode, and the switching regulator controller 350 may control the switching regulator 330 based on the control of the main controller 360 .

[0431] Therefore, the switching regulator 330 can generate a modulation voltage VSR according to the APT mode, and provide the generated modulation voltage VSR as an output voltage VET_APT to the power amplifier ( Figure 1 PA).

[0432] In more detail, in order to generate the modulation voltage VSR according to the APT mode, the digital-to-analog converter DAC of the switching regulator controller 350 may receive the average power signal D_REF from the modem 100 and convert the average power signal D_REF received from the modem 100 into a reference voltage signal A_REF. The digital-to-analog converter DAC may provide the converted reference voltage signal A_REF to the output comparator OCP, and the output comparator OCP may compare the output voltage VET_APT with the reference voltage signal A_REF. In addition, the output comparator OCP may output the comparison result to the multiplexer MUX, and the multiplexer MUX may output the output of the output comparator OCP as the switching regulator control signal SRC to the switching regulator 330. The switching regulator 330 may generate the modulation voltage VSR according to the APT mode based on the switching regulator control signal SRC received from the multiplexer MUX, and provide the generated modulation voltage VSR as the output voltage VET_APT to the power amplifier ( Figure 1 PA).

[0433] For reference, in the embodiment of the inventive concept, a method of controlling the output voltage VET_APT by using the output comparator OCP in the APT mode (e.g., a hysteresis (bang-bang) control method) is shown, but it is not limited thereto. That is, in the embodiment of the inventive concept, a method of controlling the output voltage VET_APT by using a compensator instead of a comparator in the APT mode (e.g., a voltage mode control method) can be used. However, for ease of explanation, in the embodiment of the inventive concept, a case where the method of controlling the output voltage VET_APT based on the output comparator OCP in the APT mode is used is described as an example.

[0434] Furthermore, the main controller 360 may control the switch controller 380 based on the determined tracking mode, and the switch controller 380 may control the switch array 370 based on the control of the main controller 360 .

[0435] In more detail, the switch controller 380 may control switching operations of some of the plurality of switches S1 to SN based on the control of the main controller 360. Therefore, the switch array 370 may turn on the switch SN connected to the ground voltage GND based on the control of the switch controller 380, and the coupling capacitor CAC may be used as a decoupling capacitor in the APT mode through the turned-on switch SN.

[0436] As a reference, although Figure 23Although not shown in the figure, a separate capacitor (not shown) may also be included in the output terminal of the power supply modulator 300-5. In this case, the capacitor connected to the output terminal of the power supply modulator 300-5 may also be used as a decoupling capacitor in the APT mode.

[0437] In addition, although Figure 23 Although not shown in FIG, the multi-output voltage regulator 310 may also generate a modulation voltage according to the APT mode based on the control of the main controller 360.

[0438] However, for convenience of explanation, in an embodiment of the inventive concept, a case where the coupling capacitor CAC is used as a decoupling capacitor and the switching regulator 330 generates and outputs the output voltage VET_APT in the APT mode will be described as an example.

[0439] Then, refer to Figure 24 , shows the operation of the power modulator 300 - 5 in the DL-ET mode.

[0440] The main controller 360 may receive a DL-ET mode determination signal from the modem 100 and determine the DL-ET mode of the power modulator 300 - 5 based on the DL-ET mode determination signal received from the modem 100 .

[0441] In this case, the main controller 360 can control the multi-output voltage regulator 310, the switching regulator controller 350, the switch controller 380, and the discrete level controller 390 based on the determined tracking mode. In addition, the switching regulator controller 350 can control the switching regulator 330, and the switch controller 380 can control the switch array 370. Therefore, the switching regulator 330 and the multi-output voltage regulator 310 can generate a modulation voltage together according to the DL-ET mode and provide the generated modulation voltage to the power amplifier ( Figure 1 PA).

[0442] In more detail, the multi-output voltage regulator 310 can receive a plurality of reference output voltage signals VREF1 to VREFN-1 from the main controller 360, and can provide a plurality of voltages V1 to VN-1 having different levels from each other by raising or lowering an input voltage (e.g., a power source VIN provided from a battery, etc.) based on the plurality of reference output voltage signals VREF1 to VREFN-1 received from the main controller 360.

[0443] The discrete level controller 390 may receive the digital envelope signal D_ENV from the modem 100 and generate a level control signal ENV_LV including a plurality of pieces of envelope level information based on the digital envelope signal D_ENV received from the modem 100. In addition, the discrete level controller 390 may provide the generated level control signal ENV_LV to the switch controller 380.

[0444] The switch controller 380 may receive a level control signal ENV_LV from the discrete level controller 390 and control switching operations of the plurality of switches S1 to SN based on the level control signal ENV_LV received from the discrete level controller 390. That is, the switch controller 380 may control the switching operation of the switch array 370 to select a voltage to be supplied to the power amplifier PA from among a plurality of voltages V1 to VN-1 having different levels from each other and the ground voltage GND.

[0445] Therefore, a switch (e.g., S1) selected from among the plurality of switches S1 to SN by the switch control signal SW may be turned on, and a voltage (e.g., V1) having a specific level corresponding to the switch may be provided to the power amplifier ( Figure 1 A voltage (e.g., V1) having a specific level outputted through the turned-on switch (e.g., S1) may be summed with the voltage VAC of the coupling capacitor CAC to become a final output voltage VET_APT, and the final output voltage VET_APT may be provided to the power amplifier ( Figure 1 PA).

[0446] For reference, the power amplifier ( Figure 1 The output current IHF of the multi-output voltage regulator 310 (PA) may be sensed by the feedback loop FL of the switching regulator controller 350, and the sensed value SV may be provided to the summer ADD.

[0447] The OTA in the switching regulator controller 350 may receive a target voltage signal VCCMIN from the main controller 360 via a positive terminal + and receive a voltage VAC of the coupling capacitor CAC via a negative terminal -. Furthermore, the OTA may compare the target voltage signal VCCMIN with the voltage VAC of the coupling capacitor CAC and output a difference DV between the target voltage signal VCCMIN and the voltage VAC of the coupling capacitor CAC based on the comparison result.

[0448] The summer ADD may sum the difference value output from the OTA with the sensed value SV of the output current IHF of the multi-output voltage regulator 310 sensed by the feedback loop FL and output the summed value as the compensation value CV. In addition, the compensation value CV output from the summer ADD may be provided to the compensation comparator CCP.

[0449] The compensation comparator CCP can receive the compensation value CV output from the summer ADD through the positive terminal + and receive the reference value through the negative terminal -. In addition, the compensation comparator CCP can output a comparison result between the received compensation value CV and the reference value to the multiplexer MUX.

[0450] In the DL-ET mode, the multiplexer MUX may output the output of the compensation comparator CCP to the switching regulator 330 as the switching regulator control signal SRC.

[0451] The switching regulator 330 may generate a modulation voltage VSR according to the DL-ET mode based on the switching regulator control signal SRC received from the multiplexer MUX, and supply the generated modulation voltage VSR to the power amplifier ( Figure 1 PA).

[0452] For reference, the output current ILF of the switching regulator 330 output based on the switching regulator control signal SRC may be combined with the output current IHF of the multi-output voltage regulator 310 described above and may be provided to the power amplifier ( Figure 1 PA).

[0453] Finally, refer to Figure 25 , shows the operation of the power supply modulator 300 - 5 in the CL-ET mode.

[0454] The main controller 360 may receive a CL-ET mode determination signal from the modem 100 and determine the CL-ET mode of the power modulator 300 - 5 based on the CL-ET mode determination signal received from the modem 100 .

[0455] In this case, the main controller 360 may control the linear regulator LA and the switching regulator controller 350 based on the determined tracking mode. In addition, the switching regulator controller 350 may control the switching regulator 330. Therefore, the switching regulator 330 and the linear regulator LA may generate a modulation voltage together according to the CL-ET mode and provide the generated modulation voltage to the power amplifier ( Figure 1 PA).

[0456] In more detail, the linear regulator LA may receive the analog envelope signal A_ENV from the modem 100 and output the analog envelope signal A_ENV received from the modem 100 to output the output current IHF. In addition, the output current IHF output by the linear regulator LA may be provided to the power amplifier ( Figure 1 PA).

[0457] For reference, the output current IHF of the linear regulator LA may be sensed by the feedback loop FL of the switching regulator controller 350 , and the sensed value SV may be provided to the summer ADD.

[0458] The OTA in the switching regulator controller 350 may receive a target voltage signal VCCMIN from the main controller 360 via a positive terminal + and receive a voltage VAC of the coupling capacitor CAC via a negative terminal -. Furthermore, the OTA may compare the target voltage signal VCCMIN with the voltage VAC of the coupling capacitor CAC and output a difference DV between the target voltage signal VCCMIN and the voltage VAC of the coupling capacitor CAC based on the comparison result.

[0459] The summer ADD can sum the difference value output from the OTA with the sensed value SV of the output current IHF of the linear regulator LA sensed by the feedback loop FL, and output the summed value as the compensation value CV. In addition, the compensation value CV output from the summer ADD can be provided to the compensation comparator CCP.

[0460] The compensation comparator CCP can receive the compensation value CV output from the summer ADD through the positive terminal + and receive the reference value through the negative terminal -. In addition, the compensation comparator CCP can output a comparison result between the received compensation value CV and the reference value to the multiplexer MUX.

[0461] The multiplexer MUX may output the output of the compensation comparator CCP to the switching regulator 330 as the switching regulator control signal SRC.

[0462] The switching regulator 330 may generate a modulation voltage VSR according to the CL-ET mode based on the switching regulator control signal SRC received from the multiplexer MUX, and provide the generated modulation voltage VSR to the power amplifier ( Figure 1 PA).

[0463] For reference, the output current ILF of the switching regulator 330 output based on the switching regulator control signal SRC may be combined with the output current IHF of the linear regulator LA described above and may be provided to the power amplifier ( Figure 1 PA).

[0464] As described above, since the power modulator 300-5 is driven according to the APT mode, the DL-ET mode, or the CL-ET mode based on the above principle, hereinafter, reference is made to Figures 26 to 28 , a sixth example of a power supply modulator according to an embodiment of the inventive concept will be described.

[0465] Figure 26 is a circuit diagram illustrating a sixth example of a power modulator 300 - 6 included in a wireless communication device according to an embodiment of the inventive concept. Figure 27 It shows Figure 26 FIG. 3 is a diagram illustrating the APT mode operation of the power supply modulator 300 - 6 . Figure 28 It shows Figure 26 FIG. 3 is a diagram illustrating the DL-ET mode operation of the power supply modulator 300 - 6 .

[0466] In the following, for the convenience of explanation, it is assumed that the power supply modulator 300-6 is implemented as Figure 1 The power supply modulator 300 of the wireless communication device 1 shown in FIG. Figure 1 describe Figure 26 In addition, due to Figure 26 The power supply modulator 300-6 with Figure 18 The power supply modulator 300 - 5 is the same or similar except for some structures and mechanisms, so the following will mainly describe the differences.

[0467] Reference Figure 26 , a sixth example of the power modulator 300 according to an embodiment of the inventive concept (i.e., power modulator 300-6) may include a multi-output voltage regulator 310, a switching regulator 330, a switching regulator controller 350, a main controller 360, a switch array 370, a switch controller 380 and / or a discrete level controller 390.

[0468] In detail, with Figure 18 The power supply modulator 300-5 is different, Figure 26 The power supply modulator 300 - 6 may not include the linear regulator LA.

[0469] Therefore, the power modulator 300 - 6 can operate in either the DL-ET mode or the APT mode.

[0470] First, the switching regulator 330 may operate together with the multi-output voltage regulator 310 in the DL-ET mode to generate the output voltage VET_APT, and the switching regulator 330 may operate in the APT mode to generate the output voltage VET_APT.

[0471] Furthermore, in the DL-ET mode, the switching regulator controller 350 may sense the output current IHF of the multi-output voltage regulator 310 and control the switching regulator 330 based on the sensed value SV.

[0472] In detail, in the DL-ET mode, the feedback loop FL of the switching regulator controller 350 may sense the output current IHF of the multi-output voltage regulator 310 and provide the sensed value SV to the summer ADD.

[0473] In addition, in the APT mode, the multiplexer MUX of the switching regulator controller 350 can output the output of the output comparator OCP as the switching regulator control signal SRC to the switching regulator 330, and in the DL-ET mode, the multiplexer MUX of the switching regulator 330 can output the output of the compensation comparator CCP as the switching regulator control signal SRC to the switching regulator 330.

[0474] The main controller 360 may generate a plurality of reference output voltage signals VREF1 to VREFN-1 and provide the plurality of reference output voltage signals VREF1 to VREFN-1 to the multi-output voltage regulator 310. In addition, the main controller 360 may generate a target voltage signal VCCMIN for the coupling capacitor CAC and provide the target voltage signal VCCMIN for the coupling capacitor CAC to the switching regulator controller 350. Furthermore, the main controller 360 may determine a tracking mode and control at least one of the multi-output voltage regulator 310, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390 according to the determined tracking mode.

[0475] The main controller 360 can be connected via MIPI ( Figure 1 130) receives various signals (e.g., various control signals (such as output voltage level signals, etc.)) other than the tracking mode determination signal from the modem 100, and controls components (such as the multi-output voltage regulator 310, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390) based on the received various signals.

[0476] As a reference, in Figure 26 , the main controller 360 is shown as controlling at least one of the multi-output voltage regulator 310, the switch controller 380, the switching regulator controller 350, and the discrete level controller 390, but is not limited thereto. That is, the main controller 360 may control the operation of components other than the above components.

[0477] However, for convenience of explanation, in the embodiment of the inventive concept, a case where the main controller 360 controls at least one of the multi-output voltage regulator 310 , the switch controller 380 , the switching regulator controller 350 , and the discrete level controller 390 is described as an example.

[0478] As described above, since the power supply modulator 300-6 has the above structure and characteristics, it is Figure 18 Compared with the power modulator 300-5, the circuit area and manufacturing cost of the power modulator 300-6 can be reduced. In addition, based on the structure and characteristics, the power modulator 300-6 can be driven in either the DL-ET mode or the APT mode, and provide the output voltage VET_APT to the power amplifier PA.

[0479] As a reference, in Figure 27 and Figure 28 The following table shows the Figure 26 The operation activation paths of the APT mode and DL-ET mode of the power supply modulator 300-6.

[0480] However, due to Figure 27 The power supply modulator 300-6 operates in APT mode with Figure 23 The operations are the same or similar to those described in Figure 28 The power supply modulator 300-6 operates in DL-ET mode with Figure 24 The operations described in are the same or similar, so their detailed description will be omitted.

[0481] As described above, since the power supply modulator 300-6 operates according to the APT mode or the DL-ET mode based on the above principle, reference will be made to the following. Figure 29 A seventh example of the power supply modulator according to an embodiment of the inventive concept is described.

[0482] Figure 29 is a circuit diagram illustrating a seventh example of a power modulator 300 - 7 included in a wireless communication device according to an embodiment of the inventive concept.

[0483] For reference, in the following, for ease of explanation, it is assumed that the power supply modulator 300-7 is implemented as Figure 1 The power supply modulator 300 of the wireless communication device 1 is shown in FIG. Figure 29 The power supply modulator 300-7 with Figure 18 The power supply modulator 300 - 5 is the same or similar except for some structures and mechanisms, so the following will mainly describe the differences.

[0484] Reference Figure 29, a seventh example of the power modulator 300 according to an embodiment of the inventive concept (i.e., power modulator 300-7) may include a multi-output voltage regulator 310, a first switching regulator 330 and a second switching regulator 333, a first linear regulator LA1 and a second linear regulator LA2, a first switching regulator controller 350 and a second switching regulator controller 353, a main controller 360, a first switch array 370 and a second switch array 373, a first switch controller 380 and a second switch controller 383, a first discrete level controller 390 and a second discrete level controller 393 and / or a first coupling capacitor CAC1 and a second coupling capacitor CAC2.

[0485] In detail, Figure 29 The power supply modulator 300-7 can provide the first output voltage VET_APT1 and the second output voltage VET_APT2 to multiple power amplifiers (when there is Figure 1 power amplifier PA; for example, a first power amplifier and a second power amplifier).

[0486] Therefore, in Figure 29 In the case of the power supply modulator 300-7, with Figure 18 Compared to the power supply modulator 300 - 5 , the number of each of the switching regulator, the linear regulator, the switching regulator controller, the switch array, the switch controller, the discrete level controller, and the coupling capacitor may be greater than one.

[0487] In addition, due to Figure 29 Power supply modulator 300-7 ratio Figure 18 The power modulator 300-5 receives more signals, so the power modulator 300-7 can receive more signals from the modem ( Figure 1 100) receives the first and second average power signals D_REF1 and D_REF2, the first and second analog envelope signals A_ENV1 and A_ENV2, and the first and second digital envelope signals D_ENV1 and D_ENV2.

[0488] In addition, Figure 29In the power supply modulator 300-7, since the plurality of capacitors C1 to CN-1 of the multi-output voltage regulator 310 are connected to both sides of the first power amplifier and the second power amplifier, the plurality of capacitors C1 to CN-1 of the multi-output voltage regulator 310 can be shared for each of the first output voltage VET_APT1 and the second output voltage VET_APT2. Therefore, the main controller 360 can jointly generate a plurality of reference output voltage signals VREF1 to VREFN-1 for each of the first output voltage VET_APT1 and the second output voltage VET_APT2, and provide the plurality of reference output voltage signals VREF1 to VREFN-1 to the multi-output voltage regulator 310.

[0489] However, in Figure 29 In the power supply modulator 300-7, the first coupling capacitor CAC1 may be connected to the first power amplifier, and the second coupling capacitor CAC2 may be connected to the second power amplifier. Therefore, the main controller 360 may generate target voltage signals VCCMIN1 and VCCMIN2 for each of the first coupling capacitor CAC1 and the second coupling capacitor CAC2, and provide the target voltage signals VCCMIN1 and VCCMIN2 to the first OTA1 and the second OTA2, respectively.

[0490] For reference, when each of the target voltage signals VCCMIN1 and VCCMIN2 is set to be different from each other, the voltages VAC1 and VAC2 of each of the first coupling capacitor CAC1 and the second coupling capacitor CAC2 may also be different from each other. Therefore, although the multi-output voltage regulator 310 commonly generates and outputs a plurality of voltages V1 to VN-1 for each of the first output voltage VET_APT1 and the second output voltage VET_APT2, the ranges of the first output voltage VET_APT1 and the second output voltage VET_APT2 provided to the first power amplifier and the second power amplifier, respectively, may be different from each other. That is, in the case of power amplifiers, since the optimized or improved power supply voltage range of the power amplifiers varies depending on the RF carrier frequency, manufacturer, etc., in the power supply modulator 300-7 according to an embodiment of the inventive concept, by providing a difference between the voltages VAC1 and VAC2 of each of the first coupling capacitor CAC1 and the second coupling capacitor CAC2, a difference between the range of the first output voltage VET_APT1 and the range of the second output voltage VET_APT2 can be provided to the first power amplifier and the second power amplifier, respectively. Additionally, through this difference, the power efficiency of each of the first power amplifier and the second power amplifier may be individually optimized or improved.

[0491] As described above, in an embodiment of the inventive concept, even in the case where multiple power supply voltages are generated for multiple power amplifiers, the increase in circuit area can be minimized or reduced because the number of output capacitors occupying most of the circuit area is the same or similar to the case where the power supply voltage is generated for a single power amplifier.

[0492] For ease of explanation, assuming that the first linear regulator LA1, the first switching regulator 330, the first switching regulator controller 350, the first switch array 370, the first discrete level controller 390, the first switch controller 380 and the first coupling capacitor CAC1 form a first modulation circuit, and the second linear regulator LA2, the second switching regulator 333, the second switching regulator controller 353, the second switch array 373, the second discrete level controller 393, the second switch controller 383 and the second coupling capacitor CAC2 form a second modulation circuit, a brief description of each component of the power supply modulator 300-7 is as follows.

[0493] The first modulation circuit may include a first linear regulator LA1 and a first switching regulator 330, wherein the first linear regulator LA1 operates in a CL-ET mode to Figure 1The first modulation circuit 100 receives a first analog envelope signal A_ENV1 and generates a first output voltage VET_APT1. The first switching regulator 330 operates in conjunction with the multi-output voltage regulator 310 in DL-ET mode to generate the first output voltage VET_APT1. The first switching regulator 330 operates in conjunction with the first linear regulator LA1 in CL-ET mode to generate the first output voltage VET_APT1. The first switching regulator 330 also operates in APT mode to generate the first output voltage VET_APT1. Furthermore, the first modulation circuit 100 may include a first switching regulator controller 350 that selectively senses either an output current IHF1 of the multi-output voltage regulator 310 or an output current IHF1 of the first linear regulator LA1 and controls the first switching regulator 330 based on the sensed value SV1. Furthermore, the first modulation circuit 100 may include a first switch array 370 comprising a plurality of switches S1 to SN. The first switch array 370 can select one of the multiple voltages V1 to VN-1 having different levels from each other and the ground voltage GND through the multiple switches S1 to SN, and provide the one of the multiple voltages V1 to VN-1 having different levels from each other and the ground voltage GND to the first power amplifier. For reference, any one switch SN among the multiple switches S1 to SN can be connected to the ground voltage GND, and the remaining switches S1 to SN-1 among the multiple switches S1 to SN can be connected to the multi-output voltage regulator 310 to respectively correspond to the multiple voltages V1 to VN-1 having different levels output from the multi-output voltage regulator 310. In addition, the first modulation circuit may include a first discrete level controller 390 and a first switch controller 380. The first discrete level controller 390 is based on the output voltage from the modem ( Figure 1 The first switching controller 380 generates a first level control signal ENV_LV1 including multiple pieces of envelope level information based on the first digital envelope signal D_ENV1 provided by the first discrete level controller 390. The first switching controller 380 receives the first level control signal ENV_LV1 from the first discrete level controller 390 and controls the switching operations of the multiple switches S1 to SN based on the first level control signal ENV_LV1 received from the first discrete level controller 390. In addition, one end of the first coupling capacitor CAC1 may be connected to the first linear regulator LA1 and the first switch array 370, and the other end of the first coupling capacitor CAC1 may be connected to the first power amplifier (e.g., connected between the inductor L1 of the first switching regulator 330 and the first output terminal of the power supply modulator 300-7 (the output terminal of the first output voltage VET_APT1)).

[0494] The second modulation circuit may include a second linear regulator LA2 and a second switching regulator 333, wherein the second linear regulator LA2 operates in a CL-ET mode to Figure 1 The second modulation circuit may include a second switching regulator controller 353 that selectively senses either output current IHF2 of the multi-output voltage regulator 310 or the second linear regulator LA2 and controls the second switching regulator 333 based on the sensed value SV2. Furthermore, the second modulation circuit may include a second switch array 373 that includes a plurality of switches S1′ to SN′. The second switch array 373 can select one of the plurality of voltages V1 to VN-1 having different levels from each other and the ground voltage GND through the plurality of switches S1' to SN', and provide the voltage to the second power amplifier. For reference, any one switch SN' of the plurality of switches S1' to SN' can be connected to the ground voltage GND, and the remaining switches S1' to SN-1' of the plurality of switches S1' to SN' can be connected to the multi-output voltage regulator 310 to respectively correspond to the plurality of voltages V1 to VN-1 having different levels from each other output from the multi-output voltage regulator 310. In addition, the second modulation circuit may include a second discrete level controller 393 and a second switch controller 383. The second discrete level controller 393 generates a second level control signal ENV_LV2 including a plurality of envelope level information based on the second digital envelope signal D_ENV2 provided from the modem 100. The second switch controller 383 receives the second level control signal ENV_LV2 from the second discrete level controller 393 and controls switching operations of the plurality of switches S1′ to SN′ based on the second level control signal ENV_LV2 received from the second discrete level controller 393. In addition, one end of the second coupling capacitor CAC2 may be connected to the second linear regulator LA2 and the second switch array 373, and the other end of the second coupling capacitor CAC2 may be connected to the second power amplifier (e.g., connected between the inductor L2 of the second switching regulator 333 and the second output terminal (the output terminal of the second output voltage VET_APT2)) of the power supply modulator 300-7.

[0495] In the DL-ET mode, the multi-output voltage regulator 310 can output a plurality of voltages V1 to VN-1 having different levels from each other to correspond to the plurality of reference output voltage signals VREF1 to VREFN-1, respectively, to generate a first output voltage VET_APT1 or a second output voltage VET_APT2. That is, the multi-output voltage regulator 310 can operate in parallel with the switching regulators operating in the DL-ET mode among the first switching regulator 330 and the second switching regulator 333.

[0496] The main controller 360 can generate a plurality of reference output voltage signals VREF1 to VREFN-1 and provide the plurality of reference output voltage signals VREF1 to VREFN-1 to the multi-output voltage regulator 310. Furthermore, the main controller 360 can generate a target voltage signal VCCMIN1 for the first coupling capacitor CAC1 and provide the target voltage signal VCCMIN1 for the first coupling capacitor CAC1 to the first switching regulator controller 350. Furthermore, the main controller 360 can generate a target voltage signal VCCMIN2 for the second coupling capacitor CAC2 and provide the target voltage signal VCCMIN2 for the second coupling capacitor CAC2 to the second switching regulator controller 353. Furthermore, the main controller 360 can determine a tracking mode for each of the first power amplifier and the second power amplifier. That is, the main controller 360 can determine a different tracking mode for each of the first power amplifier and the second power amplifier, or can determine the same or similar tracking mode for each of the first power amplifier and the second power amplifier. In addition, the main controller 360 can control the first linear regulator LA1 and the second linear regulator LA2, the first switch controller 380 and the second switch controller 383, the first switch regulator controller 350 and the second switch regulator controller 353, the first discrete level controller 390 and the second discrete level controller 393, and at least one of the multi-output voltage regulator 310 based on the determined tracking mode.

[0497] Each component may include a component-specific controller (e.g., first switching regulator controller 350 and second switching regulator controller 353) therein or externally, and each dedicated controller may be controlled by main controller 360. In addition, there may be a controller that integrates and controls at least two components, and the corresponding controllers may be controlled by main controller 360.

[0498] As described above, based on the above structure and characteristics, the power modulator 300-7 can be driven in at least one tracking mode among the DL-ET mode, the CL-ET mode and the APT mode, and based on the Figure 18The power modulator 300 - 5 is based on the same principle or a similar principle, and provides the first output voltage VET_APT1 and the second output voltage VET_APT2 to the first power amplifier and the second power amplifier respectively.

[0499] For reference, the power supply modulator 300-7 is shown as including components that are bilaterally symmetrical with respect to the multi-output voltage regulator 310. However, Figure 29 The power supply modulator 300-7 may include components that are asymmetrical on both sides relative to the multi-output voltage regulator 310. For example, each of the linear regulator, the switching regulator, the switching regulator controller, the switch array, the switch controller, the discrete level controller, and the coupling capacitor, etc. may be provided in pairs on the left side of the figure, but as shown on the right side of the figure, each of the linear regulator, the switching regulator, the switching regulator controller, the switch array, the switch controller, the discrete level controller, and the coupling capacitor, etc. may be provided in pairs. However, for ease of explanation, a case where the power supply modulator 300-7 includes components that are symmetrical on both sides relative to the multi-output voltage regulator 310 will be described as an example. Figure 29 In the figure, reference numerals VHF1 and VHF2 are Figure 18 The reference numerals VHF in FIG.

[0500] Figure 30 is a circuit diagram illustrating an eighth example of a power modulator 300 - 8 included in a wireless communication device according to an embodiment of the inventive concept.

[0501] For reference, in the following, for ease of explanation, it is assumed that the power supply modulator 300-8 is implemented as Figure 1 The power modulator 300 of the wireless communication device 1 is shown in FIG. In addition, in addition to some structures and mechanisms, Figure 30 The power supply modulator 300-8 with Figure 26 The power supply modulator 300-6 is the same or similar, and the differences will be mainly described below.

[0502] Reference Figure 30 , the eighth example of the power modulator 300 according to an embodiment of the inventive concept (i.e., the power modulator 300-8) may include a multi-output voltage regulator 310, a first switching regulator 330 and a second switching regulator 333, a first switching regulator controller 350 and a second switching regulator controller 353, a main controller 360, a first switch array 370 and a second switch array 373, a first switch controller 380 and a second switch controller 383, a first discrete level controller 390 and a second discrete level controller 393, and / or a first coupling capacitor CAC1 and a second coupling capacitor CAC2.

[0503] In detail, Figure 30The power supply modulator 300-8 can supply the first output voltage VET_APT1 and the second output voltage VET_APT2 to a plurality of power amplifiers (when there is Figure 1 power amplifier PA; for example, a first power amplifier and a second power amplifier).

[0504] Therefore, in Figure 30 In the case of the power supply modulator 300-8, with Figure 26 Compared to the power supply modulator 300 - 6 , the number of each of the switching regulator, the switching regulator controller, the switch array, the switch controller, the discrete level controller, and the coupling capacitor may be greater than one.

[0505] In addition, due to Figure 30 Power supply modulator 300-8 ratio Figure 26 The power modulator 300-6 receives more signals, so the power modulator 300-8 can receive more signals from the modem ( Figure 1 100) receives the first and second average power signals D_REF1 and D_REF2, the first and second analog envelope signals A_ENV1 and A_ENV2, and the first and second digital envelope signals D_ENV1 and D_ENV2.

[0506] In addition, Figure 30 In the power supply modulator 300-8, since the multiple capacitors C1 to CN-1 of the multi-output voltage regulator 310 are connected to both sides of the first power amplifier and the second power amplifier, the multiple capacitors C1 to CN-1 of the multi-output voltage regulator 310 can be shared for each of the first output voltage VET_APT1 and the second output voltage VET_APT2. Therefore, the main controller 360 can jointly generate multiple reference output voltage signals VREF1 to VREFN-1 for each of the first output voltage VET_APT1 and the second output voltage VET_APT2, and provide the multiple reference output voltage signals VREF1 to VREFN-1 to the multi-output voltage regulator 310.

[0507] However, in Figure 30 In the power supply modulator 300-8, the first coupling capacitor CAC1 may be connected to the first power amplifier, and the second coupling capacitor CAC2 may be connected to the second power amplifier. Therefore, the main controller 360 may generate target voltage signals VCCMIN1 and VCCMIN2 for each of the first coupling capacitor CAC1 and the second coupling capacitor CAC2, and provide the target voltage signals VCCMIN1 and VCCMIN2 to the first OTA1 and the second OTA2, respectively.

[0508] For reference, when each of the target voltage signals VCCMIN1 and VCCMIN2 is set to be different from each other, the voltages VAC1 and VAC2 of each of the first coupling capacitor CAC1 and the second coupling capacitor CAC2 may also be different from each other. In this case, although the multi-output voltage regulator 310 commonly generates and outputs a plurality of voltages V1 to VN-1 for each of the first output voltage VET_APT1 and the second output voltage VET_APT2, the ranges of the first output voltage VET_APT1 and the second output voltage VET_APT2 provided to the first power amplifier and the second power amplifier, respectively, may be different from each other. That is, in the case of power amplifiers, since the optimized or improved power supply voltage range of the power amplifiers varies depending on the RF carrier frequency, manufacturer, etc., in the power supply modulator 300-8 according to an embodiment of the inventive concept, by providing a difference in the voltages VAC1 and VAC2 of each of the first coupling capacitor CAC1 and the second coupling capacitor CAC2, a difference in the range of the first output voltage VET_APT1 and the range of the second output voltage VET_APT2 can be provided to the first power amplifier and the second power amplifier, respectively. Additionally, through this difference, the power efficiency of each of the first power amplifier and the second power amplifier may be individually optimized or improved.

[0509] As described above, in an embodiment of the inventive concept, even in the case where multiple power supply voltages are generated for multiple power amplifiers, the increase in circuit area can be minimized or reduced because the number of output capacitors occupying most of the circuit area is the same or similar to the case where the power supply voltage is generated for a single power amplifier.

[0510] For ease of explanation, assuming that the first switching regulator 330, the first switching regulator controller 350, the first switch array 370, the first discrete level controller 390, the first switch controller 380 and the first coupling capacitor CAC1 form a first modulation circuit, and the second switching regulator 333, the second switching regulator controller 353, the second switch array 373, the second discrete level controller 393, the second switch controller 383 and the second coupling capacitor CAC2 form a second modulation circuit, a brief description of each component of the power supply modulator 300-8 is as follows.

[0511] The first modulation circuit may include a first switching regulator 330 that operates in DL-ET mode with the multi-output voltage regulator 310 to generate a first output voltage VET_APT1. Furthermore, the first modulation circuit may include a first switching regulator controller 350 that senses the output current of the multi-output voltage regulator 310 and controls the first switching regulator 330 based on the sensed value SV1. Furthermore, the first modulation circuit may include a first switch array 370 that includes a plurality of switches S1 to SN. The first switch array 370 may select one of a plurality of voltages V1 to VN-1 having different levels and a ground voltage GND through the plurality of switches S1 to SN, and provide the selected voltage to the first power amplifier. For reference, any one switch SN among the plurality of switches S1 to SN may be connected to the ground voltage GND, and the remaining switches S1 to SN-1 among the plurality of switches S1 to SN may be connected to the multi-output voltage regulator 310 to respectively correspond to the plurality of voltages V1 to VN-1 having different levels from each other output from the multi-output voltage regulator 310. In addition, the first modulation circuit may include a first discrete level controller 390 and a first switch controller 380. The first discrete level controller 390 controls the output of the first modulation circuit based on the output of the first modulation circuit ( Figure 1 The first switching controller 380 generates a first level control signal ENV_LV1 including multiple pieces of envelope level information based on the first digital envelope signal D_ENV1 provided by the first discrete level controller 390. The first switching controller 380 receives the first level control signal ENV_LV1 from the first discrete level controller 390 and controls the switching operations of the multiple switches S1 to SN based on the first level control signal ENV_LV1 received from the first discrete level controller 390. In addition, one end of the first coupling capacitor CAC1 may be connected to the first switch array 370, and the other end of the first coupling capacitor CAC1 may be connected to the first power amplifier (for example, connected between the inductor L1 of the first switching regulator 330 and the first output terminal of the power supply modulator 300-8 (the output terminal of the first output voltage VET_APT1)).

[0512] The second modulation circuit may include a second switching regulator 333 that operates in conjunction with the multi-output voltage regulator 310 in DL-ET mode to generate a second output voltage VET_APT2. The second switching regulator 333 also operates in APT mode to generate the second output voltage VET_APT2. Furthermore, the second modulation circuit may include a second switching regulator controller 353 that senses the output current of the multi-output voltage regulator 310 and controls the second switching regulator 333 based on the sensed value SV2. Furthermore, the second modulation circuit may include a second switch array 373 that includes a plurality of switches S1' to SN'. The second switch array 373 may select one of a plurality of voltages V1 to VN-1 having different levels and a ground voltage GND through the plurality of switches S1' to SN', and provide the selected voltage to the second power amplifier. For reference, any one switch SN' among the plurality of switches S1' to SN' may be connected to the ground voltage GND, and the remaining switches S1' to SN-1' among the plurality of switches S1' to SN' may be connected to the multi-output voltage regulator 310 to respectively correspond to the plurality of voltages V1 to VN-1 having different levels output from the multi-output voltage regulator 310. In addition, the second modulation circuit may include a second discrete level controller 393 and a second switch controller 383. The second discrete level controller 393 generates a second level control signal ENV_LV2 including a plurality of pieces of envelope level information based on the second digital envelope signal D_ENV2 provided from the modem 100. The second switch controller 383 receives the second level control signal ENV_LV2 from the second discrete level controller 393 and controls switching operations of the plurality of switches S1' to SN' based on the second level control signal ENV_LV2 received from the second discrete level controller 393. In addition, one end of the second coupling capacitor CAC2 can be connected to the second switch array 373, and the other end of the second coupling capacitor CAC2 can be connected to the second power amplifier (for example, connected between the inductor L2 of the second switching regulator 333 and the second output end of the power supply modulator 300-8 (the output end of the second output voltage VET_APT2)).

[0513] In the DL-ET mode, the multi-output voltage regulator 310 can output a plurality of voltages V1 to VN-1 having different levels from each other to correspond to the plurality of reference output voltage signals VREF1 to VREFN-1, respectively, to generate a first output voltage VET_APT1 or a second output voltage VET_APT2. That is, the multi-output voltage regulator 310 can operate in parallel with the switching regulators operating in the DL-ET mode among the first switching regulator 330 and the second switching regulator 333.

[0514] The main controller 360 can generate a plurality of reference output voltage signals VREF1 to VREFN-1 and provide the plurality of reference output voltage signals VREF1 to VREFN-1 to the multi-output voltage regulator 310. Furthermore, the main controller 360 can generate a target voltage signal VCCMIN1 for the first coupling capacitor CAC1 and provide the target voltage signal VCCMIN1 for the first coupling capacitor CAC1 to the first switching regulator controller 350. Furthermore, the main controller 360 can generate a target voltage signal VCCMIN2 for the second coupling capacitor CAC2 and provide the target voltage signal VCCMIN2 for the second coupling capacitor CAC2 to the second switching regulator controller 353. Furthermore, the main controller 360 can determine a tracking mode for each of the first power amplifier and the second power amplifier. That is, the main controller 360 can determine a different tracking mode for each of the first power amplifier and the second power amplifier, or can determine the same or similar tracking mode for each of the first power amplifier and the second power amplifier. In addition, the main controller 360 can control at least one of the first and second switch controllers 380 and 383, the first and second switching regulator controllers 350 and 353, the first and second discrete level controllers 390 and 393, and the multi-output voltage regulator 310 based on the determined tracking mode.

[0515] Each component may include a component-specific controller (e.g., first switching regulator controller 350 and second switching regulator controller 353) therein or externally, and each dedicated controller may be controlled by main controller 360. In addition, there may be a controller that integrates and controls at least two components, and the corresponding controllers may be controlled by main controller 360.

[0516] As described above, based on the above structure and characteristics, the power modulator 300-8 can be driven in at least one tracking mode of the DL-ET mode and the APT mode, and based on the Figure 26The power supply modulator 300 - 6 is based on the same principle or a similar principle, and provides the first output voltage VET_APT1 and the second output voltage VET_APT2 to the first power amplifier and the second power amplifier respectively.

[0517] For reference, the power supply modulator 300-8 is shown as including components that are bilaterally symmetrical with respect to the multi-output voltage regulator 310. However, Figure 30 The power supply modulator 300-8 may include components that are asymmetrical relative to the multi-output voltage regulator 310. For example, as shown, the linear regulator may not be provided on the left side of the figure, but may be provided on the right side of the figure. However, for ease of explanation, the case where the power supply modulator 300-8 includes components that are symmetrical relative to the multi-output voltage regulator 310 is described as an example.

[0518] Figure 31 is a block diagram of a mobile terminal 2000 to which a wireless communication device according to an embodiment of the inventive concept is applied.

[0519] Reference Figure 30 , the mobile terminal 2000 may include an application processor (AP) 2100, a memory 2200, a display 2300 and / or an RF module 2400. In addition, the mobile terminal 2000 may further include various components (such as a lens, a sensor, an audio module, etc.).

[0520] The AP 2100 may be implemented as a system on a chip (SoC) and may include a central processing unit (CPU) 2110, a random access memory (RAM) 2120, a power management unit (PMU) 2130, a memory interface (I / F) 2140, a display controller (DCON) 2150, a modem 2160, and / or a system bus 2170. The AP 2100 may also include various Internet protocols (IPs). Since the functions of the modem chip are integrated into the AP 2100, the AP 2100 may be referred to as a ModAP.

[0521] The CPU 2110 may control all operations of the AP 2100 and the mobile terminal 2000. The CPU 2110 may control the operation of each component of the AP 2100. In addition, the CPU 2110 may be implemented as a multi-core. A multi-core is a computing component having two or more independent cores.

[0522] The RAM 2120 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 2200 may be temporarily stored in the RAM 2120 according to the control or boot code of the CPU 2110. The RAM may be implemented as a dynamic RAM (DRAM) or a static RAM (SRAM).

[0523] The PMU 2130 may manage power of each component of the AP 2100. The PMU 2130 may also determine an operating state of each component of the AP 2100 and control operations.

[0524] The memory I / F 2140 may control all operations of the memory 2200 and may control data exchange between each component of the AP 2100 and the memory 2200. The memory I / F 2140 may write data to or read data from the memory 2200 according to a request of the CPU 2110.

[0525] The DCON 2150 may transmit image data to be displayed on the display 2300 to the display 2300. The display 2300 may be implemented as a flat panel display or a flexible display such as a liquid crystal display (LCD), an organic light emitting diode (OLED), etc.

[0526] For wireless communication, the modem 2160 may modulate data to be transmitted suitable for a wireless environment and recover received data. The modem 2160 may perform digital communication with the RF module 2400.

[0527] As a reference, Figures 1 to 3 The described modem 100 may be implemented in the modem 2160 .

[0528] The RF module 2400 may convert a high-frequency signal into a low-frequency signal and transmit the converted low-frequency signal to the modem 2160 via the antenna. In addition, the RF module 2400 may convert a low-frequency signal received from the modem 2160 into a high-frequency signal and transmit the converted high-frequency signal to the outside of the mobile terminal 2000 via the antenna. In addition, the RF module 2400 may amplify or filter the signal.

[0529] As a reference, Figures 1 to 3 The RFIC 200, power modulator 300, power amplifier PA, duplexer 400, and antenna ANT described above may be implemented in the RF module 2400. Figures 4 to 30 The described power supply modulators 300 - 1 to 300 - 8 may also be implemented in the RF module 2400 .

[0530] Therefore, in the mobile terminal 2000 , power consumption for communication can be reduced when performing broadband communication.

[0531] According to an embodiment, it is described herein as comprising a wireless communication device 1, a modem 100, an RFIC 200, a power modulator 300, a duplexer 400, a power amplifier PA, a digital transmission processor 110, a digital reception processor 120, a MIPI interface 130, a transmission circuit TXC, a reception circuit RXC, a local oscillator LO, a first analog baseband filter ABF1, a first mixer MX1, an amplifier 210, a second analog baseband filter ABF2, a second mixer MX2, a low noise amplifier 220, a wireless communication device 2, a second digital transmission processor 205, a power modulator 300-1, and a multi-output voltage regulator 300. 10. Switching regulator 330, linear regulator LA, switching regulator controller 350, main controller 360, switch controller 380, discrete level controller 390, multi-output voltage regulator 310-1, multiple single output voltage regulators SOVR1 to SOVRN, switching regulator SR, SIMO controller 312, multiple output voltage regulator 310-2, single inductor multiple output (SIMO) DC-DC converter, SIMO buck-boost converter, multiple output voltage regulator 310-3, boost converter, multiple LDOs LDO1 to LDO(N-1), a boost converter controller 314, a plurality of OTAs OTA1 to OTAN, a first multiplexer MUX1, a second multiplexer MUX2, a summer ADD, a compensation comparator CCP, an output comparator OCP, a power modulator 300-2, a power modulator 300-3, a first switching regulator 330 and a second switching regulator 333, a first linear regulator LA1 and a second linear regulator LA2, a first switching regulator controller 350 and a second switching regulator controller 353, a first switch controller 380 and a second switch controller 383, a first discrete level controller 390 and a second discrete level controller 393, a power modulator 300-4, a power modulator 300-5, a multiple output voltage regulator 310-4, a plurality of single output voltage regulators SOVR1 to SOVRN-1, a multiple output voltage regulator 310-5, a multiple output voltage regulator 310-6, and a plurality of LDOs The operations performed by LDO1 to LDO(N-2), OTA, multiplexer MUX, power modulator 300-6, power modulator 300-7, power modulator 300-8, mobile terminal 2000, AP 2100, RF module 2400, CPU 2110, PMU 2130, DCON 2150, and / or modem 2160 may be performed using processing circuitry. In addition, operations described herein as being performed by a DAC and / or ADC may be performed using processing circuitry. As used in this disclosure, the term "processing circuitry" may refer to, for example, hardware including logic circuitry, a hardware / software combination (such as a processor executing software), or a combination thereof.For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0532] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A power supply modulator, configured to be driven in a tracking mode and provide an output voltage to a power amplifier, wherein the tracking mode is an average power tracking mode or a discrete level envelope tracking mode, the power supply modulator comprising: a multi-output voltage regulator configured to output a plurality of voltages in a discrete-level envelope tracking mode, wherein the plurality of voltages have different levels from one another, and the different levels correspond to a plurality of reference output voltage signals, respectively; a switching regulator configured to output a switching regulator voltage, the output voltage depending on a selected voltage among the plurality of voltages and the switching regulator voltage in a discrete level envelope tracking mode, and the output voltage depending on the switching regulator voltage in an average power tracking mode; A switching regulator controller configured as: sensing an output current of the multiple output voltage regulator to obtain a sensed value, and controlling a switching regulator based on a sensed value in a discrete level envelope tracking mode; a switch array comprising a plurality of switches corresponding to the plurality of voltages, the switch array being configured to selectively connect a selected voltage to the power amplifier by performing a switching operation; a discrete level controller configured to generate a level control signal based on the digital envelope signal; a switch controller configured to control a switching operation of the switch array based on a level control signal; as well as The main controller is configured as: generating the plurality of reference output voltage signals, Determine the tracking mode from between average power tracking mode and discrete level envelope tracking mode, and At least one of a multiple output voltage regulator, a switching controller, a switching regulator controller, and a discrete level controller is controlled based on a tracking mode.

2. The power supply modulator according to claim 1, wherein The switching regulator controller includes: a plurality of transconductance operational amplifiers configured to output a plurality of difference values by comparing the plurality of voltages with the plurality of reference output voltage signals; a first multiplexer configured to output a selected difference value among the plurality of difference values based on a level control signal; a summer configured to sum the selected difference value and the sensed value to obtain a compensation value; a compensation comparator configured to compare the compensation value with a reference value to obtain a first comparison value; a digital-to-analog converter configured to convert the average power signal into a reference voltage signal; an output comparator configured to compare the reference voltage signal with the output voltage to obtain a second comparison value; and The second multiplexer is configured to output one of the first comparison value and the second comparison value as a switching regulator control signal to the switching regulator.

3. The power supply modulator according to claim 2, wherein: The second multiplexer is configured to output the first comparison value based on the tracking mode being the discrete level envelope tracking mode.

4. The power supply modulator according to claim 2, wherein: The second multiplexer is configured to output a second comparison value based on the tracking mode being the average power tracking mode.

5. The power supply modulator according to claim 2, wherein: The power modulator is configured to provide a sum current to the power amplifier in a discrete level envelope tracking mode, the sum current being the sum of the output current of the switching regulator and the output current of the multi-output voltage regulator, and The switching regulator is configured to control an output current of the switching regulator based on a switching regulator control signal so that an average value of the output current of the multi-output voltage regulator is approximately zero.

6. The power supply modulator according to claim 5, wherein: The output current of the switching regulator includes low-frequency current, and The output current of the multiple output voltage regulator includes high-frequency current.

7. The power supply modulator according to claim 1, wherein: The multi-output voltage regulator includes a plurality of capacitors corresponding to the plurality of voltages, respectively, and The switch array is configured to selectively connect at least one of the plurality of capacitors to a power amplifier by performing a switching operation.

8. The power supply modulator according to claim 7, wherein: The switch controller is configured to control the switching operation so that the switch array connects one of the plurality of capacitors to the power amplifier via one of the plurality of switches in an average power tracking mode.

9. The power supply modulator according to any one of claims 1 to 8, wherein: The multi-output voltage regulator includes a plurality of single-output voltage regulators configured to output the plurality of voltages.

10. The power supply modulator according to any one of claims 1 to 8, wherein: The multiple-output voltage regulator includes a single-inductor multiple-output DC-DC converter or a single-inductor multiple-output buck-boost converter.

11. The power supply modulator according to any one of claims 1 to 8, wherein: Multiple output voltage regulators include: a boost converter configured to generate a first voltage having a highest level among the plurality of voltages; and A plurality of low dropout regulators are configured to generate a subset of voltages among the plurality of voltages using a first voltage, the subset of voltages excluding the first voltage.

12. A power supply modulator, the power supply modulator being configured to be driven in a tracking mode and provide an output voltage to a power amplifier, the tracking mode being an average power tracking mode or a discrete level envelope tracking mode, the power supply modulator comprising: a multi-output voltage regulator configured to output a plurality of voltages in a discrete-level envelope tracking mode, wherein the plurality of voltages have different levels from one another, and the different levels correspond to a plurality of reference output voltage signals, respectively; a switching regulator configured to output a switching regulator voltage, the output voltage depending on a selected voltage among the plurality of voltages and the switching regulator voltage in a discrete level envelope tracking mode, and the output voltage depending on the switching regulator voltage in an average power tracking mode; A switching regulator controller configured as: sensing an output current of the multiple output voltage regulator to obtain a sensed value, and controlling a switching regulator based on a sensed value in a discrete level envelope tracking mode; a switch array comprising a plurality of switches, the switch array being configured to selectively connect a selected voltage to a power amplifier by performing a switching operation, wherein a first switch among the plurality of switches is connected to a ground voltage, and a subset of switches among the plurality of switches is connected to a multi-output voltage regulator to respectively correspond to the plurality of voltages, the subset of switches excluding the first switch; a discrete level controller configured to generate a level control signal based on the digital envelope signal; a switch controller configured to control a switching operation of the switch array based on a level control signal; a coupling capacitor having one end connected to the switch array and another end connected to the power amplifier; and The main controller is configured as: generating the plurality of reference output voltage signals, Generate the target voltage signal of the coupling capacitor, Determine the tracking mode from between average power tracking mode and discrete level envelope tracking mode, and At least one of a multiple output voltage regulator, a switching controller, a switching regulator controller, and a discrete level controller is controlled based on a tracking mode.

13. The power supply modulator of claim 12, wherein: The switching regulator controller includes: a transconductance operational amplifier configured to output a difference value by comparing a voltage of the coupling capacitor with a target voltage signal; a summer configured to sum the difference value and the sensed value to obtain a compensation value; a compensation comparator configured to compare the compensation value with a reference value to obtain a first comparison value; a digital-to-analog converter configured to convert the average power signal into a reference voltage signal; an output comparator configured to compare the reference voltage signal with the output voltage to obtain a second comparison value; and The multiplexer is configured to output one of the first comparison value and the second comparison value as a switching regulator control signal to the switching regulator.

14. The power supply modulator of claim 13, wherein: The multiplexer is configured to output a first comparison value based on the tracking mode being a discrete level envelope tracking mode.

15. The power supply modulator of claim 13, wherein: The multiplexer is configured to output a second comparison value based on the tracking mode being the average power tracking mode.

16. The power supply modulator of claim 13, wherein: The power modulator is configured to provide a sum current to the power amplifier in a discrete level envelope tracking mode, the sum current being the sum of the output current of the switching regulator and the output current of the multi-output voltage regulator, and The switching regulator is configured to control an output current of the switching regulator based on a switching regulator control signal so that an average value of the compensation value output from the summer is approximately zero.

17. The power supply modulator of claim 16, wherein: The output current of the switching regulator includes low-frequency current, and The output current of the multiple output voltage regulator includes high-frequency current.

18. The power supply modulator of claim 12, wherein: The multi-output voltage regulator includes a plurality of capacitors corresponding to the plurality of voltages, respectively, and The switch array is configured to selectively connect at least one of the plurality of capacitors to a power amplifier by performing a switching operation.

19. The power supply modulator of claim 18, wherein: The switch controller is configured to control the switching operation so that the switch array connects the first switch to the coupling capacitor.

20. The power supply modulator according to any one of claims 12 to 19, wherein: The multi-output voltage regulator includes a plurality of single-output voltage regulators configured to output the plurality of voltages.

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