Integrated circuit and design method of hybrid static combinational circuit and dynamic combinational circuit

Abstract

An integrated circuit that mixes static combinational circuits and dynamic combinational circuits, comprising: a first stage, receiving a previous stage output data and a clock signal, and generating a first output data; a second stage, receiving the first output data and the clock signal, and generating a second output data; the first stage comprises: a trigger circuit, a static combinational circuit, a dynamic combinational circuit and a multi-phase generator; a data input end of the trigger circuit receives the previous stage output data, a clock input end of the trigger circuit receives the clock signal, a data output end of the trigger circuit generates an input data, the static combinational circuit receives the input data and generates an intermediate data, the multi-phase generator receives the clock signal and generates a delayed clock signal, a data input end of the dynamic combinational circuit receives the intermediate data, a clock input end of the dynamic combinational circuit receives the delayed clock signal, and a data output end of the dynamic combinational circuit generates the first output data.

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a related design method, and more particularly to an integrated circuit that mixes a static combinational circuit and a dynamic combinational circuit and a related design method. Background Art

[0002] As is known to all, an integrated circuit includes multiple sub-circuits with various functions. When the integrated circuit is running, each sub-circuit performs a corresponding specific function. In order to allow data to be transmitted smoothly between each sub-circuit, each sub-circuit is operated according to a clock signal. In other words, the multiple sub-circuits in an integrated circuit can be regarded as multiple stages. For example, according to the operation of the clock signal, the data generated by the first stage can be transmitted to the second stage for processing, and the data generated by the second stage can be transmitted to the third stage for processing, and so on.

[0003] Please refer to Figure 1 , which shows a circuit diagram used in an integrated circuit. The circuit diagram of the integrated circuit includes a plurality of stages 110, 120 and operates according to a clock signal CLK. Each stage 110, 120 includes a flip-flop circuit 112, 122 and a static combinational circuit 114, 124. The clock input terminal CKin of the flip-flop circuit 112, 122 receives the clock signal CLK. Furthermore, the flip-flop circuit 112, 122 includes a plurality of latches.

[0004] In the nth stage 110, the flip-flop circuit 112 latches the output data Dout of the previous stage. n-1 Become input data Din n Furthermore, the static combinational circuit 114 receives and processes the input data Din n After that, the output data Dout of the nth stage 110 is generated n Similarly, in the (n+1)th stage 120, the flip-flop circuit 122 latches the output data Dout of the nth stage 110 n Become input data Din n+1 Furthermore, the static combinational circuit 124 receives and processes the input data Din n+1 Afterwards, the output data Dout of the (n+1)th stage 120 is generatedn+1 .

[0005] Basically, the static combinational circuits 114 and 124 can be composed of various static logic elements, such as a NOT gate, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, and the like.

[0006] For example, the static combinational circuit 114 in the nth stage 110 is an adder, the static combinational circuit 124 in the (n+1)th stage 120 is a multiplier, and the output data Dout is n-1 It includes three values: A, B, and C.

[0007] In the nth stage 110, the flip-flop circuit 112 latches the output data Dout of the previous stage. n-1 Becomes input data Din n , the static combination circuit 114 adds the value A to the value B and outputs the data Dout n It includes two values ​​(A+B) and C.

[0008] In the (n+1)th stage 120, the flip-flop circuit 122 latches the output data Dout. n Become input data Din n+1 , the static combination circuit 124 multiplies the two values ​​(A+B) by the value C, and generates the output data Dout of the value (A+B)×C n+1 .

[0009] Therefore, in the first cycle of the clock signal CLK, the first stage 110 outputs the data Dout according to the three values ​​of A, B and C. n-1 Perform addition operation and generate output data Dout of two values ​​(A+B) and C n In the second cycle of the clock signal CLK, the second stage 120 outputs the data Dout according to the two values ​​of (A+B) and C. n Perform multiplication and generate output data Dout of (A+B)×C n+1 .

[0010] Of course, in addition to the adders and multipliers mentioned above, the static combinational circuits 114 and 124 can be designed into various arithmetic logic circuits according to actual conditions to perform various operations in sequence according to the clock signal CLK.

[0011] when Figure 1 After the circuit diagram design is completed, it is necessary to perform layout before making an integrated circuit. That is, placement and routing are performed on each electronic element in the circuit diagram on the semiconductor substrate. Generally speaking, the layout can be completed using an automatic placement and routing tool (APR tool for short).

[0012] The APR tool is a computer software that can configure each electronic component in the circuit diagram on a semiconductor substrate, and then connect the various electronic components. Furthermore, in order to allow the integrated circuit to run smoothly, the APR tool will also perform clock tree balancing (clock tree balancing) on ​​the clock signal CLK, that is, clock tree synthesis (CTS) action.

[0013] Basically, the clock tree balancing operation is used to control the clock path so that the clock signal CLK received by each stage of the clock input terminal CKin is synchronous. Figure 1 For example, when the clock tree balancing action is completed, during the operation of the integrated circuit, the clock signal CLK received by the clock input terminal CKin of each stage 110 and 120 will simultaneously convert from a low level to a high level, and will also simultaneously convert from a high level to a low level.

[0014] Dynamic combinational circuits have the advantages of high speed, space saving and low energy consumption. Therefore, dynamic combinational circuits composed of dynamic logic elements have been designed in central processing units (CPUs), system-on-chips (SOCs) and application-specific integrated circuits (ASICs).

[0015] Dynamic combinational circuits can be composed of various dynamic logic elements, such as dynamic NOT gates (dynamic NOT), dynamic AND gates (dynamic AND gates), dynamic NAND gates (dynamic NAND gates), dynamic OR gates (dynamic OR gates), dynamic NOR gates (dynamic NOR gates), dynamic XOR gates (dynamic XOR gates), etc.

[0016] The main feature of the dynamic combinational circuit is that it uses the clock signal CLK to operate. When the clock signal CLK is at a low level, it is in the pre-charge phase. When the clock signal CLK is at a high level, it is in the evaluation phase. The following takes the operation of the dynamic NAND gate as an example to illustrate.

[0017] like Figure 2 When the clock signal CLK is at a low level (eg, the ground voltage GND), it is a pre-charge phase, the transistor Mu is turned on, the transistor Md is turned off, and the capacitor C is charged to the supply voltage Vdd.

[0018] When the clock signal CLK is at a high level (e.g., the supply voltage Vdd), it is an evaluation phase, the transistor Mu is turned off, the transistor Md is turned on, and the output data OUT is determined according to the input signal A and the input signal B. Furthermore, when the input signal A and the input signal B are both at a high level, the output data OUT is at a low level. When the input signal A and the input signal B are both at a low level, or one of the input signal A and the input signal B is at a low level, the output data OUT is at a high level.

[0019] From the above description, it can be known that the dynamic combinational circuit composed of various dynamic logic elements needs to operate according to the clock signal CLK.

[0020] However, when dynamic combinational circuits and static combinational circuits are simultaneously designed within each level of an integrated circuit, the integrated circuit will not be able to operate normally after performing a clock tree balancing operation using an APR tool. Summary of the invention

[0021] The present invention proposes an integrated circuit that mixes static combinational circuits and dynamic combinational circuits, including: a first stage, receiving a previous stage output data and a clock signal, and generating a first output data; and, a second stage, receiving the first output data and the clock signal, and generating a second output data; wherein the first stage includes: a first trigger circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator; a data input end of the first trigger circuit receives the previous stage output data, a clock input end of the first trigger circuit receives the clock signal, a data output end of the first trigger circuit generates an input data, the first static combinational circuit receives the input data and generates an intermediate data, the multi-phase generator receives the clock signal and generates a delayed clock signal, a data input end of the dynamic combinational circuit receives the intermediate data, a clock input end of the dynamic combinational circuit receives the delayed clock signal, and a data output end of the dynamic combinational circuit generates the first output data.

[0022] The present invention proposes a design method for the above-mentioned integrated circuit, comprising the following steps: setting the first trigger circuit, the first static combinational circuit, the dynamic combinational circuit and the multi-phase generator in the first stage as a macro block; performing a configuration and connection operation on the integrated circuit; performing a clock tree balancing operation on the integrated circuit; and restoring the macro block to the first trigger circuit, the first static combinational circuit, the dynamic combinational circuit and the multi-phase generator. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to better understand the above and other aspects of the present invention, the following preferred embodiments are specifically described in detail with reference to the accompanying drawings as follows:

[0024] Figure 1 The present invention is a circuit diagram currently used in integrated circuits.

[0025] Figure 2 Dynamic NAND gate.

[0026] Figure 3 The circuit diagram is a mixed static combinational circuit and dynamic combinational circuit.

[0027] Figure 4 The circuit diagram is a hybrid static combinational circuit and a dynamic combinational circuit of the present invention.

[0028] Figure 5 Schematic diagram of a multi-phase generator.

[0029] Figure 6 It is a flow chart of the design method of the present invention.

[0030] The reference numerals are described as follows:

[0031] 110, 310, 410: nth level

[0032] 112, 122, 312, 322, 412: Trigger circuit

[0033] 114, 124, 314, 324, 414: Static combinational circuits

[0034] 120, 320: (n+1)th level

[0035] 316, 416: Dynamic Combinational Circuits

[0036] 418: Multi-phase generator

[0037] 501~50y:Delay element

[0038] 520: Multiplexer DETAILED DESCRIPTION

[0039] When designing a mixed static combinational circuit and dynamic combinational circuit in an integrated circuit, at least one level includes a dynamic combinational circuit. Figure 3 , which shows a circuit diagram of a mixed static combinational circuit and a dynamic combinational circuit.

[0040] The circuit diagram of the integrated circuit includes a plurality of stages 310 and 320 and operates according to a clock signal CLK. The nth stage 310 includes a flip-flop circuit 312, a static combinational circuit 314, and a dynamic combinational circuit 316. The (n+1)th stage 320 includes a flip-flop circuit 322 and a static combinational circuit 324. The clock input terminals CKin of the flip-flop circuits 312 and 322 receive the clock signal CLK. Furthermore, the flip-flop circuits 312 and 322 include a plurality of latches.

[0041] In the nth stage 310, the flip-flop circuit 312 latches the output data Doutn-1 of the previous stage to become the input data Dinn. Furthermore, after receiving and processing the input data Dinn, the static combinational circuit 314 generates the intermediate data Dx. In addition, the clock input terminal CKin of the dynamic combinational circuit 316 receives the clock signal CLK. According to the clock signal CLK, the dynamic combinational circuit 316 receives and processes the intermediate data Dx and generates the output data Doutn of the nth stage 310.

[0042] In the (n+1)th stage 320 , the flip-flop circuit 322 latches the output data Doutn of the nth stage 310 into the input data Dinn+1. Furthermore, the static combinational circuit 324 receives and processes the input data Dinn+1 and generates the output data Doutn+1 of the (n+1)th stage 320 .

[0043] according to Figure 3 When the integrated circuit is running, in the previous cycle of the clock signal CLK, the nth stage 310 must process the output data Doutn-1 of the previous stage and generate the output data Doutn of the nth stage 310. In the next cycle of the clock signal CLK, the (n+1)th stage 320 must process the output data Doutn of the nth stage 310 and generate the output data Doutn+1 of the (n+1)th stage 320.

[0044] Figure 3 After the circuit diagram design is completed, the automatic configuration and wiring tool (APR tool) needs to be used to complete the layout. Figure 3 The circuit diagram is a design of a mixed static combinational circuit and a dynamic combinational circuit. When the APR tool performs clock tree balancing on the clock signal CLK, the clock signal CLK received by each stage of the clock input terminal CKin will be synchronous, and the integrated circuit will not be able to achieve the above operation. The following is an explanation.

[0045] As is known to all, there is a specific processing time for the static combinational circuit 314 from receiving the input data Dinn to generating the intermediate data Dx. Since the clock input terminal CKin of the flip-flop circuit 312 in the nth stage 310 is synchronous with the clock signal CLK received by the clock input terminal CKin of the dynamic combinational circuit 316, in other words, when the dynamic combinational circuit 316 starts to operate according to the clock signal CLK, the flip-flop circuit 312 is just beginning to latch the output data Doutn-1, so it can be determined that the intermediate data Dx of the static combinational circuit 314 is not ready at all, resulting in the dynamic combinational circuit 316 being unable to receive the correct intermediate data Dx and generating the wrong output data Doutn.

[0046] In order to solve the above problem and enable the integrated circuit to operate normally, the present invention further adds a multi-phase generator to the design of the hybrid static combinational circuit and the dynamic combinational circuit to dynamically adjust the delay time of the clock signal so that the integrated circuit can operate correctly.

[0047] Please refer to Figure 4, which shows a circuit diagram of a hybrid static combinational circuit and a dynamic combinational circuit of the present invention. The integrated circuit includes a plurality of stages 410, 320 and operates according to a clock signal CLK. The nth stage 410 includes a trigger circuit 412, a static combinational circuit 414, a multi-phase generator 418 and a dynamic combinational circuit 416. The structure of the (n+1)th stage 320 is the same as Figure 3 The same is omitted here. The clock input terminal CKin of the flip-flop circuit 412, 322 receives the clock signal CLK. Furthermore, the flip-flop circuit 412, 322 includes a plurality of latches.

[0048] According to an embodiment of the present invention, in the nth stage 410, the data input terminal of the flip-flop circuit 412 receives the output data Doutn-1 of the previous stage as the input data Dinn, and the data output terminal of the flip-flop circuit 412 generates the input data Dinn. Furthermore, after receiving and processing the input data Dinn, the static combinational circuit 414 generates the intermediate data (intermediatedata) Dx. In addition, the multi-phase generator 418 receives the clock signal CLK and generates the delayed clock signal CLK_d. The clock input terminal CKin of the dynamic combinational circuit 416 receives the delayed clock signal CLK_d, the data input terminal of the dynamic combinational circuit 416 receives the intermediate data Dx, and the data output terminal of the dynamic combinational circuit generates the output data Doutn. That is, according to the delayed clock signal CLK_d, the dynamic combinational circuit 416 receives and processes the intermediate data Dx and generates the output data Doutn of the nth stage 410.

[0049] Similarly, in the (n+1)th stage 320, the data input terminal of the flip-flop circuit 322 receives the output data Doutn of the nth stage 310 as the input data Dinn+1, and the data output terminal of the flip-flop circuit 322 generates the input data Dinn+1. The static combinational circuit 324 receives and processes the input data Dinn+1 and generates the output data Doutn+1 of the (n+1)th stage 320.

[0050] Since the static combinational circuit 414 has a specific processing time from receiving the input data Dinn to generating the intermediate data Dx, the multi-phase generator 418 is used to generate the delayed clock signal CLK_d, and the phase of the delayed clock signal CLK_d is controlled to lag behind the clock signal CLK by at least the processing time. Therefore, when the dynamic combinational circuit 416 starts to operate according to the delayed clock signal CLK_d, it can be determined that the intermediate data Dx of the static combinational circuit 314 is ready, and the dynamic combinational circuit 416 receives the intermediate data Dx and successfully generates the output data Doutn.

[0051] According to the above description, when the integrated circuit operates normally, in the previous cycle of the clock signal CLK, the nth stage 410 processes the output data Doutn-1 of the previous stage and generates the output data Doutn of the nth stage 410. In the next cycle of the clock signal CLK, the (n+1)th stage 320 processes the output data Doutn of the nth stage 310 and generates the output data Doutn+1 of the (n+1)th stage 320.

[0052] Please refer to Figure 5 , which shows a schematic diagram of a multi-phase generator. The multi-phase generator 418 includes a plurality of delay elements 501 to 50y connected in series, each of which can delay the received clock signal by a delay time. The first delay unit 501 receives the clock signal CLK to generate a clock signal CLK1, the second delay unit 502 receives the clock signal CLK1 to generate a clock signal CLK2, and so on..., the yth delay unit 50y receives the clock signal CLKy-1 to generate a clock signal CLKy. In addition, the multiplexer 520 receives the clock signals CLK1 to CLKy generated by the plurality of delay elements 501 to 50y. The output end of the multiplexer 520 can be connected to one of the plurality of input ends to select one of the plurality of clock signals CLK1 to CLKy, so that the output end generates a delayed clock signal CLK_d. In other words, when the integrated circuit is running, the internal control circuit (not shown) can select a suitable delayed clock signal CLK_d to the dynamic combinational circuit 416 via the multiplexer 520 according to the processing time of the static combinational circuit 414 .

[0053] Furthermore, the present invention proposes a design method for a hybrid static combinational circuit and a dynamic combinational circuit. Figure 6 , which shows a flow chart of the design method of the present invention.

[0054] When the circuit diagram of the integrated circuit is designed, the trigger circuit, static combinational circuit, dynamic combinational circuit and multi-phase generator inside the stage with mixed static combinational circuit and dynamic combinational circuit are set as a macro block (step S602). According to the embodiment of the present invention, the macro block can be regarded as an electronic element. Figure 4 For example, the macro block includes a trigger circuit 412, a static combination circuit 414, a dynamic combination circuit 416 and a multi-phase generator 418. Furthermore, the macro block has a plurality of signal input terminals receiving the output data Doutn-1 of the previous stage, a clock input terminal CLKin receiving the clock signal, and a plurality of signal output terminals generating output data Doutn.

[0055] Next, the integrated circuit is configured and connected (step S604 ). That is, the APR tool is used to lay out the macro blocks and other electronic components in the (n+1)th level 320 .

[0056] Afterwards, a clock tree balancing operation is performed on the integrated circuit (step S606 ), that is, the APR tool is used to perform a clock tree synthesis operation on the clock signal, and the macro block is synchronized with the clock signal CLK received by the (n+1)th stage clock input terminal CKin.

[0057] Next, the macro block is restored to the connection relationship among the flip-flop circuit 412 , the static combination circuit 414 , the dynamic combination circuit 416 and the multi-phase generator 418 (step S608 ).

[0058] From the above description, it can be seen that when using the APR tool to perform clock tree balancing, the APR tool only performs clock tree synthesis (CTS) on the clock input of the macro block and the clock input of other levels. Therefore, the APR tool does not perform clock tree balancing on the clock input of the dynamic combinational circuit inside the macro block.

[0059] Furthermore, after the clock tree balancing operation is completed, the macro block is restored to the trigger circuit, the static combinational circuit, the dynamic combinational circuit and the multi-phase generator. Therefore, the clock signal CLK received by the clock input end of the dynamic combinational circuit and the clock input end of the trigger circuit can be made asynchronous, and the integrated circuit can operate correctly.

[0060] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. An integrated circuit that mixes static combinational circuits and dynamic combinational circuits, comprising: A first stage receives a previous stage output data and a clock signal, and generates a first output data; as well as a second stage, receiving the first output data and the clock signal, and generating a second output data; Among them, the first stage includes: a first trigger circuit, a first static combination circuit, a dynamic combination circuit and a multi-phase generator; a data input end of the first trigger circuit receives the previous stage output data, a clock input end of the first trigger circuit receives the clock signal, a data output end of the first trigger circuit generates an input data, the first static combination circuit receives the input data and generates an intermediate data, the multi-phase generator receives the clock signal and generates a delayed clock signal, a data input end of the dynamic combination circuit receives the intermediate data, a clock input end of the dynamic combination circuit receives the delayed clock signal, and a data output end of the dynamic combination circuit generates the first output data.

2. The integrated circuit of claim 1 , wherein the second stage comprises: a second flip-flop circuit and a second static combinational circuit; A data input terminal of the second flip-flop circuit receives the first output data, a clock input terminal of the second flip-flop circuit receives the clock signal, a data output terminal of the second flip-flop circuit is connected to a data input terminal of the second static combinational circuit, and a data output terminal of the second static combinational circuit generates the second output data.

3. The integrated circuit as claimed in claim 1, wherein in a first cycle of the clock signal, the first stage processes the previous stage output data and generates the first output data; in a second cycle of the clock signal, the second stage processes the first output data and generates the second output data.

4. The integrated circuit of claim 1 , wherein the multi-phase generator comprises: A plurality of delay elements connected in series and a multiplexer; The first delay element receives the clock signal, the output end of the delay element is connected to a plurality of input ends of the multiplexer, and an output end of the multiplexer is selectively connected to one of the input ends to generate the delayed clock signal.

5. A method for designing the integrated circuit according to claim 1, comprising the following steps: The first trigger circuit, the first static combination circuit, the dynamic combination circuit and the multi-phase generator in the first stage are set as a macro block; Performing a configuration and connection operation on the integrated circuit; performing a clock tree balancing operation on the integrated circuit; and The macro block is restored to the first trigger circuit, the first static combination circuit, the dynamic combination circuit and the multi-phase generator.

6. The integrated circuit design method as claimed in claim 5, wherein when performing the configuration and connection operation, an automatic configuration and connection tool is used to layout the macro block and the plurality of electronic components in the second level.

7. The integrated circuit design method as claimed in claim 5, wherein a plurality of signal input terminals of the macro block receive the previous stage output data, a clock input terminal of the macro block receives the clock signal, and a plurality of signal output terminals of the macro block generate the first output data.

8. The integrated circuit design method as claimed in claim 7, wherein when performing the clock tree balancing operation, an automatic configuration and wiring tool is used to perform a clock tree synthesis operation so that the clock input end of the macro block is synchronized with the clock signal received by the clock input end of the second stage.

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