Magnetoresistive Random Access Memory and Its Operating Method

Abstract

The present invention relates to a magnetoresistive random access memory. The magnetoresistive random access memory includes a plurality of input / output units, and each input / output unit can read and write a plurality of memory units simultaneously. Therefore, the column-to-column delay time tCCD (Column to Column Delay) of the magnetoresistive random access memory can be equivalent to or faster than that of a dynamic random access memory, and thus a data rate equal to or faster than that of the dynamic random access memory can be obtained.

Description

Technical Field

[0001] The present invention relates to a magnetoresistive random access memory (MRAM), and more particularly to a magnetoresistive random access memory with a read / write column-to-column latency equal to or faster than that of a dynamic random access memory (DRAM) and an operation method thereof. Background Art

[0002] Figure 1 And Figure 2 is the write operation of the storage cell of a conventional MRAM. As Figure 1 shown, the bit line (BL) and the source line (SL) of the storage cell 10 are respectively connected to a write high voltage VH and a write low voltage VL. When the transistor M1 is turned on, it represents that the storage cell 10 is selected for the write operation. At this time, a current I1 flows from the bit line BL through the storage cell 10 to the source line SL, causing the storage cell 10 to have a first resistance value, and this first resistance value represents that the storage cell 10 is written with parallel data "P". As Figure 2 shown, the bit line BL and the source line SL of the storage cell 10 are respectively connected to the write low voltage VL and the write high voltage VH. When the transistor M1 is turned on, the current I1 will flow from the source line SL through the storage cell 10 to the bit line BL, causing the storage cell 10 to have a second resistance value, and this second resistance value represents that the storage cell 10 is written with anti-parallel data "AP". During writing, the direction of the current I1 on the storage cell 10 of the MRAM determines the data written into the storage cell 10. When the data of the storage cell 10 needs to be changed from "P" to "AP" or from "AP" to "P", it takes a certain amount of time to flip the magnetoresistance to rewrite the data, which also results in the write speed of the conventional MRAM being slower than that of the DRAM. Thus, the column-to-column latency of the MRAM is lengthened.

[0003] Figure 3 And Figure 4 is the read operation of the storage cell of a conventional MRAM. As Figure 3 And Figure 4 shown, the bit line BL and the source line SL of the storage cell 10 are respectively connected to a read high voltage RH and a read low voltage RL, and a sense amplifier 18 is connected to the bit line BL. When the transistor M1 is turned on, it represents that the storage cell 10 is selected for the read operation. Assume Figure 3 the storage cell 10 has a first resistance value while Figure 4The storage cell 10 has a second resistance value. Since the resistance values of the storage cells 10 are different, the current passing through the storage cells 10 will be different. When the sense amplifier 18 senses the current IR1, it determines that the storage cell 10 has the first resistance value, and thus outputs the parallel data "P". When the sense amplifier 18 senses the current IR2, it determines that the storage cell 10 has the second resistance value, and thus outputs the anti-parallel data "AP". However, during reading, the current IR1 or IR2 on the storage cell 10 of the MRAM is very small, so it takes some time to determine the magnetoresistivity of the storage cell 10, which also results in the reading speed of the traditional MRAM being slower than that of the DRAM. This elongates the column-to-column delay time of the MRAM.

[0004] Figure 5 is a page 12 of the MRAM. The page 12 includes 8 input / output circuits IO0, IO1, IO2, IO3, IO4, IO5, IO6, and IO7 sharing a word line WL. As Figure 5 shown, each of the input / output circuits IO0 to IO7 has 8 input / output units 122. Each input / output unit 122 has a sense amplifier for reading the data of the storage cell 10. Therefore, each of the input / output circuits IO0 to IO7 can output 8 bits of data each time.

[0005] Figure 6It is a traditional input / output unit 122, which includes multiple memory cells MC1, MC2, MC3, and MC4 connected to voltage controllers 14 and 16 via switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW10, and SW11. When a write operation is performed, switches SW1 to SW8 are controlled according to an address signal (not shown in the figure) to select the memory cell to which data is to be written. For example, when switches SW1 and SW2 are turned on, data will be written to memory cell MC1. The bit line BL1 of memory cell MC1 is connected to voltage controller 14 via switches SW1 and SW10, and the source line SL1 of memory cell MC1 is connected to voltage controller 16 via switches SW2 and SW11. If switch SW10 is connected to the high voltage HV provided by voltage controller 14 and switch SW11 is connected to the low voltage LV provided by voltage controller 16, the data "P" will be written to memory cell MC1. If switch SW10 is connected to the low voltage LV provided by voltage controller 14 and switch SW11 is connected to the high voltage HV provided by voltage controller 16, the data "AP" will be written to memory cell MC1. When a read operation is performed, switch SW10 is turned off to prevent voltage controller 14 from providing voltage HV or LV to memory cells MC1 to MC4, and switch SW11 is connected to the low voltage LV provided by voltage controller 16. The memory cell from which data is to be read is selected according to the address signal. For example, switches SW1 and SW2 are turned on to read the data of memory cell MC1. Then, switch SW9 is turned on to enable sense amplifier 18 to provide a voltage RH to memory cell MC1 to generate a current. Sense amplifier 18 senses this current to determine the resistance value of memory cell MC1, and then outputs the data D1 stored in memory cell MC1. The data D1 is either "P" or "AP". In Figure 6 it, the write operation and the read operation use the same low voltage LV, but as Figure 3 and Figure 4 shown, another low voltage RV can also be connected to the source line SL1 of memory cell MC1 during the read operation.

[0006] However, the input / output unit 122 of the traditional MRAM can only perform a read operation or a write operation at the same time, and cannot perform a read operation and a write operation simultaneously. Moreover, the input / output unit 122 cannot write data "P" to one memory cell (such as MC1) while writing data "AP" to another memory cell (such as MC2). In addition, the traditional input / output unit 122 has only one sense amplifier 18, so only one memory cell can be read each time. SUMMARY OF THE INVENTION

[0007] The object of the present invention is to provide a magnetoresistive random access memory and an operation method thereof. When the input / output unit of the magnetoresistive random access memory reads a storage unit, data is written into another storage unit. The input / output unit of the magnetoresistive random access memory can also write different data into different storage units simultaneously. The input / output unit of the magnetoresistive random access memory can also read multiple storage units simultaneously. The read / write column-to-column delay time of the magnetoresistive random access memory is equivalent to or better than that of DRAM.

[0008] To achieve the above object, the present invention provides the following solutions:

[0009] A magnetoresistive random access memory includes a plurality of input / output units. In a first operation method of the magnetoresistive random access memory, each input / output unit can write a piece of data into another storage unit while reading a storage unit. In a second operation method of the magnetoresistive random access memory, each input / output unit can write the same or different data into different storage units. In a third operation method of the magnetoresistive random access memory, each input / output unit can read the data of multiple storage units simultaneously.

[0010] According to the specific embodiments provided by the present invention, the following technical effects are disclosed: Since the input / output unit of the magnetoresistive random access memory of the present invention can read and write multiple storage units simultaneously, the magnetoresistive random access memory of the present invention has a faster read / write column-to-column delay time, and the read / write column-to-column delay time of the magnetoresistive random access memory of the present invention is equivalent to or faster than that of DRAM. Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 is the first write operation of the storage unit of the traditional MRAM;

[0013] Figure 2 is the second write operation of the storage unit of the traditional MRAM;

[0014] Figure 3 is the first read operation of the storage unit of the traditional MRAM;

[0015] Figure 4 is the second read operation of the storage unit of the traditional MRAM;

[0016] Figure 5 is a page of the MRAM;

[0017] Figure 6 is the input / output unit of the traditional MRAM;

[0018] Figure 7 is an embodiment of the input / output unit of the MRAM of the present invention;

[0019] Figure 8 is Figure 7 an embodiment of the first selection circuit and the second selection circuit in

[0020] Symbol description:

[0021] 10 - storage unit, 12 - page, 122 - input / output unit, 14 - voltage controller, 16 - voltage controller, 18 - sense amplifier, 20 - address decoder controller, 22 - first selection circuit, 24 - second selection circuit, 26 - third selection circuit, 28 - fourth selection circuit, 30 - fifth selection circuit, 32 - sixth selection circuit, 34 - seventh selection circuit, 36 - eighth selection circuit, 38 - first voltage controller, 40 - second voltage controller, 42 - first sense amplifier, 44 - second sense amplifier. Detailed implementation manners

[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0023] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0024] As Figure 5 shown, a page of the MRAM of the present invention also includes a plurality of input / output units, Figure 7 which is an embodiment of the input / output unit of the MRAM of the present invention. Figure 7The input / output unit includes four memory cells MC1 to MC4, a first write bit line WR_BL_HV, a second write bit line WR_BL_LV, a first write source line WR_SL_LV, a second write source line WR_SL_HV, a first read bit line RD_BL1, a second read bit line RD_BL2, a first read source line RD_SL1, a second read source line RD_SL2, an address decoding controller 20, a first selection circuit 22, a second selection circuit 24, a third selection circuit 26, a fourth selection circuit 28, a fifth selection circuit 30, a sixth selection circuit 32, a seventh selection circuit 34, an eighth selection circuit 36, a first voltage controller 38, a second voltage controller 40, a first sense amplifier 42, and a second sense amplifier 44. The first voltage controller 38 provides a first signal HV to the first write bit line WR_BL_HV and provides a second signal LV to the second write bit line WR_BL_LV. The first sense amplifier 42 provides a third signal RH to the first read bit line RD_BL1. The second sense amplifier 44 provides the third signal RH to the second read bit line RD_BL2. The second voltage controller 38 provides the first signal HV to a second write source line WR_SL_HV, provides the second signal LV to the first write source line WR_SL_LV, and provides a fourth signal RL to the first read source line RD_SL1 and the second read source line RD_SL2. In Figure 7 the embodiment, the first signal HV is a first high voltage, the second signal LV is a first low voltage, the third signal RH is a second high voltage, and the fourth signal RL is a second low voltage. The voltage difference between the first high voltage and the first low voltage is greater than the voltage difference between the second high voltage and the second low voltage. Figure 8 is Figure 7 an embodiment of the first selection circuit 22 and the second selection circuit 24, where the first selection circuit 22 includes four switches SB1, SB2, SB3, and SB4 for connecting the first bit line BL1 of the first memory cell MC1 to one of the second write bit line WR_BL_LV, the first write bit line WR_BL_HV, the second read bit line RD_BL2, and the first read bit line RD_BL1, and the second selection circuit 24 includes four switches SB5, SB6, SB7, and SB8 for connecting the first source line SL1 of the first memory cell MC1 to one of the first read source line RD_SL1, the second read source line RD_SL2, the second write source line WR_SL_HV, and the first write source line WR_SL_LV. The circuit architectures of the third selection circuit 26 to the eighth selection circuit 36 are similar to those of the first selection circuit 22 and the second selection circuit 24 and will not be described again. In Figure 7In the embodiment, the input / output unit has four memory cells MC1 to MC4. However, the present invention is not limited to four memory cells MC1 to MC4, and the number of memory cells can be increased or decreased according to requirements.

[0025] The input / output unit of the MRAM of the present invention can perform read and write operations simultaneously. Taking Figure 7 memory cells MC1 and MC2 as an example, when the address decoding controller 20 sends address signals A1 and A2 to select and read the data of memory cell MC1, and sends address signals A3 and A4 to select and write data into memory cell MC2, the first selection circuit 22 connects the first bit line BL1 of the first memory cell MC1 to the first read bit line RD_BL1 according to the address signal A1, and the second selection circuit 24 connects the first source line SL1 of the first memory cell MC1 to the first read source line RD_SL1 according to the address signal A2. The first sense amplifier 42 senses and outputs the data of the first memory cell MC1. At the same time, the third selection circuit 26 and the fourth selection circuit 28 also connect the second bit line BL2 and the second source line SL2 of the second memory cell MC2 to the first write bit line WR_BL_HV and the first write source line WR_SL_LV respectively according to the address signals A3 and A4 to write the data "P", or connect them to the second write bit line WR_BL_LV and the second write source line WR_SL_HV respectively to write the data "AP". Here, only the simultaneous read and write of two memory cells MC1 and MC2 are used for illustration. However, the present invention is not limited to the simultaneous read and write of two memory cells. For example, when reading the first memory cell MC1 and writing into the second memory cell MC2, the present invention can also control the fifth selection circuit 30 and the sixth selection circuit 32 to connect the third bit line BL3 and the third source line SL3 of the third memory cell MC3 to the second read bit line RD_BL2 and the second read source line RD_SL2 respectively, so that the second sense amplifier 44 senses and outputs the data of the third memory cell MC3. Or, when reading the first memory cell MC1 and writing into the second memory cell MC2, the present invention can control the seventh selection circuit 34 and the eighth selection circuit 36 to connect the fourth bit line BL4 and the fourth source line SL4 of the fourth memory cell MC4 to the first write bit line WR_BL_HV and the first write source line WR_SL_LV to write the data "P" into the fourth memory cell MC4.

[0026] The input / output unit of the MRAM of the present invention can write the same or different data into different memory cells simultaneously. Figure 7Taking the memory cells MC1 and MC2 as an example, when the first selection circuit 22 and the second selection circuit 24 connect the first bit line BL1 and the first source line SL1 of the first memory cell MC1 to the first write bit line WR_BL_HV and the first write source line WR_SL_LV respectively according to the address signals A1 and A2 to write the data "P" into the first memory cell MC1, the third selection circuit 26 and the fourth selection circuit 28 can connect the second bit line and the second source line of the second memory cell MC2 to the second write bit line WR_BL_LV and the second write source line WR_SL_HV respectively according to the address signals A3 and A4 to write the data "AP" into the second memory cell MC2. Alternatively, the third selection circuit 26 and the fourth selection circuit 28 can connect the second bit line and the second source line of the second memory cell MC2 to the first write bit line WR_BL_HV and the first write source line WR_SL_LV respectively according to the address signals A3 and A4 to write the data "P" into the second memory cell MC2.

[0027] The input / output unit of the MRAM of the present invention can read the data of two memory cells simultaneously, so as to Figure 7 Taking the memory cells MC1 and MC2 as an example, while the first selection circuit 22 and the second selection circuit 24 connect the first bit line BL1 and the first source line SL1 of the first memory cell MC1 to the first read bit line RD_BL1 and the first read source line RD_SL1 respectively according to the address signals A1 and A2, the third selection circuit 26 and the fourth selection circuit 28 can connect the second bit line BL2 and the second source line SL2 of the second memory cell MC2 to the second read bit line RD_BL2 and the second read source line RD_SL2 respectively according to the address signals A3 and A4. In this way, the first sense amplifier 42 and the second sense amplifier 44 can sense and output the data of the first memory cell MC1 and the second memory cell MC2 simultaneously. In Figure 7 the embodiment, at most two memory cells can be read simultaneously, but the present invention is not limited thereto. For example, by adding one more sense amplifier and a set of read bit lines and read source lines, three memory cells can be read simultaneously.

[0028] Since the input / output unit of the MRAM of the present invention can read and write multiple memory cells simultaneously, the read / write column-to-column latency time of the MRAM of the present invention is equivalent to that of DRAM, and can even be faster than DRAM. For example, assuming that it takes about 5 ns for DRAM to read and write one memory cell, and it takes about 10 ns for the MRAM of the present invention to read and write one memory cell. Since DRAM can only read and write one memory cell at a time, when DRAM reads and writes two memory cells, it needs to be separated by 5 ns from reading and writing the first memory cell. When reading and writing three memory cells, it needs to be separated by 5 ns from reading and writing the second memory cell. While originally, when the MRAM reads and writes two memory cells, it needs to be separated by 10 ns from reading and writing the first memory cell. When reading and writing three memory cells, it needs to be separated by 10 ns from reading and writing the second memory cell. However, the present invention can read and write multiple memory cells simultaneously. Therefore, when the present invention reads and writes two memory cells, the separation time from reading and writing the first memory cell does not need to be 10 ns, and the separation time can be 5 ns or less than 5 ns. The read / write column-to-column latency time of the MRAM of the present invention is equivalent to or faster than DRAM. Thus, a data rate equal to or faster than that of the dynamic random access memory is obtained.

[0029] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0030] Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on the present invention.

Claims

1. A magnetoresistive random access memory, characterized in that, Including: A plurality of input / output units, each input / output unit comprising: A first storage unit having a first bit line and a first source line; A second storage unit having a second bit line and a second source line; A first write bit line for receiving a first signal; A second write bit line for receiving a second signal; A first write source line for receiving the second signal; A second write source line for receiving the first signal; A first read bit line for receiving a third signal; A second read bit line for receiving the third signal; A first read source line for receiving a fourth signal; A second read source line for receiving the fourth signal; A first selection circuit connecting the first bit line, the first read bit line, the second read bit line, the first write bit line and the second write bit line for connecting the first bit line to one of the first read bit line, the second read bit line, the first write bit line and the second write bit line; A second selection circuit connecting the first source line, the first read source line, the second read source line, the first write source line and the second write source line for connecting the first source line to one of the first read source line, the second read source line, the first write source line and the second write source line; A third selection circuit connecting the second bit line, the first read bit line, the second read bit line, the first write bit line and the second write bit line for connecting the second bit line to one of the first read bit line, the second read bit line, the first write bit line and the second write bit line; A fourth selection circuit connecting the second source line, the first read source line, the second read source line, the first write source line and the second write source line for connecting the second source line to one of the first read source line, the second read source line, the first write source line and the second write source line; A first sense amplifier connected to the first read bit line for reading data from the first storage unit or the second storage unit; A second sense amplifier connected to the second read bit line for reading data from the first storage unit or the second storage unit.

2. The magnetoresistive random access memory according to claim 1, wherein Wherein when the first selection circuit connects the first bit line to the first read bit line or the second read bit line, and the second selection circuit connects the first source line to the first read source line or the second read source line, the third selection circuit and the fourth selection circuit connect the second bit line and the second source line to the first write bit line and the first write source line respectively or to the second write bit line and the second write source line respectively.

3. The magnetoresistive random access memory according to claim 1, wherein When the first selection circuit and the second selection circuit connect the first bit line and the first source line to the first write bit line and the first write source line respectively, the third selection circuit and the fourth selection circuit connect the second bit line and the second source line to the second write bit line and the second write source line respectively.

4. The magnetoresistive random access memory according to claim 1, wherein, When the first selection circuit and the second selection circuit connect the first bit line and the first source line to the first write bit line and the first write source line respectively, the third selection circuit and the fourth selection circuit connect the second bit line and the second source line to the first write bit line and the first write source line respectively.

5. The magnetoresistive random access memory according to claim 1, wherein When the first selection circuit and the second selection circuit connect the first bit line and the first source line to the first read bit line and the first read source line respectively, the third selection circuit and the fourth selection circuit connect the second bit line and the second source line to the second read bit line and the second read source line respectively.

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