Data transmission method and circuit arrangement therefor

Abstract

A method for data transmission between an integrated circuit and an evaluation unit connected to an interrupt pin of the integrated circuit is described, characterized in that the data transmission is carried out by selectively triggering a non-typical interrupt signal or a plurality of interrupt signals composed of a regular interrupt signal and / or a non-typical interrupt signal.

Description

Technical Field

[0001] The present invention relates to a method for data transmission between an integrated circuit and an evaluation unit, the use of such a method for data transmission between an integrated circuit and an evaluation unit, and a circuit layout structure. Background Technology

[0002] According to existing technology, various methods for data transmission between integrated circuits and downstream circuits are generally known.

[0003] There are write commands for so-called NFC tags, through which data received by the NFC circuitry of the NFC tag is passed to downstream circuitry, such as being written to memory.

[0004] However, some systems may not support this write command. This may be the case for NFC-connected transmitters or NFC circuits in use. This is considered a disadvantage.

[0005] The use of interrupt pins in integrated circuits is also known in the prior art, for example, as monitoring interfaces or other data sources to selectively make events detectable. Depending on the integrated circuit, there can be a variety of reasons for changing / triggering the interrupt signal. These interrupt signals generated by the integrated circuit can have different forms and durations. For example, a permanent level change of a pulse or the generation of a signal that can be used as an interrupt signal. The duration of the generated pulse or the repetition rate of the pulse can also vary.

[0006] However, these signals generated by the integrated circuit are always used only to signal the desired event. The desired event can be an event such as "wake up" or "buffer full / buffer empty".

[0007] The signal cannot be used for data transmission. Summary of the Invention

[0008] Therefore, the fundamental objective of this invention is to further develop a method for data transfer between an integrated circuit and an evaluation unit connected to an interrupt pin of the integrated circuit. A further objective is to provide the use of the method for data transfer between an integrated circuit and an evaluation unit connected to an interrupt pin of the integrated circuit, and to specify a circuit layout including the integrated circuit and the evaluation unit, wherein the integrated circuit is configured as an NFC circuit, and the evaluation unit comprises a logic unit and a microcontroller.

[0009] The method for data transmission between an integrated circuit and an evaluation unit connected to an interrupt pin of the integrated circuit according to the present invention is characterized in that data transmission is performed by selectively triggering an atypical interrupt signal or a plurality of interrupt signals consisting of a conventional interrupt signal and / or an atypical interrupt signal.

[0010] Because data transmission is performed by selectively triggering an atypical interrupt signal or multiple interrupt signals consisting of a conventional interrupt signal and / or atypical interrupt signals, data can be transmitted by the integrated circuit even if the data is not actually provided by the integrated circuit itself or is not supported by a third-party component communicating with the integrated circuit.

[0011] According to the present invention, data transmission should be understood as freely selectable data transmission from the integrated circuit to the evaluation unit. Merely signaling a predetermined state or event does not constitute data transmission in this sense.

[0012] In this application, a distinction is made between conventional interrupts and atypical interrupts. Conventional interrupts are signals with a defined form and duration, depending on the specific integrated circuit used. Atypical interrupt signals differ from conventional interrupt signals in both form and duration. Multiple interrupt signals consisting of conventional and / or atypical interrupt signals constitute either a series of conventional interrupt signals or a series of conventional and atypical interrupt signals.

[0013] By using the interrupt outputs of integrated circuits, more information can be selectively transmitted to an evaluation unit, which can include other components such as microcontrollers or field-programmable gate arrays (FPGAs). Data can be selectively transmitted by selectively generating these interrupts evaluated by the evaluation unit. These selectively generated interrupts can be identified as a "pattern" or "sequence" at the interrupt pin.

[0014] For example, this method can be used for communication between a data source and an evaluation unit configured as a microcontroller. The data source could be a mobile phone capable of communicating with an integrated circuit (e.g., an NFC circuit) via read access only. The corresponding read access generates an interrupt signal for the integrated circuit and transmits it to the microcontroller. Now, if multiple interrupt signals are triggered consecutively by multiple read accesses according to this configuration, even if the connection between the mobile phone and the integrated circuit and / or the connection between the integrated circuit and the microcontroller was not initially designed for this purpose, this series of appropriate configurations can be utilized to transmit information from the mobile phone to the microcontroller via the integrated circuit.

[0015] The duration of atypical interrupt signals differs from that of regular interrupt signals, which specifically refer to the total duration of the interrupt signal or the duration of any change in signal level. By using atypical interrupt signals, regular interrupts and data transmissions can be clearly distinguished. This ensures that a series of regular interrupts are not confused with data transmissions.

[0016] Multiple interrupt signals are preferably configured as a sequence of conventional and / or atypical interrupt signals. This sequence is a series of consecutive signals. Different sequences can be used to transmit different information. The sequence can vary in the number and duration of the interrupt signals and / or the duration of the distance between the interrupt signals. If atypical interrupt signals are used, both the duration of the interrupt signals and the duration of the distance between the interrupt signals can be varied.

[0017] Alternatively, the sequence can be configured as a series of interrupt signals with varying distances between them. This means that when using multiple regular interrupt signals, the duration between two consecutive interrupt signals can vary.

[0018] In a preferred configuration of the method, the evaluation unit is in a sleep mode and is reactivated from the sleep mode by means of an atypical interrupt signal or a plurality of interrupt signals consisting of a conventional interrupt signal and / or an atypical interrupt signal.

[0019] Therefore, energy can be saved during normal operation in the sleep mode of the evaluation unit. The sleep mode is configured to disable many functions of the evaluation unit, and only the part of the evaluation unit that responds to a first atypical interrupt signal or a first series of interrupt signals remains active. This part is configured to wake up the rest of the evaluation unit, that is, to reactivate the evaluation unit from the sleep mode.

[0020] For example, the evaluation unit can be configured as a logic unit and a microcontroller, both of which are connected to an interrupt pin. When the evaluation unit receives an atypical interrupt signal or a predetermined series of interrupt signals, the logic unit activates the microcontroller, and the microcontroller further evaluates the interrupt signal to transmit data.

[0021] By dividing the evaluation units in this way, a particularly energy-efficient sleep mode can be achieved, in which the microcontroller can be completely disabled and activated only when necessary, i.e., if the microcontroller receives an atypical interrupt signal or a predetermined series of interrupt signals, by a logic unit (e.g., a field-programmable gate array (FPGA)). Therefore, compared to a microcontroller in sleep mode, more energy can be saved because the microcontroller can be completely disabled and only the highly energy-efficient FPGA needs to be activated.

[0022] To further improve the energy efficiency of this method, it is advantageous for the evaluation unit to return to sleep mode after a specified time or after a specified signal. This means that, depending on the configuration of the underlying circuitry, the microcontroller itself enters sleep mode, or, in the case of a two-part evaluation unit, the microcontroller is disabled while the field-programmable gate array (FPGA) remains operational.

[0023] For example, an interrupt signal for a data transmission method can be generated by reading data from an integrated circuit. Data can be read block by block.

[0024] The data can originate from a data source, which can be configured as a mobile terminal device, such as a mobile phone, and wirelessly connected to the integrated circuit. Furthermore, the data source can trigger an interrupt signal by selectively reading data and transmitting the data to the integrated circuit and downstream evaluation units.

[0025] By using a read operation to generate an interrupt signal, it is still possible to perform write operations or data transfers in circuit layouts that do not support write commands.

[0026] Therefore, data can be transmitted, for example, written to memory. However, various other types of information can also be transmitted in this way.

[0027] The reverse channel, i.e., data transmission from the evaluation unit to the integrated circuit, can be implemented by writing data from the evaluation unit to the integrated circuit's memory. This memory can be read again by a third unit, thus making the information written into the memory available.

[0028] Preferably, the above method can be used to transmit data between an integrated circuit and an evaluation unit connected to an interrupt pin of the integrated circuit.

[0029] For this purpose, the integrated circuit is preferably configured as an NFC circuit, and the evaluation unit is configured as a microcontroller or a field-programmable gate array (FPGA) with a microcontroller.

[0030] The circuit layout structure according to the present invention includes an integrated circuit and an evaluation unit. The integrated circuit is configured as an NFC circuit, and the evaluation unit consists of a logic unit and a microcontroller. The logic unit and the microcontroller are directly or indirectly connected to the interrupt pin of the integrated circuit, and the output terminal of the logic unit is connected to the input terminal of the microcontroller.

[0031] This circuit layout configuration still allows for enabling write commands for NFC circuits that do not support write commands or for reading devices that do not support write commands.

[0032] In one embodiment, both the logic unit and the microcontroller are directly connected to the interrupt pin.

[0033] The logic unit can also include a buffer for storing interrupt signal sequences.

[0034] Therefore, the interrupt signal sequence can be temporarily stored in a buffer, and if the microcontroller does not transition from sleep mode to active operation quickly enough, or if the immediate reception of the interrupt signal sequence is incomplete or interrupted for other reasons, the sequence can be retrieved again by the microcontroller. Alternatively, this can create redundancy for data transmission. Attached Figure Description

[0035] The invention will now be explained in more detail with reference to the accompanying drawings and design examples. The drawings show:

[0036] Figure 1 A first design example of a circuit layout structure in which the method according to this application can be used;

[0037] Figure 2 A second design example of a circuit layout structure in which the method according to this application can be used;

[0038] Figure 3 Subgraphs a) to c) show conventional interrupt signals, atypical interrupt signals, and sequences of conventional interrupt signals.

[0039] Figure 4 : A simplified representation of the possible sequence of methods; and

[0040] Figure 5 As based on Figure 2 The sequence of methods used in the circuit layout structure. Detailed Implementation

[0041] In the accompanying drawings, unless otherwise specified, the same reference numerals refer to the same parts or corresponding parts having the same function.

[0042] Figure 1 A first design example of circuit layout structure 1 is shown, in which the method according to this application can be used.

[0043] according to Figure 1 The circuit layout structure 1 includes an integrated circuit 3. The interrupt pin 31 of the integrated circuit 3 is connected to the evaluation unit 5 via an interrupt line 33. The evaluation unit 5 is also connected to the integrated circuit 3 via a data line 35. The integrated circuit 3 can read data from the memory 51 of the evaluation unit 5 via the data line 35. In this design example, the data line 35 is unidirectional; that is, the integrated circuit 3 can read data from the memory 51 of the evaluation unit 5, but cannot change the data stored in the memory 51 via the data line 35.

[0044] exist Figure 1 In the design example shown, data source 11 is also connected to integrated circuit 3, and the data to be transmitted to memory 51 of evaluation unit 5 is stored on data source 11.

[0045] Data source 11 is connected to integrated circuit 3 via a near-field communication (NFC) wireless link.

[0046] Selectively sending read commands to integrated circuit 3 causes selective interrupt signals to be generated in the circuit, and these interrupt signals are present on the output side of interrupt pin 31. Since evaluation unit 5 is connected to interrupt pin 31 via interrupt line 33, evaluation unit 5 is able to pick up and evaluate the series of interrupt signals generated. Therefore, data can be transmitted from data source 11 to evaluation unit 5 by means of a properly agreed-upon encoding, which both data source 11 and evaluation unit 5 must know, and which is stored, for example, in memory 51.

[0047] Figure 2 A second design example of circuit layout structure 1 is shown, in which the method according to this application can be used.

[0048] and Figure 1 Compared to the circuit layout shown, in Figure 2 In the design example, the evaluation unit 5 consists of a logic unit 7 and a microcontroller 9, whereby both the logic unit 7 and the microcontroller 9 are connected to the interrupt pin 31 of the integrated circuit 3 via the interrupt line 33.

[0049] In this design example, data line 35 is configured between integrated circuit 3 and microcontroller 9, and data line 35 will in principle support bidirectional communication between integrated circuit 3 and microcontroller 9.

[0050] However, in Figure 2 In the design example shown, the data source 11 only supports read commands for configuring an NFC connection between the data source 11 and the integrated circuit 3. Therefore, in this design example, data transmission from the data source 11 to the evaluation unit 5 is also performed through the selective execution of read commands, the triggering of interrupt signals generated therefrom, and the evaluation of these interrupt signals by the evaluation unit 5.

[0051] The memory 52 contained in integrated circuit 3 can be freely modified by evaluation unit 5, specifically by reading and writing. Data source 11 can detect this data or the modification of the data, thereby generating a response. Therefore, erroneous interrupt signals or sequences can be checked.

[0052] The advantage of the two-part configuration of the evaluation unit 5, which has a logic unit 7 and a microcontroller 9, is that the microcontroller can be disabled when no data transmission is being performed, while the logic unit 7, which can be configured, for example, as a field-programmable gate array (FPGA), monitors the interrupt line 33 for interrupts and activates the microcontroller only when necessary.

[0053] To conserve more energy, microcontroller 9 returns to a deactivated state after a specific period of no data transmission, so again only the logic unit 7 must be powered to monitor interrupt line 33. When an interrupt signal occurs, logic unit 7 switches microcontroller 9 to an active state so that microcontroller 9 can evaluate the interrupt signal.

[0054] It can be further configured that the interrupt signal is transmitted from integrated circuit 3 to microcontroller 9 via a logic unit, that is, there is no direct connection between microcontroller 9 and interrupt pin 31 of integrated circuit 3.

[0055] Alternatively, a data line may be provided between logic unit 7 and microcontroller 9. Furthermore, logic unit 7 may include a buffer where information present at interrupt pin 31 is temporarily stored. For example, if microcontroller 9 responds too slowly to the first interrupt signal to fully acquire the sequence of interrupt signals, the sequence can be retrieved from the buffer and transmitted back to microcontroller 9.

[0056] Figure 3 Different interruption signals are shown in subgraphs a) to c). Figure 3 Figure a) shows a conventional interrupt signal 90, which is implemented as a square wave signal with a periodic duration T1. Such a conventional interrupt signal 90 is known in the prior art.

[0057] Figure 3 Figure b) illustrates an atypical interrupt signal 92. In the design example shown here, the atypical interrupt signal 92 has a signal duration T2, which is a multiple of the signal length T1 of the conventional interrupt signal 90. These differences in signal length between the conventional interrupt signal 90 and the atypical interrupt signal 92 can be detected by the evaluation unit 5 and thus can be utilized for data transmission.

[0058] Figure 3 c) shows a sequence of unconventional interrupt signals 90. The unconventional interrupt signals 90 shown here have a signal length T1 and a signal distance Δt, respectively. Multiple different series, such as a mixture of conventional interrupt signals 90 and atypical interrupt signals 92 and / or their interrupt signals having different signal distances, can be used particularly effectively to transmit data from data source 11 to evaluation unit 5 via integrated circuit 3.

[0059] In each case, in the design example above, the data source is configured as a mobile phone with an NFC interface, and the integrated circuit is configured as an NFC circuit set on the NFC chip.

[0060] Figure 4 A simplified method sequence according to the method of this application is shown.

[0061] After the method begins, data is read block by block via integrated circuit 3, and data transmission is established using a series of interrupt signals. This reading can access memory 51 or 52, thereby establishing a reverse channel. The method terminates when data transmission is complete.

[0062] Figure 5 The detailed method sequence according to this application is shown, enabling... Figure 2 This method is used in the circuit layout shown.

[0063] The data source 11 of the smartphone can communicate with the integrated circuit 3 and the NFC chip via a wireless data cable 36 (e.g., an NFC wireless link).

[0064] In the first step 501, the method begins, and the evaluation unit 5 is in sleep mode. In the second step 502, the data source reads data from the integrated circuit 3 block by block via the wireless data line 36. This block-by-block reading generates an atypical interrupt signal 92 on the interrupt line 33, thus activating the evaluation unit 5. In the third step 503, the data source 11 can transmit data to the evaluation unit 5 via the wireless data line 36 and the integrated circuit 3. For this purpose, various sequences of interrupt signal 90 and / or atypical interrupt signal 92 can be used. In the fourth step 504, the block-by-block reading of the data required for this purpose can simultaneously serve as a reverse channel from the evaluation unit 5 to the data source 11. In the fifth step 505, the method terminates, and the evaluation unit 5 returns to a power-saving operating mode.

[0065] List of reference numerals

[0066] 1. Circuit layout structure

[0067] 3 Integrated Circuits

[0068] 5. Evaluation Unit

[0069] 7 Logic Units

[0070] 9 Microcontrollers

[0071] 11 Data Sources

[0072] 31 Interrupt pin

[0073] 33 Interrupted Line

[0074] 35 Data Cable

[0075] 36 Wireless Data Cables

[0076] 51 Memory

[0077] 52 Memory

[0078] 90. Conventional Interrupt Signals

[0079] 92 Atypical interrupt signal

[0080] t time

[0081] T1 duration

[0082] T2 duration

[0083] Δt distance

Claims

1. A method for transmitting data between an integrated circuit (3) and an evaluation unit (5) connected to an interrupt pin (31) of said integrated circuit (3), characterized in that, The data transmission, i.e., the freely selectable data transmission from the integrated circuit to the evaluation unit, is performed by selectively triggering atypical interrupt signals (92) or multiple interrupt signals (90, 92) consisting of conventional interrupt signals (90) and / or atypical interrupt signals (92). The conventional interrupt signal (90) is a signal with a defined form and duration depending on the integrated circuit (3), and the atypical interrupt signal (92) is a signal that differs from the conventional interrupt signal (90) in form and duration, and the plurality of interrupt signals are configured as a sequence of conventional interrupt signal (90) and / or atypical interrupt signal (92).

2. The method according to claim 1, characterized in that, The sequence is configured as a series of regular interrupt signals (90) and / or atypical interrupt signals (92) with different distances (ΔT) between the regular interrupt signal (90) and / or atypical interrupt signal (92).

3. The method according to claim 1 or 2, characterized in that, The evaluation unit (5) is in sleep mode and is reactivated from sleep mode by the atypical interruption signal (92) or the plurality of interruption signals consisting of the conventional interruption signal (90) and / or the atypical interruption signal (92).

4. The method according to claim 3, characterized in that, The evaluation unit (5) consists of two parts: a logic unit (7) and a microcontroller (9). Both the logic unit (7) and the microcontroller (9) are connected to the interrupt pin (31). When the logic unit (7) receives an atypical interrupt signal (92), the logic unit (7) activates the microcontroller (9), and the microcontroller (9) further evaluates the normal interrupt signal (90) and / or the atypical interrupt signal (92) to transmit the data.

5. The method according to claim 3, characterized in that, The evaluation unit (5) returns to the sleep mode after a specified time (t) or after a specified signal.

6. The method according to claim 4, characterized in that, The evaluation unit (5) returns to the sleep mode after a specified time (t) or after a specified signal.

7. The method according to claim 1 or 2, characterized in that, The conventional interrupt signal (90) or multiple conventional interrupt signals (90) and / or the atypical interrupt signal (92) or multiple atypical interrupt signals (92) are generated by reading data from the integrated circuit (3).

8. The method according to claim 7, characterized in that, The data is read block by block.

9. The method according to claim 1 or 2, characterized in that, The data transmission is written to the memory (51).

10. The method according to claim 1 or 2, characterized in that, The evaluation unit (5) writes into the memory (51 or 52) of the integrated circuit (3) to form a reverse channel.

11. The method according to claim 1 or 2, characterized in that, The data originates from a data source (11) wirelessly connected to the integrated circuit (3).

12. The method according to claim 1 or 2, characterized in that, The integrated circuit (3) is configured as an NFC circuit, and the evaluation unit (5) is configured as an FPGA or a microcontroller (9).

13. A circuit device (1) comprising an integrated circuit (3) and an evaluation unit (5), wherein the integrated circuit (3) is configured as an NFC circuit, and the evaluation unit (5) comprises a logic unit (7) and a microcontroller (9), wherein, The logic unit (7) and the microcontroller (9) are directly or indirectly connected to the interrupt pin (31) of the integrated circuit (3), and the output terminal of the logic unit (7) is connected to the input terminal of the microcontroller (9). The circuit device (1) is configured to perform the method according to any one of claims 1-12.

14. The circuit device (1) according to claim 13, characterized in that, Both the logic unit (7) and the microcontroller (9) are directly connected to the interrupt pin (31).

15. The circuit device (1) according to claim 13 or 14, characterized in that, The logic unit (7) includes a buffer for storing an interrupt signal sequence.

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