A multi-thread module and multi-thread control method based on ASIC

Abstract

The present invention discloses a multi-thread module and a multi-thread control method based on ASIC. Existing methods cannot take into account both efficiency and flexibility. The multi-thread module of the present invention includes a module function kernel, a multi-thread interface group, and a multi-thread priority arbitration module. The module function kernel is used to read, parse and execute the instructions of the thread that wins the arbitration, including a bus read-write module, an instruction parsing module, a register configuration module, and a function execution module. The multi-thread interface group includes multiple thread interfaces, each thread interface has an independent thread register, thread instruction, and thread interrupt, and each thread register includes a thread suspension register, a thread reset register, a thread granularity register, a thread priority register, a thread context register, and an instruction submission register. The multi-thread priority arbitration module is used for priority arbitration between multiple threads. The present invention realizes saving resource overhead, improving thread scheduling efficiency, and optimizing software and hardware interaction.

Description

Technical Field

[0001] The present invention belongs to the technical field of application specific integrated circuits, and in particular relates to a multi-thread module and a multi-thread control method based on ASIC. Background Art

[0002] In ASIC (Application Specific Integrated Circuit) design, multithreading can be divided into multi-core multithreading and single-core multithreading. Multi-core multithreading can be considered as a simple module stacking. The advantage is that the hardware module design does not need to consider multithreading related, and the performance is high. The disadvantage is that resources are relatively wasted. Single-core multithreading has only one hardware module, and the multithreading mechanism is implemented through full software, software and hardware combination, or full hardware. Most of the multithreading today is implemented at the software level. The disadvantages of software use and management include long priority switching operation processing time, insufficient software and hardware interaction performance, and difficulty in ensuring the integrity of offline compilation instructions. Especially for some modules that have or partially have the characteristics of memory to memory, multi-master call, batch processing, high reuse, etc., these problems are particularly prominent. For example, in modules without multithreading interfaces, the software needs to actively flush the CACHE operation every time it writes instructions to the DDR cache, and then submits them to the hardware module, or the software submits the instructions to the hardware only after detecting that the hardware has completed the interrupt. Such a serial software and hardware interaction method will make the hardware idle in many cases, reducing the execution efficiency of the hardware module. One solution is to use a circular instruction cache, but it has high requirements for software use. In order to avoid misjudgment of interrupts when submitting instructions (waiting for the completion interrupt after the last instruction is submitted, but the interrupt you wait for may be the completion interrupt of the last instruction submitted), you need to disable interrupts and handshake between software and hardware to ensure that there will be no errors. Generally speaking, full software has low efficiency and full hardware lacks flexibility. These two methods cannot achieve both efficiency and flexibility. Summary of the invention

[0003] An object of the present invention is to provide an ASIC-based multi-threaded module.

[0004] The ASIC-based multi-thread module proposed in the present invention exists in the hardware module, and the multi-thread module includes a module function core, a multi-thread interface group, and a multi-thread priority arbitration module. Among them:

[0005] The module function core is a single-core function module, which is used to read, parse and execute the instructions of the thread that wins the arbitration, including a bus read and write module, an instruction parsing module, a register configuration module and a function execution module.

[0006] The multi-thread interface group includes multiple thread interfaces, each of which has independent thread registers, thread instructions, and thread interrupts, which are used to provide multiple master controllers with access interfaces that can call a module function kernel at the same time. The master controller is a central processing unit or a hardware module. Each thread has its own AXI bus read and write identifier. A single hardware module can access the advanced security area and the non-advanced security area at the same time through multiple thread interfaces.

[0007] The thread registers of each thread interface include thread suspension registers, thread reset registers, thread granularity registers, thread priority registers, thread context registers, and instruction submission registers configured by software. Among them, the thread suspension register is used to actively suspend the corresponding thread; the thread reset register is used to reset the corresponding thread context register and the intermediate variable register of the multi-thread priority arbitration module; the thread granularity register is used to configure the minimum execution instruction granularity of the corresponding thread, and the module function kernel will not suspend the thread or switch to the next thread before executing the minimum granularity instruction of the thread; the thread priority register is used to configure the priority of the corresponding thread; the thread context register is used to store the context parameters passed between instructions; the instruction submission register is used to describe the starting address and the length of each instruction submitted.

[0008] Thread instructions include thread lock instructions and null instructions, which are set by software or compiler in thread instructions. Thread lock instructions are used to lock the thread containing instructions that need to be executed continuously. After the module function kernel parses the thread lock instruction, the internal thread priority arbitration will always select instructions in the locked thread for the hardware kernel to execute until the thread lock is unlocked, and then arbitration based on thread priority will be resumed. Null instructions are used to implement functions that cannot be implemented by hardware by kernel software. After the module function kernel parses the null instruction, it will directly suspend and issue a null instruction interrupt.

[0009] The multi-thread priority arbitration module is used for priority arbitration between multiple threads. The module function kernel executes the instructions of the thread that wins the arbitration.

[0010] Another object of the present invention is to provide a multi-thread control method based on an ASIC multi-thread module.

[0011] The multi-thread control method of the present invention is implemented by combining software and hardware; the software configures the start, suspension and configuration priority of threads through thread registers and thread instructions; the hardware performs priority arbitration between threads and determines the thread suspension or switching time point to ensure the integrity before and after the instructions. After the hardware completes the thread task or recognizes a specific instruction, it reports an interrupt to inform the software. The specific process is as follows:

[0012] Step (1) the software configures a plurality of groups of thread registers for a register configuration module of a module function kernel of the hardware module, and configures a control register for a hardware function execution module; each group of thread control registers includes a thread suspension register, a thread reset register, a thread granularity register, a thread priority register, a thread context register, and an instruction submission register;

[0013] Step (2) detecting whether the hardware module is started, if so, the module function core executes the instruction of the thread that wins arbitration by the multi-thread priority arbitration module, otherwise it enters a waiting state;

[0014] Step (3) Each thread has a copy of the instruction submitted to the instruction submission register, which is used to describe the starting address and length of each instruction submitted, etc. The starting address is the location of the instruction in the DDR memory; the winning thread reads the instruction in the DDR memory through the bus read-write module according to the information in the instruction submission register;

[0015] Step (4) the thread performs instruction parsing through the instruction parsing module;

[0016] Step (5) After the instruction is parsed, the function execution module executes the instruction.

[0017] Among them, the priority arbitration of the multi-threaded priority arbitration module is specifically:

[0018] Step (1) After the multi-thread priority arbitration module is turned on, the thread priority query is first performed, and the hardware module obtains the priority of each thread and compares them to obtain the highest priority thread;

[0019] Step (2) determines whether the highest priority thread has tasks to be executed: if so, the function execution module obtains the priority authority and enters the highest priority thread to execute the task instruction; if not, returns to step (1) and queries the thread priority again;

[0020] Step (3) The highest priority thread enters the work and executes an instruction of a granular size;

[0021] Step (4) returns to step (1) after executing each instruction of thread granularity size, and queries the thread priority again: if the highest priority thread queried is not the currently executing priority thread, or if a thread with the same priority as the currently executing thread exists, a thread switch is performed.

[0022] The ASIC-based multi-thread module and multi-thread control method proposed in the present invention help to time-division multiplex hardware and reduce the hardware idle time overhead between two calls; the switching time point can be determined by the hardware to ensure the integrity of the instructions before and after; the thread priority can be switched at any time, and low-priority tasks can be suspended and switched to high-priority tasks; the software does not need to implement hardware real-time, which reduces the real-time requirements of the software; different bus read and write IDs can be distinguished by different threads to achieve the sharing of the same hardware module by the security zone and the non-security zone; mutual calls between multiple hardware cores can be realized; "thread suspension + empty instruction + reserved function mode" can solve the problems of chip function expansion and BUG concealment in the later stage.

[0023] By adopting the present invention, even offline compiled instructions can seamlessly implement software and hardware scheduling, allowing kernel-state software to efficiently perform functional expansion. The present invention achieves the beneficial effects of saving resource overhead, improving thread scheduling efficiency, and optimizing software and hardware interaction. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the multi-threaded hardware and software interaction interface of the hardware module;

[0025] Figure 2 Schematic diagram of software multi-core directly calling hardware multi-threading interface;

[0026] Figure 3 This is a schematic diagram of software multi-core indirectly calling hardware multi-threading interface;

[0027] Figure 4 It is a flowchart of a multi-thread control method;

[0028] Figure 5 It is a priority arbitration flow chart of the multi-thread priority arbitration module;

[0029] Figure 6 It is a schematic diagram of static particle size;

[0030] Figure 7 It is a schematic diagram of dynamic granularity;

[0031] Figure 8 Implement a flow chart for thread lock instructions;

[0032] Fig. 9 This is a schematic diagram of the implementation of the empty instruction;

[0033] Fig.10 This is a diagram of thread switching. DETAILED DESCRIPTION

[0034] The ASIC-based multi-thread module proposed in the present invention exists in the hardware module, and the multi-thread module includes a module function core, a multi-thread interface group, and a multi-thread priority arbitration module. Among them:

[0035] The module function core is a single-core function module, which is used to read, parse and execute the instructions of the thread that wins the arbitration, including a bus read and write module, an instruction parsing module, a register configuration module and a function execution module.

[0036] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0037] like Figure 1 As shown, the software interacts with the hardware module 140 through the APB or AHB bus interface 110, the thread interrupt 120, and the instructions of the four threads in the DDR memory 130 (thread 0 instruction cache 130a, thread 1 instruction cache 130b, thread 2 instruction cache 130c, thread 3 instruction cache 130d).

[0038] The hardware module supports multiple thread interfaces. In this embodiment, the hardware module 140 can support four threads. The software on the APB bus 110 has five registers, including four groups of thread registers 140a, 140b, 140c and 140d, and a control register 140e of the hardware function execution module. Each group of thread registers includes a thread suspension register, a thread reset register, a thread granularity register, a thread priority register, a thread context register, and an instruction submission register configured by software.

[0039] The thread interrupt 120 is four bits wide, corresponding to four threads respectively. The chip system determines the connection of the four-bit interrupt line according to the actual thread usage, and the unused interrupt lines are left floating.

[0040] The hardware multithreading interface supports software multi-core calls in two main ways: multi-core direct calls and multi-core indirect calls.

[0041] Multi-core direct calling method such as Figure 2 As shown, taking four threads as an example, four cores (main control core 150, processing core one 160, processing core two 170, processing core three 180) can directly access four thread registers (thread 0 register 140a, thread 1 register 140b, thread 2 register 140c, thread 3 register 140d) and four interrupt signal lines, wherein the main control core 150 is connected to the control register 140e of the hardware function execution module.

[0042] Multi-core indirect call method Figure 3 As shown, a main control core 150 interacts with the hardware multithreading interface, and the remaining processing cores (processing core 160, processing core 2 170, processing core 3 180) all interact with the main control core 150. This method can support any number of processing cores to interact with the main control core to implement the call of the hardware module 140.

[0043] The hardware multi-threaded interface can effectively solve the problem of insufficient efficiency of software-hardware interaction. The software can continuously add instructions to the instruction cache of different threads. The CACHE needs to be refreshed before each instruction is submitted, but ping-pong operations can be performed between different threads to cover the CACHE refresh time within the hardware working time. If the software submits enough instructions, the hardware can be guaranteed to remain in working condition.

[0044] Take two threads ping-pong as an example. When the hardware module 140 finishes executing the instructions in the instruction cache 130a of thread 0, it starts to execute the instructions in the instruction cache 130b of thread 1; at this time, the software CPU receives the end interrupt of thread 0 and can submit new instructions to the instruction cache 130a of thread 0. By analogy, when the CPU finishes submitting instructions to thread 0 and the hardware module 140 finishes executing the instructions in the instruction cache 130b of thread 1, it starts to execute the instructions in the instruction cache 130a of thread 0; at this time, the software CPU receives the end interrupt of thread 1 and submits new instructions to the instruction cache 130b of thread 1.

[0045] like Figure 4 As shown, the workflow of the ASIC-based multi-threaded module is as follows:

[0046] Step (1) The software configures registers for the register configuration module of the module function core of the hardware module 140. In this embodiment, the configured registers include four groups of thread registers 140a, 140b, 140c and 140d, and a control register 140e for the hardware function execution module configuration. A group of thread registers includes a thread suspension register, a thread reset register, a thread granularity register, a thread priority register, a thread context register, and an instruction submission register.

[0047] Step (2) detects whether the hardware module is started. If it is started, the module function core executes the instruction of the thread that wins the arbitration of the multi-thread priority arbitration module, otherwise it enters the waiting state.

[0048] Step (3) Each thread has a copy of the instruction submitted to the instruction submission register, which is used to describe the starting address and length of each instruction submitted, etc. The starting address is the location of the instruction in the DDR memory 130; the winning thread reads the instruction in the DDR memory 130 through the bus read-write module according to the information in the instruction submission register.

[0049] Step (4) The thread performs instruction parsing through the instruction parsing module.

[0050] Step (5) After the instruction is parsed, the function execution module executes the instruction.

[0051] Among them, the priority arbitration process of the multi-threaded priority arbitration module is as follows: Figure 5 As shown:

[0052] Step (1) After the multi-thread priority arbitration module is turned on, the thread priority query is first performed. The hardware module obtains the priority of each thread and compares them to obtain the highest priority thread among the four threads.

[0053] Step (2) determines whether the highest priority thread has tasks to be executed: if so, the function execution module obtains priority authority and enters the highest priority thread to execute task instructions; if not, returns to step (1) and queries the thread priority again.

[0054] Step (3) The highest priority thread enters the work and executes an instruction of a granular size.

[0055] Step (4) returns to step (1) after executing each instruction of thread granularity size, and queries the thread priority again: if the highest priority thread queried is not the currently executing priority thread, or if a thread with the same priority as the currently executing thread exists, a thread switch is performed.

[0056] Each time the software submits an instruction, it updates the starting address and number of instructions, and a new instruction can only be submitted after the previously submitted instruction is executed. If you want to submit a new instruction in advance before the previously submitted instruction is completed, you need to use thread swapping.

[0057] The thread granularity is used to represent the minimum instruction packing unit for the multi-thread priority arbitration module to switch threads. The thread granularity can be in one of the following two forms:

[0058] like Figure 6 As shown, one is the static granularity configured by the thread granularity register, thread 0 instruction cache 600. If the configured granularity is one instruction, instruction one 610 is one granularity and instruction two 620 is the second granularity. If the configured granularity is two instructions, instruction one 610 and instruction two 620 are packaged into one granularity.

[0059] like Figure 7As shown, the other is dynamic granularity. For the instruction cache 700 of thread 1, a thread lock instruction 710 is configured. The thread lock instruction 710 is the instruction for opening the thread lock. The thread lock instruction is generally concerned by the application end that generates the instruction. When the application generates the instruction, it knows whether there is a dependency relationship between the previous and next instructions. The thread lock can be added at the same time when the instruction is generated. In this way, the driver can be completely unconcerned. The hardware module will wait until all the instructions locked by the thread lock are executed before performing thread switching. During the execution of the instruction, if the thread lock instruction 710 is encountered, the next unexecuted instruction is locked. If the number of instructions currently executed is greater than or equal to the static granularity configured by the thread granularity register, the thread switch is performed directly after the next instruction is completed. For thread 1, if the granularity is configured as one instruction, instruction one 720 is one granularity, and thread lock instruction 710 and instruction two 730 are packaged as the second granularity. If the granularity is configured as two instructions, instruction one 720 is one granularity, and thread lock instruction 710 and instruction two 730 are packaged as one granularity. After completing the first instruction 720 and the thread lock instruction 710, since the last instruction executed is the thread lock instruction, the thread is switched after completing the second instruction 730.

[0060] The thread lock instruction implementation process is as follows Figure 8 As shown:

[0061] Step (1) start a new instruction for the current thread;

[0062] Step (2) the instruction parsing module parses the instruction to obtain a thread lock instruction;

[0063] Step (3) the function execution module executes the thread lock instruction;

[0064] Step (4) When the thread lock instruction is 1, it indicates that the thread lock is turned on, and step (1) is executed, that is, the next instruction of the current thread is forcibly executed; when the thread lock instruction is 0, it indicates that the thread lock is not turned on, and step (5) is executed;

[0065] Step (5) queries the number of instructions continuously executed by the current thread: if the number of instructions is greater than or equal to the thread instruction granularity, execute step (6); otherwise, return to step (1) and continue to execute subsequent instructions of the current thread;

[0066] Step (6) The multi-thread priority arbitration module performs thread switching.

[0067] For instruction combinations with large context interaction requirements, they must be implemented through thread locks. Context registers are only suitable for scenarios with smaller context interaction requirements.

[0068] like Fig. 9As shown, an empty instruction 920 can be inserted into the thread instruction cache 910. After the hardware parses the empty instruction, it will be suspended directly and an empty instruction interrupt will be issued. The empty instruction implementation process is: if the current empty instruction does not add a thread lock, the thread permission will be cut off after the current thread is actively suspended, and the instructions of other threads will be executed first; if the current empty instruction adds a thread lock, the thread permission will not be cut off after the hardware actively suspends the current thread, and the entire hardware module will be suspended waiting for the software to resume the thread, and the instructions of other threads will not be executed. After the software CPU 930 restarts the current thread through the register, it will continue to obtain and execute the next instruction of the current thread.

[0069] The application scenarios are mainly to support the kernel software to implement some functions that cannot be implemented by hardware or are too complex, or the software expansion implementation of the chip when encountering new application requirements can be directly implemented in the form of adding a new function definition. The driver and the application side do not need additional interaction. From the external API point of view, the hardware module already supports such functions. The hardware module needs to reserve some custom modes or function configuration descriptions during design.

[0070] Thread switching Fig.10 As shown: the current thread 0 execution state is 1010, the default granularity is one instruction, the hardware is executing the previous instruction 1020, and the swap-in and swap-out operations are performed at this time; the software first suspends thread 1010 and saves the scene (context protection, etc.), then resets thread 1010, swaps in new instructions 1030, and continues to execute the thread's next instruction 1050 after the thread is submitted and reset.

[0071] Thread suspension means suspending a certain thread, while other threads 1040 can continue to work. The suspended thread 0 will be removed from the thread priority query list. The registers of the suspended thread can be read and written, and instructions can be submitted, but the suspended thread cannot be executed. When the software submits instructions again after the thread is suspended, the hardware module will record and accumulate the number of instructions submitted by the thread. The software needs to ensure that the instruction cache has enough space to save the submitted instructions.

[0072] Application of thread context: When two functions AB need to be implemented with two instruction configurations, and function B needs to use the output result of function A. There are two implementation methods: The first is that the driver needs to care about function A, function B, and parameter C passed between the two. After function A is completed, an interrupt is reported, the driver obtains parameter C, and then generates instruction configurations for function B in real time. The second is relatively transparent to the driver. The application side packages and generates instructions for function A and function B. Parameter C passed between the two is passed through the thread context. After function A is completed, parameter C is written to the thread context register. When function B is executed, the parameter is directly obtained from the thread context register. Of course, this context is not just a register, it can also be the content stored in a certain address segment in DDR. This is defined by the specific function. Generally, registers are used to implement small amounts of data.

Claims

1. A multi-thread control method based on an ASIC-based multi-thread module, wherein the multi-thread module exists in a hardware module and includes a module function kernel, a multi-thread interface group and a multi-thread priority arbitration module; characterized in that: The method is implemented by combining software and hardware. The software configures the start, suspension and configuration priority of threads through thread registers and thread instructions. The hardware performs priority arbitration between threads and determines the thread suspension or switching time point to ensure the integrity before and after the instruction. After the hardware completes the thread task or recognizes the instruction, it reports an interrupt to inform the software. The specific process is as follows: Step (1) the software configures a plurality of groups of thread registers for a register configuration module of a module function kernel of the hardware module, and configures a control register for a hardware function execution module; each group of thread control registers includes a thread suspension register, a thread reset register, a thread granularity register, a thread priority register, a thread context register, and an instruction submission register; Step (2) detecting whether the hardware module is started, if so, the module function core executes the instruction of the thread that wins arbitration by the multi-thread priority arbitration module, otherwise it enters a waiting state; Step (3) Each thread has a copy of the instruction submitted to the instruction submission register, which is used to describe the starting address and length of each instruction submitted, and the starting address is the location of the instruction in the DDR memory; the winning thread reads the instruction in the DDR memory through the bus read / write module according to the information in the instruction submission register; Step (4) the thread performs instruction parsing through an instruction parsing module; Step (5) After the instruction is parsed, the function execution module executes the instruction; One or more thread instruction caches are configured with a thread lock instruction, i.e., an instruction for turning on the thread lock; During the execution of instructions, if a thread lock instruction is encountered, the next unexecuted instruction will be locked; if the number of instructions currently executed is greater than or equal to the static granularity configured by the thread granularity register, the thread switch will be performed directly after the next instruction is completed; Insert a null instruction into the instruction cache of one or more threads. After the hardware parses the null instruction, it will suspend the execution and issue a null instruction interrupt. The specific implementation process is: if the current empty instruction does not have a thread lock, the thread permission will be cut off after the current thread is actively suspended, and the instructions of other threads will be executed first; if the current empty instruction has a thread lock, the thread permission will not be cut off after the hardware actively suspends the current thread, and the entire hardware module will be suspended waiting for the software to resume the thread. The instructions of other threads will not be executed until the software CPU restarts the current thread through the register, and then continue to obtain and execute the next instruction of the current thread.

2. The multi-thread control method based on the multi-thread module of ASIC according to claim 1, characterized in that: The priority arbitration of the multi-threaded priority arbitration module is specifically: Step (a) After the multi-thread priority arbitration module is turned on, the thread priority query is first performed, and the hardware module obtains the priority of each thread and compares them to obtain the highest priority thread; Step (b) determines whether the highest priority thread has tasks to be executed: if so, the function execution module obtains the priority authority and enters the highest priority thread to execute the task instruction; if not, returns to step (a) and queries the thread priority again; Step (c) The highest priority thread enters the work and executes an instruction of a granular size; Step (d) returns to step (a) after executing each instruction of thread granularity size, and queries the thread priority again: if the highest priority thread queried is not the currently executing priority thread, or if a thread with the same priority as the currently executing thread exists, a thread switch is performed.

3. The multi-thread control method based on the multi-thread module of ASIC as claimed in claim 2, characterized in that: The specific implementation process of the thread lock instruction is: Step (A) starts a new instruction for the current thread; Step (B) the instruction parsing module parses the instruction to obtain a thread lock instruction; Step (C) the function execution module executes the thread lock instruction; Step (D) When the thread lock instruction is 1, it means that the thread lock is turned on, and step (A) is executed, that is, the next instruction of the current thread is forced to execute; when the thread lock instruction is 0, it means that the thread lock is not turned on, and step (E) is executed; Step (E) queries the number of instructions continuously executed by the current thread: if the number of instructions is greater than or equal to the thread instruction granularity, execute step (F); otherwise, return to step (A) and continue to execute subsequent instructions of the current thread; Step (F) The multi-thread priority arbitration module performs thread switching.

4. The multi-thread control method based on the multi-thread module of ASIC as claimed in claim 1, characterized in that: The module function core is a single-core function module, which is used to read, parse and execute the instructions of the thread that wins the arbitration, including a bus reading and writing module, an instruction parsing module, a register configuration module and a function execution module; The multi-thread interface group includes multiple thread interfaces, each of which has independent thread registers, thread instructions, and thread interrupts, and is used to provide multiple master controllers with access interfaces that can simultaneously call a module function kernel, and the master controller is a central processing unit or a hardware module; each thread has its own different AXI bus read and write identifier, and a single hardware module can be accessed simultaneously through multiple thread interfaces; The thread registers of each thread interface include a thread suspension register, a thread reset register, a thread granularity register, a thread priority register, a thread context register, and an instruction submission register configured by software; wherein the thread suspension register is used to actively suspend the corresponding thread; the thread reset register is used to reset the corresponding thread context register, and reset the intermediate variable register of the multi-thread priority arbitration module; the thread granularity register is used to configure the minimum execution instruction granularity of the corresponding thread, and the module function kernel will not suspend the thread or switch to the next thread before executing the minimum granularity instruction of the thread; the thread priority register is used to configure the priority of the corresponding thread; the thread context register is used to store the context parameters passed between instructions; the instruction submission register is used to describe the starting address and submission instruction length of each instruction submitted; The multi-thread priority arbitration module is used for priority arbitration among multiple threads, and the module function core executes the instructions of the thread that wins the arbitration.

5. The multi-thread control method based on the multi-thread module of ASIC as claimed in claim 1, characterized in that: The thread instructions include thread lock instructions, which are set in the thread instructions by software or compiler and are used to lock the thread where the instructions that need to be executed continuously are located. After the module function kernel parses the thread lock instruction, the internal thread priority arbitration always selects the instructions in the locked thread for the hardware kernel to execute until the thread lock is unlocked, and then arbitration according to the thread priority will be resumed.

6. The multi-thread control method based on the multi-thread module of ASIC according to claim 1, characterized in that: The thread instructions include null instructions, which are set in the thread instructions by software or a compiler and are used to implement functions that cannot be implemented by hardware by kernel software. After the module function kernel parses the null instruction, it directly suspends and issues a null instruction interrupt.

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