Neural network extension execution computer system based on RISC-V

Abstract

The invention discloses a neural network extension execution computer system based on RISC-V. The neural network extension execution computer system comprises an RISC-V processor based on an out-of-order execution system structure, a neural network hardware accelerator, an instruction memory, a data memory and a dynamic scheduler. The dynamic scheduler is used for switching different working modes for the computer system according to the current calculation load, and distributing a calculation task to be executed to the RISC-V processor or the neural network hardware accelerator for execution; the working modes comprise a standard calculation mode, a neural network acceleration mode and a low power consumption mode; the computing tasks comprise a general computing task and a neural network computing task. According to the technical scheme, the intelligence of the computer system is improved, and the calculation efficiency, the resource consumption and the power consumption are well balanced.

Description

Technical Field

[0001] The present invention belongs to the technical field of intelligent computer architecture, and in particular to a RISC-V-based neural network extension execution computer system. Background Art

[0002] RISC-V (Reduced Instruction Set Computing Architecture, Fifth Generation) is an open source, modular, RISC-V architecture with scalability. Its basic instruction set includes 32-bit integer instructions (RV32I) and 64-bit integer instructions (RV64I), and its extended instruction set includes multiplication and division (RV32M), floating-point operations (RV32F), etc., and can be combined according to needs. For example, RV32IM means that it includes 32-bit integer instruction set and multiplication and division extended instructions. In addition, users can customize some RISC-V instructions according to the needs of application scenarios to speed up certain operations. As a design specification of a reduced instruction set architecture (RISC), the RISC-V instruction set defines the basic set of instructions that a computer processor can understand and execute. Therefore, a RISC-V computer processor or a RISC-V computer system is the actual hardware designed by different researchers based on the RISC-V instruction set architecture. Therefore, different design ideas and hardware architectures will bring different functions and performance to the RISC-V computer system. Moreover, some processors can customize the RISC-V instruction set for specific applications.

[0003] At present, the design of processors based on the RISC-V instruction set architecture mainly focuses on two major directions: on the one hand, low-power design, mainly for embedded applications such as mobile devices and edge computing; on the other hand, high-performance design, mainly for scenarios that require a large amount of computing resources, such as servers and artificial intelligence. Low-power design usually adopts a simplified hardware architecture, such as fewer pipeline stages and sequential execution, to reduce hardware resource overhead and meet power consumption requirements. However, such a design is weak in computing efficiency and is prone to pipeline pauses due to data conflicts, thereby wasting computing time. This makes some applications with high requirements for timeliness and computing power, such as unmanned driving and edge computing, unable to meet real-time requirements. In contrast, existing high-performance designs use complex superscalar architectures, using multi-issue and out-of-order execution technologies to improve instruction parallelism and processing efficiency. Although it can significantly improve computing power, it also leads to increased hardware resource consumption and energy consumption. In scenarios that are sensitive to power consumption and cost, such as edge computing, how to balance low power consumption with efficient computing and improve computing performance with limited hardware resources has become a challenge that needs to be solved.

[0004] In addition, as artificial intelligence gradually migrates to edge devices (such as smartphones, drones, self-driving cars, smart sensors, etc.), these devices have high real-time requirements for neural network reasoning and often cannot rely on remote data centers for calculations. Therefore, processors with integrated neural network accelerators can directly perform neural network reasoning locally, reducing dependence on cloud computing. However, the training and reasoning process of neural networks usually involves a large number of matrix operations and parallel computing tasks, which are less efficient for traditional processors (such as CPUs); and although high-performance graphics processors (GPUs) can quickly perform neural network training and reasoning, they are difficult to apply to edge devices due to their high power consumption and high cost. Summary of the invention

[0005] The technical problem to be solved by the present invention is to propose a neural network extension execution computer system based on RISC-V, which aims to improve computing efficiency and reduce power consumption by designing a set of flexible computer system hardware micro-architectures, and to have the function of neural network computing acceleration, thereby improving the versatility and flexibility of the computer system with neural network computing acceleration function, adapting to high computing requirements and power consumption sensitive scenarios such as neural network reasoning in mobile and edge scenarios, so as to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above-mentioned object, the present invention provides a RISC-V-based neural network extension execution computer system, comprising: a RISC-V processor based on an out-of-order execution architecture, a neural network hardware accelerator, an instruction memory, a data memory, and a dynamic scheduler; The dynamic scheduler is used to switch different working modes for the computer system according to the current computing load, and assign the computing tasks to be executed to the RISC-V processor or the neural network hardware accelerator for execution; the working modes include: standard computing mode, neural network acceleration mode and low power consumption mode; the computing tasks include general computing tasks and neural network computing tasks; The RISC-V processor is used to receive and decode externally input RISC-V instructions in the standard computing mode, form an instruction stream for out-of-order transmission according to the instruction type and the current computing load, and execute the general computing task and the neural network computing task by executing the RISC-V instructions in the out-of-order transmission instruction stream one by one; The neural network hardware accelerator is used to perform the neural network computing task in the neural network acceleration mode; The dynamic scheduler is further used to compile the computing task to be executed into one or more RISC-V instructions, and write the RISC-V instructions into the instruction memory for storage; The instruction memory is used to sequentially store one or more RISC-V instructions corresponding to the computing task to be executed; The data storage device is used to store interaction data transmitted between the RISC-V processor and the neural network hardware accelerator through a dedicated communication protocol; The dynamic scheduler is also used to use gated clock logic to reduce the clock flip rate of the RISC-V processor and the neural network hardware accelerator when there is no computing task or the computing load is lower than a preset value, so as to control the RISC-V processor and the neural network hardware accelerator to operate in the low power consumption mode.

[0007] Preferably, the RISC-V processor comprises in sequence: an instruction receiving unit, an instruction decoding unit, a physical register stack, an out-of-order execution unit and a write-back unit; The instruction receiving unit is used to pre-read a plurality of RISC-V instructions from the instruction memory for internal caching, and search among the pre-read plurality of RISC-V instructions whether there is a RISC-V instruction corresponding to the program counter value; if there is, output the retrieved RISC-V instruction to the instruction decoding unit; if not, access the instruction memory, search for the corresponding RISC-V instruction in the instruction memory and output it to the instruction decoding unit; The instruction decoding unit is used to parse the received RISC-V instruction, identify the register access information and data operation information carried by the RISC-V instruction, and mix and encode them into instruction identification information; The physical register file is used to store logical register data used by the RISC-V processor during execution through multiple physical registers; The out-of-order execution unit is used to classify the decoded RISC-V instructions into multiple emission queues according to instruction types, and form an instruction stream for out-of-order emission in each emission queue according to the current computing load, and execute the general computing task and the neural network computing task by out-of-order execution of the RISC-V instructions in the instruction stream; The write-back unit is used to write the execution result back to the physical register file.

[0008] Preferably, the neural network hardware accelerator comprises: A model compression unit, used to perform knowledge distillation on the convolutional neural network in the neural network computing task and compress the model parameters of the convolutional neural network; A computing unit, including a convolution operation module, a matrix multiplication module, a quantization module, an activation function module, and a pooling module, for performing forward propagation computing operations in a convolutional neural network; A storage unit, including an independent input feature map cache, a weight cache, a bias cache, an intermediate value cache, a pooling cache, an output feature map cache, and a shared cache, which is used to reduce storage access conflicts and lower data access latency through a multi-level cache system; A data flow control unit, used to control the flow of data to ensure efficient transmission of data between the computing unit and the storage unit; A communication interface is used to transmit data with the RISC-V processor, load input image data and model parameters of the convolutional neural network, and output the recognition result of the convolutional neural network.

[0009] Preferably, the convolution operation module comprises a convolution calculation array and a first addition tree, and is used to slide the convolution kernel in the input feature map, sequentially use the convolution calculation array to perform element-by-element multiplication operations in the sliding area, and accumulate the intermediate calculation results of the element-by-element multiplication operations based on the first addition tree to generate an output feature map; The matrix multiplication module includes a multiplication calculation array and a second addition tree, which are used to perform output calculations of a fully connected layer of a convolutional neural network; wherein the multiplication calculation array is used to perform multiplication operations on the connected multi-channel feature map and the corresponding point convolution kernel, and the second addition tree is used to accumulate intermediate calculation results of the multiplication calculation array.

[0010] Compared with the prior art, the technical solution provided by the present invention has the following advantages and technical effects: The RISC-V-based neural network extended execution computer system provided by the present invention can, on the one hand, improve the computing efficiency and reduce the power consumption of the overall system under the premise of maintaining efficient execution of instructions, so as to achieve a better balance between the performance and energy efficiency of the computer system; on the other hand, it takes into account the execution requirements of general computing tasks and neural network computing tasks, and can switch different working modes for the computer system based on the current computing load. When the computing load is not large and the neural network computing speed is not demanding, the computing resources in the execution unit of the RISC-V processor can be used to execute the neural network computing task; when the neural network computing speed is required to be high, a dedicated neural network hardware accelerator is called to perform hardware acceleration on the neural network computing task to meet the computing requirements of the neural network computing task. Deploying the computer system provided by the present invention on edge devices and mobile devices can not only reduce data transmission delays and meet real-time requirements, but also improve the privacy protection capabilities of the device and reduce dependence on the network. In addition, this integrated design improves the comprehensive performance of the processor when executing traditional general computing tasks and artificial intelligence (AI) tasks, and can also promote the popularization of AI applications on edge computing devices and mobile devices, bringing a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of the overall micro-architecture of an embodiment of a RISC-V-based neural network extension execution computer system provided by the present invention; Figure 2 A functional block diagram of an embodiment of a RISC-V processor based on an out-of-order execution architecture provided by the present invention; Figure 3 A principle block diagram of an embodiment of a neural network hardware accelerator provided by the present invention; Figure 4 A principle block diagram of an embodiment of a branch prediction unit of a RISC-V processor provided by the present invention; Figure 5 A principle block diagram of an embodiment of a register renaming unit provided by the present invention; Figure 6 A logical operation structure diagram of an embodiment of the priority arbitration tree provided by the present invention. DETAILED DESCRIPTION

[0012] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0013] It should be noted that the signal transmission process shown in the drawings refers to an execution process that can be performed in a computer system such as a set of computer executable instructions.

[0014] Aiming at the common characteristics of current embedded, mobile communications, Internet of Things (IoT), edge computing, smart terminals and other application scenarios, where hardware resources and energy consumption are limited but computing performance and intelligence are required to be high, this invention proposes a customized processor based on the RISC-V instruction set with high performance, low power consumption, single-issue, out-of-order execution and neural network computing acceleration function. The processor seeks the best balance between computing performance, intelligence and power consumption, aiming to provide higher instruction execution efficiency. Its core goal is to solve three key problems in the design of intelligent computer systems: first, how to improve the computing performance and task processing efficiency of the processor, increase the parallelism of instruction execution, and reduce instruction execution delay to meet the growing demand for high-speed computing; second, how to reduce the energy consumption of the processor so that it can run efficiently in an environment with limited hardware resources and energy, such as embedded and mobile devices; third, to efficiently customize dedicated hardware accelerators for neural network computing tasks, significantly improving the efficiency of neural network operations. The goal of the embodiments of the present invention is to comprehensively consider low-power design while improving the parallelism and efficiency of processor instructions, and to significantly improve the computing throughput of the neural network through innovative micro-architecture solutions, so that the computer system can select the optimal computing method and working mode according to the computing load and application needs, and better adapt to application scenarios where high-performance computing, intelligent computing and low power consumption requirements coexist.

[0015] The embodiment of the present invention proposes a flexible, intelligent, high-performance, and low-power computer system based on the RISC-V instruction set architecture, which can operate in multiple working modes, improves the instruction parallelism of the RISC-V processor to obtain higher computing performance while taking into account the low power consumption characteristics of the micro-architecture, achieves a better balance between computing efficiency and power consumption, and has a neural network computing acceleration function, which can be used for convolutional neural network computing acceleration to meet the growing needs of smart devices.

[0016] like Figure 1 As shown, a schematic diagram of a structure of a possible implementation of a RISC-V-based neural network extension execution computer system provided by the present invention is shown. Specifically, the RISC-V-based neural network extension execution computer system includes: a RISC-V processor 100 based on an out-of-order execution architecture, a neural network hardware accelerator 200, an instruction memory 300, a data memory 400, and a dynamic scheduler 500.

[0017] The dynamic scheduler 500 is used to switch different working modes for the computer system according to the current computing load, and assign the computing tasks to be executed to the RISC-V processor 100 or the neural network hardware accelerator 200 for execution; the working modes include: standard computing mode, neural network acceleration mode and low power consumption mode; the computing tasks include general computing tasks and neural network computing tasks.

[0018] The RISC-V processor 100 is used to receive and decode externally input RISC-V instructions in the standard computing mode, form an out-of-order instruction stream according to the instruction type and the current computing load, and execute the general computing task and the neural network computing task by executing the RISC-V instructions in the out-of-order instruction stream one by one.

[0019] The neural network hardware accelerator 200 is used to execute the neural network computing task in the neural network acceleration mode.

[0020] The dynamic scheduler 500 is also used to compile the computing task to be executed into one or more RISC-V instructions, and write the RISC-V instructions into the instruction memory 200 for storage.

[0021] The instruction memory 300 is used to sequentially store one or more RISC-V instructions corresponding to the computing task to be executed.

[0022] The data storage device 400 is used to store interaction data transmitted between the RISC-V processor 100 and the neural network hardware accelerator 200 via a dedicated communication protocol.

[0023] The dynamic scheduler 500 is also used to use gated clock logic to reduce the clock flip rate of the RISC-V processor 100 and the neural network hardware accelerator 200 when there is no computing task or the computing load is lower than a preset value, so as to control the RISC-V processor 100 and the neural network hardware accelerator 200 to operate in the low power consumption mode.

[0024] In the RISC-V instruction set architecture, the instruction types of its 32-bit integer instruction set RV32I mainly include register type instructions (R type instructions), immediate number instructions (I type instructions), storage instructions (S type instructions), conditional jump instructions or branch instructions (B type instructions), etc. Among them, R type instructions are mainly used to control the arithmetic and logical operations between the 32 logical registers defined by RV32I, so R type instructions are also called arithmetic and logical operation instructions; I type instructions are used to control the operations between logical registers and immediate numbers; S type instructions are mainly used to perform storage operations, write data to memory or load data from the outside; B type instructions are also called branch instructions, which are used to perform conditional branch operations and decide whether to jump according to the value of the logical register. In addition, RV32I also includes U type instructions and J type instructions, etc., which can be specifically referred to the standard definition of the RISC-V instruction set. It should be noted that the RISC-V instruction set architecture also includes the 64-bit integer instruction set RV64I, the single-precision floating point instruction set RV32F, the double-precision floating point instruction set RV64F and various extended instruction sets. For example, the multiplication and division extended instruction sets RV32IM and RV64IM, and the vector extended instruction sets RV32IMV and RV64IMV based on them. Different RISC-V processors can support different instruction sets and the corresponding hardware implementation architecture and complexity.

[0025] In an embodiment of the present invention, the designed RISC-V processor 100 can be compatible with the instruction sets RV32IFMV and RV64IFMV of floating-point operations, multiplication and division operations extensions, and vector calculation extensions on the basic integer instruction set. The instructions that the RISC-V processor 100 can process include but are not limited to arithmetic and logic operation instructions, floating-point operation instructions, branch instructions, load instructions, memory access instructions, and custom extended vector calculation instructions (for example, vector calculation instructions based on RV32V and RV64V extensions). Those skilled in the art can adaptively expand the compatible extended instructions based on the actual application scenarios and under the inspiration of the embodiments of the present invention.

[0026] Based on the above instruction architecture, the embodiment of the present invention designs a computationally efficient, low-power, intelligent out-of-order execution RISC-V processor, the hardware architecture schematic diagram of which is as follows: Figure 2 In a preferred implementation, the RISC-V processor 100 includes in sequence: an instruction receiving unit 110, an instruction decoding unit 120, a physical register stack 130, an out-of-order execution unit 140 and a write-back unit 150.

[0027] Among them, the instruction receiving unit 110 is used to pre-read a number of RISC-V instructions from the instruction memory 300 for internal caching, and search whether there is a RISC-V instruction corresponding to the program count value in the pre-read several RISC-V instructions; if so, output the retrieved RISC-V instruction to the instruction decoding unit 120; if not, access the instruction memory 300, find the corresponding RISC-V instruction in the instruction memory 300 and output it to the instruction decoding unit 120.

[0028] The instruction decoding unit 120 includes a decoder 121, which is used to parse the received RISC-V instructions, identify the register access information and data operation information carried by the RISC-V instructions, and mix and encode them into instruction identification information.

[0029] The physical register stack 130 is used to store the logical register data used by the RISC-V processor 100 during execution through multiple physical registers. In the RISC-V instruction architecture, the R-type instructions involved need to operate on the data in the register. In order to distinguish them from the physical registers implemented by hardware, these registers defined in the instruction architecture are called logical registers or general registers. Taking the RV32I basic integer instruction set architecture as an example, a total of 32 logical registers are defined, and the names are represented by x0 to x31. Among them, the x0 logical register is a constant register, and its value is always "0"; the x1-x31 logical registers can be used for general-purpose data storage (i.e., destination logical register) and data reading (i.e., source logical register). In R-type or I-type instructions, specific operations on a certain logical register have been defined. However, based on the complexity of computer programs, the compiled instructions may repeatedly read and write certain logical registers multiple times, which is easy to cause read-write conflicts. Therefore, some technical solutions are needed to realize the mapping of physical registers to logical registers to avoid the occurrence of register read-write conflicts.

[0030] The out-of-order execution unit 140 is used to classify the decoded RISC-V instructions into multiple transmission queues according to the instruction type, and form an out-of-order transmission instruction stream in each transmission queue according to the current computing load, and execute the general computing task and the neural network computing task by out-of-order execution of the RISC-V instructions in the instruction stream. The write-back unit 150 is used to write the execution result back to the physical register file 130 .

[0031] Unlike existing computer systems, the computer system provided by the embodiment of the present invention is suitable for processing a wide range of computing tasks, has strong flexibility, and can work in three modes: standard computing mode, neural network acceleration mode, and low power consumption mode. In the standard computing mode, the computer system provided by the present embodiment can perform basic arithmetic and logical operations, floating-point operations, and even neural network computing tasks relatively slowly based on the computing resources carried by the RISC-V processor itself, but the processing efficiency is usually low and the power consumption is relatively high. Therefore, in order to be compatible with the rapidly developing neural network computing needs, through the built-in neural network hardware accelerator 200, a dedicated hardware specially designed for neural network computing, by switching the neural network acceleration mode, the neural network task can be performed with lower power consumption and higher efficiency, which is particularly suitable for application scenarios with high computing performance requirements and limited power consumption, such as edge computing devices, smart phones, autonomous driving, Internet of Things devices, etc. In addition, when there is no computing task, the computer system provided by the present embodiment will start the low power consumption mode to save more energy consumption.

[0032] like Figure 3 , which is a structural block diagram of an implementation method of a neural network hardware accelerator provided by an embodiment of the present invention.

[0033] In a preferred implementation, the neural network hardware accelerator 200 includes: The model compression unit 210 is used to perform knowledge distillation on the convolutional neural network in the neural network computing task and compress the model parameters of the convolutional neural network. In the convolutional neural network, its model parameters mainly include weight values, bias values, etc. This embodiment introduces the knowledge distillation (KD) technology. By connecting a complex and powerful large model as a teacher model, the hardware neural network model deployed on the neural network hardware accelerator 200 is trained and compressed online. The knowledge and performance of the teacher model can be passed to the hardware neural network model, thereby avoiding the online deployment of a complex and computationally expensive large model. The hardware model after knowledge distillation has fewer parameters and lower computational complexity but has the knowledge of the teacher model, which makes it more efficient than the teacher model in reasoning and can accelerate the reasoning process in practical applications.

[0034] The computing unit 220 includes a convolution operation module 221, a matrix multiplication module 222, a quantization module 223, an activation function module 224 and a pooling module 225, and is used to perform forward propagation computing operations in a convolutional neural network. The forward propagation computing operation mainly refers to various operations in sequence between the input image from the neural network input to the output layer. Preferably, the convolution operation module 221 includes a convolution computing array 2211 and a first addition tree 2212, which is used to slide the convolution kernel in the input feature map, sequentially use the convolution computing array 2211 to perform element-by-element multiplication operations in the sliding area, and accumulate the intermediate calculation results of the element-by-element multiplication operations based on the first addition tree 2212 to generate an output feature map. In one achievable manner, the matrix multiplication module 222 includes a multiplication calculation array 2221 and a second addition tree 2222, which are used to perform output calculations of a fully connected layer of a convolutional neural network; wherein the multiplication calculation array 2221 is used to perform multiplication operations on the connected multi-channel feature map and the corresponding point convolution kernel, and the second addition tree 2222 is used to accumulate the intermediate calculation results of the multiplication calculation array 2221. In specific implementation, the convolution operation module 221 is mainly used for image feature extraction, which performs element-by-element multiplication and accumulation operations of the convolution kernel and the input data, focusing on spatial local information processing. The matrix multiplication module 222 is used to process matrix operations of network layers such as the fully connected layer, focusing on efficient processing of large-scale data and complex matrix calculations.

[0035] The storage unit 230 includes an independent input feature map cache 231, a weight cache 232, a bias cache 233, an intermediate value cache 234, a pooling cache 235, an output feature map cache 236, and a shared cache 237, which are used to reduce storage access conflicts and reduce data access latency through a multi-level cache system. Among them, the sizes of the input feature map cache 231, the output feature map cache 236, and the shared cache 237 can be the same, and the resources of the shared cache 237 can be combined with other caches under different model settings to obtain different storage modes. The choice of storage mode is mainly determined by the convolution mode, accelerator control signal, and feature map characteristics in the network layer configuration parameters.

[0036] The data flow control unit 240 is used to control the data flow, ensure the efficient transmission of data between the computing unit 220 and the storage unit 230, reduce the transmission delay between various cache data and the computing unit 220, and reduce power consumption. In hardware design, the access process of storage resources is often the most time-consuming and energy-consuming operation. Therefore, in the design process, the distance between the storage space and the computing resources should be shortened as much as possible, the access operation should be simplified, and the access frequency to the storage space should be reduced.

[0037] The communication interface 250 is used to transmit data with the RISC-V processor 100, load input image data and model parameters of the convolutional neural network, and output the recognition result of the convolutional neural network.

[0038] For the RISC-V processor, it plays the role of a central processing unit in the computer system provided in this embodiment. Figure 2 As shown, the low-power single-issue out-of-order execution RISC-V processor provided in this embodiment includes a five-stage pipeline architecture, which are respectively: an instruction receiving unit 110, an instruction decoding unit 120, a physical register stack 130, an out-of-order execution unit 140, and a write-back unit 150. It should be noted that the various levels of pipeline architecture provided in this embodiment can be divided into a multi-stage pipeline architecture according to the needs of the application scenario, so as to adapt to different instructions or computing efficiency needs, shorten the critical path, and increase the operating frequency of the processor.

[0039] The instruction receiving unit 110 is used to read the corresponding RISC-V instruction from the off-chip memory (i.e., the instruction memory 300) according to the output value (referred to as PC value) of the program counter (Program Counter, PC) of the current cycle. In specific implementation, the program counter is a register, and the PC value in the program counter points to the off-chip memory address of the instruction to be executed. Therefore, the PC value can be used as the read address to fetch the RISC-V instruction in the instruction memory 300. In the pipeline architecture, although the instructions are sequentially executed in each stage, when a conditional branch instruction is encountered, the execution direction or jump address of the instruction stream may change. However, in modern computer processors, the execution of programs is relatively complex, and the RISC-V instruction stream obtained by its compilation and conversion is usually not completely sequentially executed instructions, and is interspersed with some jump instructions or branch instructions. In the absence of branch predictor support, the processor must usually be informed after decoding is completed, and it is necessary to wait for at least one clock cycle, which will cause discontinuous execution and jamming of the processor, thereby causing performance degradation. Therefore, this embodiment further provides a mechanism for dynamic branch prediction of instructions, and predicts the instruction type when receiving the instruction, and predicts whether the PC value will jump to a non-continuous instruction fetch address. In a preferred implementation, in the RISC-V processor 100, its instruction receiving unit 110 includes: a dynamic branch prediction unit 111.

[0040] like Figure 4 As shown, the dynamic branch prediction unit 111 includes: a branch target cache unit 1111 , a jump history cache unit 1112 , a global history prediction register unit 1113 and a jump arbitration unit 1114 .

[0041] Specifically, the branch target cache unit 1111 is used to record the program counter value (i.e., PC value) and the jump address corresponding to the branch instruction that has jumped. The branch target cache unit 1111, as a branch target buffer (BTB), can accelerate the acquisition of the jump target address of the branch instruction. By pre-storing the jump target address of the branch instruction, the BTB allows the instruction receiving unit 110 to obtain the jump target in advance, avoiding the time of waiting for the jump target address calculation, thereby accelerating the execution of the jump instruction.

[0042] The jump history cache unit 1112 is used to record the jump direction and jump number corresponding to each program count value in the instruction execution history process; the jump direction and jump number corresponding to each program count value are updated using a saturated counter according to the jump result of the executed instruction. The jump history cache unit 1112 stores a pattern history table (PHT) for storing the historical behavior pattern of branch instructions. Each entry in the PHT stores a saturated count value, which indicates whether to jump. The PHT helps the branch predictor to infer future branch behaviors based on "similar history". For example, if a branch instruction has jumped multiple times in the past, the branch predictor will predict that it may also jump next time, and vice versa. Among them, each saturated count value in the PHT can be calculated and updated using a 2-bit wide saturated counter (SC). The value range of the 2-bit wide SC is 2-bit binary number 00~11, which is used to indicate the jump status of the corresponding instruction, corresponding to strong no jump (00), weak no jump (01), weak jump (10) and strong jump (11). Among them, when the branch actually jumps, the counter is increased by one bit (for example, 00 is updated to 01, 01 is updated to 10), indicating that the prediction confidence of the jump increases; when the branch does not actually jump, the counter is reduced by one bit (for example, 10 is updated to 01, 11 is updated to 10), indicating that the prediction confidence of no jump increases. If the saturated count value is weak jump (10) or strong jump (11), the counter remains unchanged or continues to increase, but will not exceed 11 (the update direction is 0001→10→11). If the saturated count value is weak no jump (01) or strong no jump (00), the counter remains unchanged or continues to decrease, but will not be lower than 00 (the update direction is 11→10→01→00). In this way, the saturated counter can adjust the prediction of branch jumps through historical information, especially for stable branches, which follow the jump or no jump mode for a long time, so the jump behavior of the branch is relatively regular, and the saturated counter can maintain accurate prediction by gradually increasing confidence (i.e. entering a strong jump or strong no jump state). For unstable branches, i.e. branches with irregular jump and no jump patterns, the saturated counter used in this embodiment has anti-interference ability, because it can avoid too frequent prediction changes through weak jump or weak no jump states. For example, in the case of a sudden change in branch behavior, the saturated counter will not make an incorrect prediction immediately, but will gradually adjust, so as to avoid performance loss caused by incorrect prediction. The 2-bit wide saturated counter provides higher accuracy through a moderate complexity design, while avoiding the high hardware overhead caused by a more complex prediction mechanism. Compared with more advanced prediction machines, the 2-bit wide saturated counter is a simple but effective prediction tool that can provide better performance with low overhead.The saturated count value maintained by the saturated counter is stored in the PHT. The saturated count value is obtained by addressing the PHT to predict the branch jump.

[0043] It should be noted that, in this embodiment, the access address of the jump history cache unit 1112 is indexed by the PC, but due to the hardware resource limitation of the processor, it is difficult for the PHT to cover all PC values ​​(for example, the PC value is 32 bits for the RV32I instruction architecture). Therefore, in this embodiment, only a relatively small storage space is used to implement the jump history cache unit 1112, and only a partial bit width of the PC is used to address the PHT in the jump history cache unit 1112. For example, when the storage depth of the PHT is 1024, only the lower ten bits of the PC (the 2nd to 11th bits, the minimum storage unit is 1 byte, so the 0th and 1st bits are invalid) are taken as the access address of the PHT. However, this solution will also cause the problem that multiple branch instructions can address the same entry of the PHT, which may cause the historical data of these branches to interfere with or overwrite each other, and cause the aliasing problem of the branch instruction, thereby affecting the accuracy of branch prediction. Therefore, the embodiment of the present invention designs a global history prediction register unit 1113 to increase the diversity of branch history, thereby reducing sharing and conflicts between different branch instructions, improving the accuracy of branch prediction and reducing performance loss.

[0044] like Figure 4As shown, the global history prediction register unit 1113 is used to predict the instruction jump results of several consecutive instructions after execution, and generate a global jump history prediction value. The global history prediction register unit 1113 stores the execution history of the most recent series of branch instructions in the program. The global history prediction register unit 1113 can be implemented using a shift register, and each bit of data represents the jump behavior of a branch instruction (jump or no jump). After the branch instruction is executed and retired, the global history prediction register unit 1113 will record the jump result of the instruction (the updated value is "1" for jump, and "0" for no jump). Specifically, the global history prediction register unit 1113 will shift one bit to the left when updated to provide space for a new branch execution, and its lowest bit will be set to the jump result of the branch (1 or 0). At this time, the historical information stored in the global history prediction register unit 1113 includes the execution results of all previous branches, forming a sliding window. The number of bits of the global history prediction register unit 1113 determines the length of the branch history that can be stored. The longer the history register is, the more historical information can be recorded, which may improve the accuracy of branch prediction. However, due to resource constraints, this embodiment preferably uses a global history prediction register unit 1113 with a bit width of 6 bits. In order to solve the alias problem of branch instructions, this embodiment improves the index mechanism of PHT, and does not only use PC as the index of PHT, but uses a partial PC value (for example, a local 6-bit PC value: PC[12:7]) and the output value of the global history prediction register unit 1113 to perform XOR to obtain a new PHT index.

[0045] The jump arbitration unit 1114 is used to predict and obtain the second program counter value of the current RISC-V instruction to be read according to the first program counter value of the previous RISC-V instruction, including: Performing a logical operation on the first program counter value and the global jump history prediction value to obtain an index address, querying the jump history cache unit according to the index address to determine whether the second program counter value has jumped; If the second program counter value jumps, it is determined whether the first program counter value hits any branch instruction in the branch target cache unit; if it hits, it is determined whether the hit branch instruction is a function return instruction; if it is the function return instruction, the corresponding function call target address in the return address stack (RAS) is predicted as the jump address of the second program counter value; if it is not the function return instruction, the jump address corresponding to the hit branch instruction is predicted as the jump address of the second program counter value; If the second program counter value does not jump, or if a jump occurs but the first program counter value does not hit any branch instruction in the branch target cache unit, the jump address of the second program counter value is predicted to be PC+k; wherein PC is the first program counter value and k is a user-defined constant.

[0046] The return address stack is used to process function calls and returns. By storing the return address of the function call, it helps the branch predictor to predict the target address of the function return, so that when the function returns, the instruction receiving unit 110 can quickly obtain the target address and jump.

[0047] The jump arbitration unit 1114 arbitrates from multiple possible jump addresses to obtain the jump address of the next cycle. Specifically, if the jump direction of the instruction fetched by the current PC is a jump, and the target address of the PC corresponding to the instruction exists in the BTB (that is, the BTB hits the instruction), and the instruction hit in the BTB is not a function return instruction, then the target address hit by the BTB is used as the jump address of the next cycle of the instruction; if it is a function return address, the address in the RAS is popped up as the jump address; when the instruction jump direction is predicted to be no jump, or the BTB is not hit, PC+4 is used as the jump address of the next cycle (k=4), that is, the instruction is read sequentially. The reason for selecting k=4 is that the instructions in the instruction memory 300 are stored in bytes with a bit width of 8 bits, and for the RV32IM instruction set, the width of the instruction is 32 bits, so each 4 bytes are required to fully read the information of an RV32IM instruction. Similarly, for instruction sets with other bit widths and different forms of instruction storage, the k value needs to be adaptively adjusted.

[0048] Specifically, the method steps for branch instruction jump prediction provided in this embodiment are as follows: Step S1: Read the program counter, obtain the PC value output by it, and only take part of the bit width value (for example, the 6-bit PC intermediate value PC[11:6]); Step S2: Read the global jump history prediction value P-GHR of the global history prediction register unit 1113; Step S3: Using the middle-bit width PC value, such as the middle 6-bit PC[11:6], and the 6-bit length global history prediction register unit 1113 in the global history prediction register unit 1113, perform an XOR operation to obtain the middle value and then concatenate the lower 4-bit PC[5:2] to obtain a 10-bit (corresponding to 1024 bits of PHT) index that incorporates the global jump information, that is, the PHT read address is {{PC[11:6] (XOR) P-GHR[5:0]}, PC[5:2]}. Using this index to address the PHT can effectively avoid the aliasing problem caused by the PHT size limit.

[0049] Step S4: Using the above-mentioned combined 10-bit query address, read the pattern history table (PHT) in the jump history cache unit 1112 with a depth of 1024, and determine whether the PC value corresponding to the instruction to be executed in the next cycle jumps according to the query result of the PHT: if it jumps, execute step S5; if not, execute step S6.

[0050] Step S5: Search the BTB to see if there is record information corresponding to the current PC value. If not, that is, there is no hit, execute step S6; if there is any item in the BTB that is equal to the PC of the current cycle, it means that the current PC value hits the BTB item. However, since the BTB also uses the function return instruction to record the call record of the return function, its priority is higher. Therefore, if the current PC hits the BTB item, it is necessary to execute step S7 to determine whether it is a function return instruction. The present embodiment preferably uses a 32-item fully associative cache to form the BTB, and any cache block can be stored at any position in the cache without being restricted by the address.

[0051] Step S6: Predict the PC value of the next cycle as PC+k. In this embodiment, if there is a miss in PHT and BTB, the current PC value is predicted as "no jump", that is, direct sequential fetch. For RV32I, the PC is incremented by k=4 each time.

[0052] Step S7: Determine whether the instruction of the BTB hit by the current PC is a function return instruction; if not, execute step S8; if yes, execute step S9.

[0053] Step S8: Use the target address recorded in the BTB corresponding to the hit item as the jump address of the current PC, that is, obtain the predicted value of the next PC.

[0054] Step S9: Pop the corresponding function return address in RAS and pop it from the stack as the prediction result.

[0055] The processor will select the instruction address to be read in the next cycle according to the prediction result of the dynamic branch prediction unit 111. Branch prediction provides input for speculative execution, determines the branch path in advance and starts execution, which can improve pipeline throughput, reduce pauses caused by branch delays, maintain efficient operation of the pipeline, and greatly improve the parallelism and execution efficiency of the processor, so that the processor of the embodiment of the present invention can reduce the potential performance bottleneck caused by branch instructions while maintaining high performance. This embodiment can complete the access to PHT and BTB within one clock cycle, that is, the prediction result can be obtained within one clock cycle, achieving the effect of fast prediction and preventing the further deepening of the micro-architecture pipeline.

[0056] The dynamic branch prediction unit 111 of this embodiment predicts whether the instruction fetch address will jump based on the historical information of the branch (such as branch history, global history, etc.). For example, based on the previous branch execution situation (jump or not jump), it is predicted whether the current branch will jump. In addition to predicting the jump direction of whether to jump, the dynamic branch prediction unit 111 of this embodiment also predicts the target address of the jump. Based on the dynamic branch prediction unit 111, this embodiment adopts the technical solution of speculative execution to improve the throughput of instructions. When encountering a conditional branch, the processor will determine in advance whether the branch will jump according to the dynamic branch prediction unit 111, and try to execute the instructions on the branch path in advance.

[0057] After fetching the instruction corresponding to the current PC value, the PC value of the next cycle is predicted by the dynamic branch prediction unit 111 as the read address of the next instruction. The RISC-V instructions to be executed are stored outside the RISC-V processor, which helps to reduce the hardware resource consumption and chip area of ​​the RISC-V processor itself; but there is usually an additional off-chip read delay as a cost. Therefore, in order to reduce the time required for instruction reading and realize efficient reading of off-chip stored instructions, the embodiment of the present invention further sets an instruction prefetch unit 112 and an instruction query unit 113 in the instruction receiving unit 110.

[0058] Furthermore, if Figure 2 As shown, the instruction receiving unit 110 further includes an instruction pre-fetching unit 112 and an instruction querying unit 113 .

[0059] The instruction prefetch unit 112 is used to access the instruction memory 300 through a dedicated bus interface according to the first program counter value, and read the RISC-V instruction corresponding to the first program counter value and several adjacent RISC-V instructions from the instruction memory 300 for caching.

[0060] The instruction query unit 113 is used to query whether there is a RISC-V instruction corresponding to the second program counter value output by the dynamic branch prediction unit 111 in the instruction prefetch unit 112; if so, output the corresponding RISC-V instruction in the instruction prefetch unit 112 to the instruction decoding unit 120; if not, search for the RISC-V instruction corresponding to the second program counter value in the instruction memory 300 and output it to the instruction decoding unit 120.

[0061] The instruction prefetch unit 112 can speed up the reading speed of instructions by storing commonly used instructions and reduce the time for the RISC-V processor to access the computer system memory. When the processor executes a software program, the instructions must be loaded from the instruction memory 300, but the access speed of the memory is slow. By caching copies of some commonly used instructions in the instruction prefetch unit 112, the instruction receiving unit 110 can read instructions from the cache of the instruction prefetch unit 112 faster, avoiding obtaining them from the computer's main memory (off-chip storage for RISC-V processors) every time. Specifically, when the instruction query unit 113 obtains the address of the current instruction from the PC, it will first send a request to the instruction prefetch unit 112 to read the instruction. The instruction prefetch unit 112 will first check whether the requested instruction is already stored in the cache. If it exists, it is a "cache hit", and if it does not exist, it is a "cache miss". When the cache hits, the instruction receiving unit 110 directly reads the instruction from the cache of the instruction prefetch unit 112, skipping the step of accessing the main memory instruction memory 300, which greatly improves the instruction reading speed. When the cache misses, the instruction receiving unit 110 accesses the instruction memory 300 through the cache bus and the AXI interface to read the corresponding RISC-V instruction, and reads and caches the RISC-V instruction corresponding to the current read address of the instruction memory 300 and multiple adjacent instructions into the instruction prefetch unit 112, so as to facilitate the subsequent PC's fast access and instruction reading. The energy consumption required for the instruction receiving unit 110 to access the instruction prefetch unit 112 is much less than that of accessing the off-chip instruction memory 300, and this strategy helps to reduce the number of accesses to the instruction memory 300, thereby helping to save the overall power consumption of the processor microarchitecture.

[0062] Furthermore, if Figure 2 As shown, the instruction decoding unit 120 also includes a register renaming unit 122, which is used to dynamically map the logical registers contained in the RISC-V instruction set to the corresponding physical registers in the physical register stack 130, and generate register access control information for preventing read and write conflicts in the register data path; the logical registers include destination logical registers and source logical registers.

[0063] Among them, the architecture of a preferred implementation of the register renaming unit provided in this embodiment is as follows: Figure 5 The register renaming unit 122 includes: a physical register free table 1221 , a predictive renaming mapping table 1222 , a physical register ready table 1223 and a register allocation circuit 1224 .

[0064] Specifically, the physical register free table 1221 is used to mark the free state of each physical register. In specific implementation, a flag bit can be set for the physical register free table 1221 to indicate whether the physical register can be used for the renamed allocation: when the corresponding physical register flag bit in the physical register free table is "1", it indicates that the physical register is in the free state and can be used for the renamed allocation; when the flag bit is "0", it indicates that the physical register is occupied and cannot be used for the renamed allocation.

[0065] The predicted renaming mapping table 1222 is used to record the dynamic mapping relationship between logical registers and physical registers. The predicted renaming mapping table 1222 can query and update the mapping relationship between logical registers and physical registers. When it is necessary to execute a write register, when the register allocation circuit 1224 allocates an idle physical register to the destination logical register of the instruction, the allocation information will be written into the predicted renaming mapping table 1222, that is, the mapping relationship between the logical register and the physical register in the predicted renaming mapping table 1222 is updated. When the instruction needs to read the register, the two source logical registers of the instruction entering the renaming stage need to query the corresponding physical registers by reading the predicted renaming mapping table 1222, and the instruction will use the queried physical register as the access entry address of the physical register stack 130 to read the data in the corresponding physical register.

[0066] The physical register ready table 1223 is used to mark the data ready status of each physical register.

[0067] The register allocation circuit 1224 is used to detect whether the physical register free table 1221 is available when decoding and obtaining the destination logical register to be written of the RISC-V instruction; if not, wait for the release of any physical register; if so, select a free physical register in the physical register free table 1221 through the priority arbitration tree 1225, allocate it as the destination physical register to the destination logical register to be written, and update the mapping relationship between the corresponding logical register and the physical register in the predicted renaming mapping table 1222.

[0068] The register allocation circuit 1224 is also used to find out the corresponding physical register as the source physical register in the predicted renaming mapping table 1222 when decoding and obtaining the source logical register to be read of the RISC-V instruction, and find out the data ready status of the corresponding source physical register in the physical register ready table 1223.

[0069] The register allocation circuit 1224 is also used to integrate the idle destination physical registers, source physical registers and data ready status of the source physical registers associated with the current RISC-V instruction into the register access control information.

[0070] The register renaming unit 122 allocates physical registers to the logical registers in the RISC-V instructions, so that the operation of each instruction can be performed independently, improving the parallelism of instruction execution and avoiding register data conflicts. The physical register does not directly correspond to the logical register converted into an instruction in the software program, but is a specific hardware resource used to store data in the processor. The setting of the register renaming unit 122 takes into account the following possible data conflicts: in a program, multiple instructions may read or write the same logical register, including WAR (read before write) data dependency and WAW (write after write) data dependency. Specifically, WAR data dependency means that in the program, two instructions need to read the same register first and then write it, and the write operation of the second instruction depends on the read operation of the first instruction. However, due to the circuit structure design and the limited number of logical registers in the RISC-V instruction set, the data may be rewritten first in the pipeline because the second instruction is executed first, that is, the data of the register is written first and then read, resulting in incorrect data writing, which will cause WAR data conflicts. WAW means that two instructions attempt to write to the same register or storage location, but their execution order is not correct, resulting in the later executed write operation overwriting the earlier executed write operation, thus causing a conflict. Given the limitations of the number of logical registers in the RISC-V instruction set (for example, the RV32I basic instruction set only defines 32 logical registers), data conflicts between WAW and WAR are prone to occur more frequently in the program. In order to solve the data dependency problem caused by register resource conflicts, this embodiment introduces a new independently designed register renaming technology. This technology avoids competition between different instructions for the same logical register by using more physical registers than the number of logical registers and dynamically mapping the logical registers of each instruction to different physical registers.

[0071] Preferably, in this embodiment, the logical registers in the instruction set are renamed by adopting a doubling of physical registers. For example, 64 physical registers are used to rename the 32 logical registers defined by RV32I. Specifically, the 32 logical registers defined by RV32I are dynamically mapped to 64 physical registers, and the processor can eliminate WAW and WAR conflicts without adding too much hardware overhead, enhance instruction parallelism, and improve the execution efficiency of the processor, thereby improving the overall performance. Experiments have shown that the doubling of physical registers is sufficient in this embodiment to rename the logical registers defined by the instruction set, avoiding possible WAW or WAR conflicts, without consuming too many register resources.

[0072] In specific implementation, in order to quickly arbitrate an idle physical register in the register renaming unit 122 to map the destination logical register required to perform a write operation in the instruction, this embodiment provides a preferred priority arbitration tree implementation structure.

[0073] Figure 6 It is a design principle diagram of an embodiment of a priority arbitration tree provided by the present invention.

[0074] In a preferred implementation, the priority arbitration tree 1225 is a comparison selection merging arbiter with fixed low-order priority. The comparison selection merging arbiter includes: a plurality of one-bit comparators (MAX), and a plurality of two-to-one multiplexers (MUX) corresponding one to one with the one-bit comparator (MAX). A one-bit comparator means that the bit width of the input signal for comparison is 1 bit, and it is a dual-input comparator. The two input signals of the two-to-one multiplexer (MUX) are the numbers of physical registers, and their values ​​can be any value from 0 to n-1 (n>1), so the bit width of its input signal can be multiple bits.

[0075] The multiple one-bit comparators form a binary tree structure, which is used to compare the idle states of all physical registers in the physical register idle table 1221 in pairs; if each physical register is idle, its idle state is marked as "1", and if it is not idle, its idle state is marked as "0".

[0076] Each of the one-bit comparators is a maximum value comparator, and when the idle states of the input physical registers are compared pairwise: if the idle states of the two input physical registers are different or the idle states of the two input physical registers are both idle, the comparison result of the current one-bit comparator is "1"; if the idle states of the two input physical registers are both non-idle, the comparison result of the current one-bit comparator is "0".

[0077] The multiple two-to-one multiplexers form a binary tree structure, which is used to filter out the first idle physical register in the physical register file in the order of numbering from low to high.

[0078] Each of the two-to-one multiplexers is used to use the comparison result of the corresponding one-bit comparator as a selection signal to screen out the physical registers with corresponding numbers, including: if the comparison result of the current one-bit comparator is "1", then determine whether the idle states of the two physical registers connected to the current one-bit comparator are the same; if they are different, select the physical register number whose idle state is marked as "1" as the input of the next level of two-to-one multiplexer; if they are the same, then use the physical register number at a lower position as the input of the next level of two-to-one multiplexer; if the comparison result of the current one-bit comparator is "0", then use the physical register number at a higher position as the input of the next level of two-to-one multiplexer.

[0079] The comparison selection merging arbiter is used to select the idle physical register with the corresponding number as the destination physical register of the current RISC-V instruction when the comparison result of the one-bit comparator at the top of the tree is "1".

[0080] The arbitration logic of the priority arbitration tree 1225 is to use multiple groups of MAX and MUX with fixed low bits as the priority for pairwise comparison and result transmission. The input data of the priority arbitration tree 1225 is two groups of information, one of which is the idle state of each physical register saved in the physical register idle table 1221, which can be expressed in binary sequence R0~R n-1 Indicates the idle state of the physical register of the corresponding bit. When idle, the corresponding bit is "1", and when not idle, the corresponding bit is "0". The other group is the corresponding physical register number I0~I in the physical register stack. n-1 , when there are more than two physical registers, they are numbered I0~I n-1 An integer fixed-point value.

[0081] The physical register release mechanism of this embodiment is as follows: when an instruction writes to a logical register, before the next time the logical register is written, the value of the register may be read, so the mapping of the logical register to the physical register must be retained (that is, the idle state of the physical register is not idle). The corresponding physical register can only be released when the subsequent instructions that read this value have been completed. Therefore, in addition to overwriting the mapping of the logical register to the physical register, the original physical register (that is, the previous destination physical register) must also be recorded. When the instruction retires in the ROB, it means that all instructions that may have previously relied on this physical register have been completed. At this time, the original physical register can be released, that is, the physical register is set to "1" at the corresponding position of the physical register idle table 1221.

[0082] It should be noted that if the comparison result of the one-bit comparator at the top of the tree is "0", it means that there is no free physical register at present. However, this situation where all registers are occupied can be overcome in this embodiment. Since the number of physical registers is at least twice that of logical registers, at least one write-destination logical register can be mapped to two physical registers. At this time, if you want to write to the same destination logical register in the third instruction, you can overwrite the physical register mapped in the first instruction. Because when the second instruction is executed, the first instruction has been executed. Therefore, when the third instruction is executed, the write-destination physical register mapped by the first instruction is overwritten, and it will not bring erroneous data to the processor's calculation. Therefore, in this embodiment, it is only necessary to record the previous destination physical register information corresponding to the previous instruction of the currently executed instruction in the register access control information, so that when executing the next instruction, the physical register of the previous instruction can be used to write data. At the same time, it is also proved that the scheme can avoid the data read and write conflict problem of the logical register by renaming twice the number of physical registers.

[0083] In addition, relying solely on register remapping technology can eliminate WAW and WAR conflicts, but cannot eliminate RAW (write first, read later) conflicts. RAW conflict refers to the situation in which, during program execution, the next instruction needs to read the value of a register, while the value of the register has not yet been written by the previous instruction. RAW conflict essentially involves data dependency between instructions, and register renaming cannot change the dependency between data. Even if each logical register has a different physical register, when there is a RAW conflict, the next instruction still needs to wait for the write-back data after the previous instruction is executed, and data dependency still exists. Therefore, the register renaming unit 122 also needs to complete the RAW conflict between instructions. To this end, the physical register ready table 1223 proposed in the embodiment of the present invention records the ready state of each physical register, and completes the detection of data dependency by querying the ready state of the instruction physical register. Specifically, when the instruction completes register renaming, a new physical register will be assigned. If the new physical register has not been written back by the out-of-order execution unit 140, and the subsequent instruction needs to read the physical register, a RAW conflict will occur, that is, the physical register is in an unready state. The corresponding flag position of the physical register in the physical register ready table 1223 is "0". When a physical register is executed and written back by an instruction, the corresponding flag position of the physical register in the physical register ready table 1223 is "1". When the subsequent instruction needs to read the physical register again, no RAW conflict will occur, and the correct result can be read. The instruction obtains the ready status of the source physical register of the instruction by querying the physical register ready table 1223. If there is a physical register in the unready state, it indicates that the instruction has data dependency and needs to wait for the data dependency to be released, that is, it needs to wait for the instruction to be executed and written back to the physical register until all the physical registers of the instruction become ready.

[0084] It is worth noting that since the dynamic branch prediction unit 111 determines in advance whether the input instruction jumps, its branch judgment result is "speculative". If the speculation is correct, then these instructions will continue to be executed; if the speculation is wrong, then all instructions in the pipeline that were speculatively executed before the wrong instruction need to be revoked, that is, recovery from branch prediction failure is required. The RISC-V processor provided in this embodiment has complete branch prediction and branch prediction failure recovery functions.

[0085] like Figure 4 As shown, further, the dynamic branch prediction unit 111 also includes: a global history register 1115, which is used to record the actual jump history of several RISC-V instructions after execution.

[0086] like Figure 5As shown, the register renaming unit 122 is also provided with: a physical register free table checkpoint 1226 and an architecture renaming mapping table 1227. The physical register free table checkpoint 1226 is used to assign a branch number to the current RISC-V instruction when the current RISC-V instruction is a branch instruction, and to back up the physical register free table 1221; the architecture renaming mapping table 1227 is used to record the mapping relationship between each logical register and the physical register when the previous RISC-V instruction is executed. For branch instructions, it is necessary to complete the backup of the physical register free table checkpoint 1226 first. When it enters the register renaming unit 122, the physical register free table checkpoint 1226 will generate a branch number, and use the checkpoint content corresponding to the branch number to back up the current physical register free table 1221. For all RISC-V instructions, it is necessary to complete the dynamic mapping of logical registers to physical registers.

[0087] The write-back unit 150 includes: a branch prediction failure recovery logic 151 .

[0088] The branch prediction failure recovery logic 151 is used to overwrite the data of the global history register 1115 to the global history prediction register unit 1113 when the dynamic branch prediction unit 111 incorrectly predicts the jump address of the second program counter value, overwrite the data of the corresponding numbered physical register free table checkpoint 1226 to the physical register free table 1221, and overwrite the data of the architecture rename mapping table 1227 to the prediction rename mapping table 1222.

[0089] The global history register can be referred to as GHR for short. The update node setting of GHR is particularly important. GHR can be updated according to the result of branch prediction in the pipeline instruction receiving stage, or it can be updated after calculating the jump direction of the branch instruction in the execution stage, or it can be updated in the final write-back retirement stage of the pipeline. However, when the pipeline architecture of the RISC-V processor is deep, if the solution of updating GHR when the instruction is executed or retired is adopted, it may cause many subsequent instructions to enter the pipeline and fail to benefit from the result of the branch instruction updating GHR; if the solution of updating in the instruction receiving stage is adopted, the instructions after the branch instruction may be in the speculation path, and updating GHR before these instructions retire may cause data errors.

[0090] Therefore, the present invention sets a global history pairing update scheme, and sets a global history prediction register unit 1113 and a global history register 1115 at the same time, wherein the storage data of the global history prediction register unit 1113 is updated by the prediction result of the dynamic branch prediction unit 111 in the instruction receiving stage, and the storage data of the global history register 1115 is updated by the branch prediction failure recovery logic 151 in the retirement write-back stage after the instruction is executed. Therefore, the global history register 1115 does not participate in branch prediction, and the storage data therein is truly accurate global history jump information. Therefore, the storage data of the global history register 1115 can be used to realize the recovery of the storage data of the global history prediction register unit 1113 when a branch prediction failure occurs. Specifically, when a branch prediction failure occurs, by overwriting all the data stored in the global history register 1115 into the global history prediction register unit 1113, all instructions on the wrong path are cleared, and the global history prediction register unit 1113 is restored to the correct state of the previous cycle, and the recovery time is only one clock cycle, thereby realizing the rapid recovery of the global history prediction.

[0091] Similarly, various mapping information in the register renaming unit 122 can be backed up in real time first. When a branch prediction fails, the backup information is used to restore the data of the physical register free table 1221 and the predicted renaming mapping table 1222 in the register renaming unit 122 to the state after the execution of the last instruction that did not predict a failure, so as to realize the data rollback of the physical register free table 1221 and the predicted renaming mapping table 1222. The rollback operation consumes only one clock cycle, thereby completing the fast state recovery of the renaming mapping table. Since the state recovery of this embodiment is only performed when the instruction is submitted, all instructions are on the wrong path before the instruction is submitted. Therefore, the physical register ready table of this embodiment only needs to perform a full refresh (flush) operation, and all bits are reset to complete the recovery. No additional resource consumption is required, and the refresh operation only needs one clock cycle to complete, which reduces the time cost required to restore the processor state after a branch prediction failure occurs, improves the performance of the kernel, and reduces the power consumption of the processor state recovery.

[0092] In summary, the dynamic branch prediction unit 111 provided in the embodiment of the present invention adopts a two-level adaptive structure. The first level records the global branch jump information of the program through the global history prediction register unit 1113, and the second level is composed of PHT, BTB, and RAS. The current instruction PC value is obtained by integrating the global branch history information of the first level, and the branch jump direction and address are predicted in the second level through the cooperation of PHT, BTB, and RAS. The dynamic branch prediction unit 111 with a two-level adaptive structure provided in this embodiment can complete the prediction of the current instruction within one clock cycle, quickly obtain jump information and use it for speculative execution. The use of this fast branch prediction structure can effectively balance the accuracy and complexity of the branch predictor, achieve more accurate branch prediction with less resource consumption, and balance the power consumption and performance of the overall micro-architecture.

[0093] Furthermore, in a preferred implementation, the out-of-order execution unit 140 includes: an instruction issuing unit 141 , an arithmetic logic unit 142 , a floating point operation unit 143 , a load memory access unit 144 , and a vector processing unit 145 .

[0094] Among them, the instruction emission unit 141 is used to determine whether the decoded RISC-V instruction is ready to be emitted, and distribute the RISC-V instruction ready to be emitted to one of the emission queues according to its instruction type; the RISC-V instructions in each emission queue are sorted by age, and the oldest RISC-V instruction in each emission queue is arbitrated for parallel emission. If all the source physical registers associated with the current instruction are awakened, the current RISC-V instruction is determined to be ready to be emitted. The instruction emission unit 141 receives and temporarily stores the renamed instructions, and emits the ready instructions to the corresponding computing unit in the instruction out-of-order execution unit 140 for execution. Therefore, according to the instruction type, the instruction emission unit 141 can allocate various instructions to be executed to the distributed parallel emission architecture to form corresponding emission queues. Multiple parallel emission queues will receive instructions from the instruction decoding unit 120 after decoding and renaming, and monitor the readiness of the instructions. Unready instructions need to wait for awakening, and ready instructions wait for the oldest instruction to be arbitrated and emit it to the corresponding computing unit in the out-of-order execution unit 140 for execution. The computing unit includes an arithmetic logic unit 142 , a floating point operation unit 143 , a load memory access unit 144 and a vector processing unit 145 .

[0095] In specific implementation, the arithmetic logic unit 142 is used to receive and execute the arithmetic logic operation instructions emitted by the instruction emission unit 141; the arithmetic logic operation instructions are fixed-point operation instructions. The arithmetic logic unit 142 is mainly responsible for performing arithmetic addition and subtraction, logical AND or NOT, shift and comparison operations. Some branch operation instructions, including calculation of the branch jump address of the branch instruction and calculation to determine whether the branch prediction is correct, as well as the multiplier and divider can be deployed in the arithmetic logic unit 142 in this embodiment for implementation.

[0096] The floating-point operation unit 143 is used to receive and execute the floating-point operation instructions issued by the instruction issuing unit 141 .

[0097] The load memory access unit 144 is used to receive and execute the load instruction or memory access instruction issued by the instruction issuing unit 141 to load or store external data. The load memory access unit 144 calculates the effective memory access target address based on the register, immediate value, offset and other information in the instruction, and sends the address to the load queue and the store queue to ensure that the data is read or written from the correct memory location.

[0098] The vector processing unit 145 is used to receive and execute the custom extended vector calculation instructions issued by the instruction issuing unit 141 to implement the vector operation and matrix operation in the neural network calculation task. The RISC-V instruction set includes extended instructions dedicated to vectorized computing (RVV instruction set for short) to support large-scale data parallel computing. Therefore, the RISC-V processor provided in this embodiment is designed with a vector processing unit 145 that can execute RVV instructions in the out-of-order execution unit 140 according to the definition of the RVV instruction set, which is used to call the RISC-V processor's own hardware resources to perform intensive computing tasks such as matrix operations, so as to call its own computing resources to implement computing tasks for applications such as image processing and machine learning, and optimize the parallel processing of multiple data elements. The vector processing unit 145 can use vector registers connected by a multi-stage pipeline architecture to store multiple data elements for parallel operations, thereby improving the instruction throughput and the parallel processing capability of the processor.

[0099] The out-of-order execution unit 140 executes the corresponding instruction operation according to the decoding result of the instruction to obtain the execution result. The execution result will be written back to the physical register stack 130 by the write-back unit 150. A first-in-first-out reorder cache (ROB) is set in the write-back unit 150 to realize the detection and recovery processing of accurate exceptions and branch prediction failures of the RISC-V processor. In this embodiment, the state of the physical register stack is consistent with the result of sequential execution by setting the ROB. Each ROB item records the state of the instruction, the destination logical register, the destination physical register and the previous destination physical register. The ROB will check the instruction at the head of the queue. If it has been executed and there is no exception, the result can be made effective and the instruction can be deleted from the head of the queue, and the subsequent instructions can be checked. When the instruction decoding unit 120 decodes an instruction, the instruction will be inserted into the tail of the ROB, and the status will be updated as the instruction is executed. When an abnormal instruction is encountered, the instructions in the emission queue, the intermediate data of the emission and execution process are cleared, and the execution is re-started from the exception handling address.

[0100] In addition, in order to reduce the overall power consumption of the system, this embodiment is equipped with a low-power working mode for the computer system. By comprehensively using a variety of technical means such as gated clock, input gating and glitch optimization, the power consumption of the overall core is successfully reduced while ensuring the efficient execution of the computer system, so that a better balance is achieved between computing performance and energy efficiency. For example, an input gating circuit design mechanism can be adopted in the out-of-order execution unit 140, that is, by controlling whether the operand of the instruction can enter each computing unit in the out-of-order execution unit 140, thereby affecting the function and behavior of the circuit. In a specific implementation, when the gating signal is high, the operand of the instruction is valid, and the input signal can enter the circuit through the gating gate; when the gating signal is low, the operand of the instruction is invalid, and the input signal will be blocked or shielded. The circuit module only needs to work when the current operand is valid, which reduces the unnecessary flipping of the functional unit in the out-of-order execution unit 140 and effectively reduces the power consumption of the execution unit. The design of each pipeline stage of the RISC-V processor 100 not only pursues performance improvement, but also focuses on achieving low power consumption. This embodiment adopts a balanced design strategy, which not only ensures the normal implementation of functions, but also simplifies the logical structure and reduces unnecessary changes in the data path, thereby achieving a more ideal balance between performance and power consumption of the overall computer system.

[0101] In addition, the computer system in this embodiment also integrates a neural network hardware accelerator, which optimizes the implementation of neural network computing operations such as matrix multiplication, convolution operations, and activation functions. For neural network computing tasks, it can obtain higher execution efficiency than the RISC-V processor, greatly improve computing throughput, and significantly reduce reasoning time, making edge real-time applications such as autonomous driving, speech recognition, and video analysis possible. In this embodiment, neural network computing tasks can be executed on both RISC-V processors and dedicated neural network hardware accelerators, and are specifically set according to the needs of actual application scenarios and specific operating load conditions.

[0102] The computer system core micro-architecture of the present invention has completed prototype verification on an FPGA of model XC7Z020CLG400-2, and the Coremark benchmark program has been run on the FPGA platform. In addition, the operating frequency, power consumption and area of ​​the system core have been further evaluated on a 40-nanometer CMOS integrated circuit process library. Among them, the RISC-V processor can run stably on the XC7Z020CLG400-2 chip at a maximum frequency of 95MHz, and the benchmark program report has reached 3.6Coremark / MHz, which is better than most sequentially executed computer cores. Under the 40nm CMOS integrated circuit process, after comprehensive optimization, the maximum operating frequency of the computer core is increased to 555.56MHz, the normalized dynamic power consumption is only 17.19μW / MHz, and the chip area is 0.081mm². Compared with other embedded computer cores, the processor core of the present invention shows significant advantages in frequency and power consumption, which is attributed to the low-power dynamic scheduling scheme, optimized circuit configuration and a series of low-power design methods for micro-architecture. Experimental results show that the low-power computer system designed by the present invention has excellent performance and power consumption, and is particularly suitable for application scenarios with high computing requirements and power consumption sensitivity.

[0103] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A RISC-V-based neural network extension execution computer system, characterized in that: include: RISC-V processor based on out-of-order execution architecture, neural network hardware accelerator, instruction memory, data memory and dynamic scheduler; The dynamic scheduler is used to switch different working modes for the computer system according to the current computing load, and assign the computing tasks to be executed to the RISC-V processor or the neural network hardware accelerator for execution; the working modes include: standard computing mode, neural network acceleration mode and low power consumption mode; the computing tasks include general computing tasks and neural network computing tasks; The RISC-V processor is used to receive and decode externally input RISC-V instructions in the standard computing mode, form an instruction stream for out-of-order transmission according to the instruction type and the current computing load, and execute the general computing task and the neural network computing task by executing the RISC-V instructions in the out-of-order transmission instruction stream one by one; The neural network hardware accelerator is used to perform the neural network computing task in the neural network acceleration mode; The dynamic scheduler is further used to compile the computing task to be executed into one or more RISC-V instructions, and write the RISC-V instructions into the instruction memory for storage; The instruction memory is used to sequentially store one or more RISC-V instructions corresponding to the computing task to be executed; The data storage device is used to store interaction data transmitted between the RISC-V processor and the neural network hardware accelerator through a dedicated communication protocol; The dynamic scheduler is also used to use gated clock logic to reduce the clock flip rate of the RISC-V processor and the neural network hardware accelerator when there is no computing task or the computing load is lower than a preset value, so as to control the RISC-V processor and the neural network hardware accelerator to operate in the low power consumption mode.

2. The RISC-V-based neural network extension execution computer system according to claim 1, characterized in that: The RISC-V processor includes in sequence: an instruction receiving unit, an instruction decoding unit, a physical register stack, an out-of-order execution unit and a write-back unit; The instruction receiving unit is used to pre-read a plurality of RISC-V instructions from the instruction memory for internal caching, and search among the pre-read plurality of RISC-V instructions whether there is a RISC-V instruction corresponding to the program counter value; if there is, output the retrieved RISC-V instruction to the instruction decoding unit; if not, access the instruction memory, search for the corresponding RISC-V instruction in the instruction memory and output it to the instruction decoding unit; The instruction decoding unit includes a decoder for parsing the received RISC-V instruction, identifying the register access information and data operation information carried by the RISC-V instruction, and encoding the mixed information into instruction identification information; The physical register file is used to store logical register data used by the RISC-V processor during execution through multiple physical registers; The out-of-order execution unit is used to classify the decoded RISC-V instructions into multiple emission queues according to instruction types, and form an instruction stream for out-of-order emission in each emission queue according to the current computing load, and execute the general computing task and the neural network computing task by out-of-order execution of the RISC-V instructions in the instruction stream; The write-back unit is used to write the execution result back to the physical register file.

3. The RISC-V-based neural network extension execution computer system according to claim 2, characterized in that: The out-of-order execution unit comprises: The instruction emission unit is used to determine whether the decoded RISC-V instruction is ready to be emitted, and distribute the ready-to-emit RISC-V instruction to one of the emission queues according to its instruction type; sort the RISC-V instructions in each emission queue by age, and arbitrate the oldest RISC-V instruction in each emission queue for parallel emission; an arithmetic logic unit, configured to receive and execute an arithmetic logic operation instruction issued by the instruction issuing unit; the arithmetic logic operation instruction is a fixed-point operation instruction; A floating-point operation unit, used for receiving and executing the floating-point operation instruction issued by the instruction issuing unit; a load and memory access unit, configured to receive and execute a load instruction or a memory access instruction issued by the instruction issuing unit, so as to load or store external data; and The vector processing unit is used to receive and execute the custom extended vector calculation instructions emitted by the instruction emission unit to realize the vector operation and matrix operation in the neural network calculation task.

4. The RISC-V-based neural network extension execution computer system according to claim 2, characterized in that: The instruction receiving unit includes: a dynamic branch prediction unit; The dynamic branch prediction unit comprises: A branch target cache unit, used to record the program counter value and jump address corresponding to the branch instruction that has jumped; A jump history cache unit, used to record the jump direction and jump number corresponding to each program count value in the instruction execution history process; the jump direction and jump number corresponding to each program count value are updated using a saturated counter according to the jump result of the executed instruction; A global history prediction register unit is used to predict the instruction jump results of a number of consecutive instructions after they are executed, and generate a global jump history prediction value; A jump arbitration unit, used to predict and obtain a second program counter value of a current RISC-V instruction to be read according to a first program counter value of a previous RISC-V instruction, comprising: Performing a logical operation on the first program counter value and the global jump history prediction value to obtain an index address, querying the jump history cache unit according to the index address to determine whether the second program counter value has jumped; If the second program counter value jumps, it is determined whether the first program counter value hits any branch instruction in the branch target cache unit; if it hits, it is determined whether the hit branch instruction is a function return instruction; if it is the function return instruction, the corresponding function call target address in the return address stack is predicted as the jump address of the second program counter value; if it is not the function return instruction, the jump address corresponding to the hit branch instruction is predicted as the jump address of the second program counter value; If the second program counter value does not jump, or if a jump occurs but the first program counter value does not hit any branch instruction in the branch target cache unit, the jump address of the second program counter value is predicted to be PC+k; wherein PC is the first program counter value and k is a user-defined constant.

5. The RISC-V-based neural network extension execution computer system according to claim 4, characterized in that: The instruction receiving unit also includes an instruction pre-fetching unit and an instruction querying unit; The instruction prefetch unit is used to access the instruction memory through a dedicated bus interface according to the first program counter value, and read the RISC-V instruction corresponding to the first program counter value and several adjacent RISC-V instructions from the instruction memory for caching; The instruction query unit is used to query whether there is a RISC-V instruction corresponding to the second program counter value output by the dynamic branch prediction unit in the instruction prefetch unit; if so, output the corresponding RISC-V instruction in the instruction prefetch unit to the instruction decoding unit; if not, search for the RISC-V instruction corresponding to the second program counter value in the instruction memory and output it to the instruction decoding unit.

6. The RISC-V-based neural network extension execution computer system according to claim 4, characterized in that: The instruction decoding unit also includes a register renaming unit, which is used to dynamically map the logical registers included in the RISC-V instruction set to the corresponding physical registers in the physical register stack, and generate register access control information for preventing read and write conflicts in the register data path; the logical registers include a destination logical register and a source logical register; The register renaming unit includes: a physical register free table, a prediction renaming mapping table, a physical register ready table and a register allocation circuit; The physical register idle table is used to mark the idle state of each physical register; The predicted renaming mapping table is used to record the dynamic mapping relationship between logical registers and physical registers; The physical register ready table is used to mark the data ready state of each physical register; The register allocation circuit is used to detect whether the physical register free table is available when decoding and obtaining the destination logical register to be written of the RISC-V instruction; if not, wait for the release of any physical register; if so, select a free physical register in the physical register free table through a priority arbitration tree, allocate it as the destination physical register to the destination logical register to be written, and update the mapping relationship between the corresponding logical register and the physical register in the prediction rename mapping table; The register allocation circuit is further used to find out the corresponding physical register as the source physical register in the prediction rename mapping table when decoding to obtain the source logical register to be read of the RISC-V instruction, and find out the data ready state of the corresponding source physical register in the physical register ready table; The register allocation circuit is also used to integrate the idle destination physical register, source physical register and data ready status of the source physical register associated with the current RISC-V instruction into the register access control information.

7. The RISC-V-based neural network extension execution computer system according to claim 6, characterized in that: The priority arbitration tree is a fixed low-order first comparison selection merging arbitrator; The comparison selection merging arbiter includes: a plurality of one-bit comparators, and a plurality of two-to-one multiplexers corresponding one to each of the one-bit comparators; The plurality of one-bit comparators form a binary tree structure, and are used to compare the idle states of all the physical registers in the physical register idle table in pairs; if each of the physical registers is idle, its idle state is marked as "1", and if it is not idle, its idle state is marked as "0"; Each of the one-bit comparators is a maximum value comparator, and when comparing the idle states of the input physical registers in pairs: if the idle states of the two input physical registers are different or the idle states of the two input physical registers are both idle, the comparison result of the current one-bit comparator is "1"; if the idle states of the two input physical registers are both non-idle, the comparison result of the current one-bit comparator is "0"; The plurality of two-to-one multiplexers form a binary tree structure, and are used to select the first free physical register in the physical register stack in the order of numbering from low to high bits; Each of the two-to-one multiplexers is used to use the comparison result of the corresponding one-bit comparator as a selection signal to screen out the physical registers with corresponding numbers, including: if the comparison result of the current one-bit comparator is "1", then determine whether the idle states of the two physical registers connected to the current one-bit comparator are the same; if they are different, select the physical register number whose idle state is marked as "1" as the input of the next level of the two-to-one multiplexer; if they are the same, then use the physical register number at the lower position as the input of the next level of the two-to-one multiplexer; if the comparison result of the current one-bit comparator is "0", then use the physical register number at the higher position as the input of the next level of the two-to-one multiplexer; The comparison selection merging arbiter is used to select the idle physical register with the corresponding number as the destination physical register of the current RISC-V instruction when the comparison result of the one-bit comparator at the top of the tree is "1".

8. The RISC-V-based neural network extension execution computer system according to claim 6, characterized in that: The dynamic branch prediction unit also includes: a global history register for recording the actual jump history of several RISC-V instructions after execution; The register renaming unit is further provided with: a physical register free table checkpoint and an architecture renaming mapping table; the physical register free table checkpoint is used to assign a branch number to the current RISC-V instruction when the current RISC-V instruction is a branch instruction, and to back up the physical register free table; the architecture renaming mapping table is used to record the mapping relationship between each logical register and the physical register when the previous RISC-V instruction is executed; The write-back unit includes: branch prediction failure recovery logic; The branch prediction failure recovery logic is used to overwrite the data of the global history register into the global history prediction register unit, overwrite the data of the corresponding numbered physical register free table checkpoint into the physical register free table, and overwrite the data of the architecture rename mapping table into the prediction rename mapping table when the dynamic branch prediction unit incorrectly predicts the jump address of the second program counter value.

9. The RISC-V-based neural network extension execution computer system according to any one of claims 1 to 8, characterized in that: The neural network hardware accelerator comprises: A model compression unit, used to perform knowledge distillation on the convolutional neural network in the neural network computing task and compress the model parameters of the convolutional neural network; A computing unit, including a convolution operation module, a matrix multiplication module, a quantization module, an activation function module, and a pooling module, for performing forward propagation computing operations in a convolutional neural network; A storage unit, including an independent input feature map cache, a weight cache, a bias cache, an intermediate value cache, a pooling cache, an output feature map cache, and a shared cache, which is used to reduce storage access conflicts and lower data access latency through a multi-level cache system; A data flow control unit, used to control the flow of data to ensure efficient transmission of data between the computing unit and the storage unit; A communication interface is used to transmit data with the RISC-V processor, load input image data and model parameters of the convolutional neural network, and output the recognition result of the convolutional neural network.

10. The RISC-V-based neural network extension execution computer system according to claim 9, characterized in that: The convolution operation module includes a convolution calculation array and a first addition tree, and is used to slide the convolution kernel in the input feature map, sequentially use the convolution calculation array to perform element-by-element multiplication operations in the sliding area, and accumulate intermediate calculation results of the element-by-element multiplication operations based on the first addition tree to generate an output feature map; The matrix multiplication module includes a multiplication calculation array and a second addition tree, which are used to perform output calculations of a fully connected layer of a convolutional neural network; wherein the multiplication calculation array is used to perform multiplication operations on the connected multi-channel feature map and the corresponding point convolution kernel, and the second addition tree is used to accumulate intermediate calculation results of the multiplication calculation array.

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