Distributed Packet Termination for Multiple Memory Integrated Circuit Systems

Abstract

The disclosed apparatus and method provide transmission line termination. The apparatus includes a homogeneous memory die stack and a memory controller. Each homogeneous memory die in the homogeneous memory die stack is serially coupled to a transmission line by wire bonding to form a transmission path. Each memory die includes an on-die termination resistor circuit connected to the transmission line. The on-die termination resistor circuit provides a minimum termination resistance. The memory controller addresses a target homogeneous memory die for operation. The memory controller enables the on-die termination resistor circuits of a plurality of homogeneous memory dies along the transmission path. The memory controller transmits a data signal for the operation to the target homogeneous memory die with the on-die termination resistor circuits of the plurality of homogeneous memory dies enabled.

Description

[0001] Cross - reference to related patents

[0002] This application claims the benefit of U.S. Patent 10,468,073, filed Dec. 29, 2017, and U.S. Patent 10,637,533, filed Sep. 28, 2018. BACKGROUND OF THE DISCLOSURE

[0003] Memory systems may transmit signals carrying data, commands, or timing information for data storage within the memory system. The signals may be transmitted along transmission paths each having an overall characteristic impedance. Within a single transmission path, different sections or segments may have their own characteristic impedance, which contributes to the overall characteristic impedance of the transmission path. Generally, it may be desirable for each of these different sections or segments to have the same characteristic impedance or as close to the same characteristic impedance as possible. Conversely, different or substantially different characteristic impedances between two or more of the different sections can result in undesirable energy reflections, leading to degradation of signal integrity and ultimately performance. In the event that impedance mismatches do occur, methods for mitigating these impedance mismatches may be desirable.

[0004] One method of addressing this problem is to use die termination at the end. However, using die termination at the end may introduce increased parasitic capacitance on input / output (IO) signals. Additionally, some proposals may require the use of electronic components specifically configured to provide electrical termination of the signal for die termination at the end. However, such proposals complicate the manufacturing, assembly, and quality control processes. Manufacturing is more efficient and less error-prone when the components (memory dies) are all uniform or have the same design and manufacture (uniform memory dies).

[0005] Accordingly, there is a need for a transmission path termination solution that can be implemented using uniform memory dies mounted on a printed circuit board. There is also a need to implement this transmission path termination solution in a manner that does not introduce a detrimental increase in parasitic capacitance on the IO signals (data signals). The claimed and disclosed embodiments address these needs. SUMMARY OF THE DISCLOSURE

[0006] The present disclosure relates to an apparatus providing transmission line termination. The disclosed embodiments include electronic components (such as memory dies and / or on-die termination resistor circuits) configured to provide a minimum termination resistance as long as the electronic components are connected to a transmission path, whether the electronic components are powered or enabled. Additionally, some embodiments include electronic components having an active resistor circuit coupled in parallel to the transmission path to manage the termination resistance.

[0007] The device includes a uniform memory die stack and a memory controller. The uniform memory die stack is coupled to a transmission line by a set of wire bonds that serially connect each uniform memory die of the uniform memory die stack to form a transmission path. Each memory die includes an on-die termination resistor circuit connected to the transmission line. The on-die termination resistor circuit provides a minimum termination resistance. The memory controller addresses a target uniform memory die for operation. The memory controller enables the on-die termination resistor circuits of a plurality of uniform memory dies along the transmission path. The memory controller transmits data signals for the operation to the target uniform memory die with the on-die termination resistor circuits enabled for the plurality of uniform memory dies.

[0008] The present disclosure further relates to a device including a memory controller that provides transmission line termination. Coupled to the transmission line by a set of wire bonds that serially connect each uniform memory die to form a transmission path. Each uniform memory die includes an on-die termination resistor circuit that is connected to the transmission line when the uniform memory die is powered on. The on-die termination resistor circuit includes a programmable resistor circuit that provides a termination resistance during transmission of a data signal to a target uniform memory die. The memory controller sends a memory command to the target uniform memory die for operation. The memory controller directs at least four uniform memory dies along the transmission path to provide a termination resistance during operation. The at least four uniform memory dies are different from the target uniform memory die. The memory controller transmits a plurality of data signals for the operation to the target uniform memory die, wherein the at least four uniform memory dies produce an effective termination resistance for the transmission path during the operation.

[0009] Finally, the present disclosure relates to a method for providing transmission line termination. A memory command is sent to a target uniform memory die for operation. Serially connected to the transmission line by wire bonds to form a transmission path. The on-die termination resistor circuits of at least four adjacent uniform memory dies along the transmission path are activated to provide an effective termination resistance that is individually lower than the minimum termination resistance of each of the on-die termination resistor circuits. The at least four uniform memory dies are different from the target uniform memory die. Data signals for the operation are transmitted to the target uniform memory die, wherein the at least four uniform memory dies provide a parallel termination resistance during the operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To easily identify the discussion of any particular element or action, the most significant digit in the reference numeral refers to the drawing number in which the element was first introduced.

[0011] Figure 1AIt is a block diagram of an example memory system.

[0012] Figure 1B It shows the storage modules of the example memory system.

[0013] Figure 1C It is a block diagram showing a hierarchical storage system.

[0014] Figure 2A It is a block diagram of an example component of the controller of the example memory system.

[0015] Figure 2B It is a block diagram of an example component of the memory die of the example memory system.

[0016] Figure 3 It is a block diagram of the structural layout of a storage controller and N uniform memory dies.

[0017] Figure 4 It is a cross-sectional side view of multiple uniform memory dies stacked and integrated as a uniform memory die stack.

[0018] Figure 5 It is a partial circuit schematic of the circuit model of a single-ended transmission line, where the storage controller transmits a single-ended signal to Figure 3 the N uniform memory dies.

[0019] Figure 6 It is a partial circuit schematic of the circuit model of a differential transmission line, where the storage controller transmits a differential signal to Figure 3 the N uniform memory dies.

[0020] Figure 7 It is a partial circuit schematic of the circuit model of a single-ended transmission line, where Figure 3 the target uniform memory die of the N uniform memory dies transmits a single-ended signal to the storage controller.

[0021] Figure 8 It is a partial circuit schematic of the circuit model of a differential transmission line, where Figure 3 the target uniform memory die of the N uniform memory dies transmits a differential signal to the storage controller.

[0022] Figure 9 It shows the die stack interconnect model 900 according to one embodiment.

[0023] Figure 10 It shows the die stack interconnect model 1000 according to one embodiment.

[0024] Figure 11 It is a block diagram of a storage controller and N uniform memory dies in a memory system according to one embodiment.

[0025] Figure 12 It is a block diagram of N uniform memory dies in a storage controller and a memory system according to an embodiment.

[0026] Figure 13 Shows a programmable resistor circuit 1300 according to an embodiment.

[0027] Figure 14 Shows a programmable resistor circuit 1400 according to an embodiment.

[0028] Figure 15 Shows a programmable resistor circuit 1500 according to an embodiment.

[0029] Figure 16 Shows a method for providing electrical termination 1600 according to an embodiment. Detailed Description

[0030] As disclosed herein, the effective impedance of a transmission path can be reduced to match the characteristic impedance of a transmission line using uniform memory dies. Instead of a single on-die termination resistor circuit on the last memory die being serially connected to the transmission path, electrical termination circuits of multiple uniform memory dies can be connected to act in parallel during operation to achieve a higher bandwidth, signal transmission frequency, and / or number of memory dies in a memory die stack. The solutions disclosed herein can reduce the parasitic capacitance contributed by each memory die and wire bond by only using uniform memory dies each containing an on-die termination resistor circuit having a termination resistance at or above a minimum termination resistance.

[0031] "Electrical termination" refers to the practice of ending a line with a device that matches the characteristic impedance of the transmission line. This is to prevent signals from reflecting at the end of the transmission line. Reflection at the end of an unterminated transmission line causes distortion, which can result in ambiguous digital signal levels and misoperation of digital systems. (Searched "electrical termination" on Wikipedia.com on July 23, 2018. Modified. Accessed on June 5, 2020.)

[0032] There are two types of electrical terminations: passive or resistive termination, and active termination. Passive electrical termination is a circuit of passive electrical components that includes, for example, a resistor or a set of resistors connected in parallel. Active electrical termination is a circuit of active electrical components that includes, for example, a transistor or a set of transistors configured to perform electrical termination on an input signal.

[0033] The disclosed solutions allow for the connection of a larger number of uniform memory dies and / or operation at high frequencies, which can permit higher bandwidth signaling. One benefit of the disclosed solutions is that they use uniform memory dies across the entire transmission path. This eliminates the need to install specially designed memory dies or electronic components at specific locations within the memory die stack, thus simplifying manufacturing and assembly. Additionally, the on-die termination resistor circuit can be configured such that it is physically impossible for the on-die termination resistor circuit to provide a termination resistance less than a minimum termination resistance. This can reduce the amount of parasitic capacitance contributed by each uniform memory die and wire bond to the transmission path.

[0034] In one embodiment, the on-die termination resistor circuit disclosed herein can be constantly connected to the transmission line even when the uniform memory die is disconnected. In this disconnected state, the uniform memory die can be powered off or disabled, and / or the on-die termination resistor circuit can be disabled, but a minimum resistance can still be provided. When the uniform memory die is powered on / enabled and / or the on-die termination resistor circuit is enabled, the disclosed on-die termination resistor circuit can also be connected to the transmission line through a switch.

[0035] In some embodiments, two or more on-die termination resistor circuits of the uniform memory dies of the transmission path can be activated / enabled during the operation of another uniform memory die, the target uniform memory die. These two or more on-die termination resistor circuits of the uniform memory dies of the transmission path can include the last two or more uniform memory dies along the transmission path. In this way, electrical termination can be distributed along the transmission path. The distribution of the terminal die electrical termination allows the enabled on-die termination resistor circuits to act in parallel. When resistors of a certain value are connected in parallel, they can effectively act as a single resistor having a value equal to the total resistance of all the connected resistors divided by the number of resistors. For example, connecting four 200Ω resistors in parallel results in an effective resistance of 50Ω. To implement a single 50Ω resistor on one memory die designed for a terminal die slot, the physical configuration used to form the resistance can result in higher parasitic capacitance than that which can be achieved by four 200Ω resistors distributed across four terminal dies.

[0036] Additionally, the disclosed configuration for the termination resistor can be implemented with a resistance higher than the minimum termination resistance. For example, each uniform memory die can be configured to exhibit a termination resistance of 200Ω while being physically or otherwise limited to a minimum termination resistance of 100Ω. In this way, it can be prevented that the termination resistance on a specific die drops to a level that would disrupt the balance of the distributed on-die termination resistor circuit and cause more electrical strain on a single die.

[0037] "Transmission line" or "electrical transmission line" refers to a specialized cable or other structure designed to conduct alternating current or oscillating signals or voltages at radio frequencies (approx. 20 kHz - 300 GHz) or higher. The frequency of the signal is high enough such that the wave nature of the signal must be considered. The purpose of a transmission line is, for example, to connect radio transmitters and receivers via their antennas (which are then referred to as feeder lines or feeders), distribute cable television signals, trunk lines that route calls between telephone switching centers, computer network connections, and high-speed computer data buses. (Search Wikipedia.com for "Transmission line" and "Radio frequency" on May 28, 2020. Modified. Accessed June 4, 2020.)

[0038] "Termination resistance" refers to the level, value, or amount of resistance and / or impedance provided by a device, equipment, circuit, sub-circuit when coupled or connected to a transmission line and / or transmission path carrying an electrical signal for the purpose of providing electrical termination. The termination resistance is the result of electrical termination and is measured in units of ohms. Generally, it is desirable to provide a termination resistance that matches the impedance of the transmission line and / or transmission path.

[0039] In some embodiments, the plurality of uniform memory dies are configured to have an effective termination resistance. "Effective termination resistance" refers to a termination resistance that represents the level or amount of resistance and / or impedance for the entire transmission path. The effective termination resistance can be different from the termination resistance used independently for any one electronic component or circuit or logic within the transmission path, and the effective termination resistance can take into account aspects of signal transmission along the transmission path in either one or both directions (sender to receiver, receiver to sender).

[0040] In some embodiments, the signals on the transmission path carry host read commands, clock signals, and / or data signals. "Data signal" refers to an electrical signal (wired or wireless) sent from one component, circuit, driver, device, manager, or controller to another component, circuit, driver, device, manager, or controller. Specifically, a data signal is a signal configured to represent a data value. A data signal can be contrasted with a control signal configured to cause another device, component, manager, or controller to act in response to the control signal.

[0041] The following embodiments describe systems, devices, apparatuses, circuits, and methods for reducing the effective impedance of a transmission path and / or matching the characteristic impedance of a transmission line or other electronic components of a transmission path using uniform memory dies. A plurality of electrical termination circuits of a plurality of uniform memory dies may be connected to operate in parallel during operation to distribute electrical termination near and at one end of the transmission path while operating with respect to another uniform memory die along the transmission path. Managing the characteristic impedance, effective termination resistance, and on-die termination resistance along the transmission path may enable more efficient signal communication and / or improved signal quality, including increased bandwidth, frequency, and / or transmission rate, higher signal-to-noise ratio, reduced jitter, and / or lower duty cycle distortion. Before turning to these and other embodiments, the following paragraphs provide a discussion of exemplary memory systems and storage modules that may be used with these embodiments. These are merely examples, and other suitable types of systems, devices, apparatuses, or circuits may be used, including other types of memory systems and / or storage modules.

[0042] Figure 1A FIG. 4 is a block diagram showing a memory system 100, such as a memory system. Memory system 100 may include a storage controller 102 and a memory that may be composed of a plurality of memory dies 104. A "memory die" refers to a small piece of semiconducting material on which a given functional circuit is fabricated. Typically, integrated circuits are mass-produced in batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor (such as GaAs) through a process such as photolithography. The wafer is cut (diced) into many pieces, each containing a copy of the circuit. Each of these pieces is called a die. (Search 'Die (integrated circuit)' on Wikipedia.com on October 9, 2019. Accessed on November 18, 2019.) In one embodiment, the memory die is a die that includes functional circuits for operating as a memory medium and / or a memory array. The memory medium and / or memory array may include one or more of non-volatile memory media and volatile memory media.

[0043] Additionally, the term die generally can refer to a circuit or circuit component on a single semiconductor substrate, but may or may not include memory cells for storing data. The storage controller 102 can interface with a host system and transmit command sequences for read, program, and erase operations to the memory die 104. Here, the storage controller 102 is referred to as the storage controller die 102 to identify or highlight that the circuitry of the storage controller 102 is configured or located on a die separate from the plurality of memory dies 104 in some embodiments. Each of the storage controller die 102 and the memory dies 104 can be configured as or act as transceiver circuits since they can each transmit and receive signals. As described further in detail below, the storage controller die 102 and the plurality of memory dies 104 are configured to communicate with each other over a plurality of transmission lines.

[0044] The storage controller die 102 can be in the form of a processing circuit, a microprocessor or a processor, and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by, for example, a (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. The storage controller die 102 can be configured with hardware and / or firmware to perform the various functions described below. Also, some components shown to be inside the storage controller die 102 can also be stored outside the storage controller die 102, and other components can be used. Additionally, the phrase "operatively communicate with" can mean communicate directly with, or communicate indirectly (wired or wireless) with through one or more components that may or may not be shown or described herein.

[0045] The storage controller die 102 is configured to manage data stored in the memory cells of the memory die 104 and also communicate with a host such as a computer or an electronic device. The storage controller die 102 may have various functionalities in addition to the specific functionality described herein. For example, the storage controller die 102 may format the memory cells and / or circuitry of the memory die 104 to ensure proper operation of the memory die 104, map out bad or defective memory cells, and allocate spare cells to replace future failing cells. A portion of the spare cells may be used to hold firmware to operate the storage controller die 102 and implement other features. In operation, when the host needs to read data from or write data to the memory die 104, the host communicates with the storage controller die 102. If the host provides a logical address at which to read / write data, then the storage controller die 102 may translate the logical address received from the host into a physical address in the memory die 104. (Alternatively, the host may provide a physical address). The storage controller die 102 may also be configured to perform various memory management functions such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of the memory that would otherwise be repeatedly written) and garbage collection (after a block is full, moving valid data pages to a new block so that the full block can be erased and reused).

[0046] The interface between the storage controller die 102 and the memory die 104 may be any suitable memory interface such as Toggle Mode 200, 400, or 800. In one embodiment, the memory system 100 may be a card-based system such as a Secure Digital (SD) or a Micro Secure Digital (Micro SD) card. In an alternative embodiment, the system 100 may be part of an embedded memory system.

[0047] Figure 1B A storage module 200 is shown that includes a plurality of memory systems 100. Thus, the storage module 200 may include a storage controller 202 that interfaces with a host and with a storage system 204 that includes a plurality of memory systems 100. A "storage controller" refers to any hardware, device, component, element, or circuit configured to manage data operations on a memory medium (non-volatile and / or volatile) and may include one or more processors, programmable processors (such as an FPGA), an ASIC, a microcontroller, etc. In some embodiments, the storage controller is configured to store data on and / or read data from a memory medium (non-volatile and / or volatile), transfer data to / from a memory device (non-volatile and / or volatile), etc.

[0048] The interface between the storage controller 202 and the memory system 100 can be a bus interface, such as a Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), Peripheral Component Interconnect Express (PCIe) interface, Embedded Multimedia Card (eMMC) interface, SD interface, or Universal Serial Bus (USB) interface, as non-limiting examples. In one embodiment, the storage module 200 can be, for example, a Solid State Drive (SSD) present in portable computing devices such as laptop computers and tablet computers, and mobile phones.

[0049] Figure 1C is a block diagram showing a hierarchical storage system 210. The hierarchical storage system 210 can include multiple storage controllers 202, each of which controls a corresponding storage system 204. The host system 212 can access the memory within the hierarchical storage system 210 via a bus interface. Example bus interfaces can include, for example, Non-Volatile Memory Express (NVMe), Fibre Channel over Ethernet (FCoE) interface, SD interface, USB interface, SATA interface, SAS interface, PCIe interface, or eMMC interface. In one embodiment, the storage system 210 shown in Figure 1C can be, for example, a rack-mounted mass storage system accessible by multiple host computers as seen in a data center or other locations that require large-capacity storage.

[0050] Figure 2A is a block diagram showing exemplary components of the storage controller die 102 in more detail. The storage controller die 102 can include a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with the memory die 104, and various other modules that perform various functions of the memory system 100. Generally, a module can be hardware or a combination of hardware and software. For example, each module can include an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), circuitry, digital logic circuitry, analog circuitry, discrete circuitry, gates, or any other type of hardware combination, or a combination thereof. Additionally or alternatively, each module can include memory hardware that includes instructions executable by a processor or processor circuitry to implement one or more of the features of the module. When any of the modules includes a portion of the memory that includes instructions executable by a processor, the module may or may not include a processor. In some instances, each module can exactly be a portion of the memory that includes instructions executable by a processor to implement the features of the corresponding module without having a module that includes any other hardware. Because each module includes at least some hardware even when the included hardware includes software, each module can be interchangeably referred to as a hardware module.

[0051] The storage controller die 102 may include a buffer manager / bus controller module 114 that manages buffers in the random access memory (RAM) 116 and controls internal bus arbitration for communication on the internal communication bus 117 of the storage controller die 102. The read-only memory (ROM) 118 may store and / or access system boot code. Although shown in FIG. 2A as being located separately from the storage controller die 102, in other embodiments, one or both of the RAM 116 and the ROM 118 may be located within the storage controller die 102. In still other embodiments, portions of the RAM 116 and the ROM 118 may be located within and outside of the storage controller die 102. Additionally, in some implementations, the storage controller die 102, the RAM 116, and the ROM 118 may be located on separate semiconductor dies.

[0052] In addition, the front-end module 108 may include a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface to a host or a lower-level storage controller. The choice of the type of the host interface 120 may depend on the type of memory being used. Examples of the host interface 120 may include but are not limited to SATA, high-speed SATA, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 120 generally may facilitate the transfer of data, control signals, and timing signals.

[0053] The back-end module 110 may include an error correction controller (ECC) engine 124 that encodes data bytes received from a host and decodes and corrects errors in data bytes read from the memory die 104. In addition, the back-end module 110 may include a RAID (redundant array of independent drives) module 126 that manages the generation of RAID parity and the recovery of failed data. The RAID parity may be used as an additional level of integrity protection for writing data into the memory system 100. In some cases, the RAID module 126 may be part of the ECC engine 124.

[0054] Additionally, the back-end module 110 may include a command sequencer 128 and a memory interface 130. The command sequencer may be configured to generate command sequences to be transmitted to the memory die 104, such as programming, read, and erase command sequences. The commands of the command sequences output by the command sequencer 128 may be referred to as context commands. For example, the commands of the command sequence for a read operation may be referred to as read context commands, and the commands of the command sequence for a write operation may be referred to as write context commands.

[0055] The memory interface 130 is configured to output a command sequence or a context command to the memory die 104 and receive status information from the memory die 104. Along with the command sequence and the status information, the memory interface 130 may also be configured to send and receive data to be programmed into and read from the memory die 104, such as data in the form of data signals. The memory interface 130 may also be configured to output a clock signal or a strobe signal to control the timing of the memory die 104 receiving data signals carrying data to be programmed and / or the timing of the memory die 104 outputting data signals carrying data that the memory controller die 102 wishes to read from the memory die 104. The memory interface 130 may have any one of a variety of configurations for sending and receiving signals. Example circuit components include input / output (I / O) driver circuits for generating and receiving signals (e.g., push-pull circuits, amplifiers, buffers, Schmitt trigger circuits, on-die termination resistor circuits, etc.), and I / O contact pads for conveying signals between the transmission line 134 and the I / O driver circuits. In one embodiment, the memory interface 130 may be a double data rate (DDR) interface, such as a double data rate mode 200, 400, or 800 interface. In some example configurations, the memory controller die 102 may include a control layer 132 (e.g., a flash controller layer) that controls the overall operation of the control backend module 110.

[0056] such as Figure 2AAs shown, the memory system 100 may include a plurality of transmission (Tx) lines 134 that connect the storage controller die 102 and the plurality of memory dies 104. Generally speaking, a transmission line is any conductive structure or combination of conductive structures configured to conduct an alternating current (AC) or radio frequency (RF) signal from a transmitter that emits the signal to a receiver that receives the signal. For the example memory system described herein, transmission lines are included to convey signals between (including in and out of) the storage controller die 102 and the memory dies 104. The storage controller die 102 and the memory dies 104 may be configured to convey signals on the plurality of transmission (Tx) lines 134, including data signals, clock signals, and command signals. Signals conveyed between the storage controller die 102 and the memory dies 104 may be transmitted from the storage controller die 102 to a memory die 104 on one of the transmission lines 134, or from a memory die 104 to the storage controller die 102 on one of the transmission lines 134. In this context, each of the storage controller die 102 and the memory dies 104 may be configured as a transceiver circuit (or die) because they can each be configured to transmit and receive signals. Additionally, the transmission lines 134 may be coupled to the transmission lines 134 via their memory interfaces 130. That is, when the storage controller die 102 wants to send a signal to a memory die 104, the storage controller die 102 may send the signal onto one of the transmission lines 134 through its memory interface 130. The memory dies 104 may each have their own respective memory interfaces for sending and receiving signals, as described in further detail below with respect to Figure 3 When referring to the memory interfaces, the memory interface of the storage controller die 102 may be referred to as the controller-side memory interface 130, and the memory interfaces of the memory dies 104 may be referred to as the memory-side memory interfaces.

[0057] Figure 2A Additional modules of the memory system 100 shown in may include a media management layer 138, which may perform certain memory functions such as address management (e.g., address translation) and wear leveling of the memory cells of the memory dies 104. The memory system 100 may also include other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that may interface with the storage controller die 102. In alternative embodiments, one or more of the RAID module 126, the media management layer 138, and the buffer management / bus controller module 114 are optional components that may not be included in the storage controller die 102.

[0058] Figure 2BFIG. is a block diagram exemplarily showing components of one of the memory dies 104 in more detail. The memory die 104 may include memory cell structures 142. In some example configurations, the memory cell structures 142 may be configured in the form of an array, such as a two-dimensional or three-dimensional array.

[0059] Any suitable type of memory may be used for the memory cells. For example, the memory may be a volatile memory such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”), or a non-volatile memory such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), magnetoresistive random access memory (“MRAM”), phase change memory (“PCM”), or other elements including semiconductors or other materials capable of storing information. Each type of memory may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0060] The memory may be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements which, in some embodiments, include resistive switching memory elements such as anti-fuse phase change materials, etc.; and optionally include guiding elements such as diodes, etc. Additionally, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements which, in some embodiments, include elements containing charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0061] Multiple memory elements may be configured such that they are connected in series or such that each element can be accessed individually. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memories) typically contain memory elements connected in series. A NAND memory array may be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements sharing a single bit line and being accessed as a group. Alternatively, the memory elements may be configured such that each element can be accessed individually, such as a NOR memory array. The NAND and NOR memory configurations are exemplary, and the memory elements may be configured in other ways.

[0062] Semiconductor memory elements located within and / or above a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure (e.g., an array).

[0063] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane extending parallel to the major surface of the substrate that supports the memory elements (e.g., in the x-z plane). The substrate can be a wafer of a layer over or in which the memory elements are formed, or can be a carrier substrate attached to the memory elements after the memory elements are formed. As a non-limiting example, the substrate can comprise a semiconductor such as silicon.

[0064] The memory elements can be arranged in a single memory device level in the form of an ordered array such as multiple rows and / or columns, for example. However, the memory elements can be arranged in an irregular or non-orthogonal configuration. Each of the memory elements can have two or more electrodes or contact lines, such as bit lines and word lines.

[0065] A three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, where the y direction is generally perpendicular to the major surface of the substrate, and the x and z directions are generally parallel to the major surface of the substrate).

[0066] As a non-limiting example, the three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, the three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending generally perpendicular to the major surface of the substrate (i.e., along the y direction)), where each column has multiple memory elements in each column. The columns can be arranged in a two-dimensional configuration (e.g., in the x-z plane), thereby resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

[0067] Additional methods of organizing the memory cells of the memory cell structure 142 can be possible. As a non-limiting example, the memory cells can be organized into blocks, and the blocks can be organized into planes. Additionally, the memory cells of the memory cell structure can be connected to bias lines, including word lines and bit lines. The circuitry on the memory die can be configured to bias the word lines and bit lines at various voltages to perform memory operations associated with the memory cells, including read, program, and erase operations.

[0068] Memory die 104 may also include a page buffer or data cache 144 that caches data sensed from and / or to be programmed to the memory cell structure 142. Memory die 104 may also include a row address decoder 146 and a column address decoder 148. When reading data from or writing data to a memory cell in the memory cell structure 142, the row address decoder 146 may decode the row address and select a particular word line in the memory cell structure 142. The column address decoder 148 may decode the column address to select a particular group of bit lines in the memory cell structure 142 to be electrically coupled to the data cache 144.

[0069] Additionally, memory die 104 may include peripheral circuitry 150. The peripheral circuitry 150 may include control logic circuitry (also referred to as an on-chip controller, die controller, or simply a controller) 152 that may be implemented as a state machine, which provides on-chip control of memory operations and provides status information to the storage controller 102. A “die controller” refers to a set of circuits, circuitry, logic, or components configured to manage the operations of a die. In one embodiment, the die controller is an integrated circuit. In another embodiment, the die controller is a combination of discrete components. In another embodiment, the die controller is a combination of one or more integrated circuits and one or more discrete components. The peripheral circuitry 150 may also include volatile memory 154. Example configurations of the volatile memory 154 may include latches, but other configurations are possible.

[0070] Also, memory die 104 may include a memory side interface 156 configured to interface and communicate with the memory interface 130 of the storage controller die 102. Specifically, the memory side interface 156 may be configured to couple to at least some of the transmission lines 134 of the memory system 100. When a given memory die 104 is to transmit a signal to the storage controller die 102, the given memory die 104 may transmit the signal via its memory side interface 156 onto one of the transmission lines 134 to the storage controller die 102. Additionally, when a given memory die 104 is to receive a signal from the storage controller die 102, the given memory die 104 may receive the signal via its memory side interface 156 from one of the transmission lines 134. As described in further detail below, the components of the memory side interface 156 together with the die capacitance of the die may form part of the transmission lines 134 and / or determine the characteristic impedance of the transmission lines.

[0071] The memory - side interface 156 may include an input / output (I / O) driver circuit 158 configured to generate and receive signals, including data signals carrying data, command signals identifying commands, clock signals, or other types of signals carrying other information to be transmitted to and received from the memory controller die 102. For example, data sensed in the data cache memory 144 may be sent to the I / O driver circuit 158 for transmission to the memory controller die 102. Similarly, data received from the memory controller die 102 may be received by the I / O driver circuit 158, and the I / O driver circuit 158 may transfer the data to the data cache memory 144. Additionally, commands to be transferred between the memory controller die 102 and the control logic 152 may be transferred via the I / O driver circuit 158. The I / O driver circuit 158 may have any of a variety of circuits or combinations of circuits, examples of which include push - pull circuits, amplifiers, buffers, Schmitt trigger circuits, combinations thereof, or any other suitable circuit configured to receive signals from or output signals to a transmission line.

[0072] Additionally, the memory - side interface 156 may include an input / output (I / O) contact pad portion 160 that communicates with the I / O driver circuit 158 configured to send signals to and receive signals from the I / O driver circuit 158. For example, signals generated by the I / O circuit 158 for transmission to the memory controller die 102 may be transferred from the I / O driver circuit 158 to the I / O contact pads 160. Similarly, signals received by the memory - side interface 156 from the memory controller die 102 may be sent from the I / O contact pads 160 to the I / O driver circuit 158. Additionally, as described in further detail below, the I / O contact pads 160 together with wire - bond elements (WBE) ( Figure 3 shown) may form a transmission line 134 or be part of it, through which the memory die 104 and the memory controller die 102 transfer signals between each other. "Wire - bonding" refers to wires used for the interconnection of integrated circuits, communication buses, and / or communication channels, often made of aluminum, aluminum - alloyed, copper, silver, gold, or doped gold.

[0073] And, as Figure 2BAs shown, the memory - side interface 156 may include an on - die termination (ODT) resistor circuit 162, which may include one or more resistors or other circuit components (e.g., electronic components) that provide the termination resistance. The on - die termination resistor circuit 162 may provide the termination resistance impedance for the transmission line 134 and may be used for impedance matching between the memory die 104 and the characteristic impedance of the transmission line 134. "On - die termination resistor circuit" refers to any circuit, sub - circuit, electronic component, hardware, software, firmware, module, logic, device, or equipment that is configured, programmed, designed, arranged, or engineered to provide electrical termination for a signal on a transmission line or transmission path. In one embodiment, the memory controller may also include an on - die termination resistor circuit.

[0074] The resistors of the on - die termination resistor circuit 162 may be connected to the I / O contact pads 160. Additionally, the on - die termination resistor circuit 162 may provide variable resistance levels or values, including one or more high levels and one or more low levels, as described in further detail below. The resistance level or value provided by the on - die termination resistor may be controlled by the memory controller die 102, the on - die control logic 152, or a combination thereof.

[0075] The memory die 104 implemented in the illustrated architecture may be a homogeneous memory die. "Homogeneous memory die" refers to a memory die that includes the same or substantially the same parts, components, electronic components, circuits, features, size, configuration, and / or capabilities as another memory die. Using homogeneous memory dies within a die stack may simplify the manufacturing and assembly of the memory system.

[0076] Figure 3 A block diagram showing the structural layout of the memory controller die 102 and N number of homogeneous memory dies 304, where the N number of homogeneous memory dies includes a first homogeneous memory die 304(1), a second homogeneous memory die 304(2), and an Nth homogeneous memory die 304(N). N may be any integer of two or more. The N number of homogeneous memory dies 304(1) - 304(N) may include all of the memory dies 104 in the memory system 100 or may be less than all of the memory dies 104. For example, the N number of homogeneous memory dies 304(1) - 304(N) may be on the same chip and / or may be part of the same chip - enabled group. The memory system 100 may include a single chip or chip - enabled group in which the memory dies 104 are located. Figure 3The N number of die 304 can represent a single die or a die-enabled group of dies. Alternatively, memory system 100 may or may include multiple dies or die-enabled groups, and some of the memory dies 104 may be located on one die or in one die-enabled group, while other memory dies 104 may be located on one or more other dies or in one or more other die-enabled groups. Figure 3 The N number of die 304 can represent one of the multiple dies or die-enabled groups. Additionally, or alternatively, the N number of die 304 can be configured as or as part of the same die stack. Various configurations are possible. Further details are provided below with reference to Figure 3 describing additional details of dies configured as a die stack.

[0077] In Figure 3 the illustrated example configuration, the uniform memory dies 304(1)-304(N) can be configured in and / or integrated with a package 302, which may include various package components such as a die substrate, traces and vias integrated in the die substrate, solder balls, contact pads, wire bonds, and a lid, as non-limiting examples. The storage controller die 102 can be configured as and / or implemented as its own die and / or integrated with its own package, which is separate from the package of the uniform memory dies 304(1)-304(N). The storage controller die 102 and the uniform memory dies 304(1)-304(N) integrated with the package 302 can be integrated on a printed circuit board 305, as Figure 3 illustrated.

[0078] The storage controller die 102 and the uniform memory dies 304(1)-304(N) can transmit signals between each other over transmission lines (e.g., Figure 2A and Figure 2B at least some of the transmission lines 134). For simplicity, Figure 3 the physical layout shows a single transmission line connecting the storage controller die 102 and the uniform memory dies 304(1)-304(N). However, in a configuration such as that referenced in Figure 2A and Figure 2BIn the described actual implementation, there may be multiple transmission lines between the storage controller 102 and the uniform memory dies 304(1)-304(N), and the transmission lines are configured to transmit data signals, clock signals, strobe signals, command signals, status signals, or any other type of signal between the storage controller die 102 and the uniform memory dies 304. For example, there may be a first transmission line through which the storage controller die 102 sends signals to the uniform memory die 304, and a second transmission line through which the uniform memory die 304 sends signals to the storage controller die 102. Additionally, at least some of the multiple transmission lines may be configured to be in parallel with each other such that two or more signals propagating on two or more parallel transmission lines can be transmitted individually and / or simultaneously. As mentioned, each transmission line may be configured to carry one of more signals, where each signal is a data signal, command signal, clock signal, or any other type of signal that can be transmitted between the storage controller 102 and the uniform memory dies 304(1)-304(N), including those for performing memory operations.

[0079] In some example configurations, the transmission line may be configured as a single-ended transmission line or signal path configured to transmit single-ended signals. For other example configurations, the transmission line may be configured as a differential transmission line or signal path configured to transmit differential signals. "Signal path" refers to an electromagnetic wave or a conductive path along which a signal travels in response to a driving force. In certain embodiments, the signal path may include a transmission line. In another embodiment, the signal path may include a transmission path. In one embodiment, the transmission path may include one or more of a transmission and / or signal path.

[0080] For any of the configurations, the transmission line may include a first conductive path and a second conductive path. As described in further detail below, the transmission line and / or its first and second conductive paths may include any one of various types of conductive elements, such as, by way of non-limiting example, traces, vias, solder balls, contact pads, wire bonds, to transmit signals between the storage controller 102 and the uniform memory die 304.

[0081] For a single-ended configuration, the first path may be the signal path component or portion (or just the signal path) of the transmission line, and the second path may be the ground reference or return component or portion (or just the ground path or return path) of the transmission line. The single-ended signal transmitted along the signal path may be a single signal or a single signal component (e.g., a voltage or current data transition, including a clock signal oscillating at a certain frequency) having a reference to the ground reference path propagating along the signal path.

[0082] For a differential configuration, the first path and the second path can be signal paths, each configured to convey a respective signal component of a differential signal. That is, a differential signal conveyed on a differential signal path can include a first signal component (or only the first signal) and a second signal component (or only the second signal). As a differential signal, at any given moment during signal propagation along the differential signal path, the first and second signal components can have amplitudes that are inversely related or are inversions of each other, and in some cases, have equal magnitudes and opposite polarities. The first signal component of the differential signal can propagate along a first signal path of the differential signal path, and the second signal component of the differential signal can propagate along a second signal path of the differential signal path.

[0083] Generally speaking, in Figure 3 the illustrated example configuration, whether for a single-ended or differential configuration, the transmission line can include a printed circuit board (PCB) portion 306, a package portion 308, a wire bonding element 310, and an input / output (I / O) contact pad portion 312. A portion or component of the first path of the transmission line is referred to as a first portion or component, and a portion or component of the second path of the transmission line is referred to as a second portion or component. Additionally, the transmission line and / or the first and second paths can also include or be coupled to a termination resistor of a memory controller 102 ( Figure 3 not shown in the figure) and an on-die termination (ODT) resistor circuit 314 of the uniform memory die 304. Compared with Figure 3 the illustrated portions, other transmission line configurations can include fewer, additional, or other portions.

[0084] More specifically, the first path can include a first PCB portion 306_1 and the second path can include a second PCB portion 306_2. Each of the first PCB portion 306_1 and the second PCB portion 306_2 can be integrated with the printed circuit board 305 and extend between the memory controller 102 and the package 302. Additionally, the first PCB portion 306_1 and the second PCB portion 306_2 can each be implemented as a conductive trace (e.g., in the form of a microstrip line or a stripline), one or more vias, a combination of traces and vias, or any other type of conductive element configured to carry signals on the printed circuit board 305 from the memory controller die 102 to the package 302.

[0085] Additionally, the first path may include a first encapsulation portion 308_1, and the second path may include a second encapsulation portion 308_2. The first PCB portion 306_1 and the second PCB portion 306_2 may be connected to their respective first encapsulation portion 308_1 and second encapsulation portion 308_2. Generally, the encapsulation portions 308_1, 308_2 may be configured to transfer signals from the PCB portions 306 to the uniform memory die 304 on a transmission line. The first encapsulation portion 308_1 and the second encapsulation portion 308_2 may each include any of a variety of conductive elements for this purpose, examples of which include solder balls, such as those of a ball grid array structure, vias and / or traces integrated in the die substrate, contact pads, and wire bonds. A variety of configurations for connecting the PCB portion 308 of the transmission line to the I / O contact pads of the uniform memory die 304 are possible.

[0086] Additionally, the first path may include a first set of wire bond elements (WBE) 310_1, and the second path may include a second set of wire bond elements 310_2. Each wire bond element 310 may include a wire bond. And, as described in further detail below, in some example configurations, at least one wire bond element 310_1 of the first path and / or at least one wire bond element 310_2 of the second path may include an additional conductive structure, referred to as an inductance increasing element, which increases the inductance provided by the wire bond of the wire bond element. Some types of additional conductive structures are described in further detail below.

[0087] In Figure 3 the illustrated example configuration, the I / O contact pad portion 312 includes an N number of I / O contact pad portions 312(1) to 312(N). Each contact pad portion 312 may include at least two contact pads, including a first contact pad that is part of the first path and a second contact pad that is part of the second path. For clarity, Figure 3 two different or separate contact pads of a given I / O contact pad portion 312 are not illustrated. And, for a configuration where the transmission line is configured to transfer signals from the memory controller die 102 to the uniform memory die 304, the contact pads that are part of the transmission line are referred to as input contact pads. Additionally, for a configuration where the transmission line is configured to transfer signals from the uniform memory die 304 to the memory controller die 102, the contact pads that are part of the transmission line are referred to as output contact pads.

[0088] In addition, each wire bonding element 310 may be configured to connect a contact pad on one uniform memory die 304 to a contact pad on another different uniform memory die 304. For example, the first wire bonding element 310_1(1) of the first path may connect a contact pad of the first I / O contact pad portion 312(1) of the first uniform memory die 304(1) to a contact pad of the second I / O contact pad portion 312(2) of the second uniform memory die 304(2). Similarly, the (N - 1)th wire bonding element 310_2(N - 1) of the second path may connect a contact pad of the (N - 1)th I / O contact pad portion 312(N - 1) of the (N - 1)th uniform memory die 304(N - 1) (not shown) to a contact pad of the Nth I / O contact pad portion 312(N) of the Nth uniform memory die 304(N).

[0089] The wire bonding elements 310 and the I / O contact pad portions 312 may, in combination, form part of a transmission line, where each I / O wire bonding element 310 and each I / O contact pad portion 312 have positions relative to each other in the transmission line corresponding to the propagation delay or electrical distance from the package portion 308. Compared to a given contact pad or a given wire bonding element positioned further away electrically from the package portion 308, a signal transmitted from the memory controller 102 may take a shorter amount of time to reach a given contact pad or a given wire bonding element positioned closer electrically to the package portion 308.

[0090] The uniform memory dies 304, the wire bonding elements 310, and the I / O contact pad portions 312 are numbered in Figure 3 correspondence to their respective positions in the transmission line. For a given index k, the higher the value of k, the further the kth wire bonding element WBE(k) and the kth I / O contact pad portion 312(k) are in the transmission line relative to lower numbered wire bonding elements 310 and I / O contact pad portions 312 and / or further away from the package portion 308, the PCB portion 306, and the memory controller 102. The Nth I / O contact pad portion 312(N) may be the memory - side end or termination of the transmission line. Additionally, the contact pads on the memory controller die 102 may be the controller - side end or termination of the transmission line. In this context, the Nth die 304 may be referred to as the end die or termination die of the plurality of dies 304 because it has contact pads that form the memory - side termination of the transmission line, i.e., contact pads that are electrically positioned furthest away on the transmission line from the package portion 308, the PCB portion 306, and the memory controller die 102.

[0091] Thus, in a case where the storage controller 102 transmits a signal to the k-th uniform memory die 304(k), the pulse of the signal will propagate on (k - 1) numbers of I / O contact pad portions 312 and (k - 1) numbers of wire bonding elements 310, and then reach the k-th I / O contact pad portion 312(k). Similarly, when the k-th uniform memory die 304(k) transmits a signal to the storage controller 102, after the pulse of the signal is output at the k-th I / O contact pad portion 312(k), the pulse will immediately propagate on (k - 1) numbers of wire bonding elements 310 and (k - 1) numbers of I / O contact pad portions 312, and then reach the package portion 308. Additionally, after being output at the k-th I / O contact pad portion 312(k), the pulse may also immediately propagate on (N - k) numbers of wire bonding elements 310 and (N - k) numbers of I / O contact pad portions 312.

[0092] In addition, the N numbers of uniform memory dies 304(1)-304(N) may be part of the same chip group. The uniform memory dies 304(1)-304(N) are located within the same package 302, and their corresponding I / O contact pad portions 312(1)-312(N) are electrically connected to the same package portion 308 and / or the same PCB portion 306 between the storage controller die 102 and the package 302, and are recognized as part of the same chip group by the storage controller die 102, or a certain combination thereof, so that they may be part of the same chip group.

[0093] A number N of uniform memory dies 304 can be configured in any of a variety of ways within a memory system. In one example configuration, the number N of dies 304 can be configured as a die stack, and specifically as a stepped stack. Generally speaking, a given die can be a generally flat structure having two opposing flat surfaces, including a first flat surface and a second flat surface. In a die stack, the dies can be positioned or "stacked" on top of one another, starting from a first or base die and extending in a direction perpendicular to the flat surfaces of the dies. As a die stack, one flat surface of one die can face and / or contact the flat surface of a second die. Also, two dies are adjacent to each other with no other stacked dies positioned therebetween. And, in some example configurations, the first or base die can be directly positioned or mounted on a base substrate or a printed circuit board. The last or Nth die in the stack can be the die that is positioned further away from the base substrate or printed circuit board on which the die stack is mounted. And, for embodiments in which the die stack is configured as a stepped stack, the dies can be stacked on top of one another such that the dies do not completely cover one another, and in fact such that each die has an exposed portion, where corresponding I / O contact pad portions can be positioned and connected to one another via wire bonding. By positioning the dies on top of one another on the die to create an exposed portion, the dies of the die stack have a "stepped" shape when viewed from the side, with each die being one of the "steps" of the step.

[0094] The dashed lines are used to demarcate the entire transmission path 316, including the transmission lines incorporated within the printed circuit board 305 and the wire bond connections between the uniform memory dies 304. A "transmission path" refers to an electrical signal that travels through a circuit or a portion of a circuit. A transmission path can include a variety of electrical components and can include one or more connections to a ground source, a signal source, and / or a power source. In certain embodiments, a transmission path can include a transmitter, a receiver, and one or more transmission lines. A transmission path can also be referred to as a'main line'.

[0095] Impedance components such as characteristic impedance, resistance, parasitic capacitance, and inductance can be added along the length of the transmission path 316. If not terminated correctly, these effects can introduce reflections and noise due to transmission line effects, thereby adversely affecting signal speed and bandwidth.

[0096] Figure 4 A cross-sectional side view showing a plurality of memory dies 402(1)-402(N) integrated or configured as a stepped stack. The plurality of memory dies 402(1)-402(N) can represent the plurality of uniform memory dies 304(1)-304(N), and shows an example configuration in which the plurality of uniform memory dies 304(1)-304(N) can be integrated with one another and with the package 302.

[0097] InFigure 4 In the example configuration shown, the stack of die 402 can be disposed on die substrate 404. Specifically, the first die 402(1) can contact the die substrate and / or can be the memory die 402 closest to the die substrate. Additionally, the other memory dies 402(2)-402(N) are stacked on the first memory die 402(1) in a stepped configuration such that the second memory die 402(2) is disposed on the first memory die 402(1), the third memory die 402(3) is disposed on the second memory die 402(2), and the Nth memory die 402(N) is disposed on the (N-1)th memory die 402(N-1) (not shown).

[0098] Moreover, each of the memory dies 402(1)-402(N) can have pads of a corresponding I / O contact pad portion. Figure 4 A cross-sectional side view of shows one of the paths and thus shows the contact pads 406 for a single path shown in Figure 4 For the single path shown, the first memory die 402(1) can include a first contact pad 406(1), the second memory die 402(2) can include a second contact pad 406(2), the third memory die 402(3) can include a third contact pad 406(3), and the Nth memory die 402(N) can include an Nth contact pad 406(N).

[0099] Figure 4 The path shown in can also include N-1 numbers of wire bonding elements 408. Each ith wire bonding element 408(i) can connect the ith contact pad to the (i+1)th contact pad 406(i+1). For example, the first wire bonding element 408(1) can connect the first contact pad 406(1) to the second contact pad 406(2), the second wire bonding element 408(2) can connect the second contact pad 406(2) to the third contact pad 406(3), the third wire bonding element 408(3) can connect the third contact pad 406(3) to the fourth contact pad 406(4) (not shown), and the (N-1)th wire bonding element 408(N-1) can connect the (N-1)th contact pad 406(N-1) (not shown) to the Nth contact pad 406(N). And, for Figure 4 the example configuration of, a wire bonding element 410 can connect the first contact pad 406(1) to the contact pad 412 of the die substrate 404.

[0100] Returning to refer Figure 3, each of the uniform memory dies 304(1)-304(N) includes a respective on-die termination (ODT) resistor circuit 314 connected to an associated I / O contact pad 312. For example, the first uniform memory die 304(1) includes a first on-die termination resistor circuit 314(1) connected to the first I / O contact pad 312(1), the second uniform memory die 304(2) includes a second on-die termination resistor circuit 314(2) connected to the second I / O contact pad 312(2), and the Nth uniform memory die 304(N) includes an Nth on-die termination resistor circuit 314(N) connected to the Nth I / O contact pad 312(N).

[0101] Each of the on-die termination resistor circuits 314(1)-314(N) can have an associated on-die termination resistance. The resistance that a given on-die termination resistor circuit 314 has can be variable. That is, the resistance of a given on-die termination resistor circuit 314 can be at one of a plurality of resistance levels.

[0102] The resistance levels to which each of the on-die termination resistor circuits 314 can be set can include at least two levels, including a high resistance level and a low resistance level. Additionally, for at least some example configurations, the resistance levels can include multiple low levels, and / or multiple high levels. Thus, at a given time, a given on-die termination resistor circuit 314 can be configured to set its on-die termination resistance to one of a plurality of high resistance levels and / or to set its on-die termination resistance to one of a plurality of low resistance levels.

[0103] Additionally, a given on-die termination resistor circuit 314 can be configured to change or adjust its on-die termination resistance from a first resistance level to a second resistance level. The first and second resistance levels can be any of various combinations of high and low resistance levels. That is, depending on the configuration, a given on-die termination resistor circuit 314 can be configured to change its on-die termination resistance from a high resistance level to a low resistance level, from a low resistance level to a high resistance level, from a first high resistance level among a plurality of high resistance levels to a second high resistance level among the plurality of high resistance levels (where the first high resistance level can be higher or lower than the second high resistance level), or from a first low resistance level among a plurality of low resistance levels to a second low resistance level among the plurality of low resistance levels (where the first low resistance level can be higher or lower than the second low resistance level).

[0104] In some embodiments, the on-die termination resistance circuit 314 of each uniform memory die is configured such that the low resistance levels that the on-die termination resistance circuit 314 can provide are not lower than a minimum termination resistance (e.g., minimum termination resistance level). Thus, although the on-die termination resistance circuit 314 may be capable of programmatically providing multiple low resistance levels, none of these are lower than the minimum termination resistance. Thus, the minimum termination resistance is the lowest termination resistance level provided by the on-die termination resistance circuit 314, regardless of whether the uniform memory die is powered on, enabled, and activated or the on-die termination resistance circuit 314 is powered on, enabled, or activated.

[0105] Generally speaking, the high resistance levels are higher than the low resistance levels. In some example configurations, the high resistance level is greater than or equal to 500 ohms (Ω) and the low resistance level is less than or equal to 200 Ω. Example high resistance levels can be 500 ohms, 1 kΩ, or 10 kΩ. Example low resistance levels include 110 ohms, 125 ohms, 135 ohms, 150 ohms, 175 ohms, and 200 ohms. Example minimum termination resistance levels can be 100 ohms, 150 ohms, or 200 ohms. Other high resistance levels may be possible. Additionally, or alternatively, the high resistance level can be greater than or equal to ten times the characteristic impedance of the transmission line.

[0106] Furthermore, for some example configurations, the high resistance level is a single or fixed value, and the low resistance level can be any one of a plurality of low resistance levels each greater than the minimum termination resistance level at any given time. For such configurations, each of the low resistance levels is lower than the single high resistance level.

[0107] Also, in some example configurations, for a given i-th die 304(i) that includes the i-th on-die termination resistance circuit 314(i), at a given time point, the i-th on-die termination resistance circuit 314(i) can set its resistance level to a high resistance level within a high resistance level range that includes an upper high resistance level and a lower high resistance level, and / or can set its resistance level to a low resistance level within a low resistance level range that includes an upper low resistance level and a lower low resistance level.

[0108] At any given time point, the i-th on-die termination resistance circuit 314(i) can set its resistance to any one of a plurality of high resistance levels within the high resistance level range, and / or can set its resistance level to any one of a plurality of low resistance levels within the low resistance level range. Additionally, or alternatively, the resistance levels can be discrete values or levels, and the last three or more on-die termination resistance circuits 314(i) can set their resistance levels to one of the discrete resistance levels.

[0109] The resistance level provided by each of the on-die termination resistor circuits 314(1)-314(N) can be determined and / or controlled by the memory controller die 102, the plurality of homogeneous memory dies 304(1)-304(N) themselves (e.g., by their control logic 152( Figure 3 )) or a combination thereof. As Figure 3 shown, each of the on-die termination resistor circuits 314(1)-314(N) can be configured to receive corresponding control signals CTRL(1)-CTRL(N) for setting and / or adjusting the resistance level. For some example configurations, the memory controller die 102 can send command signals to the plurality of homogeneous memory dies 304 indicating one or more resistance levels of one or more of the on-die termination circuits 314. In response, the homogeneous memory dies 304 can set the on-die termination resistor circuits 314 to the resistance levels indicated by the command signals. For example, the on-die control circuit 152 can output the corresponding control signals CTRL to the corresponding on-die termination resistor circuits 314.

[0110] Additionally, the on-die termination resistor circuits 314 can be part of a transmission line or coupled to a transmission line. As previously described, the Nth homogeneous memory die 304(N) can be the end die or last die of the plurality of homogeneous memory dies 304 (or die stack). In certain embodiments, two or more of the homogeneous memory dies in the transmission path 316 before the end memory die, as well as the end memory die, can be used to provide distributed on-die termination. Thus, the on-die termination resistor circuit 314(N) of the Nth homogeneous memory die 304(N) and two or more of the homogeneous memory dies in the transmission path 316 before the end die can be referred to as distributed on-die termination resistor circuits, which together provide electrical termination of the transmission line. Distributed on-die termination uses two or more of the homogeneous memory dies at the end of the transmission path to distribute the functionality of electrical termination among the plurality of homogeneous memory dies along the transmission path.

[0111] Figures 5 to 8 is a partial circuit schematic of a circuit model of a transmission line between the memory controller die 102 and Figure 3 the plurality of homogeneous memory dies 304. Figure 5 and Figure 6 illustrate the circuit model when the memory controller die 102 transmits a signal on the transmission line. Figure 7 and Figure 8 illustrate the circuit model when the kth target memory die 104(k) transmits a signal on the transmission line. Additionally, Figure 5 and Figure 7 illustrate the circuit model of a transmission line configured as a single-ended transmission line. Figure 6 and Figure 8A circuit model of a transmission line configured as a differential transmission line is shown.

[0112] In particular, referring to Figure 5 (and also back to Figure 3 and Figure 4 ), the circuit model includes two paths of the transmission line, including a first path 502 and a second path 504. The first path 502 can be a signal path and the second path 504 can be a ground path of a single-ended transmission line. In this way, the transmission line disclosed herein can be a single-ended transmission line.

[0113] Generally, the conductive elements of the paths can be represented by inductors or inductive elements that provide inductance to the transmission line or be modeled as inductors or inductive elements. The inductive element of the first signal path 502 is represented by inductor LS, and the inductive element in the second ground path 504 is represented by inductor LG. The transmission line model can also include a capacitor C to represent capacitive elements of or coupled to the transmission line. The capacitive elements can include the substrate in which the conductive / inductive elements are placed or coupled, such as the substrate of the uniform memory die 304, the die substrate 404, or the circuit parasitic load. Generally, the inductive elements LS or LG of a given path are connected in series with each other and in parallel with the capacitive element C. In a simpler model, the inductance of the ground path 504 can be "folded" into the inductance of the signal path 502.

[0114] In the signal path, the inductance provided by the first PCB and package portions 306_1, 308_1 can be represented by inductor LSp; the inductance provided by the first wire bonding element 310(1) and (optionally) by the I / O contact pads of the first I / O contact pad 312(1) and / or the second I / O contact pad 312(2) that are part of the first path can be represented by inductor LS 1-2 ; the inductance provided by the second wire bonding element 310(1) and (optionally) by the I / O contact pads of the second I / O contact pad 312(2) and / or the third I / O contact pad 312(3) that are part of the first path can be represented by inductor LS 2-3 ; and the inductance extending to the (N - 1)th wire bonding element 310(N - 1) and (optionally) by the I / O contact pads of the (N - 1)th I / O contact pad 312(N - 1) and / or the Nth I / O contact pad 312(N) that are part of the first path can be represented by inductor LS (N-1)-N ; The inductive components of the second ground path 504 can be similarly represented by inductors LGp, LG 1-2 , LG 2-3 ; and extending to LG (N-1)-N .

[0115] The circuit model of the single - ended transmission path may also include a capacitor C(P), which may represent the capacitance provided by the capacitive elements on which the inductive package portions 306, 308 extend, this die substrate 404. The circuit model may also include capacitors C(M1), C(M2), and extending to C(MN) that are connected in parallel with the signal path 502 and the ground path 503. The capacitors C(M1), C(M2), and extending to C(MN) may respectively represent the capacitance provided by the die substrates of the first uniform memory die 304(1), the second uniform memory die 304(2), and extending to the Nth uniform memory die 304(N).

[0116] And, as Figure 5 shown, the total or effective termination resistance provided by the on - die termination circuit 314 may be represented by the memory - side ODT resistor R ODT (M). And, in Figure 5 it, a voltage source 506 may be included to represent the voltage offset for termination to accommodate the voltage offset of the data signal source 510. For example, if the data signal source 510 signal amplitude is between ground (GND) and the power - supply voltage, then the termination voltage source is at the power - supply voltage. Other examples include near - ground signaling, where the signal source 510 signal voltage is near GND, and where the voltage source will then be zero, the GND level.

[0117] The circuit model may also include a single - ended signal generator 508, which may represent the circuit of the memory controller die 102 that generates a signal to be transmitted on the single - ended transmission line. As Figure 5 shown, the single - ended signal generator 508 may include a data signal source 510 configured to generate a signal. An example configuration of the data signal source 510 may be a stepped digital signal source, but other configurations may be possible. The data signal source 510 may include a first positive terminal coupled to the signal path 502 and a second negative terminal coupled to the ground path 504. And, as Figure 5 shown the positive terminal may be coupled to the signal path 502 by means of a controller - side resistor R ODT (C), and the controller - side resistor may represent the controller - side termination resistance provided by the memory controller die 102 for the single - ended transmission line.

[0118] To complete, Figure 5 the circuit model of also includes an example single - ended transmission line 511 that connects the memory controller die 102 to the plurality of uniform memory dies 304. The transmission line 511, in combination with the inductive and capacitive transmission - line elements of the uniform memory die 304 shown in Figure 5 it, may represent the complete single - ended transmission line between the memory controller die 102 and the uniform memory die 304.

[0119] And, asFigure 5 As shown, a circuit model of a transmission line coupled to a plurality of input (I / P) circuits 512, the plurality of input circuits including a first input circuit 512(M1), a second input circuit 512(M2), and extending to an Nth input circuit 512(MN). Each input circuit 512 can be a component of a corresponding I / O driver circuit 158( Figure 3 ). In a particular example configuration, the input circuit 512 is configured as a buffer circuit, but other configurations may be possible. Additionally, each input circuit 512 can be an input circuit of a corresponding one of the uniform memory dies 304 configured to receive signals transmitted from the memory controller die 102. Thus, for example, the first input circuit 512(M1) can represent the input circuit of the first die 304(1), the second input circuit 512(M2) can represent the input circuit of the second die 304(2), and the Nth input circuit 512(MN) can represent the input circuit of the Nth die 304(N). In the circuit model, each ith input circuit 512(i) is coupled to a corresponding ith capacitor C(Mi), and includes a first input terminal coupled to the first end of the ith capacitor C(Mi) and the signal path 502, and a second input terminal coupled to the second end of the ith capacitor C(Mi) and the ground path 504.

[0120] In particular, referring to Figure 6 , the differential circuit model can be similar to Figure 5 's single-ended circuit model, except that both the first path 602 and the second path 604 can be signal paths, each configured to propagate a corresponding signal component of a differential signal. The inductive element of the first signal path 602 is labeled LS1 and the inductive element of the second signal path 604 is labeled LS2. In this configuration, the transmission lines disclosed herein can include differential transmission lines.

[0121] As a differential transmission line, the first signal path 602 can be terminated by a first memory-side termination resistor R ODT1 (M) connected to a first voltage source 606(1), to represent a voltage offset for termination to accommodate the voltage offset of the first data signal source 610(1). Similarly, the second signal path 604 can be terminated by a second memory-side termination resistor R ODT2 (M) connected to a second voltage source 606(2), to represent a voltage offset for termination to accommodate the voltage offset of the second data signal source 610(2).

[0122] The circuit model can also include a differential signal generator 608, which can represent the circuit of the memory controller die 102 that generates the signals transmitted on the differential transmission line. As Figure 6As shown, the differential signal generator 608 may include a first data signal source 610(1) configured to generate a first signal component of a differential signal. The first data signal source 610(1) may be coupled to the first signal path 602 by means of a first controller side termination resistor R of the memory controller die 102 ODT2 (C). Additionally, the differential signal generator 608 may include a second data signal source 610(2) configured to generate a second signal component of the differential signal. The second data signal source 610(2) may be coupled to the second signal path 602 by means of a second controller side termination resistor R of the memory controller die 102 ODT2 (C). In some example configurations, the first data signal source 610(1) and the second data signal source 610(2) may be stepped digital signal sources, but other example configurations may be possible.

[0123] For completeness, Figure 6 the circuit model of also includes an example differential transmission line 611 that connects the memory controller die 102 to the plurality of uniform memory dies 304. The transmission line 611 in combination with the inductive and capacitive transmission line elements of the uniform memory die 304 shown in Figure 6 may represent the complete differential transmission line between the memory controller die 102 and the uniform memory die 304.

[0124] Additionally, similar to the single - ended circuit model, the differential transmission line may be coupled to a plurality of input circuits 612, each of which represents an input circuit, such as an input buffer of a respective one of the uniform memory dies 304, and is configured to receive the differential signal transmitted from the differential signal generator 608. Each i - th input circuit 612(Mi) may include a first input terminal coupled to a first end of a respective i - th capacitor C(Mi) and to the first signal path 602, and a second input terminal coupled to a second end of the i - th capacitor C(Mi) and to the second signal path 604.

[0125] Referring to Figure 7 , the single - ended circuit model of the transmission line is similar to Figure 5 the single - ended circuit model of the transmission line of, except that the k - th die 304(k) transmits a signal on the transmission line instead of the memory controller die 102. Similar to Figure 5 the single - ended circuit model of, Figure 7 the transmission line model of includes a first path 702 that may be a single - ended transmission line for the signal path, and a second path 704 that may be a single - ended transmission line for the ground path. Similar to Figure 5 the model of, the inductive component of the signal path 702 is labeled LS and the inductive component of the ground path 704 is labeled LG. As for Figure 5As mentioned, a simpler model can "fold" the inductive component LG of the ground path 704 into the signal path 702. Also, the capacitive components of the uniform memory dies 304C (M1), C (M2), and extending to C (MN) are connected in parallel with the signal path 702 and the ground path 704. Additionally, as Figure 7 shown, the signal path 702 and the ground path 704 are terminated by a memory-side termination resistor R ODT (M) provided by the on-die termination resistor circuit 314 of the uniform memory die 304. The memory-side termination resistor R ODT (M) can be connected to the voltage source 706 to represent a voltage offset for termination, to accommodate the voltage offset of the data signal source of the k-th die 304(k) of the transmitted signal.

[0126] In Figure 7 , since the k-th target die 304(k) is transmitting and the memory controller die 102 is receiving, and thus the model includes that the memory controller die 102 includes an input circuit 708, such as an input buffer, which is configured to receive the signal transmitted on the transmission line from the k-th target die 304(k). The input terminals of the input circuit 708 can be connected across the capacitive element C(C) of the memory controller die 102. The capacitive element can represent the die capacitance provided by the memory controller die 102. Also, the first path 702 and the second path 704 can be terminated by a controller-side termination resistor R ODT (C) provided by the on-die termination resistor of the memory controller die 102. The controller-side termination resistor R ODT (C) can be connected in series with the voltage source 710 to represent a voltage offset for termination, to accommodate the voltage offset of the data signal source of the k-th die 304(k) of the transmitted signal.

[0127] To complete, Figure 7 the circuit model also includes an example single-ended transmission line 711 that connects the memory controller die 102 to the plurality of uniform memory dies 304. The transmission line 611, which is a combination of the inductive and capacitive transmission line elements of the uniform memory die 304 shown in Figure 7 , can represent the complete single-ended transmission line between the memory controller die 102 and the uniform memory die 304.

[0128] And, in Figure 7In this case, it is not the input circuit. The circuit model of the single-ended transmission line is coupled to the output (O / P) circuit 712 located on the uniform memory die 304, including the first output circuit 712(M1) on the first uniform memory die 304(1), the second output circuit 712(M2) on the second uniform memory die 304(2), and the Nth output circuit 712(MN) extending to the Nth uniform memory die 304(N). Each ith output circuit 712(Mi) can be configured to generate and output a single-ended signal on the single-ended transmission line, such as a data signal source (e.g., a stepped digital signal source). As Figure 7 shown, each ith output circuit 712(Mi) includes a first output terminal connected to the first end of the associated capacitive element C(Mi) and the signal path 702, and a second output terminal connected to the second end of the associated capacitive element C(Mi) and the ground path 704.

[0129] Referring to Figure 8 , the differential circuit model is similar to Figure 6 's differential circuit model because it includes a first signal path 802 and a second signal path 804. The inductive element of the first signal path is labeled LS1 and the inductive element of the second signal path is labeled LS2. Additionally, the first signal path 802 is terminated by a first memory-side termination resistor R ODT1 (M) provided by the on-die termination resistor circuit 314 coupled to the first signal path 802 of the differential transmission line, and the second signal path 804 is terminated by a second memory-side termination resistor R ODT2 (M) provided by the on-die termination resistor circuit 314 coupled to the second signal path 804 of the differential transmission line. The memory-side termination resistors R ODT1 (M), R ODT2 (M) are each connected to the corresponding voltage sources 806(1), 806(2) to represent the voltage offsets for termination, in order to accommodate the voltage offsets of the data signal sources of the kth die 304(k) for the transmitted signal.

[0130] Additionally, since the kth target die 304(k) is transmitted on the differential transmission line of the differential model for Figure 8 , the first signal path 802 is also terminated by a first controller-side termination resistor R ODT1 (C) provided by the on-die termination resistor circuit of the memory controller die 102 coupled to the first signal path 802 of the differential transmission line, and the second signal path 804 is terminated by a second controller-side termination resistor R ODT2 (C) provided by the on-die termination resistor circuit of the controller di 102 coupled to the second signal path 804 of the differential transmission line. The controller-side termination resistors R ODT1 (C), RODT2 (C) are each connected to respective voltage sources 808(1), 808(2) to represent voltage offsets for termination to accommodate voltage offsets of the data signal sources of the k-th die 304(k) of the transmitted signal.

[0131] And, similar to Figure 7 the single-ended model of, since the k-th target die 304(k) is in transmission, the memory controller die 102 includes an input circuit 810 configured to receive differential signals, such as an input buffer. The input circuit 810 includes terminals connected across a capacitive element C(C) representing the on-die capacitance of the memory controller die 102, having a first input terminal connected to the first signal path 802 and a second input terminal connected to the second signal path 804.

[0132] To complete, Figure 8 the circuit model of also includes differential transmission lines 711 connecting the memory controller die 102 to the plurality of uniform memory dies 304. Similar to Figure 7 the transmission line 611 which is a combination of inductive and capacitive transmission line elements of the uniform memory die 304 shown in, the differential transmission lines 711 can represent the complete differential transmission line between the memory controller die 102 and the uniform memory die 304.

[0133] Additionally, similar to Figure 7 the single-ended model of, the differential transmission lines are coupled to output circuits 812, each of which is configured to generate and output differential signals on the differential transmission lines, including a first output circuit 812(M1) on the first uniform memory die 304(1), a second output circuit 812(M2) on the second uniform memory die 304(2), and an N-th output circuit 812(MN) extending to the N-th uniform memory die 304(N). Each i-th output circuit 812(Mi) may include output terminals coupled across an associated capacitive element C(Mi) representing the on-die capacitance of the corresponding uniform memory die 304(i), and includes a first terminal connected to the first signal path 802 and a second terminal connected to the second signal path 804.

[0134] Returning to Figure 3 , the characteristic impedance of the transmission lines between the memory controller die 102 and the N number of uniform memory dies 304(1) to 304(N) can be modeled by their inductive and capacitive elements and can be equal to or proportional to the square root of the equivalent inductance of the inductive element divided by the equivalent capacitance of the capacitive element. In some example configurations, it may be necessary to increase the effective inductance in order to increase the characteristic impedance, such as to more closely match the termination resistance of the end die. One way to do this is to increase the inductance of one or more wire bond elements 310 of the transmission line.

[0135] Figure 9 The die stack interconnect model 900 is shown. The memory controller introduced in the previous figures can be modeled as a variable voltage source 902, an impedance 904, and a parasitic capacitance 906. In Figure 3 The transmission path 908, first introduced in

[0136] "Impedance" refers to the measure of opposition that a circuit presents to current when a voltage is applied.

[0137] Quantitatively, the impedance of a two-terminal circuit element is the ratio of the complex representation of the sinusoidal voltage between its terminals to the complex representation of the current flowing through the circuit. Generally speaking, impedance depends on the frequency of the sinusoidal voltage.

[0138] Impedance extends the concept of resistance to alternating current (AC) circuits and has both magnitude and phase, unlike resistance which only has magnitude. Impedance is a complex number with the same units as resistance, where the SI unit is the ohm (Ω). Its symbol is usually Z, and it can be represented by writing its magnitude and phase in polar form as |Z|∠θ. However, the Cartesian complex representation is often more powerful for circuit analysis purposes. (Search "Impedance" on Wikipedia.com, May 31, 2020. Modified. Accessed June 2, 2020.)

[0139] "Characteristic impedance" refers to the ratio of the amplitudes of the voltage and current of a single signal wave propagating along a line; i.e., a wave traveling in one direction in the absence of reflections in the other direction. The characteristic impedance (usually written as Z0) is typically defined with respect to a uniform transmission line. Alternatively, and equivalently, the characteristic impedance can be defined as the input impedance of a transmission line when the length of the transmission line is infinite. The characteristic impedance is determined by the geometry and material of the transmission line and, for a uniform transmission line, does not depend on the length of the uniform transmission line. The SI unit of characteristic impedance is the ohm.

[0140] The characteristic impedance of a lossless transmission line is a pure real number and has no reactive component. The energy supplied by a source at one end of this line is transmitted through the line without being dissipated in the line itself. A finite length of transmission line (lossless or lossy) terminated at one end with an impedance equal to the characteristic impedance behaves like a source similar to an infinitely long transmission line and does not produce reflections. (Search "Characteristic impedance" on Wikipedia.com, May 17, 2020. Modified. Accessed June 2, 2020.)

[0141] "Parasitic capacitance" refers to the inevitable and usually unwanted capacitance that exists between parts of an electronic component or circuit solely due to their physical proximity to each other. When two electrical conductors at different voltages are close together, the electric field between them causes charge to be stored on them; this effect is parasitic capacitance. Circuit elements such as inductors, diodes, and transistors have internal capacitances, which can cause their behavior to deviate from that of an 'ideal' circuit element. Additionally, there is always a non-zero capacitance between two conductors; this parasitic capacitance can be significant at higher frequencies for closely spaced conductors such as wires or printed circuit board traces. (Search "Parasitic capacitance" on Wikipedia.com, March 16, 2020. Modified. Accessed June 2, 2020.)

[0142] In the illustrated die stack interconnect model 900, parasitic capacitance elements 916 and inductance elements 914 represent the interconnections to the first memory die in the die stack. Parasitic capacitance elements 916 and inductance elements 914 represent the connections to the next die in the stack, and so on. Inductance elements 914 and parasitic capacitance elements 916 represent the connections to the end die.

[0143] To match the impedance of the entire transmission path 908 and reduce signal reflections along the path, on-die termination resistor circuits 918 can be provided on multiple uniform memory dies in the die stack that are furthest from the memory controller. In the model of one illustrated embodiment, the four on-die termination resistor circuits 918 of the last four uniform memory dies can be activated to provide distributed on-die electrical termination for the transmission path 908. The impedance of the transmission path 908 can be considered as the aggregation of all the elements along the transmission path 908, including the transmission line characteristic impedance 912, parasitic capacitance, and the inductance shown. Therefore, the on-die termination resistor circuits 918 can be configured to terminate the transmission line effects due to these components.

[0144] Figure 10 A die stack interconnect model 1000 is shown having active die electrical termination 1002. In addition to the on-die termination resistor circuits 918 on multiple uniform memory dies at the end of the transmission path 908 / transmission path 1004 introduced in Figure 9 which cancel the transmission line effects along the entire transmission path 1004 by introducing distributed end die termination resistors, active die electrical termination 1002 can also be provided to cancel additional effects that are induced at a particular memory die when that particular uniform memory die is in active use, such as being read, as the sender of a data signal.

[0145] The active die electrical termination 1002 is often configurable such that it can be turned on or off and / or use a programmable termination resistor. Thus, the active die electrical termination 1002 circuit can be turned on to absorb reflections and other noise at the active die when the die is in use, but can be cut off when the die is not in use to save power and thus not introduce additional reflections along the transmission path 1004. The illustrated active die electrical termination 1002 is associated with a node representing the first memory die in a die stack, and is also characterized as a parasitic capacitance element 916 and an inductance element 914 to model the active die electrical termination 1002 when the first die is in operation. Similar structures can be modeled, having a similar relationship to the parasitic capacitance element 916 and the inductance element 914 to model the active die electrical termination 1002 when the second memory die is in operation, the third memory die is in operation, and so on.

[0146] Figure 11 FIG. 4 illustrates an example memory system 1100 according to one embodiment. A storage controller 1102 is connected to a stack 1104 of homogeneous memory dies that may be grouped within a package 1106. The storage controller 1102 and the homogeneous memory dies 1108 may be connected by a transmission path 1110 that includes transmission lines 1112 on a printed circuit board 1114, on which the storage controller 1102 and the homogeneous memory dies 1108 and / or their package 1106 may be mounted. The transmission path 1110 may also include wire bonds 1116 that serially connect each of the homogeneous memory dies 1108 as illustrated.

[0147] "Homogeneous memory die stack" refers to a group of two or more homogeneous memory dies arranged in a stacked configuration relative to each other. In one embodiment, each member of the group of homogeneous memory dies is positioned directly above or below another homogeneous memory die or substrate.

[0148] In one embodiment, each of the stacked homogeneous memory dies is positioned relative to the other homogeneous memory dies to form a stepped structure, where each homogeneous memory die is one of the "steps" of the step.

[0149] Each homogeneous memory die 1108 may include I / O contact pads 1118 for attaching wire bonds 1116. The I / O contact pads 1118 may be connected to an on-die termination resistor circuit. In certain embodiments, the on-die termination resistor circuit is a programmable resistor circuit 1120. Examples of the programmable resistor circuit 1120 are further shown in Figures 13 - 15 In one embodiment, the programmable resistor circuit 1120 may provide a minimum termination resistance.

[0150] The memory controller 1102 can address a target homogeneous memory die 1122 of the homogeneous memory die stack 1104 for operation. A "target homogeneous memory die" refers to a homogeneous memory die configured to communicate with the memory controller to complete an operation.

[0151] The memory controller 1102 can enable on-die termination resistor circuits of a plurality of homogeneous memory dies 1124 along the transmission path 1110. The memory controller 1102 can then transmit a data signal for an operation to the target homogeneous memory die 1122, where the on-die termination resistor circuits are enabled for the plurality of homogeneous memory dies 1124. In the illustrated example, the plurality of homogeneous memory dies 1124 includes four adjacent homogeneous memory dies located at one end (on the memory side) of the transmission path 1110. In another example, the plurality of homogeneous memory dies 1124 includes two adjacent homogeneous memory dies located at one end (on the memory side) of the transmission path 1110.

[0152] In one embodiment, the memory controller 1102 can transmit data signals at a frequency greater than 1600 Hz. In another embodiment, the homogeneous memory die stack 1104 can include more than four homogeneous memory dies 1108, and the plurality of homogeneous memory dies 1124 enabled for an operation or a part of an operation can include more than two homogeneous memory dies 1108. In one embodiment, the programmable resistor circuit 1120 that enables the plurality of homogeneous memory dies 1124 generates an effective termination resistance 1126 for the transmission path 1110, which is less than the minimum termination resistance of any one of the individual homogeneous memory dies 1108 of the homogeneous memory die stack 1104.

[0153] In some embodiments, the programmable resistor circuit 1120 can be configured to connect to the transmission line 1112 in response to the homogeneous memory die 1108 being powered on and / or enabled (e.g., receiving an enable signal). The programmable resistor circuit 1120 can include a programmable resistor circuit configured to provide a termination resistance during the transmission of a data signal to the target homogeneous memory die 1122.

[0154] In such embodiments, the memory controller 1102 may send a memory command to a target uniform memory die 1122 of the uniform memory die stack 1104 for an operation. A "memory command" refers to any command related to an operation. Examples of memory commands include but are not limited to read commands, write commands, maintenance commands, configuration commands, management commands, diagnostic commands, test mode commands, countermeasure commands, and any other commands that the memory controller may receive from a host or issue to another component, device, or system. Generally speaking, a memory command is a command issued from a host or a master device or another component or device to a storage or memory device. A memory command typically initiates one or more operations.

[0155] An "operation" refers to an operation performed on, within, to, or with respect to a processor, logic component, memory, storage device, and / or storage medium (non-volatile or volatile). Examples of operations include but are not limited to power-on reset operations, firmware initialization operations, data refresh operations, data cleaning operations, garbage collection operations, erase operations, maintenance operations, test mode operations, programmed storage operations, read scan operations, host memory buffer access operations, host memory buffer maintenance operations, cache access operations, computing operations, cache maintenance operations, memory address translation lookup operations, memory address translation cache swap / paging operations, memory commands, and so on. Additional examples of operations include but are not limited to reading data (or sensing its state) from a memory cell, writing (or programming) data to a memory cell, and / or erasing data stored in a memory cell.

[0156] The memory controller 1102 may direct at least four uniform memory dies 1108 along the transmission path 1110 to provide a termination resistance during an operation. The at least four uniform memory dies 1108 may be different from the target uniform memory die 1122, as shown by the plurality of uniform memory dies 1124. The memory controller 1102 may then transmit a plurality of data signals for the operation to the target uniform memory die 1122, where the at least four uniform memory dies 1108 (the plurality of uniform memory dies 1124) generate an effective termination resistance 1126 for the transmission path 1110 during the operation.

[0157] The at least four uniform memory dies 1108 that are guided to provide a termination resistance during operation can provide a distributed termination resistance that substantially matches the characteristic impedance of the transmission line 1112. "Distributed termination resistance" refers to a termination resistance that includes a termination resistance contributed by two or more electronic components along a transmission line or transmission path. In one embodiment where two termination resistance circuits are connected in series as stubs, the two termination resistance circuits contribute a termination resistance to the transmission line or transmission path as if the two termination resistance circuits were connected in parallel in a DC circuit.

[0158] For example, assume that each uniform memory die includes a programmable resistance circuit 1120 configured to provide an electrical termination of no less than 200 ohms (e.g., minimum termination resistance). This means that the additional parasitic capacitance added by each additional uniform memory die is approximately 0.1 pF, which helps to match the impedance from the transmission line to the end of the uniform memory die stack, adding more uniform memory dies to the die stack of uniform memory dies, increasing the bandwidth and / or signal frequency. If the target uniform memory die 1122 is activated by the memory controller 1102 and the programmable resistance circuits 1120 of the plurality of uniform memory dies 1124 are activated / enabled such that each programmable resistance circuit 1120 of the plurality of uniform memory dies 1124 provides a 200-ohm termination resistance, then the effective termination resistance provided by the plurality of uniform memory dies 1124 is 50 ohms, which matches the impedance of the transmission line 1112.

[0159] The programmable resistance circuit 1120 can be configured to provide a range of termination resistances between a minimum termination resistance and a maximum termination resistance. "Minimum termination resistance" refers to the level, value, or amount of the lowest electrical termination resistance or termination impedance that a device, apparatus, circuit, sub-circuit can physically provide when coupled or connected to a transmission line and / or transmission path carrying an electrical signal. "Maximum termination resistance" refers to the highest or maximum electrical termination resistance or termination impedance level, value, or amount that a device, apparatus, circuit, sub-circuit can physically provide when coupled or connected to a transmission line and / or transmission path carrying an electrical signal.

[0160] There is an inverse relationship between the parasitic capacitance contributed to the transmission path by each additional uniform memory die when added to the uniform memory die stack and the amount of on-die termination resistance added to the transmission path by the added uniform memory die. Specifically, the minimum termination resistance added to the transmission path by adding another uniform memory die (when the on-die termination resistance circuit is connected to the transmission path, regardless of whether the on-die termination resistance circuit is activated or powered or enabled) is inversely related to the parasitic capacitance added by the added uniform memory die.

[0161] For example, if the minimum termination resistance for a uniform memory die (including any on-die termination resistance circuitry) is 200 ohms, then the parasitic capacitance contributed by such uniform memory die is 0.1 pF. If the minimum termination resistance for a uniform memory die (including any on-die termination resistance circuitry) is 100 ohms, then the parasitic capacitance contributed by such uniform memory die is 0.2 pF. If the minimum termination resistance for a uniform memory die (including any on-die termination resistance circuitry) is 50 ohms, then the parasitic capacitance contributed by such uniform memory die is 0.4 pF. Thus, to reduce the added parasitic capacitance to support more than 4, 8, or 16 memory dies in a uniform memory die stack, the on-die termination resistance circuitry can be designed to have a minimum termination resistance greater than 100 ohms, or 200 ohms, or even 300 ohms. The disclosed embodiments can be configured to have a predefined minimum termination resistance such that the parasitic capacitance brought by each added uniform memory die remains substantially low.

[0162] Figure 12 Illustrates an example memory system 1200 in accordance with one embodiment. The example memory system 1200 may largely include components introduced and described with respect to Figure 11 and the example memory system 1100.

[0163] In one embodiment, the uniform memory die stack 1104 may include eight uniform memory dies 1108. The plurality of uniform memory dies 1124 may include at least four end dies (die N-3 to die N). The programmable resistance circuitry 1202 of each of the plurality of uniform memory dies 1124 may be programmed to 200 ohms. Thus, each of the plurality of uniform memory dies 1124 may contribute 0.1 pF of parasitic capacitance. However, the programmable resistance circuitry 1202 may be capable of providing a termination resistance as low as 100 ohms. However, because the plurality of uniform memory dies 1124 contribute to the effective termination resistance as if these memory dies were connected in parallel, the effective termination resistance for subtracting the transmission path of the transmission line 1112 is 50 ohms, which substantially matches the impedance of the transmission line 1112.

[0164] Advantageously, the plurality of uniform memory dies 1124 programmed to 200 ohms means that each of the plurality of uniform memory dies 1124 contributes a parasitic capacitance of nominally 0.1 pF. Additionally, each of the uniform memory dies in the uniform memory die stack 1104 is configured to provide a termination resistance not less than a minimum termination resistance (e.g., 100 ohms in the illustrated embodiment, see programmable resistance circuit 1204). As illustrated, the programmable resistance circuit 1204 of a uniform memory die that is not activated / enabled and / or powered on is at least 100 ohms, the minimum termination resistance, and these uniform memory dies contribute a parasitic capacitance of nominally 0.2 pF. In one embodiment, the programmable resistance circuit 1120, programmable resistance circuit 1202, and / or programmable resistance circuit 1204 are programmed, designed, engineered, and / or manufactured to achieve the desired minimum termination resistance. In one embodiment, the termination resistance circuit can be such that the minimum termination resistance is configured to reduce the parasitic capacitance contributed by each of the plurality of uniform memory dies in the uniform memory die stack by 25%.

[0165] The programmable resistance circuits 1202 and 1204 can be configured using a combination of one or more of the active resistance circuit and the passive resistance circuit based on the design and control signals sent from the memory controller 1102, shown here as "CTRL 1", "CTRL 2", etc. to "CTRL N" for each uniform memory die 1108.

[0166] Figure 13 An exemplary arrangement of a programmable resistance circuit 1300 is shown that can be used to reduce mismatch reflections and improve the signal integrity and bandwidth of a high - bandwidth transmission line. The programmable resistance circuit 1300 can be similar in form, capabilities, and operation to the ODT termination resistance circuit 162, programmable resistance circuit 314, programmable resistance circuit 1120, programmable resistance circuit 1202, and / or programmable resistance circuit 1204. "Programmable resistance circuit" refers to a class of on - die termination resistance circuits that include means for changing the termination resistance level based on data values, register settings, logic, and / or how one or more switching components such as transistors are configured. The programmable resistance circuit is configured to provide a variable level of termination resistance. In some embodiments, the programmable resistance circuit increases the termination resistance by activating switches in the circuit to add resistive elements in parallel.

[0167] It should be noted that while the programmable resistance circuit is configured to provide a variable level of termination resistance based on a programmable resistance setting, the physical configuration of the programmable resistance circuit and its electronic components may result in the programmable resistance circuit providing one or more of a minimum termination resistance and a maximum termination resistance.

[0168] "Programmable resistance setting" refers to the value used by a programmable resistance circuit to provide a configurable termination resistance. In one embodiment, the programmable resistance setting defines which switches in a set of switches the programmable resistance circuit will set / activate or reset / deactivate such that the programmable resistance circuit provides a desired level of termination resistance.

[0169] The programmable resistance circuit 1300 may include a set of resistors 1302, including one or more resistive elements 1304, which may be arranged in parallel along a transmission line 1308 between each transmission line 1308 to a power rail 1310, and between the transmission line 1308 and a power reference rail 1312. "Resistive element" refers to an electronic component configured to provide resistance to current passing through the resistive element. Examples of resistive elements include, but are not limited to, resistors, capacitors, transistors, transistors configured to operate in their active regions, and the like. In certain embodiments, each resistive element 1304 may provide a different level of termination resistance relative to other resistive elements 1304 of the set of resistors 1302.

[0170] The memory controller and / or ODT controller 1314 may dynamically and / or individually activate and / or deactivate (open and close) the set of resistors 1302 to tune the termination resistance of the programmable resistance circuit 1300 to match the impedance of the transmission line 1308.

[0171] The set of switches 1306 may be controlled by the ODT controller 1314 to tune the impedance of the transmission line 1308 to the data rate. For example, assume an array of three 100Ω resistors connected in parallel between a typical transmission line and a power reference rail 1312 (e.g., signal ground (GND)). Impedance matching can be performed by switching the resistance between 50Ω and 75Ω on the transmission line. This can be achieved by bistate switching the set of switches 1306 to connect two of the set of resistors 1302 to the power reference rail 1312 to obtain an effective added resistance of 50Ω. This added resistance can attenuate high-frequency noise artifacts from the signal on the transmission line 1308, resulting in a cleaner data transmission. The set of resistors 1302 improves termination alignment and allows transmission at high data rates.

[0172] In one embodiment, the die termination resistor circuit includes an active resistor circuit configured from a shown set of resistors 1302 and a set of switches 1306. "Active resistor circuit" refers to a type of die termination resistor circuit that mainly uses active electronic components. Examples of active electronic components include transistors, diodes, and / or integrated circuits. This die termination resistor circuit can be a programmable resistor circuit, where the ODT controller 1314 sets or releases switches in the set of switches 1306 to configure a variable resistor through the set of resistors 1302. The programmable resistor circuit can include a parallel circuit formed from the set of resistors and the set of switches shown as the set of resistors 1302 and the set of switches 1306.

[0173] "Parallel circuit" refers to a circuit that includes one or more of active electronic components and / or passive electronic components arranged such that at least two of the electronic components are connected in parallel. In some embodiments, the parallel circuit includes a set of resistors configured to be connected in parallel by means of a set of switches.

[0174] This programmable resistor circuit can be activated by a die controller of the plurality of uniform memory dies based on programmable resistor settings stored in registers of the die controller, and the die controller can incorporate a logic structure such as the ODT controller 1314. "Register" refers to a temporary storage location used to store an address or data value used in a computational operation of a processor, circuit, or logic. Some registers can be named based on the type of data normally stored in the register, such as an address register that stores an address, a data register that stores data, or an operand register that stores a value used in a firmware instruction. A register can be implemented with logic gates, flip-flops, SRAM, or the like.

[0175] Figure 14 An exemplary arrangement of a programmable resistor circuit 1400 is shown that can be used to reduce mismatch reflections and improve signal integrity and bandwidth of a high-bandwidth transmission line. The programmable resistor circuit 1400 can be similar to Figure 13 the programmable resistor circuit 1300, except that the transmission line 1308 can be disconnected from the programmable resistor circuit 1400 until one or more of the switches in the set of switches 1402 are activated by the ODT controller 1314.

[0176] The set of switches 1402 selectively couples the set of resistors 1302 connected to the power rail 1310 and the set of resistors 1302 connected to the power reference rail 1312 to the transmission line 1308 itself, as shown. In this way, if the uniform memory die is powered off, not activated, or not enabled, the programmable resistor circuit 1400 can remain disconnected from the transmission line 1308. When the uniform memory die including the programmable resistor circuit 1400 is powered on, enabled, or activated, the ODT controller 1314 can activate one or more of the set of switches 1402 and the set of switches 1306, thereby providing a programmatically determined termination resistance. The on-die termination resistor circuit can include a programmable resistor circuit configured from the illustrated components to provide a termination resistance during the transmission of data signals to the target uniform memory die.

[0177] Figure 15 An exemplary arrangement of a programmable resistor circuit 1500 is shown that can be used to reduce mismatch reflections and improve the signal integrity and bandwidth of high-bandwidth transmission lines. The programmable resistor circuit 1500 can be similar to Figure 13 the programmable resistor circuit 1300 or Figure 14 the programmable resistor circuit 1400. In one embodiment, the set of resistors 1302, the set of switches 1306, and the set of switches 1402 configured by the ODT controller 1314 can include active resistor circuits.

[0178] Figure 15 An embodiment of Figure 13 and Figure 14 differs from an embodiment of

[0179] In addition to the set of resistors 1302 that can be configured to provide a higher resistance through the implementation of the set of switches 1306 and / or the set of switches 1402, the passive resistor circuit 1502 also provides a minimum termination resistance 1504. In one embodiment, the passive resistor circuit 1502 can be connected between the transmission line 1308 and the power rail 1310, and between the transmission line 1308 and the power reference rail 1312, as shown. Since the passive resistor circuit 1502 is always connected to the transmission line 1308, the programmable resistor circuit 1500 provides the minimum termination resistance 1504 based on the configuration of the passive resistor circuit 1502. In one embodiment, the minimum termination resistance 1504 can include a termination resistance of at least 100 Ω and / or not less than 200 Ω.

[0180] Figure 16 FIG. 4 shows a method for providing an electrical termination 1600 for providing transmission line termination according to one embodiment. In block 1602, a storage controller or some other logic component can send a storage command to a target uniform memory die of a uniform memory die stack for operation. The uniform memory die stack can be serially connected to a transmission line using wire bonding to form a transmission path.

[0181] In block 1604, on-die termination resistor circuits of at least four adjacent uniform memory dies along the transmission path can be activated to individually provide an effective termination resistance that is lower than the minimum termination resistance of each of the on-die termination resistor circuits. In one embodiment, this can be performed by the storage controller. The at least four uniform memory dies can be different from the target uniform memory die of block 1602. In one embodiment, the at least four uniform memory dies along the transmission path can be the last uniform memory dies along the transmission path.

[0182] In block 1606, a storage controller or similar logic can transmit a data signal for operation to the target uniform memory die. The at least four uniform memory dies can provide a parallel termination resistance during operation. "Parallel termination resistance" refers to a circuit, device, apparatus, or logic configured to provide a termination resistance by means of a parallel electrical connection to the transmission path.

[0183] It is desirable to understand the foregoing detailed description as an illustration of selected forms and aspects that embodiments of the solution can take. Finally, it should be noted that any aspect of any of the embodiments described herein can be used alone or in combination with each other.

[0184] Within this disclosure, different entities (which may variously be referred to as "units", "circuits", other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This recitation of an [entity] "configured" to [perform one or more tasks] is used herein to refer to a structure (i.e., a physical article such as an electronic circuit). More specifically, this recitation is used to indicate that the structure is arranged to perform one or more tasks during operation. Even if the structure is not currently being operated, the structure may still be referred to as "configured" to perform some task. A "credit assignment circuit configured to assign credits to multiple processor cores" is intended to encompass, for example, an integrated circuit having circuitry that performs such a function during operation, even if the integrated circuit being discussed is not currently in use (e.g., not connected to a power source). Thus, an entity described or recited as "configured" to perform a certain task refers to something physical, such as a device, a circuit, a memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

[0185] The term "configured" is not intended to mean "configurable". For example, although an unprogrammed FPGA is "configurable" to perform some specific function after being programmed, the unprogrammed FPGA would not be considered "configured" to perform that function.

[0186] As used herein, the term "based on" is used to describe one or more factors that affect a determination. This term does not exclude the possibility that additional factors may affect the determination. That is, the determination may be based solely on the specified factors or based on the specified factors and other unspecified factors. Consider the phrase "determine A based on B". This phrase specifies B as a factor for determining A or influencing the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor such as C. This phrase is also intended to encompass embodiments where A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on".

[0187] As used herein, the phrase "responsive to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect. That is, the effect may be responsive solely to those factors, or may be responsive to the specified factors and other unspecified factors. Consider the phrase "perform A responsive to B". This phrase specifies B as a factor that triggers the performance of A. This phrase does not exclude the possibility that A may also be performed responsive to some other factor such as C. This phrase is also intended to encompass embodiments where A is performed responsive solely to B.

[0188] As used herein, unless otherwise stated, the terms "first", "second", etc. are used as labels for the nouns preceding them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, in a register bank having eight registers, the terms "first register" and "second register" can be used to refer to any two of the eight registers, rather than, for example, only logical registers 0 and 1.

[0189] When used in a claim, the term "or" is used in an inclusive sense rather than an exclusive sense. For example, the phrase "at least one of x, y or z" means any one of x, y and z, as well as any combination thereof.

Claims

1. A storage device, comprising: A uniform memory die stack, the uniform memory die stack being coupled to a transmission line through a set of wire bonds, the set of wire bonds connecting each uniform memory die of the uniform memory die stack in series to form a transmission path; Each memory die of the uniform memory die stack includes: An on-die termination resistance circuit, the on-die termination resistance circuit being connected to the transmission line, the on-die termination resistance circuit being configured to provide a minimum termination resistance; and A storage controller, the storage controller being configured to: Address a target uniform memory die of the uniform memory die stack for operation; Enable the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path; and Transmit a data signal for the operation to the target uniform memory die in a case where the on-die termination resistance circuits of the plurality of uniform memory dies are enabled.

2. The storage device according to claim 1, wherein the storage controller is configured to transmit the data signal at a frequency greater than 1600 Hz, and wherein the plurality of uniform memory dies includes four uniform memory dies.

3. The storage device according to claim 1, wherein the uniform memory die stack includes more than four uniform memory dies, and wherein the plurality of uniform memory dies includes more than two uniform memory dies.

4. The storage device according to claim 1, wherein the on-die termination resistance circuit includes a passive resistance circuit.

5. The storage device according to claim 1, wherein the on-die termination resistance circuit includes an active resistance circuit.

6. The storage device according to claim 1, wherein the on-die termination resistance circuit includes a programmable resistance circuit.

7. The storage device according to claim 6, wherein the programmable resistance circuit includes a parallel circuit of a set of resistors and a set of switches, the parallel circuit being configured to be activated by a die controller of the plurality of uniform memory dies based on a programmable resistance setting stored in a register of the die controller.

8. The storage device according to claim 1, wherein the minimum termination resistance is configured such that the parasitic capacitance contributed by each of the uniform memory dies in the uniform memory die stack is reduced by 25%.

9. The storage device according to claim 1, wherein the minimum termination resistance includes a termination resistance of at least 100 ohms.

10. The storage device according to claim 1, wherein the minimum termination resistance includes a termination resistance not less than 200 ohms.

11. The storage device according to claim 1, wherein the plurality of uniform memory dies are positioned adjacent to each other at one end of the transmission path.

12. The storage device according to claim 1, wherein enabling the on-die termination resistance circuits of the plurality of uniform memory dies generates an effective termination resistance for the transmission path, the effective termination resistance being less than the minimum termination resistance of any one of the individual uniform memory dies of the uniform memory die stack.

13. The storage device according to claim 1, wherein the transmission line includes a single-ended transmission line.

14. The storage device according to claim 1, wherein the transmission line includes a differential transmission line.

15. A storage device, comprising: A uniform memory die stack coupled to a transmission line by a set of wire bonds, the set of wire bonds serially connecting each uniform memory die of the uniform memory die stack to form a transmission path; Each uniform memory die of the uniform memory die stack includes: An on-die termination resistance circuit configured to connect to the transmission line when the uniform memory die is powered on, the on-die termination resistance circuit including a programmable resistance circuit configured to provide a termination resistance during transmission of a data signal to a target uniform memory die; and A storage controller configured to: Send a storage command to a target uniform memory die of the uniform memory die stack for an operation; Direct at least four uniform memory dies along the transmission path to provide a termination resistance during a portion of the operation, the at least four uniform memory dies being different from the target uniform memory die; and Transmit a plurality of data signals for the operation to the target uniform memory die, wherein the at least four uniform memory dies generate an effective termination resistance for the transmission path during the operation.

16. The storage device according to claim 15, wherein the uniform memory die stack includes eight uniform memory dies, and the at least four uniform memory dies are programmed to provide a termination resistance of 200 ohms, which is greater than a minimum termination resistance of 100 ohms.

17. The storage device according to claim 15, wherein the at least four uniform memory dies directed to provide a termination resistance during the operation provide a distributed termination resistance substantially matching the characteristic impedance of the transmission line, and wherein the programmable resistance circuit is configured to provide a range of termination resistances between a minimum termination resistance and a maximum termination resistance.

18. A method for a storage device, comprising: Sending a storage command to a target uniform memory die of a uniform memory die stack for an operation, the uniform memory die stack being serially connected to a transmission line by wire bonds to form a transmission path; Activating on-die termination resistance circuits of at least four adjacent uniform memory dies along the transmission path to individually provide an effective termination resistance lower than a minimum termination resistance of each of the on-die termination resistance circuits, the at least four uniform memory dies being different from the target uniform memory die; And Transmitting data signals for the operation to the target uniform memory die, wherein the at least four uniform memory dies provide a shunt termination resistance during the operation.

19. The method according to claim 18, wherein the at least four adjacent uniform memory dies include the last uniform memory die along the transmission path.

20. The method according to claim 18, wherein the die-terminating resistor circuit includes at least one electronic component, the at least one electronic component including hardware configured to provide the minimum termination resistance to the transmission path during operation when the uniform memory die is powered off and connected to the transmission line.

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