Method for forming a semiconductor structure

Abstract

The present disclosure relates to a method for forming a semiconductor structure, comprising: forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cutting pattern including a first cutting feature and a second cutting feature, wherein the first cutting feature and the second cutting feature respectively expose portions of the first and second line features. In a top view, at least one of the first and second cutting features is asymmetrically arranged relative to a central axis of the corresponding first or second line feature. At least one tilted ion implantation is performed to expand the first and second cutting features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the first and second cutting features, respectively, are then removed.

Description

Technical Field

[0001] The present disclosure relates to methods for forming semiconductor structures. Background Art

[0002] Integrated circuit (IC) technology is constantly improving. Such improvements often involve scaling down device geometries to achieve lower manufacturing costs, higher device integration density, higher speeds, and better performance. Photolithography is commonly used to form the components of integrated circuit devices. Typically, an exposure tool passes light through a photomask and focuses the light onto a photoresist layer on a substrate, creating a photoresist layer with an image of the integrated circuit components. The formation of device patterns with smaller dimensions is limited by the resolution of the exposure tool. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a pattern on a substrate, the pattern comprising a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a cutting pattern comprising a first cutting feature and a second cutting feature, the first cutting feature exposing a portion of the first line feature, and the second cutting feature exposing a portion of the second line feature, wherein, in a top view, at least one of the first cutting feature and the second cutting feature is asymmetrically arranged relative to a central axis of the corresponding first line feature or the second line feature; performing at least one tilted ion implantation to enlarge the first cutting feature and the second cutting feature in at least one direction perpendicular to the first direction; removing the portion of the first line feature exposed by the first cutting feature and the portion of the second line feature exposed by the second cutting feature; and removing the photoresist layer.

[0004] According to another embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a pattern on a substrate, wherein the pattern comprises a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a first cutting feature exposing a portion of the first line feature and a second cutting feature exposing a portion of the second line feature, wherein, in a top view, the first cutting feature is asymmetrically arranged relative to a central axis of the first line feature; performing a first tilted ion implantation to expand the first cutting feature and the second cutting feature in a second direction perpendicular to the first direction; removing the portion of the first line feature exposed by the first cutting feature and the portion of the second line feature exposed by the second cutting feature; and removing the photoresist layer.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: etching a patterned target layer to form a pattern on a substrate, wherein the pattern includes a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a first cut feature exposing a portion of the first line feature and a second cut feature exposing a portion of the second line feature, wherein each of the first cut feature and the second cut feature has a first sidewall and a second sidewall extending in the first direction, and a first spacing between the first sidewall of the first cut feature and the first line feature is greater than a spacing between the second sidewall of the first cut feature and the first line feature a second spacing, a first spacing between the first side wall of the second cutting feature and the second line feature is smaller than a second spacing between the second side wall of the second cutting feature and the second line feature, the second side wall of the first cutting feature is adjacent to the second line feature, and the first side wall of the second cutting feature is adjacent to the first line feature; performing a first tilted ion implantation to expand the first cutting feature and the second cutting feature in a second direction perpendicular to the first direction; performing a second tilted ion implantation to expand the first cutting feature and the second cutting feature in a third direction opposite to the second direction; removing a portion of the first line feature exposed by the first cutting feature and a portion of the second line feature exposed by the second cutting feature; and removing the photoresist layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flow chart of an example method for fabricating a semiconductor structure according to some embodiments.

[0008] Figures 2A-8B According to some embodiments, Figure 1 Various views of a semiconductor structure at various stages of fabrication as constructed by a method.

[0009] Figure 9 The effect of ion implantation on the pattern profile of an exemplary cut feature is shown.

[0010] Figures 10A-11C According to the first alternative embodiment, Figure 1Various views of a semiconductor structure at various stages of fabrication as constructed by a method.

[0011] Figures 12A-14C According to the second alternative embodiment, Figure 1 Various views of a semiconductor structure at various stages of fabrication as constructed by a method. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the description below may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0014] Various photolithography techniques can be used to form integrated circuits. Such techniques involve exposing a photoresist layer to a light source through a photomask, thereby forming a pattern in the photoresist layer. Removing areas of the photoresist layer exposes the underlying substrate to an etching process, which is used to transfer the pattern to the underlying substrate. As the pattern formed in the photoresist layer becomes increasingly dense, it becomes difficult to use a single photomask to form the pattern in the photoresist layer because the features are smaller than the resolution of the light source to which the photoresist layer is exposed. Therefore, multiple masks can be used to form features within the pattern.

[0015] In some cases, a target pattern is formed by using both a main pattern and a cutting pattern. The cutting pattern is used to remove features formed by the main pattern from unwanted areas in order to obtain the desired target pattern. As the density of features in the main pattern increases, some cutting features in the cutting pattern may be too close to each other, so when an immersion lithography system is used, a single photomask will not be able to form such a cutting pattern. In some methods, multiple photomasks are used to form the cutting pattern. However, the use of multiple photomasks will increase process errors and manufacturing costs. Extreme ultraviolet (EUV) lithography is known to extend the range of lithography processes to smaller feature sizes and spacings. However, EUV lithography requires very complex reflective optics or mirrors, which greatly increases manufacturing costs.

[0016] In embodiments of the present disclosure, the photolithographic printability of cut features with small pitches is expanded through a pitch relaxation process, in which some cut features are moved apart to increase the distance between them, thereby allowing the cut features to be printed using a single photomask. Ion implantation is then used to increase the size of some cut features to restore the cut margin, thereby ensuring a sufficient cut window. Embodiments of the present disclosure advantageously reduce manufacturing costs and processing errors.

[0017] Figure 1 is a flow chart of a method 100 for fabricating a semiconductor structure 200 according to some embodiments. Figures 2A-8B are various views of the semiconductor structure 200 at various stages of the method 100 according to some embodiments. Figures 2A-8B Method 100 is discussed in detail with reference to semiconductor structure 200 in FIG. In some embodiments, additional operations are performed before, during, and / or after method 100, or some of the operations described are replaced and / or eliminated. In some embodiments, additional features are added to semiconductor structure 200. In some embodiments, some of the features described below are replaced or eliminated. One of ordinary skill in the art will understand that although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

[0018] refer to Figure 1 and Figure 2A-2B , the method 100 includes operation 102 , in which a patterned target layer 204 is formed over a substrate 202 . Figure 2A is a top view of the semiconductor structure after forming a patterned target layer 204 over a substrate 202 , according to some embodiments. Figure 2B It is taken along the line B-B' Figure 2A Cross-sectional view of a semiconductor structure.

[0019] refer to Figure 2A and Figure 2B In some embodiments, substrate 202 is a bulk semiconductor substrate comprising a semiconductor material or a stack of semiconductor materials, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon-doped silicon (Si:C), silicon germanium carbon (SiGeC); or a Group III-V compound semiconductor, such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide phosphide (GaInAsP). In some embodiments, the bulk semiconductor substrate comprises, for example, a single crystalline semiconductor material, such as single crystalline silicon. In some embodiments, substrate 202 is a semiconductor-on-insulator (SOI) substrate comprising a top semiconductor layer formed on an insulator layer (not shown). The top semiconductor layer includes the aforementioned semiconductor materials, such as Si, Ge, SiGe, Si:C, SiGeC; or Group III-V compound semiconductors, including GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInASP. For example, the insulator layer is a silicon oxide layer, etc. The insulator layer is disposed on a base substrate (typically a silicon substrate or a glass substrate). Substrate 202 may also include additional features and / or material layers, such as various isolation features formed in the substrate. In some embodiments, substrate 202 may include various doped regions, such as p-type doped regions and / or n-type doped regions configured and coupled to form various device and functional features. The term "p-type" refers to the addition of impurities that create valence electron deficiencies to an intrinsic semiconductor. Exemplary p-type dopants (i.e., p-type impurities) include, but are not limited to, boron, aluminum, gallium, and indium. The term "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. Exemplary n-type dopants (i.e., n-type impurities) include, but are not limited to, antimony, arsenic, and phosphorus. If the substrate 202 is doped, in some embodiments, the dopant concentration of the substrate is in the range of 1.0×10 14 atoms / cm 3 to 1.0x10 17 atoms / cm 3 , but the dopant concentration can be greater or less. All doping features can be achieved using appropriate processes, such as ion implantation in various steps and techniques. In some embodiments, substrate 202 can include other features, such as shallow trench isolation (STI).

[0020] A patterned target layer 204 is formed over substrate 202. In some embodiments, patterned target layer 204 is the layer that forms the final pattern over substrate 202. In some embodiments, patterned target layer 204 has a thickness in the range of about 5 nm to about 50 nm. If patterned target layer 204 is too thin, it cannot be deposited as a uniform layer. If patterned target layer 204 is too thick, it requires a longer etching time, which increases manufacturing costs. In some embodiments, patterned target layer 204 is formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), atomic layer CVD (ALCVD), or spin coating. In some embodiments, patterned target layer 204 is formed by converting a surface portion of substrate 202 using a thermal oxidation or nitridation process. In some embodiments, patterned target layer 204 includes one or more dielectric materials, such as silicon oxide (SiO2) and / or silicon nitride (Si3N4). In some embodiments, patterned target layer 204 includes one or more metal materials. In some embodiments, the patterned target layer 204 is an upper portion of the substrate 202 and includes one or more semiconductor materials.

[0021] refer to Figure 1 and Figure 3A-Figure 3B , the method 100 proceeds to operation 104 , where the patterning target layer 204 is patterned to form a main pattern 210 . Figure 3A After the patterning target layer 204 is patterned to form the main pattern 210 on the substrate 202 according to some embodiments Figure 2A and Figure 2B A top view of a semiconductor structure. Figure 3B It is taken along the line B-B' Figure 3A Cross-sectional view of a semiconductor structure.

[0022] refer to Figure 3A and Figure 3B , the main pattern 210 includes a plurality of line features 212, 214, 216, 218 extending in a first direction (e.g., X direction). The line features 212, 214, 216, 218 are spaced apart from each other in a second direction (e.g., Y direction which is different from the first direction (X direction)). In some embodiments, the first direction (i.e., X direction) is a horizontal direction, and the second direction (i.e., Y direction) is a vertical direction. Although in Figure 3A, four line features 212, 214, 216, 218 are shown and described, but any number of line features is contemplated. Furthermore, while line features 212, 214, 216, 218 are shown as rectangular lines, this is not required for some embodiments, and line features of any shape are contemplated. In some embodiments, line features 212, 214, 216, 218 are dummy features and are removed at a subsequent manufacturing stage. In some embodiments, line features 212, 214, 216, 218 are functional features, such as semiconductor fins or metal lines.

[0023] Line features 212, 214, 216, 218 can be formed to have the same or different widths (one or more). In some embodiments, line features 212, 214, 216, 218 are formed to correspond to, for example, an active area in a static random access memory (SRAM) cell. Therefore, the outer line features (i.e., line features 212 and 218) are formed to be wider than the inner line features (i.e., line features 214 and 216), and the spacing between the two inner line features (i.e., line features 214 and 216) is smaller than the spacing between the inner line features (i.e., line features 214 and 216) and the corresponding adjacent outer line features (i.e., line features 212 and 218). In some embodiments, each outer line feature 212, 218 has a width of 15.5 nm, and each inner line feature 214, 216 has a width of 8 nm. In some embodiments, the pitch between the inner line features 214 , 216 is about 32 nm, and the pitch between the inner line feature 216 and the outer line feature 218 is about 39 nm.

[0024] As integrated circuit feature sizes continue to shrink, the spacing and critical dimensions of line features 212, 214, 216, and 218 also shrink. In some embodiments, the spacing between adjacent internal line features (i.e., line features 214 and 216) is between 20 nm and 40 nm. As used herein, the term "pitch" is the distance between identical points in two adjacent features. In some cases, the spacing can be considered the distance from the center of one feature to the center of another adjacent feature.

[0025] The patterned target layer 204 can be patterned by any suitable method. In some embodiments, the patterned target layer 204 is patterned using a single photolithography process. In some embodiments, a first photoresist layer (not shown) is applied over the patterned target layer 204. In some embodiments, the first photoresist layer includes a chemical that is sensitive to light, such as UV light. In some embodiments, the first photoresist layer includes one or more organic polymer materials. In some embodiments, the deposition of the first photoresist layer includes a spin coating process and can be followed by a baking process. In some embodiments, the first photoresist layer is formed to have a thickness in the range of about 30 nm to about 100 nm, although smaller or larger thicknesses may also be used.

[0026] The first photoresist layer is then patterned using a photolithography process. In some embodiments, patterning the first photoresist layer includes exposing the first photoresist layer to radiation, post-exposure baking, developing the first photoresist layer in a resist developer, and hard baking, thereby removing the exposed portions if the first photoresist layer is a positive resist (or removing the unexposed portions if the first photoresist layer is a negative resist), thereby leaving the unexposed portions as a resist pattern on the patterned target layer 204. The resist pattern corresponds to the main pattern 210 to be formed in the patterned target layer 204. In some embodiments, the photolithography process may alternatively employ other suitable techniques, such as electron beam direct writing.

[0027] The patterned first photoresist layer is then used as an etching mask to transfer the pattern in the first photoresist layer to the patterned target layer 204. In some embodiments, one or more anisotropic etching processes are used to remove areas of the patterned target layer 204 not covered by the patterned first photoresist layer, thereby leaving areas corresponding to the main pattern 210 in the patterned target layer 204. In some embodiments, the one or more anisotropic etching processes include a dry etching process (e.g., a plasma etching process or a reactive ion etching (RIE) process), a wet etching process, or a combination thereof. In some embodiments, the anisotropic etching process includes using an etching gas including at least one of carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), other suitable etching gases, or a combination thereof.

[0028] After forming the main pattern 210 in the patterned target layer 204, the patterned first photoresist layer is removed. In some embodiments, the patterned first photoresist layer is removed by a wet stripping process, a plasma ashing process, other suitable methods, and / or combinations thereof. In some embodiments, the plasma ashing process includes using a gas including at least one of oxygen (O2), carbon dioxide (CO2), nitrogen (N2), hydrogen (H2), or a combination thereof.

[0029] In some embodiments, the patterned target layer 204 is patterned using two or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-aligned processes, allowing for the creation of patterns having, for example, a pitch smaller than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over the patterned target layer 204 and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the patterned target layer 204 to form the main pattern 210.

[0030] refer to Figure 1 and Figure 4A-4B , the method 100 proceeds to operation 106 where a second photoresist layer 220 is deposited over the substrate 202 to cover the main pattern 210 . Figure 4A According to some embodiments, after depositing a second photoresist layer 220 on the substrate 202 to cover the main pattern 210 Figure 3A and Figure 3B A top view of a semiconductor structure. Figure 4B It is taken along the line B-B' Figure 4A Cross-sectional view of a semiconductor structure.

[0031] refer to Figure 4A and Figure 4BA second photoresist layer 220 is formed over the main pattern 210 and the substrate 202. In some embodiments, the second photoresist layer 220 includes a chemical that is sensitive to light, such as UV light. In some embodiments, the second photoresist layer 220 includes one or more organic polymer materials. In some embodiments, the second photoresist layer 220 includes a material substantially similar to that of the first photoresist layer. In some embodiments, the deposition of the second photoresist layer 220 includes a spin coating process, which may be followed by a baking process. In some embodiments, the second photoresist layer 220 is formed to completely fill the spaces between the line features 212, 214, 216, and 218 of the main pattern 210. Thus, the top surface of the second photoresist layer 220 is located above the top surfaces of the line features 212, 214, 216, and 218. In some embodiments, the thickness of the second photoresist layer 220 ranges from approximately 10 nm to approximately 100 nm, although smaller or larger thicknesses may also be employed.

[0032] refer to Figure 1 and Figure 5A-5B , the method 100 proceeds to operation 108 , where the second photoresist layer 220 is patterned to form a patterned second photoresist layer 222 including a cutting pattern 230 . Figure 5A According to some embodiments, after patterning the second photoresist layer 220 to form the patterned second photoresist layer 222 including the cutting pattern 230 Figure 4A and Figure 4B A top view of a semiconductor structure. Figure 5B It is taken along the line B-B' Figure 5A Cross-sectional view of a semiconductor structure.

[0033] refer to Figure 5A and Figure 5B, the cutting pattern 230 includes a plurality of cutting features, such as cutting features 232, 234, 236 that overlay the main pattern 210. The cutting features 232, 234, 236 are intended to remove unnecessary portions of the line features 212, 214, 216, 218 so that the circuit associated with the resulting target pattern will function properly. In some embodiments, the cutting features 232, 234, 236 are formed to expose portions of the internal line features (i.e., line features 214, 216), which will be removed in the following operations according to the design specifications. In some embodiments, the cutting features 232, 234, 236 are grooves extending through the second photoresist layer 220. In some embodiments, the cutting pattern 230 includes: a first cutting feature 232 that exposes a first portion of the line feature 214; a second feature 234 that is adjacent to the first feature 232 and exposes a second portion of the line feature 214; and a third feature 236 that exposes a portion of the line feature 216. Although in Figure 5A Three cutting features 232, 234, 236 are shown and described in FIG, but any number of cutting features is contemplated in the present disclosure. Figure 5A As shown, first cut feature 232 includes opposing sidewalls 232A, 232B, wherein sidewall 232A extends into the space between closely spaced linear features 214 and 216, while sidewall 232B extends into the space between widely spaced linear features 212 and 214. Second cut feature 234 includes opposing sidewalls 234A, 234B, wherein sidewall 234A extends into the space between closely spaced linear features 214 and 216, while sidewall 234B extends into the space between widely spaced linear features 212 and 214. Third cut feature 236 includes opposing sidewalls 236A, 236B, wherein sidewall 236A extends into the space between closely spaced linear features 214 and 216, while sidewall 236B extends into the space between widely spaced linear features 216 and 218.

[0034] In some embodiments, a single direct photolithography process is performed to pattern the second photoresist layer 220 to form the cut features 232, 234, 236. In some embodiments, the photolithography process includes exposing the second photoresist layer 220 to a light source using a photomask, performing a post-exposure bake process, and developing the second photoresist layer 220 to form the cut features 232, 234, 236 in the second photoresist layer 220. The cut features 232, 234, 236 can be formed in any shape, such as a square, rectangle, circle, or oval. In some embodiments, as Figure 5BAs shown, the cut features 232, 234, 236 are formed with substantially vertical sidewalls. In some other embodiments, the cut features 232, 234, 236 are formed with angled sidewalls (not shown). In some embodiments, the cut features 232, 234, 236 are formed to have the same size. In some embodiments, the cut features 232, 234, 236 are formed to have different sizes.

[0035] Like all features in an integrated circuit, the cut features 232, 234, 236 must conform to design rules and other constraints. To be formed using a single exposure with a single photomask at a given technology node, thereby eliminating the need for multiple photomasks or expensive EUV lithography, the spacing between each pair of adjacent cut features 232, 234, 236 must be greater than the minimum spacing achievable using a single lithography process at the given technology node. For example, the first spacing P1 between the first cut feature 232 and the third cut feature 236 and the second spacing P2 between the second cut feature 234 and the third cut feature 236 need to be greater than the minimum spacing for a single lithography process. To provide a sufficient lithography window, the cut features 232, 234, 236 are formed in a relaxed-pitch arrangement with a relatively large spacing. This can be accomplished by shifting at least one cut feature 232, 234, and / or 236 in the cut pattern 230 along the Y direction to increase the distance between adjacent cut features 232, 234, 236. Therefore, the spacing P1 and / or P2 between adjacent cut features 232, 234, 236 can be increased, thereby allowing the cut features 232, 234, 236 to be formed by a single photolithography process using a single photomask. Figure 5A As shown, cut features 232, 234 move in the positive Y direction toward outer line feature 212, while cut feature 236 moves in the negative Y direction toward outer line feature 218. As a result, spacing P1 between cut features 232 and 236 and spacing P2 between cut features 234 and 236 are relaxed.

[0036] Due to the relaxed spacing, the cut features 232, 234, and 236 are asymmetrically arranged relative to the respective central axes of the line features 214 and 216. For example, the first cut feature 232 is asymmetrically arranged relative to the central axis C1 of the line feature 214 extending along the X-direction, such that the sidewall 232A of the first cut feature 232 is positioned closer to the line feature 214 than the opposing sidewall 232B. Consequently, the spacing D1 between the sidewall 232A of the first cut feature 232 and the line feature 214 is smaller than the spacing D2 between the opposing sidewall 232B of the first cut feature 232 and the line feature 214. Similarly, the second cut feature 234 is asymmetrically arranged relative to the central axis C1 of the line feature 214, such that the sidewall 234A of the second cut feature 234 is positioned closer to the line feature 214 than the opposing sidewall 234B. Therefore, a spacing D3 between the sidewall 234A of the second cut feature 234 and the line feature 214 is smaller than a spacing D4 between the opposite sidewall 234B of the second cut feature 234 and the line feature 214. The third cut feature 236 is asymmetrically arranged relative to a central axis C2 of the line feature 216 extending along the X-direction, such that the sidewall 236B of the third cut feature 236 is positioned closer to the line feature 216 than the opposite sidewall 236A. Therefore, a spacing D5 between the sidewall 236B of the third cut feature 236 and the line feature 216 is smaller than a spacing D6 between the opposite sidewall 236A of the third cut feature 236 and the line feature 216.

[0037] Despite Figure 5A and Figure 5B In the illustrated embodiment, both cutting features in a pair of adjacent cutting features 232 and 236 or 234 and 236 are moved in the positive or negative Y direction to relax the spacing P1 or P2, but it is contemplated that P1 or P2 can be relaxed by moving only one cutting feature in the adjacent cutting feature pair (e.g., cutting features 232 and 236 or cutting features 234 and 236) to provide the desired distance between the adjacent cutting features (cutting features 232 and 236 or cutting features 234 and 236).

[0038] However, in some embodiments, the narrow spacing between one sidewall 232A, 234A, 236B of each cutting feature 232, 234, 236 and the corresponding line feature 214, 216 does not provide sufficient cutting budget for the subsequent etching process. The cutting features 232, 234, 236 must be enlarged to ensure sufficient cutting budget for the subsequent etching process.

[0039] refer to Figure 1 and Figure 6A-Figure 6BThe method 100 proceeds to operation 110 where a first tilted ion implantation process is performed to implant ions 240 into the sidewalls 232B, 234B, 236B of the respective cut features 232 , 234 , 236 . Figure 6A According to some embodiments, after performing a first tilted ion implantation process to implant ions 240 into the sidewalls 232B, 234B, 236B of the corresponding cut features 232, 234, 236 Figure 5A and Figure 5B A top view of a semiconductor structure. Figure 6B It is taken along the line B-B' Figure 6A Cross-sectional view of a semiconductor structure.

[0040] refer to Figure 6A and Figure 6B ions 240 having a first implantation direction are directed toward the sidewalls 232B, 234B, 236B of the corresponding cut features 232, 234, 236. An incident angle θ1 of the ions 240 (defined as the angle between the ions 240 and a normal to the top surface of the substrate 202) is selected such that the sidewalls 232B, 234B, 236B on the first side of the cut features 232, 234, 236 are exposed to the ions 240, while the sidewalls 232A, 234A, 236A on the second side of the cut features 232, 234, 236 are substantially not exposed to the ions 240. In this manner, the ion implantation process does not require any additional masking steps and therefore does not incur any additional manufacturing costs. In some embodiments, the incident angle θ1 can be achieved by placing the substrate 102 on a platform and tilting the platform to tilt the substrate 102. In some embodiments, the platform can be tilted at an angle between about 5 degrees and about 60 degrees. During the first angled ion implantation, ions 240 impact the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236 to sputter the photoresist from the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236, resulting in localized removal of the photoresist from the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236. After the first angled ion implantation, the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236 may be substantially vertical or angled or have an hourglass profile.

[0041] Since the photoresist is partially removed from the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236, the cut features 232, 234, 236 are enlarged in the positive Y direction so that the sidewalls 232B, 234B, 236B of the cut features 232, 234, 236 are positioned away from the respective line features 214, 216. The narrow spacing between the sidewall 236B of the cut feature 236 and the line feature 216 is thereby increased, which allows the undesired portion of the line feature 216 to be easily removed.

[0042] Exemplary ions 240 that can be used in the present disclosure include noble gas ions such as helium, neon, argon, krypton, xenon, and radon ions. In some embodiments, argon ions are used. The ion energy and dose of the ions 240 are adjusted to control the degree of end-push of the cut features 232, 234, 236. The ion energy can be about hundreds of eV or greater. In some embodiments, the ions 240 are charged at an energy of about 0.5 keV to about 20 keV and a charge of about 1.0×10 14 ions / cm 2 to 8.0×10 18 ions / cm 2 dose implantation, but smaller and larger ion energies and doses can be used.

[0043] The incident angle, energy, and / or dose of the ions 240 may be controlled to control the amount of photoresist removed from the sidewalls 232B, 234B, 236B of the respective diced features 232 , 234 , 236 .

[0044] refer to Figure 1 and Figure 7A-7B The method 100 proceeds to operation 112 where a second tilted ion implantation process is performed to implant ions 242 into the sidewalls 232A, 234A, 236A of the respective cut features 232 , 234 , 236 . Figure 7A After performing a second tilted ion implantation process to implant ions 242 into the sidewalls 232A, 234A, 236A of the corresponding cut features 232, 234, 236 according to some embodiments Figure 6A and Figure 6B A top view of a semiconductor structure. Figure 7B It is taken along the line B-B' Figure 7A Cross-sectional view of a semiconductor structure.

[0045] refer to Figure 7A and Figure 7Bions 242 having a second implantation direction are directed toward the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236. An incident angle θ2 of the ions 242 (defined as the angle between the ions 242 and a normal to the top surface of the substrate 202) is selected such that the sidewalls 232A, 234A, 236A on the second side of the cut features 232, 234, 236 are exposed to the ions 242, while the sidewalls 232B, 234B, 236B on the first side of the cut features 232, 234, 236 are substantially not exposed to the ions 242. In this manner, the second ion implantation process advantageously does not require any additional masking steps and therefore does not incur any additional manufacturing costs. In some embodiments, the incident angle θ2 can be achieved by placing the substrate 102 on a platform and tilting the platform to tilt the substrate 102. In some embodiments, the platform can be tilted at an angle between about 5 degrees and about 60 degrees. During the second angled ion implantation, ions 242 impact the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236 to sputter the photoresist from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236, resulting in localized removal of the photoresist from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236. After the second angled ion implantation, the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236 may be substantially vertical or angled or have an hourglass profile.

[0046] Since the photoresist is removed from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236, the cut features 232, 234, 236 are enlarged in the negative Y direction so that the sidewalls 232A, 234A, 236A of the cut features 232, 234, 236 are positioned away from the respective line features 214, 216. Each narrow spacing between the sidewalls 232A, 234A of the respective cut features 232, 234 and the line feature 214 is thereby increased, which allows undesired portions of the line feature 214 to be easily removed.

[0047] Exemplary ions 242 that can be used in the present disclosure include noble gas ions such as helium, neon, argon, krypton, xenon, and radon ions. In some embodiments, argon ions are used. The ion energy can be about several hundred eV or greater. In some embodiments, the ions 242 are generated at an energy of about 0.5 keV to about 20 keV and a charge of about 1.0×10 14 ions / cm 2 to 8.0×10 18 ions / cm 2 dose implantation, but smaller and larger ion energies and doses can be used.

[0048] The incident angle, energy, and / or dose of the ions 242 can be controlled to control the amount of photoresist removed from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236. In some embodiments, the conditions of the second ion implantation (e.g., the incident angle, energy, and / or dose of the ions 242) can be selected to allow for more photoresist to be removed by the second angled ion implantation compared to the first angled ion implantation. In some embodiments, the conditions of the second ion implantation (e.g., the incident angle, energy, and / or dose of the ions 242) can be selected to allow for less photoresist to be removed by the second angled ion implantation compared to the first angled ion implantation.

[0049] By using the directional end push of the tilted implant process to expand the size of the cut features 232, 234, 236, the cut margin reduced by the pitch relaxation operation is restored. In some embodiments, the total amount of end-to-end push (i.e., size increase) after the first tilted implant and the second tilted implant can be about 3 nm to about 8 nm. As a result, the cut process window for subsequent etching processes is improved.

[0050] In some embodiments, the cut features 232, 234, 236 may have an oval shape, which may result in uneven cutting during a subsequent cutting process. It has been shown that the tilted ion implantation process also helps improve the pattern profile of the cut features 232, 234, 236, and that after the ion implantation process, the profiles of the cut features 232, 234, 236 are closer to a rectangle, which helps improve the uniformity of subsequent etching.

[0051] exist Figure 9 The effect of the tilted ion implantation process on the pattern profile of the exemplary cut features is shown in FIG. Curve 1 represents the pattern profile of an elliptical cut feature with a critical dimension (CD) of 55 nm without ion implantation. Curve 2 represents the pattern profile of the elliptical cut feature with a CD of 55 nm after ion implantation. Curve 3 represents the pattern profile of an elliptical cut feature with a CD of 64 nm without ion implantation. Curve 4 represents the simulation results of a rectangular cut pattern with a CD of 64 nm. Figure 9 It can be seen that the ion implantation process not only expands the CD of the cut features, but also causes the pattern profile of the cut features to be closer to a rectangle, which is ideal for achieving uniform etching.

[0052] refer to Figure 1 and Figure 8A-8B , the method 100 proceeds to operation 114 where portions of the line features 214 , 216 exposed by the cut features 232 , 234 , 236 are removed. Figure 8Ais after removing portions of the line features 214, 216 exposed by the cut features 232, 234, 236 according to some embodiments Figure 7A and Figure 7B A top view of a semiconductor structure. Figure 8B It is taken along the line B-B' Figure 8A Cross-sectional view of a semiconductor structure.

[0053] refer to Figure 8A and Figure 8B , one or more etching processes are used to remove portions of the line features 214, 216 exposed by the cut features 232, 234, 236. In some embodiments, the one or more etching processes include a dry etching process (e.g., a plasma etching process or RIE), a wet etching process, or a combination thereof, so that the corresponding portions of the line features 214, 216 can be selectively etched without affecting the substrate 202. In some embodiments, the etching process includes using an etching gas including at least one of the following: carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), other suitable etching gases, or a combination thereof. In some embodiments, the etching process can use a solution such as tetramethylammonium hydroxide (TMAH), hydrofluoric acid (HF), HF / HNO3 / CH3COOH solution, NH4OH, potassium hydroxide (KOH), or other suitable solutions.

[0054] Thus, line feature 214 is cut by cutting features 232, 234, thereby forming segmented line features 214A, 214B, and 214C that are spaced apart from one another. Similarly, line feature 216 is cut by cutting feature 236, thereby forming segmented line features 216A and 216B that are spaced apart from one another. The resulting segmented line features 214A-214C, 216A, and 216B, together with line features 212 and 218, constitute target pattern 250.

[0055] After etching, the second photoresist layer 222 is subsequently removed. In some embodiments, the patterned second photoresist layer 222 is removed by a wet stripping process, a plasma ashing process, other suitable methods, and / or combinations thereof. In some embodiments, the plasma ashing process includes using a gas including at least one of oxygen (O2), carbon dioxide (CO2), nitrogen (N2), hydrogen (H2), or a combination thereof.

[0056] In some embodiments, segmented line features 214A-214C, 216A, 216B and line features 212, 218 represent a plurality of fins for forming a FinFET. In some embodiments, segmented line features 214A-214C, 216A, 216B and line features 212, 218 are dummy features and are used as an etch mask to pattern substrate 202, thereby forming a plurality of fins in an upper portion of substrate 202 for forming a FinFET.

[0057] In various embodiments, relevant CMOS processing can be used to continue processing operations and form suitable p-type and n-type FinFET devices utilizing fins. For example, a first gate structure can be formed over a portion of a first set of fins, and a first source / drain region including a dopant of n-type conductivity can be formed on an opposite side of the first gate structure to provide an n-type FinFET. A second gate structure can be formed over a portion of a second set of fins, and a second source / drain region including a dopant of p-type conductivity can be formed on an opposite side of the second gate structure to provide a p-type FinFET. The gate structures can be formed using a gate-first or gate-last process known in the art. Each gate structure can include a gate dielectric and a gate conductor.

[0058] Figures 10A-11C 1 are various views of intermediate stages in the formation of a semiconductor structure 200 according to a first alternative embodiment. Unless otherwise noted, the materials and formation processes of the components in the first alternative embodiment are substantially the same as those of their similar components. Figures 2A-8B In the illustrated embodiment, the same reference numerals are used to designate them. Figures 2A-8B A discussion of the illustrated embodiments can be found in Figures 10A-11C Details of the component formation process and materials are shown.

[0059] The initial steps of the first alternative embodiment are substantially similar to Figures 2A-4B The initial step in the process. Operation 102 is performed, in which a patterned target layer 204 ( Figure 2A and Figure 2B Next, operation 104 is performed in which the patterning target layer 204 is patterned to form a main pattern 210 including line features 212, 214, 216, 218 ( Figure 3A and Figure 3B Next, operation 106 is performed in which a second photoresist layer 220 is deposited on the main pattern 210 ( Figure 4A and Figure 4B). Next, operation 108 is performed in which the second photoresist layer 220 is patterned to form a patterned second photoresist layer 222 including a cutting pattern 230.

[0060] Figures 10A-10C Various views of the semiconductor structure are shown after operation 108 . Figure 10A According to some embodiments, after patterning the second photoresist layer 220 to form the patterned second photoresist layer 222 including the cutting pattern 230 Figure 4A and Figure 4B A top view of a semiconductor structure. Figure 10B It is taken along the line B-B' Figure 10A Cross-sectional view of a semiconductor structure. Figure 10C It is taken along the line C-C' Figure 10A Cross-sectional view of a semiconductor structure.

[0061] refer to Figures 10A-10C , the cutting pattern 230 includes a plurality of cutting features, such as cutting features 232, 234, 236 covering the main pattern 210. Figure 5A and Figure 5B The embodiment shown is different in that all three cutting features 232, 234, 236 need to be moved away from the corresponding outer line features 212, 218 to relax the spacing P1 between the cutting features 232 and 236, and the spacing P2 between the cutting features 234 and 236. Figures 10A-10C In the illustrated first alternative embodiment, the first and second cut features 232, 234 covering the line feature 214 need only be moved away from each other in the positive Y direction toward the outer line feature 212 to provide sufficient spacing between each cut feature pair (i.e., cut features 232 and 236, or cut features 234 and 236). This allows a single photomask to be used when forming these cut features 232, 234, 236. Consequently, the distance D1 between the sidewall 232A of the first cut feature 232 and the line feature 214, and the distance D3 between the sidewall 234A of the second cut feature 234 and the line feature 214, remain small, which does not provide sufficient cut budget for subsequent etching processes. In contrast, the distance D5 between the sidewall 236B of the third cut feature 236 and the line feature 216 (which is greater than distances D1 or D3) is sufficiently large to provide sufficient cut budget for subsequent etching processes. Therefore, only a single ion implantation process is required to push the ends of each cut feature 232, 234 along the negative Y direction so that the sidewalls 232A, 234A of the corresponding cut features 232, 234 can be further away from the line feature 214. No ion implantation process is required to push the ends of the cut features along the positive Y direction because the sidewalls 236B of the cut feature 236 are sufficiently away from the line feature 216. Therefore, operation 110 is omitted.

[0062] Next, operation 112 is performed in which a tilted ion implantation process is performed to implant ions 242 into the sidewalls 232A, 234A, 236A of the respective cut features 232 , 234 , 236 . Figure 11A After performing an angled ion implantation process to implant ions 242 into the sidewalls 232A, 234A, 236A of the corresponding cut features 232, 234, 236 according to some embodiments Figures 10A-10C A top view of a semiconductor structure. Figure 11B It is taken along the line B-B' Figure 11A Cross-sectional view of a semiconductor structure. Figure 11C It is taken along the line C-C' Figure 11A Cross-sectional view of a semiconductor structure.

[0063] refer to Figures 11A-11C , ions 242 are directed toward the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236. The angle of incidence of the ions 242 (which is defined as the angle between the ions 242 and a normal to the top surface of the substrate 202) is selected such that the sidewalls 232A, 234A, 236A on the second side of the cut features 232, 234, 236 are exposed to the ions 242, while the sidewalls 232B, 234B, 236B on the first side of the cut features 232, 234, 236 are not substantially exposed to the ions 242. In this manner, the ion implantation process advantageously does not require any additional masking steps and, therefore, does not incur any additional manufacturing costs. During the tilted ion implantation, ions 242 impact the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236 to sputter the photoresist off the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236, thereby resulting in localized removal of the photoresist from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236.

[0064] Since the photoresist is removed from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236, the cut features 232, 234, 236 are enlarged in the negative Y direction so that the sidewalls 232A, 234A, 236A of the cut features 232, 234, 236 are positioned away from the respective line features 214, 216. Each narrow spacing between the sidewalls 232A, 234A of the respective cut features 232, 234 and the line feature 214 is thereby increased, which allows undesired portions of the line feature 214 to be easily removed.

[0065] By enlarging the size of the cut features 232, 234 using the directional tip push of the tilted implant process, the cut margin reduced by the pitch relaxation operation is restored. As a result, the cut process window for the subsequent etching process is improved.

[0066] Next, operation 114 is performed in which portions of the line features 214, 216 exposed by the cut features 232, 234, 236 are removed to provide the semiconductor structure 200 ( Figure 8A and Figure 8B ).

[0067] In various embodiments, relevant CMOS processing can be used to continue processing operations and form suitable p-type and n-type FinFET devices utilizing fins. For example, a first gate structure can be formed over a portion of a first set of fins, and a first source / drain region including a dopant of n-type conductivity can be formed on an opposite side of the first gate structure to provide an n-type FinFET. A second gate structure can be formed over a portion of a second set of fins, and a second source / drain region including a dopant of p-type conductivity can be formed on an opposite side of the second gate structure to provide a p-type FinFET. The gate structures can be formed using a gate-first or gate-last process known in the art. Each gate structure can include a gate dielectric and a gate conductor.

[0068] Figures 12A-14C 1 are various views of intermediate stages in the formation of a semiconductor structure 200 according to a second alternative embodiment. Unless otherwise noted, the materials and formation processes of the components in the second alternative embodiment are substantially the same as those of their similar components. Figures 2A-8B In the illustrated embodiment, the same reference numerals are used to designate them. Figures 2A-8B A discussion of the illustrated embodiments can be found in Figures 12A-14C Details of the component formation process and materials are shown.

[0069] The initial steps of the second alternative embodiment are substantially similar to Figures 2A-4B The initial step in the process. Operation 102 is performed, in which a patterned target layer 204 ( Figure 2A and Figure 2B Next, operation 104 is performed in which the patterning target layer 204 is patterned to form a main pattern 210 including line features 212, 214, 216, 218 ( Figure 3A and Figure 3B Next, operation 106 is performed in which a second photoresist layer 220 is deposited on the main pattern 210 ( Figure 4A and Figure 4B). Next, operation 108 is performed in which the second photoresist layer 220 is patterned to form a patterned second photoresist layer 222 including a cutting pattern 230.

[0070] Figures 12A-12C Various views of the semiconductor structure are shown after operation 108 . Figure 12A According to some embodiments, after patterning the second photoresist layer 220 to form the patterned second photoresist layer 222 including the cutting pattern 230 Figure 4A and Figure 4B A top view of a semiconductor structure. Figure 12B It is taken along the line B-B' Figure 12A Cross-sectional view of a semiconductor structure. Figure 12C It is taken along the line C-C' Figure 12A Cross-sectional view of a semiconductor structure.

[0071] refer to Figures 12A-12C , the cutting pattern 230 includes a plurality of cutting features, such as cutting features 232, 234, 236, which overlap the main pattern 210. The cutting features 232, 234, 236 are positioned to relax the spacing requirements so that they can be manufactured using a single photomask. Figure 12A As shown, the cut features 232, 234, and 236 are positioned such that the distance S1 between the sidewall 232B of the first cut feature 232 and the adjacent line feature 212 is smaller than the distance S2 between the sidewall 236A of the third cut feature 236 and the adjacent line feature 218, while the distance S3 between the sidewall 232A of the first cut feature 232 and the line feature 216 is larger than the distance S4 between the sidewall 236B and the line feature 214. Therefore, such a cut feature arrangement makes the space in the positive Y direction smaller than the space in the negative Y direction, and thus asymmetric implantation can be used to expand the size of the corresponding cut features 232, 234, and 236.

[0072] Next, operation 110 is performed in which a first tilted ion implantation process is performed to implant ions 240 into the sidewalls 232B, 234B, 236B of the corresponding cut features 232, 234, 236 ( Figures 13A-13C ). Figure 13A According to some embodiments, after performing a first tilted ion implantation process to implant ions 240 into the sidewalls 232B, 234B, 236B of the corresponding cut features 232, 234, 236 Figures 12A-12C A top view of a semiconductor structure. Figure 13B It is taken along the line B-B' Figure 13A Cross-sectional view of a semiconductor structure. Figure 13C It is taken along the line C-C' Figure 13A Cross-sectional view of a semiconductor structure.

[0073] refer to Figures 13A-13C , ions 240 having a first implantation direction are directed toward the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236. The angle of incidence of the ions 240 (which is defined as the angle between the ions 240 and a normal perpendicular to the top surface of the substrate 202) is selected such that the sidewalls 232B, 234B, 236B on a first side of the cut features 232, 234, 236 are exposed to the ions 240, while the sidewalls 232A, 234A, 236A on a second side of the cut features 232, 234, 236 are not substantially exposed to the ions 240. During the first tilted ion implantation, ions 240 impact the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236 to sputter the photoresist off the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236, thereby resulting in localized removal of the photoresist from the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236.

[0074] Because the spacing between sidewall 232A of first cut feature 232 and underlying line feature 216 is greater than the spacing between sidewall 236B of third cut feature 236 and line feature 214 (i.e., S3 > S4), less photoresist needs to be removed from sidewall 236B of third cut feature 236 to provide sufficient cut budget to remove the unwanted portion of line feature 216. Therefore, the energy and / or dose of ions 240 are controlled to remove a relatively small portion of photoresist from each sidewall 232B, 234B, 236B of the corresponding cut features 232, 234, 236. In some embodiments, each removed photoresist portion has a triangular cross-sectional shape with a substantial length ΔL1. After the first angled ion implantation, each sidewall 232B, 234B, 236B of the cut features 232, 234, 236 is tilted at a first angle β1 relative to a normal to the top surface of substrate 202.

[0075] As the photoresist is removed from the sidewalls 232B, 234B, 236B of the respective cut features 232, 234, 236, the cut features 232, 234, 236 are enlarged in the positive Y direction, so that the sidewalls 232B, 234B, 236B of the cut features 232, 234, 236 are positioned away from the respective line features 214, 216. The spacing between the sidewall 236B of the cut feature 236 and the line feature 216 is thus increased, which allows undesired portions of the line feature 216 to be easily removed.

[0076] Next, operation 112 is performed in which a second tilted ion implantation process is performed to implant ions 242 into the sidewalls 232A, 234A, 236A of the corresponding cut features 232, 234, 236 ( Figures 14A-14C ). Figure 14A After performing a second tilted ion implantation process to implant ions 242 into the sidewalls 232A, 234A, 236A of the corresponding cut features 232, 234, 236 according to some embodiments Figures 13A-13C A top view of a semiconductor structure. Figure 14B It is taken along the line B-B' Figure 14A Cross-sectional view of a semiconductor structure. Figure 14C It is taken along the line B-B' Figure 14A Cross-sectional view of a semiconductor structure.

[0077] refer to Figures 14A-14C , ions 242 having a second implantation direction are directed toward the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236. The angle of incidence of the ions 242 (which is defined as the angle between the ions 242 and a normal perpendicular to the top surface of the substrate 202) is selected such that the sidewalls 232A, 234A, 236A on the second side of the cut features 232, 234, 236 are exposed to the ions 242, while the sidewalls 232B, 234B, 236B on the first side of the cut features 232, 234, 236 are not substantially exposed to the ions 242. During the second angled ion implantation, ions 242 impact the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236 to sputter the photoresist off the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236, thereby resulting in localized removal of the photoresist from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236.

[0078] In the second alternative embodiment, because the distance S3 between the sidewall 232A of the first cut feature 232 and the adjacent line feature 216 is greater than the distance S4 between the sidewall 236B of the third cut feature 236 and the adjacent line feature 214, i.e., S3>S4, more photoresist can be removed from the sidewall 232A of the first cut feature 232 to provide a sufficient cutting budget for removing the unwanted portion of the line feature 214 below the first cut feature 232. Therefore, the energy and / or dose of the ions 242 are controlled to be higher than the energy and / or dose of the ions 240. As a result, a relatively large amount of photoresist is removed from each sidewall 232A, 234A, 236A of the corresponding cut features 232, 234, 236, compared to the amount of photoresist removed from each sidewall 232B, 234B, 236B of the corresponding cut features 232, 234, 236. In some embodiments, each removed photoresist portion has a cross-sectional shape of a triangle with a base length ΔL2, where the base length ΔL2 is greater than ΔL1. After the second angled ion implantation, each sidewall 232A, 234A, 236A of the cut features 232, 234, 236 is tilted at a second angle β2 relative to a normal perpendicular to the top surface of the substrate 202. The second tilt angle β2 is greater than the first tilt angle β1.

[0079] As the photoresist is removed from the sidewalls 232A, 234A, 236A of the respective cut features 232, 234, 236, the cut features 232, 234, 236 are enlarged in the negative Y direction, so that the sidewalls 232A, 234A, 236A of the cut features 232, 234, 236 are positioned away from the respective line features 214, 216. Each narrow spacing between the sidewalls 232A, 234A of the respective cut features 232, 234 and the line feature 214 is thereby increased, which allows undesired portions of the line feature 214 to be easily removed.

[0080] Next, operation 114 is performed in which portions of the line features 214, 216 exposed by the cutting features 232, 234, 236 are removed to provide the semiconductor structure 200 ( Figure 8A and Figure 8B ).

[0081] In various embodiments, relevant CMOS processing can be used to continue processing operations and form suitable p-type and n-type FinFET devices utilizing fins. For example, a first gate structure can be formed over a portion of a first set of fins, and a first source / drain region including a dopant of n-type conductivity can be formed on an opposite side of the first gate structure to provide an n-type FinFET. A second gate structure can be formed over a portion of a second set of fins, and a second source / drain region including a dopant of p-type conductivity can be formed on an opposite side of the second gate structure to provide a p-type FinFET. The gate structures can be formed using a gate-first or gate-last process known in the art. Each gate structure can include a gate dielectric and a gate conductor.

[0082] One aspect of the present specification relates to a method for forming a semiconductor structure. The method includes: forming a pattern on a substrate, the pattern including a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; and patterning the photoresist layer to form a cut pattern including a first cut feature and a second cut feature, the first cut feature exposing a portion of the first line feature and the second cut feature exposing a portion of the second line feature. In a top view, at least one of the first cut feature and the second cut feature is asymmetrically arranged relative to a central axis of the corresponding first line feature or second line feature. The method also includes: performing at least one tilted ion implantation to expand the first cut feature and the second cut feature in at least one direction perpendicular to the first direction, removing the portion of the first line feature exposed by the first cut feature and the portion of the second line feature exposed by the second cut feature, and removing the photoresist layer.

[0083] Another aspect of the present specification relates to a method for forming a semiconductor structure. The method includes forming a pattern on a substrate. The pattern includes a first line feature and a second line feature extending in a first direction; and depositing a photoresist layer on the substrate to cover the pattern. The method also includes patterning the photoresist layer to form a first cut feature that exposes a portion of the first line feature and a second cut feature that exposes a portion of the second line feature. In a top view, the first cut feature is asymmetrically arranged relative to a central axis of the first line feature. The method also includes performing a first tilted ion implantation to expand the first cut feature and the second cut feature in a second direction perpendicular to the first direction, removing the portion of the first line feature exposed by the first cut feature and the portion of the second line feature exposed by the second cut feature, and removing the photoresist layer.

[0084] Another aspect of the present specification relates to a method for forming a semiconductor structure. The method includes etching a patterned target layer to form a pattern on a substrate. The pattern includes a first line feature and a second line feature extending in a first direction; and depositing a photoresist layer on the substrate to cover the pattern. The method also includes patterning the photoresist layer to form a first cut feature that exposes a portion of the first line feature and a second cut feature that exposes a portion of the second line feature. Each of the first cut feature and the second cut feature has a first sidewall and a second sidewall extending in the first direction. A first spacing between the first sidewall of the first cut feature and the first line feature is greater than a second spacing between the second sidewall of the first cut feature and the first line feature. A first spacing between the first sidewall of the second cut feature and the second line feature is less than a second spacing between the second sidewall of the second cut feature and the second line feature. The second sidewall of the first cut feature is adjacent to the second line feature, and the first sidewall of the second cut feature is adjacent to the first line feature. A first tilted ion implantation is performed to expand the first cut feature and the second cut feature in a second direction perpendicular to the first direction. The method further includes performing a second tilted ion implantation to enlarge the first cut feature and the second cut feature in a third direction opposite to the second direction, removing a portion of the first line feature exposed by the first cut feature and a portion of the second line feature exposed by the second cut feature, and removing the photoresist layer.

[0085] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0086] Example 1 is a method for forming a semiconductor structure, comprising: forming a pattern on a substrate, the pattern comprising a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a cutting pattern comprising a first cutting feature and a second cutting feature, the first cutting feature exposing a portion of the first line feature, and the second cutting feature exposing a portion of the second line feature, wherein, in a top view, at least one of the first cutting feature and the second cutting feature is asymmetrically arranged with respect to a central axis of the corresponding first line feature or second line feature; performing at least one tilted ion implantation to enlarge the first cutting feature and the second cutting feature in at least one direction perpendicular to the first direction; removing the portion of the first line feature exposed by the first cutting feature and the portion of the second line feature exposed by the second cutting feature; and

[0087] The photoresist layer is removed.

[0088] Example 2 is the method of Example 1, wherein performing the at least one tilted ion implantation includes performing a first tilted ion implantation to enlarge the first cut feature and the second cut feature in a second direction perpendicular to the first direction.

[0089] Example 3 is the method described in Example 2, wherein performing the first tilted ion implantation includes: impacting the first sidewall of each of the first cutting feature and the second cutting feature with a first ion to increase the spacing between the first sidewall of the first cutting feature and the first line feature and the spacing between the first sidewall of the second cutting feature and the second line feature.

[0090] Example 4 is the method of Example 3, wherein performing at least one tilted ion implantation further comprises performing a second tilted ion implantation to enlarge the first cut feature and the second cut feature in a third direction opposite to the second direction.

[0091] Example 5 is the method described in Example 4, wherein performing the second tilted ion implantation includes: impacting the second sidewall of each of the first cutting feature and the second cutting feature with a second ion to increase the spacing between the second sidewall of the first cutting feature and the first line feature and the spacing between the second sidewall of the second cutting feature and the second line feature.

[0092] Example 6 is the method of Example 1, wherein a pitch between the first cut feature and the second cut feature is equal to or greater than a minimum pitch of a single lithography at a given technology node.

[0093] Example 7 is a method for forming a semiconductor structure, comprising: forming a pattern on a substrate, wherein the pattern includes a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a first cutting feature that exposes a portion of the first line feature and a second cutting feature that exposes a portion of the second line feature, wherein, in a top view, the first cutting feature is asymmetrically arranged relative to a central axis of the first line feature; performing a first tilted ion implantation to expand the first cutting feature and the second cutting feature in a second direction perpendicular to the first direction; removing the portion of the first line feature exposed by the first cutting feature and the portion of the second line feature exposed by the second cutting feature; and removing the photoresist layer.

[0094] Example 8 is the method of Example 7, wherein the patterning of the photoresist layer is performed using a single photomask.

[0095] Example 9 is the method of Example 7, wherein each of the first and second cutting features has opposing first and second sidewalls extending in the first direction.

[0096] Example 10 is the method described in Example 9, wherein a first spacing between a first sidewall of the first cutting feature and the first line feature is greater than a second spacing between a second sidewall of the first cutting feature and the first line feature, the second sidewall being adjacent to the second line feature, and wherein the first inclined ion implantation enlarges the second spacing between the second sidewall of the first cutting feature and the first line feature.

[0097] Example 11 is the method of Example 9, wherein performing the first angled ion implantation includes implanting first ions into a second sidewall of each of the first cut feature and the second cut feature to remove a portion of the photoresist layer.

[0098] Example 12 is the method described in Example 9, wherein the second cutting feature is asymmetrically arranged relative to the central axis of the second line feature in a top view, wherein a first spacing between a first side wall of the second cutting feature and the second line feature is smaller than a second spacing between a second side wall of the second cutting feature and the second line feature, and the first side wall is adjacent to the first line feature.

[0099] Example 13 is the method of Example 12, further comprising performing a second tilted ion implantation to enlarge the first cut feature and the second cut feature in a third direction opposite to the second direction.

[0100] Example 14 is the method of Example 13, wherein the second angled ion implantation increases the first spacing between the first sidewall of the second cut feature and the second line feature.

[0101] Example 15 is the method of Example 13, wherein performing the second angled ion implantation comprises implanting second ions into a first sidewall of each of the first cut feature and the second cut feature to remove other portions of the photoresist layer.

[0102] Example 16 is a method for forming a semiconductor structure, comprising: etching a patterned target layer to form a pattern on a substrate, wherein the pattern includes a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a first cut feature that exposes a portion of the first line feature and a second cut feature that exposes a portion of the second line feature, wherein each of the first cut feature and the second cut feature has a first sidewall and a second sidewall extending in the first direction, a first spacing between the first sidewall of the first cut feature and the first line feature is greater than a second spacing between the second sidewall of the first cut feature and the first line feature, A first spacing between the first side wall of the second cutting feature and the second line feature is smaller than a second spacing between the second side wall of the second cutting feature and the second line feature, the second side wall of the first cutting feature is adjacent to the second line feature, and the first side wall of the second cutting feature is adjacent to the first line feature; performing a first tilted ion implantation to expand the first cutting feature and the second cutting feature in a second direction perpendicular to the first direction; performing a second tilted ion implantation to expand the first cutting feature and the second cutting feature in a third direction opposite to the second direction; removing a portion of the first line feature exposed by the first cutting feature and a portion of the second line feature exposed by the second cutting feature; and removing the photoresist layer.

[0103] Example 17 is the method of Example 16, wherein performing the first angled ion implantation includes striking second sidewalls of each of the first cut feature and the second cut feature with first ions having a first implantation direction.

[0104] Example 18 is the method of Example 17, wherein performing the second angled ion implantation comprises striking first sidewalls of each of the first cut feature and the second cut feature with second ions having a second implantation direction different from the first implantation direction.

[0105] Example 19 is the method of Example 18, wherein the first ions have a first implantation dose, and the second ions have a second implantation dose different from the first implantation dose.

[0106] Example 20 is the method of Example 18, wherein the first ions have a first implantation energy and the second ions have a second implantation energy different from the first implantation energy.

Claims

1. A method for forming a semiconductor structure, comprising: forming a pattern on a substrate, the pattern comprising first and second line features extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a cutting pattern including a first cutting feature and a second cutting feature, the first cutting feature exposing a portion of the first line feature and the second cutting feature exposing a portion of the second line feature, wherein in a top view, at least one of the first cutting feature and the second cutting feature is asymmetrically arranged with respect to a central axis of the corresponding first line feature or second line feature; performing at least one tilted ion implantation to enlarge the first cut feature and the second cut feature in at least one direction perpendicular to the first direction; removing the portion of the first line feature exposed by the first cutting feature and the portion of the second line feature exposed by the second cutting feature; and The photoresist layer is removed.

2. The method according to claim 1, wherein Performing the at least one tilted ion implantation includes performing a first tilted ion implantation to enlarge the first cut feature and the second cut feature in a second direction perpendicular to the first direction.

3. The method according to claim 2, wherein: Performing the first tilted ion implantation includes: bombarding a first sidewall of each of the first cut feature and the second cut feature with a first ion to increase a spacing between the first sidewall of the first cut feature and the first line feature and a spacing between the first sidewall of the second cut feature and the second line feature.

4. The method according to claim 3, wherein: Performing at least one tilted ion implantation further includes performing a second tilted ion implantation to enlarge the first cut feature and the second cut feature in a third direction opposite to the second direction.

5. The method according to claim 4, wherein Performing the second tilted ion implantation includes: bombarding the second sidewall of each of the first cut feature and the second cut feature with second ions to increase the spacing between the second sidewall of the first cut feature and the first line feature and the spacing between the second sidewall of the second cut feature and the second line feature.

6. The method according to claim 1, wherein A pitch between the first cutting feature and the second cutting feature is equal to or greater than a minimum pitch of a single lithography at a given technology node.

7. A method for forming a semiconductor structure, comprising: forming a pattern on a substrate, wherein the pattern includes first and second line features extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a first cut feature exposing a portion of the first line feature and a second cut feature exposing a portion of the second line feature, wherein the first cut feature is asymmetrically arranged with respect to a central axis of the first line feature in a top view; performing a first tilted ion implantation to enlarge the first cutting feature and the second cutting feature in a second direction perpendicular to the first direction; removing the portion of the first line feature exposed by the first cutting feature and the portion of the second line feature exposed by the second cutting feature; and The photoresist layer is removed.

8. The method according to claim 7, wherein: The patterning of the photoresist layer is performed using a single photomask.

9. The method according to claim 7, wherein: Each of the first and second cutting features has opposing first and second sidewalls extending in the first direction.

10. The method according to claim 9, wherein: A first distance between a first sidewall of the first cutting feature and the first line feature is greater than a second distance between a second sidewall of the first cutting feature and the first line feature, and the second sidewall is adjacent to the second line feature, wherein the first inclined ion implantation enlarges the second distance between the second sidewall of the first cutting feature and the first line feature.

11. The method according to claim 9, wherein: Performing the first angled ion implantation includes implanting first ions into a second sidewall of each of the first cut feature and the second cut feature to remove a portion of the photoresist layer.

12. The method according to claim 9, wherein In a top view, the second cut feature is asymmetrically arranged relative to a central axis of the second line feature, wherein a first spacing between a first sidewall of the second cut feature and the second line feature is smaller than a second spacing between a second sidewall of the second cut feature and the second line feature, the first sidewall being adjacent to the first line feature.

13. The method according to claim 12, further comprising: A second angled ion implantation is performed to enlarge the first and second cut features in a third direction opposite to the second direction.

14. The method according to claim 13, wherein The second angled ion implantation increases the first distance between the first sidewall of the second cut feature and the second line feature.

15. The method according to claim 13, wherein Performing the second angled ion implantation includes implanting second ions into a first sidewall of each of the first cut feature and the second cut feature to remove other portions of the photoresist layer.

16. A method for forming a semiconductor structure, comprising: etching the patterned target layer to form a pattern on the substrate, wherein the pattern includes a first line feature and a second line feature extending in a first direction; depositing a photoresist layer on the substrate to cover the pattern; patterning the photoresist layer to form a first cut feature exposing a portion of the first line feature and a second cut feature exposing a portion of the second line feature, wherein each of the first cut feature and the second cut feature has a first sidewall and a second sidewall extending in the first direction, a first spacing between the first sidewall of the first cut feature and the first line feature is greater than a second spacing between the second sidewall of the first cut feature and the first line feature, a first spacing between the first sidewall of the second cut feature and the second line feature is less than a second spacing between the second sidewall of the second cut feature and the second line feature, the second sidewall of the first cut feature is adjacent to the second line feature, and the first sidewall of the second cut feature is adjacent to the first line feature; performing a first tilted ion implantation to enlarge the first cut feature and the second cut feature in a second direction perpendicular to the first direction; performing a second tilted ion implantation to enlarge the first cut feature and the second cut feature in a third direction opposite to the second direction; removing the portion of the first line feature exposed by the first cutting feature and the portion of the second line feature exposed by the second cutting feature; and The photoresist layer is removed.

17. The method according to claim 16, wherein Performing the first angled ion implantation includes impinging on second sidewalls of each of the first cut feature and the second cut feature with first ions having a first implantation direction.

18. The method according to claim 17, wherein: Performing the second angled ion implantation includes impinging first sidewalls of each of the first cut feature and the second cut feature with second ions having a second implantation direction different from the first implantation direction.

19. The method according to claim 18, wherein The first ions have a first implantation dose, and the second ions have a second implantation dose different from the first implantation dose.

20. The method according to claim 18, wherein The first ions have a first implantation energy, and the second ions have a second implantation energy different from the first implantation energy.

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