Small size and low power consumption time-to-digital converter

Abstract

This disclosure relates to a time-to-digital converter (TDC) with small area and low power consumption. A TDC for converting a time period into a digital value is disclosed. An example TDC includes a ring oscillator and a margin generation circuit. Each stage of the margin generation circuit is configured to operate on the outputs of two different stages of the ring oscillator. The TDC also includes a counter for counting the number of times the output of one of the ring oscillator stages is switched between a first signal level and a second signal level during the time period to which the value is converted. The TDC includes a combiner for generating a digital value by combining a value indicating the number of times counted by the counter with the output of the margin generation circuit. Compared to conventional TDC designs, such a TDC can have a relatively small area and low power consumption while producing sufficient linear behavior.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices and systems, and more specifically to time-to-digital converters. Background Technology

[0002] In electronic instrumentation and signal processing, a time-to-digital converter (TDC) is a device used to identify events and provide a digital representation of the time when an event occurs or the time period during which an event occurs. For example, a TDC might output a digital value representing the arrival time of each incoming pulse. Some applications prefer to measure the time interval between two events rather than the concept of absolute time. For instance, a TDC used in a phase-locked loop (PLL) circuit can measure the phase difference between an input clock signal and a feedback clock signal. A TDC can digitize the phase difference between the pulses of the input clock signal and the pulses of the feedback clock signal and output a digitized indication of the phase difference.

[0003] Several factors can affect the cost, quality, and durability of a TDC. Physical constraints such as space / surface area can impose further constraints on TDC requirements or specifications, so trade-offs and ingenuity must be weighed when designing the optimal TDC for a given application. Summary of the Invention

[0004] According to one aspect of this disclosure, a time-to-digital converter (TDC) is provided, comprising: a ring oscillator having multiple stages; a margin generation circuit having multiple stages, wherein each stage of the margin generation circuit is configured to operate on outputs from two stages of the ring oscillator; a counter coupled to the output of one of the multiple stages of the ring oscillator and configured to count a number of times a signal at the output of one of the multiple stages of the ring oscillator switch is between a first signal level and a second signal level during a time period to be converted into a digital value; and a combiner configured to combine a value indicating the number of times counted by the counter with the output of the margin generation circuit to generate a digital value.

[0005] According to another aspect of this disclosure, an electronic device is provided, comprising: a time-to-digital converter (TDC) configured to convert a time period indicating a phase difference between a reference clock signal and an input clock signal into a digital value; and a phase-locked loop (PLL) circuit configured to generate an output signal having a phase related to the phase of the input clock signal based on the digital value generated by the TDC, wherein the TDC comprises: a ring oscillator including multiple stages, a margin generation circuit including multiple stages, wherein each stage of the margin generation circuit is configured to operate on the outputs of two stages of the ring oscillator, and a combiner configured to generate a digital value based on the output of the margin generation circuit.

[0006] According to another aspect of this disclosure, a method is provided for converting a time period indicating a phase difference between an input clock signal and a reference clock signal into a digital value. The method includes: providing an enable signal to each of a ring oscillator and a margin generation circuit via pulse adjustment logic, wherein: the enable signal is valid during the time period and invalid before and after the time period; the ring oscillator includes multiple stages; the margin generation circuit includes multiple stages; and each stage of the margin generation circuit is configured to operate on the outputs of two stages of the ring oscillator; counting a number of times, the number being a signal at the output of one of the multiple stages of the ring oscillator switch that is between a first signal level and a second signal level during the time the enable signal is valid; and generating the digital value based on a value indicating the number of times counted by the counter and the output of the margin generation circuit. Attached Figure Description

[0007] To provide a more complete understanding of this disclosure and its features and advantages, reference is made to the following description in conjunction with the accompanying drawings, wherein like reference numerals denote like parts, wherein:

[0008] Figure 1 Circuit diagrams of example TDCs according to some embodiments of the present disclosure are provided;

[0009] Figure 2 Provided some embodiments according to this disclosure Figure 1 Circuit diagram of the ring oscillator and margin generation circuit of the TDC.

[0010] Figure 3 Some embodiments of the present disclosure are provided that can be used in Figure 1 A schematic diagram of the counters used in the TDC.

[0011] Figure 4 Some embodiments according to this disclosure are provided. Figure 1 Timing diagram of TDC;

[0012] Figure 5 Schematic diagrams of example systems according to some embodiments of the present disclosure are provided, in which example systems can be implemented Figure 1 One or more TDCs.

[0013] Figure 6 This is a block diagram of an exemplary electrical device according to some embodiments of the present disclosure, which may include... Figure 1 One or more TDCs.

[0014] Figure 7Block diagrams illustrating example data processing systems according to some embodiments of the present disclosure are provided, which can be configured to control Figure 1 One or more TDC operations. Detailed Implementation

[0015] Overview

[0016] The systems, methods, and apparatuses disclosed herein all possess several innovative aspects, none of which alone is responsible for all the desired properties disclosed herein. Details of one or more embodiments of the subject matter described herein are set forth in the following description and accompanying drawings.

[0017] To illustrate the TDC with low area and low power consumption presented herein, it may be helpful to first understand the phenomena that may function in such a device. The following basic information can be considered as the basis for a proper interpretation of this disclosure. This information is provided for illustrative purposes only and should not be construed in any way as limiting the broad scope of this disclosure and its potential applications.

[0018] Like many electronic devices, the chip area occupied by the TDC and the power consumed by the TDC during operation are two key design parameters. The linearity of the TDC is another key design parameter. The linearity of an electronic device (or electronic component or system) is theoretically easy to understand. That is, linearity generally refers to the ability of a device to provide an output signal proportional to the input signal. In other words, if the device is perfectly linear, the ratio of the output signal to the input signal is a straight line. Achieving this behavior in real-world devices is far more complex and requires addressing many challenges related to linearity, often at the expense of other design parameters such as die area or power consumption.

[0019] Many types of TDCs have been explored in the past, such as delay-chain TDCs and cyclic TDCs. Conventional delay-chain TDCs offer the simplest implementation but suffer from drawbacks including poor linearity and a relatively large die surface area required to achieve the desired range. In contrast, conventional cyclic TDCs offer advantageously better linearity and occupy less surface area, but require power-intensive circuitry.

[0020] Embodiments of this disclosure relate to a time-varying control (TDC) for converting time periods into digital values, and to devices and systems in which such a TDC can be implemented. An example TDC includes a ring oscillator and a margin generation circuit, each circuit comprising the same number of stages (i.e., the ring oscillator comprises multiple stages, and the margin generation circuit further comprises multiple stages equal in number to the ring oscillator stages). Each stage of the margin generation circuit is configured to operate on the outputs of two different stages from the ring oscillator. The TDC also includes a counter configured to count, within a given time period when the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level (e.g., a voltage level corresponding to a high logic state) and a second signal level (e.g., a voltage level corresponding to a low logic state) (e.g., incrementing the counter value by 1 starting from a certain initial value, such as 0). For example, the counter may be configured to count the number of times the output of that stage of the ring oscillator switches from 0 to 1 and from 1 to 0 during a time period when the enable signal of the ring oscillator and the margin generation circuit is in a first logic state (e.g., a high logic state). The TDC also includes a combiner configured to generate a digital value representing the time period to be transitioned (e.g., when the enable signal of the ring oscillator and the margin generation circuit switches to a second logic state (e.g., a low logic state)) by combining a value representing the number of times the counter counts with the output of the margin generation circuitry. In such a TDC, the counter can be configured to operate only on one of the ring oscillator outputs (e.g., on the output of the last stage of the ring oscillator shown in this figure, although in other embodiments the counter can operate on the output of any other stage of the ring oscillator), which advantageously allows keeping the total size and number of counters relatively small, while the margin generation circuitry can be used to provide a code corresponding to the state of the ring oscillator as the ring oscillator's enable signal, and the margin generation circuitry switches to the second logic state. As a result, this TDC can be implemented with a relatively small area and low power consumption compared to conventional TDC designs, while producing sufficiently linear behavior. For this reason, although the relative name may change as the technology further develops, the TDC described herein can be referred to as a "TDC with relatively low area and power consumption".

[0021] Some TDCs that utilize margin generation are known in the art. However, their operating principles are quite different from the TDC proposed herein. For example, as will be described in more detail below, the TDC described herein is reset each time a time period is converted to a digital value. The duration between the start of the time period to be converted to a digital value and the start of the next corresponding time period can be called a “TDC cycle”. Therefore, the TDC described herein is a single-cycle TDC because the ring oscillator and margin generation circuitry are reset after each conversion and before the start of the next conversion. This differs from the gated ring oscillator (GRO) TDC architecture, in which the margin of one TDC cycle is carried over to the next and the result is averaged or filtered within the TDC cycle. In another form of margin calculation for MASH TDC, the output of the ring oscillator is also calculated over multiple TDC cycles, and the output of the ring oscillator can be differentiated over two or more clock cycles within the TDC cycle to detect state transitions. This also differs from the TDC described herein, where a separate clock is not required to calculate the margin, and the margin calculation is completed within a single TDC cycle.

[0022] As those skilled in the art will understand, aspects of this disclosure can be embodied in various ways, particularly aspects of a TDC with relatively low area and power consumption as presented herein, for example, as a method, system, computer program product, or computer-readable storage medium. Therefore, aspects of this disclosure can take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which are generally collectively referred to herein as “circuit,” “module,” or “system.” The functionality described in this disclosure can be implemented as an algorithm executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of each method described herein can be executed by different processing units. Furthermore, aspects of this disclosure can take the form of a computer program product embodied in one or more computer-readable media, preferably non-transitory, on which computer-readable program code is embodied (e.g., stored). In various embodiments, such a computer program can be downloaded (updated) to existing devices and systems (e.g., downloaded to existing PLLs, digital signal processing (DSP) cores, and / or their controllers, etc.) or stored during the manufacture of these devices and systems.

[0023] The following detailed description provides various descriptions of certain specific embodiments. However, the innovations described herein can be embodied in many different ways, for example, as defined and covered by the selected examples.

[0024] In the following description, reference is made to the accompanying drawings, wherein similar reference numerals may indicate the same or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, some embodiments may combine any suitable combination of features from two or more drawings. Additionally, it will be understood that some embodiments may include more elements than those shown in the drawings and / or a subset of the elements shown in the drawings. In general, although some of the drawings provided herein illustrate various aspects of a TDC with relatively low area and power consumption, and systems in which such circuitry can be implemented, the details of these systems may differ in different embodiments. For example, the various components of the TDC with relatively low area and power consumption presented herein may have other components included therein or coupled thereto, which are not specifically shown in the drawings, such as logic, storage, passive elements (e.g., resistors, capacitors, inductors, etc.) or other elements (e.g., transistors, etc.). In another example, the details shown in some of the figures, such as the specific arrangement and example implementation details of the various components of the TDC presented herein (e.g., ring oscillator, margin generation circuit, etc.), the specific arrangement of the coupling connections between the outputs of the various stages of the ring oscillator and the logic elements of the margin generation circuit, etc., may differ in different embodiments. The illustrations in these figures only provide some examples of how these components can be used together to implement a TDC with a relatively small area and power consumption. In yet another example, although some embodiments shown in the figures illustrate a certain number of components (e.g., a certain number of stages of the ring oscillator in the TDC, or a certain number of TDCs in a PLL circuit), it should be understood that these embodiments can be implemented in a TDC or in any other device or system having any number of these components, based on the description provided herein. Furthermore, although some elements (e.g., the various elements of the ring oscillator and the various elements of the margin generation circuit) may be depicted in the figures as communicatively coupled using a single depicted line, in some embodiments, any of these elements may be coupled via multiple wires, such as wires that may exist in a bus, or when differential signals are involved.

[0025] The description may use the phrases “in one embodiment” or “in an embodiment,” which may refer to one or more of the same or different embodiments, respectively. Unless otherwise stated, the ordinal adjectives “first,” “second,” and “third,” etc., used to describe a common object merely indicate that different instances of the same object are being referenced, and are not intended to imply that the described object must be in a given sequence in time, space, hierarchy, or any other way. Furthermore, for the purposes of this disclosure, the phrase “A and / or B” or the symbol “A / B” means (A), (B), or (A and B), while the phrase “A, B, and / or C” refers to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the symbol “A / B / C” refers to (A, B, and / or C). When used in reference to measurement ranges, the term “between…” includes the end of the measurement range.

[0026] Various aspects of the illustrative embodiments are described using terminology commonly used by those skilled in the art to communicate the essence of their work to others skilled in the art. For example, the term “connection” refers to a direct electrical connection between connected objects without any intermediate devices / components, while the term “coupling” refers to a direct electrical connection between connected objects, or an indirect electrical connection via one or more passive or active intermediate devices / components. In another example, the term “circuit” (which may be used interchangeably) refers to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. Sometimes, the term “circuit” may be omitted in this specification (e.g., a TDC circuit may be simply referred to as “TDC”, etc.). If used, the terms “substantially,” “about,” “probably,” etc., may generally be used to refer to a target value within + / -20% of the context of a particular value described herein or known in the art, such as within + / -10% of the target value.

[0027] Example TDC

[0028] Figure 1 Circuit diagrams of an example TDC 100 according to some embodiments of the present disclosure are provided, which can be implemented with relatively low area and power. Figure 1 As shown, TDC 100 may include a ring oscillator 110, a margin generation circuit 120, a counter 130, a multiplier 140, and a combiner 150.

[0029] The ring oscillator 110 can be implemented as any ring oscillator known in the art, having any number of two or more stages. Figure 1An example is shown where the ring oscillator 110 has three stages, labeled as stage 112-1, stage 112-2, and stage 112-3, respectively; however, in other embodiments of the TDC 100, two or more additional stages may be used. In some embodiments, the ring oscillator 110 may include an odd number of three or more stages 112 (e.g., if the stages 112 of the ring oscillator are coupled to each other using single-ended connections, such as...). Figure 1 (As shown in the example). In other embodiments, the ring oscillator 110 may include (an even number) two or more stages 112 (e.g., if the stages 112 of the ring oscillator 110 are coupled using differential connections). Figure 1 As shown, each stage 112 of the ring oscillator 110 may include a corresponding logic circuit with a NOT gate response (i.e., different instances of the logic circuit) (in other words, each stage 112 of the ring oscillator 110 may include / be a digital inverter). The respective outputs from each stage 112 are... Figure 1 The outputs are labeled as RO-S1_OUT from stage 112-1, RO-S2_OUT from stage 112-2, and RO-S3_OUT from stage 112-3. These outputs are also shown in the description below. Figure 4 In the timing diagram.

[0030] like Figure 1 As shown, in some embodiments, the output from the last stage of the ring oscillator 110, for example from... Figure 1 The output RO-S3_OUT of stage 112-3 of the illustrated three-stage ring oscillator example is provided to counter 130. However, in the embodiment of TDC 100, counter 130 can be coupled to any other stage 112 of the ring oscillator 110. As is known in the art, the inputs and outputs of the individual stages 112 of the ring oscillator 110 can be coupled. For example, the output RO-S1_OUT of the first stage 112-1 can be coupled to the input of the second stage 112-2, the output RO-S2_OUT of the second stage 112-2 can be coupled to the input of the third stage 112-2, and so on, until the output of the last stage 112 can be coupled to the input of the first stage 112, thus forming a feedback loop. Figure 1 The example shown is a three-stage ring oscillator, where the latter means that the output RO-S3_OUT from the third (i.e., the last) stage 112-3 can be coupled to the input of the first stage 112-1. Similarly... Figure 1 As shown, in some embodiments, the first stage 112-1 of the ring oscillator 110 can be configured to receive an enable signal. The enable signal can be a control signal configured to activate the ring oscillator 110 (i.e., to make the ring oscillator 110 oscillate) or deactivate the ring oscillator 110 (i.e., to make the ring oscillator 110 stop oscillating).

[0031] Ring oscillator 110 can be associated with an initial or reset state from which its oscillation begins when a new time period transitions to a digital value. For a three-stage ring oscillator 110, such a reset state could be 101, meaning that each of outputs RO-S1_OUT and RO-S3_OUT has a voltage level corresponding to a high logic state (e.g., corresponding to a digital bit 1), and output RO-S2_OUT has a voltage level corresponding to a low logic state (e.g., corresponding to a digital bit 0). In the following description, for simplicity, some control signals (e.g., bit values ​​of 1 or 0) can be referred to. Figure 1 and Figure 4 The timing diagram shows enable, start, or stop signals and output signals of certain components (e.g., outputs RO-S1_OUT, RO-S2_OUT, and RO-S3_OUT of stage 112). However, these descriptions can be readily extended to more general embodiments, where a given signal may have a first signal level (e.g., a voltage level) corresponding to a first state (e.g., a high logic state) or a specific second signal level (e.g., a voltage level) corresponding to a second state (e.g., a low logic state). In this document, the term "switching" can be used to describe a change in the digital value of a signal from 0 to 1 or from 1 to 0 (or equivalently, a change in the digital value from a first level to a second level, different from the first level, or vice versa). During operation, the outputs of the various stages 112 of the ring oscillator 110 sequentially switch between values ​​of 1 and 0. Reference Figure 4 The timing diagram describes more details of the operation of the ring oscillator 110.

[0032] An example implementation of the margin generation circuit 120 is in Figure 2 Shown in. Figure 2 The ring oscillator 110 and the input and output signals from the margin generation circuit 120 are shown, such as Figure 1 As shown. Furthermore, Figure 2 The margin generation circuit 120 shown may also include multiple stages, such as... Figure 2 The diagram shows three stages 222-1, 222-2, and 222-3. Typically, the number of stages 222 in the margin generation circuit 120 can be equal to the number of stages 112 in the ring oscillator 110. Therefore, each stage 112 of the ring oscillator 110 can be associated with a corresponding stage 222 of the margin generation circuit 120 (i.e., stage 112-1 of the ring oscillator 110 can be associated with stage 222-1 of the margin generation circuit 120, stage 112-2 of the ring oscillator 110 can be associated with stage 222-2 of the margin generation circuit 120, and so on). Also... Figure 2As shown, TDC 100 may also include a plurality of latch circuits (or flip-flops) 224, wherein the number of latch circuits 224 may be equal to the number of stages of the ring oscillator 110. Therefore, each stage 112 of the ring oscillator 110 and each stage 222 of the margin generation circuit 120 may be associated with a corresponding one of the latch circuits 224 (i.e., stage 112-1 of the ring oscillator 110 and stage 222-1 of the margin generation circuit 120 may be associated with latch circuit 224-1, stage 112-2 of the ring oscillator 110, stage 222-2 of the margin generation circuit 120 may be associated with latch circuit 224-2, and so on). In some embodiments, the latch circuits 224 may be considered as part of the margin generation circuit 120.

[0033] The margin generation circuit 120 is configured to generate the output RES_OUT by means of the following configuration: The margin generation circuit 120 can be configured to receive an enable signal also provided to the ring oscillator 110. In particular, at least one of the latch circuits 224 (e.g., each latch circuit 224) can have another input configured to receive an enable signal, which is configured to cause the margin generation circuit 120 to generate the output RES_OUT once the time period converted to a digital value ends and before resetting the margin generation circuit 120 for conversion of another time period. For example, the first latch circuit 224-1 can be configured to receive an enable signal, such as Figure 2 As shown. The enable signal can be configured to activate the margin generation circuit 120, ultimately causing the margin generation circuit 120 to generate a margin output signal RES_OUT, or to deactivate the margin generation circuit 120 (i.e., to prevent the margin generation circuit 120 from generating a margin output). For example... Figure 2As shown, the first latch circuit 224-1 can be configured to receive the output RO-S1_OUT from the first stage 112-1 of the ring oscillator 110 and provide output 225-1 to each of the first stage 222-1 and the second stage 222-2 of the margin generation circuit 120. Similarly, the second latch circuit 224-2 can be configured to receive the output RO-S2_OUT from the second stage 112-2 of the ring oscillator 110 and provide output 225-2 to each of the second stage 222-2 and the third stage 222-3 of the margin generation circuit 120. For the 3-stage ring oscillator example of TDC 100, the third latch circuit 224-3 (the last latch circuit in this example) can be configured to receive the output RO-S3_OUT from the third stage 112-3 (the last stage in this example) of the ring oscillator 110 and provide output 225-3 to each of the third stage 222-3 and the first stage 222-1 of the margin generation circuit 120. Typically, for the other number of stages included in the ring oscillator 110 of TDC 100, each latch circuit 224, except for the latch circuit associated with the last stage of the ring oscillator 110, is configured to receive the output of the corresponding stage of the ring oscillator 110 and provide output 225 to the stage of the margin generation circuit 120 associated with the corresponding stage of the ring oscillator 110, as well as to the stage of the margin generation circuit 120 associated with the next stage of the ring oscillator 110. The last latch circuit 224 is configured to receive the output of the last stage of the ring oscillator 110 and provide output 225 to the last and first stages of the margin generation circuit 120. In this way, each stage 222 of the margin generation circuit 120 is coupled to the output of each stage 112 of the ring oscillator 110. Specifically, each stage 222 of the margin generation circuit 120 is configured to operate on two inputs: the first stage 222-1 of the margin generation circuit 120 is configured to operate on the output RO-S1_OUT of the first stage 112-1 of the ring oscillator 110 and the output of the last stage of the ring oscillator 110 (i.e., for...). Figure 1 and Figure 2 The third stage 112-3 of the ring oscillator 110 shown in the 3-stage example (output RO-S3_OUT), the second stage 222-2 of the margin generation circuit 120 is configured to operate on the output RO-S1_OUT of the first stage 112-1 and the output RO-S2_OUT of the second stage 112-2 of the ring oscillator 110, and the last stage 222-3 of the margin generation circuit 120 (for Figure 1 and 2The 3-stage example is configured to operate on the output RO-S2_OUT of the second stage 112-2 of the ring oscillator 110 and the output RO-S3_OUT of the last stage 112-3 of the ring oscillator 110. In some embodiments, each stage 222 of the margin generation circuit 120 may include a corresponding (i.e., different instance) logic circuit with an XOR gate response, such as Figure 2 As shown.

[0034] Figure 2 Further illustrated, the margin generation circuit 120 may further include an encoder 226 configured to combine the outputs of multiple stages 222 of the margin generation circuit 120 to produce an output RES_OUT indicating the margin calculated by the margin generation circuit 120. After the enable signal has switched to the second logic state or become inactive, the combination of the XOR stage 222 of the margin generation circuit 120 and the encoder 226 (scaled by the number of stages 112 of the ring oscillator 110) provides a margin (i.e., the output RES_OUT), which is added to the multiplier counter value to obtain the final TDC output TDC_OUT. (Refer to...) Figure 4 The timing diagram is used to describe more details of the operating margin generation circuit 120.

[0035] Continue Figure 1 The components of TDC 100 shown herein include a counter 130 that can be coupled to the output of one of the multiple stages 112 of a ring oscillator 110. For example, Figure 1 In some embodiments, counter 130 may be coupled to the output RO-S3_OUT of the last stage 112-3 of the ring oscillator 110. However, in other embodiments, counter 130 may be coupled to the output of any other stage 112 of the ring oscillator 110. Counter 130 is configured to count the number of times the signal at the output of one of the plurality of stages 112 to which counter 130 is coupled switches between a first signal level (e.g., a voltage level corresponding to a high logic state) and a second signal level (e.g., a voltage level corresponding to a low logic state) during a period of time when the signal is converted into a digital value (e.g., during a period when the enable signal of the ring oscillator 110 and the margin generation circuit 120 is in a first logic state (e.g., a high logic state)). For Figure 1 In the example shown, counter 130 is configured to count the number of times the output signal RO-S3_OUT is switched. Multiplier 140 can then be configured to multiply the counter value of counter 130 by the total number of stages 112 of the ring oscillator 110 (e.g., for...). Figure 1The 3-level example shown is multiplied by 3, thus generating the counter signal CNT_OUT. Then, combiner 150 is configured to combine a value representing the number of times counter 130 has counted with the output of margin generation circuit 120 (e.g., when the enable signals of ring oscillator 110 and margin generation circuit 120 are switched to a second logic state (e.g., a low logic state)) to generate a digital value representing the time period converted by TDC 100. For example, combiner 150 can be configured to combine the value of counter signal CNT_OUT and margin output RES_OUT to generate a digital value representing the time period converted by TDC 100.

[0036] As described above, in TDC 100, only one counter 130 exists, which is configured to operate on the output of only one stage 112 of the ring oscillator 110 (e.g., on the output RO-S3_OUT of the last stage of the ring oscillator 110, as shown in this figure, although in other embodiments, counter 130 may operate on the output of any other ring oscillator stage 112). This advantageously reduces the need for multiple counters, each operating on a single ring oscillator output, or a single counter operating on multiple ring oscillator outputs, and allows keeping the size of TDC relatively small while using counter 130 and margin generation circuitry 120 to provide codes corresponding to the state of ring oscillator 110, as the enable signals of ring oscillator 110 and margin generation circuitry 120 switch to a second logic state.

[0037] In some embodiments, counter 130 and multiplier 140 may together form a counter, which may be referred to as counter device 132, configured to receive the output of one of the stages 112 of ring oscillator 110 and generate a counter signal CNT_OUT indicating how many times the output has switched within a time period during which it is converted into a digital value. In some embodiments, it may be as follows Figure 3 The counter device 132 is shown as an implementation. The counter 130 of the counter device 132 may include a first edge generator circuit 332-1, followed by a first edge counter 334-1, and also includes a second edge generator circuit 332-2, followed by a second edge counter 334-2. As shown... Figure 3 As shown, the input received by counter 130 (e.g., for) Figure 1 The output RO-S3_OUT of the last stage of the ring oscillator 110 shown in the example is provided as input to each of the first edge generator circuit 332-1 and the second edge generator circuit 332-2.

[0038] The first edge generator circuit 332-1 can be configured to generate a first indication when a signal at the output of one of the stages 112 to which the counter 130 is coupled (e.g., the output RO-S3_OUT) switches from a first signal level (e.g., a voltage level corresponding to a high logic state) to a second signal level (e.g., a voltage level corresponding to a low logic state). For example, the first edge generator circuit 332-1 can be configured to generate the first indication when the output RO-S3_OUT switches from 1 to 0. The first edge generator circuit 332-1 can be configured to provide its output NEG_OUT to a first edge counter 334-1, which can be configured to count the number of times the first edge generator circuit 332-1 generates the switching indication from 1 to 0. For example, the indication can be provided as different signal levels in the output NEG_OUT generated by the first edge generator circuit 332-1 (e.g., as pulses in the output NEG_OUT, such as...). Figure 4 (As shown in the timing diagram).

[0039] Similarly, the second edge generator circuit 332-2 can be configured to generate a second indication when the signal at the output of one of the stages 112 to which the counter 130 is coupled (e.g., the output RO-S3_OUT) switches from a second signal level (e.g., a voltage level corresponding to a low logic state) to a first signal level (e.g., a voltage level corresponding to a high logic state). For example, the second edge generator circuit 332-2 can be configured to generate the second indication when the output RO-S3_OUT switches from 0 to 1. The second edge generator circuit 332-2 can be configured to provide its output PEG_OUT to the second edge counter 334-2, which can be configured to count the number of times the second edge generator circuit 332-2 generates the switching indication from 0 to 1. For example, the indication can be provided as different signal levels in the output PEG_OUT generated by the second edge generator circuit 332-2 (e.g., as pulses in the output PEG_OUT, such as...). Figure 4 (As shown in the timing diagram).

[0040] Then, the value of counter 130 can be (or can be based on) the sum of the number of times the first edge generator circuit 332-1 generates the first indication and the number of times the second edge generator circuit 332-2 generates the second indication during the time period during which the value is converted to a digital value. Therefore, counter 130 can be a dual-edge counter that counts the switches in the output value of one of the stages 112 from 1 to 0 and counts the switches in the output value of one of the stages 112 from 0 to 1.

[0041] The multiplier 140 of the counter device 132 may include a first multiplier 342-1 configured to receive an input indicating the output of the first edge counter 334-1, and further includes a second multiplier 342-2 configured to receive an input indicating the output of the second edge counter 334-2. The first multiplier 342-1 may be configured to produce a first multiplier output NMULT_OUT by multiplying a value representing (e.g., equal to) the stage number 112 of the ring oscillator 110 with the counter value of the first edge counter 334-1. Similarly, the second multiplier 342-2 may be configured to produce a second multiplier output PMULT_OUT by multiplying a value representing (e.g., equal to) the stage number 112 of the ring oscillator 110 with the counter value of the second edge counter 334-2. Figure 3 As further shown, the multiplier 140 of the counter arrangement 132 may further include a combiner (e.g., an adder) 344, which is configured to produce an adder output by adding the output NMULT_OUT of the first multiplier 342-1 to the output PMULT_OUT of the second multiplier 342-2. The output CNT_OUT from the counter arrangement 132 can then be based on (e.g., equal to) the value of the output of the adder 344. Therefore, the TDC 100 can use the counter 130 as a dual-edge counter, and the multiplier 140 which can multiply the total value of the counter 130 by the number of stages 112 of the ring oscillator 110. In some embodiments, the multipliers 342-1 and 342-2, and the margin generation circuit 120, can be configured to operate only after the time period for conversion to digital has ended (e.g., after the enable signal has switched to the second logic state or become invalid). Figure 3 As shown, dividing each of the counters 130 and multipliers 140 into components that operate on negative edges (e.g., edge generator circuit 332-1, edge counter 334-1, and multiplier 342-1, which operate by switching the output RO-S3_OUT from 1 to 0) and components that operate on positive edges (e.g., edge generator circuit 332-2, edge counter 334-2, and multiplier 342-2, which operate on the output RO-S3_OUT from 0 to 1) can provide advantages in terms of power and area savings by reducing the speed requirements of the counters and multipliers.

[0042] refer to Figure 4 The timing diagram describes more details of the operation counter 130, multiplier 140 and combiner 150.

[0043] As described above, combiner 150 can be configured to combine the value of counter signal CNT_OUT and residual output RES_OUT to generate a digital value representing the time period converted by TDC 100. In some embodiments, this digital value can be provided as TDC output TDC_OUT. In other embodiments, TDC 100 may optionally further include one or more of pulse conditioning logic 160, saturation logic 170, selector 180, and calibration logic 190.

[0044] Pulse conditioning logic 160 can be configured to generate enable signals for ring oscillator 110 and margin generation circuit 120 based on start and stop signals provided to pulse conditioning logic 160. Typically, the start and stop signals can be considered as two signals that define the time period for which TDC 100 converts to a digital value. For example, in an embodiment where TDC 100 is implemented in a PLL circuit, the start and stop signals can be a reference clock signal and a corresponding feedback clock signal, respectively, and convert the time period between transitions as described herein into a digital value. In this case, the duration between transitions is sometimes referred to as the phase difference between the reference clock signal and the feedback clock signal. Pulse conditioning logic 160 can be configured to enable TDC 100 to operate across all possible phase differences between the start and stop signals and to convert the time period into a digital value regardless of whether the start signal precedes or follows the stop signal. In some embodiments, when the start signal precedes the stop signal, the enable signal may be valid (e.g., possibly having a voltage level corresponding to a high logic state) when the start signal is valid (e.g., having a voltage level corresponding to a high logic state) and the stop signal is invalid (e.g., having a voltage level corresponding to a low logic state). In some embodiments, when the start signal lags the stop signal, the enable signal may be valid when the stop signal is valid (e.g., having a voltage level corresponding to a high logic state) and the start signal is invalid (e.g., having a voltage level corresponding to a low logic state). The pulse adjustment logic 160 may be further configured to provide an indication to the TDC 100 whether the start signal precedes the stop signal or vice versa. In some embodiments, such an indication may be provided as a sign bit. The enable signal may be a control signal configured to be at a first signal level (e.g., a voltage level corresponding to a high logic state) during the period of being converted to a digital value, and at a second signal level (e.g., a voltage level corresponding to a low logic state) outside of all periods of being converted to a digital value.

[0045] In this embodiment, when the pulse adjustment logic 160 is not used, the start signal and stop signal can be directly provided to the ring oscillator 110 and the margin generation circuit 120.

[0046] In some embodiments, saturation logic 170 can be configured to determine whether the digital value output by combiner 150 is greater than a saturation threshold 172 (e.g., ...). Figure 1 (As shown). When affirmatively determined (i.e., when saturation logic 170 determines that the digital value output by combiner 150 is greater than the saturation threshold 172), saturation logic 170 can provide a predetermined digital value as output 174, for example, the maximum digital value in the range of TDC 100. When negatively determined (i.e., when saturation logic 170 determines that the digital value output by combiner 150 is not greater than the saturation threshold 172), saturation logic 170 can provide the digital value output by combiner 150 as output 174. If saturation logic 170 provides the same value, multiplexer 180 can then be configured to select the digital value output by combiner 150; otherwise, it selects the value provided by saturation logic 170 as the TDC_OUT output.

[0047] In other embodiments, saturation logic 170 may be configured to determine whether the digital value output by combiner 150 is greater than a saturation threshold 172 and provide an indication of this determination in output 174. For example, the indication may be a bit set when a positive determination is made or a bit not set when a negative determination is made. Multiplexer 180 may then be configured to select, based on output 174 of saturation logic 170, either the digital value output by combiner 150 or a predetermined digital value (e.g., the maximum digital value in the range of TDC 100) as the TDC_OUT output.

[0048] In various implementations, the saturation threshold 172 may be predetermined or programmable (e.g., variable). Implementing the saturation logic 170 enables the TDC 100 to indicate overflow conditions and provide a code corresponding to the maximum available range of the TDC 100. In some embodiments, the output 174 of the saturation logic 170 may be provided to the pulse conditioning logic 160 (e.g., ...). Figure 1 As shown, there is a feedback signal path from saturation logic 170 to pulse modulation logic 160, and pulse modulation logic 160 can be configured to generate an enable signal based on output 174. For example, if pulse modulation logic circuit 160 receives output 174 indicating that TDC 100 reaches saturation before the pulse of the stop signal arrives (in the case where the start signal precedes the stop signal), the enable signal can be truncated, thereby saving power consumed by TDC 100.

[0049] Calibration logic 190 can be configured to perform calibration of various components of TDC 100, for example, to identify and compensate for variations between parts, such as those caused by manufacturing processes and / or different operating conditions (e.g., voltage and temperature variations). For example, in some embodiments, a test pulse (e.g., during startup of TDC 100) can be used and processed by TDC 100 (particularly by calibration logic 190) to perform the calibration. In some embodiments, pulse conditioning logic 160 can be further configured to allow the provision of test pulses to calibrate TDC 100, etc. The communication connection between calibration logic 190 and pulse conditioning logic 160 is... Figure 1 The arrow between these two components is shown in the diagram. The test pulse can be used to adjust the enable signal and calibrate differences between parts.

[0050] According to some embodiments of this disclosure Figure 4 Provided for Figure 1 Timing diagram 400 for TDC. Timing diagram 400 shows the various signals mentioned above, in Figure 4 One by one, they are shown, such as from Figure 4 Starting from the top, there are start signals, stop signals, enable signals, etc. Additionally, timing diagram 400 shows the TDC_RESET signal and line RO, which illustrates the output of each stage 112 of the ring oscillator 110 at different time points.

[0051] Figure 4 The diagram illustrates various signals as functions of time (i.e., Figure 4 The horizontal axis of each signal shown is used for time counting. It should be noted that although in Figure 4 The diagram illustrates some signals perfectly aligned with each other at different points in time (e.g., the rise of the start signal is shown perfectly aligned with the rise of the enable signal); therefore, alignment is only shown to illustrate possible dependencies between events in different signals. In other embodiments (typically real-world implementations), there is a time delay between the occurrence of one event (e.g., the rise of the start signal) and another event (e.g., the rise of the enable signal) that leads to that event. The dashed arrows in... Figure 4 This is used to explain the causal relationship between different events. Figure 4 Vertical dashed lines are used to indicate different points in time.

[0052] For the case where the start signal precedes the stop signal, timing diagram 400 provides a three-stage ring oscillator 110 (i.e., as shown in the figure). Figure 1 The example shown is an oscillator. However, refer to... Figure 4 The provided explanation and the above reference Figure 1-3The provided explanation can be readily extended to the ring oscillator 110 including embodiments with different numbers of stages and / or embodiments where the start signal lags behind the stop signal, all of which are within the scope of this disclosure.

[0053] like Figure 4 As shown, when the start signal goes high, the time-to-digital conversion can begin at time 402. Since this is the mode when the start signal precedes the stop signal, the arrival of the start signal will cause the enable signal to go high. Because the enable signal is provided to the ring oscillator 110, the high enable signal causes oscillation to begin in the various stages 112 of the ring oscillator 110. Therefore, starting from the original configuration (e.g., before time 402), where the outputs of the ring oscillator's stage 112 are 1, 0, and 1 (as shown in the diagram), the conversion can begin. Figure 4 As shown, RO is 101, meaning RO-S1_OUT is 1, RO-S2_OUT is 0, and RO-S3_OUT is 1. The ring oscillator 110 starts oscillating (as can be seen from the switching values ​​of each output RO-S1_OUT, RO-S2_OUT, and RO-S3_OUT) and continues oscillating until the stop signal goes high at time 404, indicating the end of the first time period to be switched (in...). Figure 4 The first time period is converted into time period 420-1. During the duration of time period 420-1, the enable signal remains high and then goes low again after the stop signal goes high. During the duration of time period 420-1, the outputs RO-S1_OUT, RO-S2_OUT, and RO-S3_OUT continue to switch their respective values. During this time period, whenever the output RO-S3_OUT switches from 1 to 0, the first edge generator circuit 332-1 generates a pulse (e.g., ...). Figure 4 As shown, the first dashed arrow between the first pulses of RO-S3_OUT and NEG_OUT when RO changes from 011 to 010; as... Figure 4 As shown, the second dashed arrow between the second pulses of RO-S3_OUT and NEG_OUT when RO changes from 011 to 010 again. Similarly, whenever the output RO-S3_OUT switches from 0 to 1, the second edge generator circuit 332-2 generates a pulse (as shown). Figure 4As shown, when RO changes from 100 to 101, the dashed arrow between the first pulses of RO-S3_OUT and PEG_OUT indicates this. Correspondingly, the output NMULT_OUT increases by 3 (i.e., one pulse of NEG_OUT is multiplied by 3, since the ring oscillator 110 has 3 stages), for example, starting from 0, whenever there is a pulse in NEG_OUT and the enable signal remains high for the duration of time period 420-1, the output PMULT_OUT increases by 3, for example, starting from 0, whenever there is a pulse in PEG_OUT and the enable signal remains high for the duration of time period 420-1. Then, whenever either NMULT_OUT or PMULT_OUT increases, the counter output CNT_OUT also increases by 3.

[0054] The high-time 404 of the stop signal causes several changes in TDC 100. First, the enable signal goes low. As a result, the ring oscillator 110 stops oscillating, and the margin generation circuit 120 calculates RES_OUT, indicating the margin in the output of stage 112 of the ring oscillator 110, during the time period 422-1 between the high-time stop signal and the low-time enable signal. Because at the end of time period 420-1, when the stop signal goes high, the state RO of the ring oscillator 110 is 110 (e.g., Figure 4 As shown), the margin generation circuit 120 outputs RES_OUT, indicating a decimal value of 2. At the end of time period 420-1, when the stop signal goes high, this decimal value is combined with (e.g., added to) the decimal value of CNT_OUT, resulting in the TDC output TDC_OUT indicating a decimal value of 11 (9+2=11). Time period 422-1 can be called the TDC code update time because this is when the duration of time period 420-1 is converted into a digital value, for example, converted to... Figure 4 The example shown represents the decimal value 11. After the TDC code update time 422-1 (i.e., when the start signal goes low again), as... Figure 4 As shown, TDC 100 can be reset using the pulse in TDC_RESET during a time period 426 starting at time 406. Resetting TDC 100 means setting the outputs of each stage 112 of the ring oscillator 110 back to their original values ​​(e.g., RO is 101) and keeping them constant until the next time the start signal goes high again (e.g., when the start signal goes high again). Figure 4 As shown, occurring at time 412), the values ​​of the counter and multiplier outputs are reset to their original values ​​(e.g., as shown). Figure 4 As shown in the figure 0), and the margin generation circuit 120 resets by resetting its output to the original starting value (e.g., as ...). Figure 4 As shown, it is also 0). The TDC output is also reset (for example, it is also reset to a value of 0, as shown). Figure 4 (As shown).

[0055] After TDC 100 is reset in time period 426, the enable signal remains low until the next start signal goes high (at time 412), which indicates the start of the next time period 420-2, which will be converted to a digital value, and the process repeats again, similar to the conversion in time period 422-1. Figure 4 The times 412, 414, and 416 shown, and the series of events associated with these times, are similar to the times 402, 404, and 406 mentioned above. Therefore, for the sake of brevity, their descriptions will not be repeated.

[0056] In various implementations, as described herein, the controller can be used to control various aspects of the operation of the TDC 100. Such a controller can be implemented, for example, as... Figure 7 The data processing system shown.

[0057] Example systems and devices

[0058] TDC 100 can be implemented in a variety of electronic devices and systems. Some examples are shown below. Figure 5 and 6 It is displayed in the middle.

[0059] Figure 5 Schematic diagrams of example systems according to some embodiments of the present disclosure are provided, in which example systems can be implemented Figure 1 One or more TDCs. In particular, Figure 5 It is shown that TDC 100 can be included as part of or communicatively coupled to PLL circuit 530. PLL circuit 530 may further include controller 520, which is configured to control various aspects of the operation of TDC 100 as described herein. PLL 530 can be included within a device such as a DSP core or DSP circuitry (e.g., one or more filters, a Fast Fourier Transform (FFT) accelerator, etc.) 540. When implemented in association with PLL 530, TDC 100 can be configured to continuously calculate the phase difference between a reference clock and a feedback clock by generating digital codes. PLL 530 can then use the TDC digital codes to adjust its feedback clock to track the reference clock, and the output of PLL 530 can be used by DSP core / circuit 540, as is known in the art.

[0060] Figure 6This is a block diagram of an exemplary electrical device 2100 according to any embodiment disclosed herein, which may include one or more TDC 100s having relatively low area and power. For example, any suitable components of the electrical device 2100 may include one or more of the TDC 100s disclosed herein. Figure 6 The diagram illustrates a number of components included in electrical device 2100, but any one or more of these components may be omitted or repeated to suit the application. In some embodiments, some or all of the components included in electrical device 2100 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-a-chip (SoC).

[0061] Additionally, in various embodiments, electronic device 2100 may not include... Figure 6 The electronic device 2100 may include one or more components, but may include interface circuitry for coupling to one or more components. For example, the electronic device 2100 may not include display device 2106, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 2106 may be coupled. In another set of examples, the electronic device 2100 may not include audio input device 1818 or audio output device 2108, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which audio input device 1818 or audio output device 2108 may be coupled.

[0062] Electrical device 2100 may include processing device 2102 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2102 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device. Electrical device 2100 may include memory 2104, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 2104 may include memory that shares a die with processing device 2102. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0063] In some embodiments, electronic device 2100 may include communication chip 2112 (e.g., one or more communication chips). For example, communication chip 2112 may be configured to manage wireless communication for transmitting data to and from electronic device 2100. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0064] The communication chip 2112 can implement any of a variety of wireless standards or protocols, including but not limited to those of the Institute of Electrical and Electronics Engineers (IEEE), such as Wi-Fi (IEEE 802.11 series), IEEE 802.16 (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any revisions, updates, and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are commonly referred to as WiMAX networks; the acronym stands for “Global Interoperability for Microwave Access,” and it is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 2112 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication chip 2112 can operate according to enhanced data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 2112 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol specified as 3G, 4G, 5G, and higher. In other embodiments, communication chip 2112 can operate according to other wireless protocols. Electrical device 2100 may include antenna 2122 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0065] In some implementations, communication chip 2112 can manage wired communication such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, communication chip 2112 may include multiple communication chips. For example, a first communication chip 2112 may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth, and a second communication chip 2112 may be dedicated to longer-range wireless communication such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2112 may be dedicated to wireless communication, and the second communication chip 2112 may be dedicated to wired communication.

[0066] Electrical device 2100 may include battery / power circuit 2114. Battery / power circuit 2114 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 2100 to a power source (e.g., AC line power) that is separate from electrical device 2100.

[0067] Electrical device 2100 may include display device 2106 (or a corresponding interface circuit as described above). Display device 2106 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0068] Electrical device 2100 may include audio output device 2108 (or a corresponding interface circuit as described above). Audio output device 2108 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0069] Electrical device 2100 may include audio input device 2118 (or a corresponding interface circuit as described above). Audio input device 2118 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0070] Electrical device 2100 may include GPS device 2116 (or a corresponding interface circuit as described above). GPS device 2116 may communicate with satellite-based systems and may receive the location of electrical device 2100, as known in the art.

[0071] Electrical device 2100 may include another output device 2110 (or a corresponding interface circuit as described above). Examples of other output devices 2110 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0072] Electrical device 2100 may include another input device 2120 (or a corresponding interface circuit as described above). Examples of other input devices 2120 may include an accelerometer, gyroscope, compass, image capture device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0073] Electrical device 2100 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop electrical device, server equipment or other networked computing components, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electronic device. In some embodiments, electronic device 2100 can be any other electronic device that processes data.

[0074] Example Data Processing System

[0075] Figure 7 Block diagrams illustrating an example data processing system 2200 according to some embodiments of the present disclosure are provided. This example data processing system 2200 can be configured to control the operation of one or more TDCs having relatively low area and power. For example, the data processing system 2200 can be configured to implement or control a portion of TDC 100, or any other embodiment of a TDC with relatively low area and power described herein. In another example, the data processing system 2200 can be configured to implement controller 520 or at least a portion of any other controller configured to control various aspects of the operation of TDC 100 as described herein.

[0076] like Figure 7 As shown, the data processing system 2200 may include at least one processor 2202, such as a hardware processor 2202 coupled to the storage element 2204 via a system bus 2206. In this way, the data processing system can store program code in the storage element 2204. Furthermore, the processor 2202 can execute program code accessed from the storage element 2204 via the system bus 2206. On one hand, the data processing system can be implemented as a computer suitable for storing and / or executing program code. However, it should be understood that the data processing system 2200 can be implemented in the form of any system including a processor and memory capable of performing the functions described herein.

[0077] In some implementations, processor 2202 may execute software or algorithms to perform the activities discussed in this disclosure, particularly those related to a TDC with relatively low area and power, as described herein. Processor 2202 may include any combination of hardware, software, or firmware providing programmable logic, including but not limited to microprocessors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), application-specific integrated circuits (ASICs), or virtual machine processors. Processor 2202 may be communicatively coupled to storage element 2204, for example, in a direct memory access (DMA) configuration so that processor 2202 can read from or write to storage element 2204.

[0078] Typically, storage element 2204 may include any suitable volatile or non-volatile storage technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory regions, magnetic or magnetic tape memory, or any other suitable technology. Unless otherwise stated, any storage element discussed herein should be construed as encompassing the broad term "memory." Information being measured, processed, tracked, or transmitted to or from any component of data processing system 2200 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced within any suitable timeframe. Any such storage option may be included within the broad term "memory" as used herein. Similarly, any potential processing elements, modules, and machines described herein should be construed as encompassing the broad term "processor." Each element shown in the current figures, for example... Figure 1-3 Any element of the TDC 100 shown may also include a suitable interface for receiving, transmitting and / or otherwise delivering data or information in a network environment, so that they can communicate with, for example, the data processing system 2200.

[0079] In some exemplary embodiments, mechanisms for implementing one or more TDCs with relatively low area and power, as outlined herein, can be implemented by logic encoded in one or more tangible media. This logic may include non-transitory media, such as embedded logic provided in ASIC or DSP instructions, software (potentially including object code and source code) to be executed by a processor or other similar machine. In some of these instances, such as Figure 7Storage elements such as storage element 2204 shown can store data or information used for the operations described herein. This includes storage elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor can execute any type of instructions associated with data or information to implement the operations detailed herein. In one example, the processor, for example... Figure 7 The processor 2202 shown can transform an element or item (e.g., data) from one state or thing to another. In another example, the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or ASIC, which includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0080] Storage element 2204 may include one or more physical memory devices, such as local memory 2208 and one or more mass storage devices 2210. Local memory may refer to RAM or other non-persistent storage devices that are typically used during the actual execution of the program code. Mass storage devices may be implemented as hard disk drives or other persistent data storage devices. Processing system 2200 may also include one or more cache memories (not shown) that provide temporary storage for at least some of the program code to reduce the number of times the program code must be retrieved from mass storage device 2210 during execution.

[0081] like Figure 7 As shown, storage element 2204 can store application program 2218. In various embodiments, application program 2218 may be stored in local memory 2208, one or more mass storage devices 2210, or separately from local memory and mass storage devices. It should be understood that data processing system 2200 may further execute an operating system that facilitates the execution of application 2218. Figure 7 (Not shown in the image). The application 2218, implemented as executable program code, can be executed by the data processing system 2200, for example, by the processor 2202. In response to executing the application, the data processing system 2200 can be configured to perform one or more of the operational or method steps described herein.

[0082] Input / output (I / O) devices, depicted as input device 2212 and output device 2214, may optionally be coupled to a data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, etc. Examples of output devices may include, but are not limited to, a monitor or display, a speaker, etc. In some embodiments, output device 2214 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some embodiments, the system may include a driver (not shown) for output device 2214. Input and / or output devices 2212, 2214 may be coupled to the data processing system directly or via an intermediate I / O controller.

[0083] In one embodiment, the input and output devices can be implemented as a combined input / output device (in... Figure 7 The image is shown in dashed lines, surrounding input device 2212 and output device 2214. An example of such a combined device is a touch-sensitive display, sometimes also called a "touchscreen display" or simply a "touchscreen". In such embodiments, input to the device can be provided by the movement of a physical object, such as a stylus or a user's finger, on or near the touchscreen display.

[0084] Network adapter 2216 may also optionally be coupled to the data processing system to enable it to couple to other systems, computer systems, remote network devices, and / or remote storage devices via an intermediate private or public network. The network adapter may include: a data receiver for receiving data transmitted to the data processing system 2200 by the systems, devices, and / or networks; and a data transmitter for transmitting data from the data processing system 2200 to the systems, devices, and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with the data processing system 2200.

[0085] Select an example

[0086] The following paragraphs provide various examples of the implementation schemes disclosed herein.

[0087] Example 1 provides a TDC including: a ring oscillator (110) comprising multiple stages (e.g., an odd number of stages, three or more); a margin generation circuit (120) wherein the number of stages of the margin generation circuit is equal to the number of stages of the ring oscillator, and wherein each stage of the margin generation circuit is configured to operate on the outputs of two different stages of the ring oscillator; and a counter (130) coupled to the output of one of the multiple stages of the ring oscillator and configured to count a number of times (e.g., switching the count of the number of times the output of the stages of the ring oscillator is switched from 0 to 1 or from 1 to 0) during a time period in which the count is converted to a digital value (e.g., ...). The signal at the output of one of the multiple stages of the ring oscillator switch, which is between a first signal level (e.g., a voltage level corresponding to the high logic state) and a second signal level (e.g., a voltage level corresponding to the low logic state) during the time period when the enable signal of the ring oscillator and the margin generation circuit is in a first logic state (e.g., logic high); and a combiner (150), configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit (e.g., when the enable signal of the ring oscillator and the margin generation circuit switches to a second logic state (e.g., logic low)) to generate a digital value indicating the time period. In such a TDC, the counter can operate on only one of the ring oscillator outputs (e.g., on the output of the last stage of the ring oscillator as shown in this figure, although in other embodiments the counter can operate on the output of any other ring oscillator stage) when the margin generation circuit is used to provide a code corresponding to the state of the ring oscillator as the enable signal of the ring oscillator and the margin generation circuit switch to the second logic state, which is beneficial for keeping the size of the counter relatively small.

[0088] Example 2 provides a TDC according to Example 1, wherein the value indicating the number of times the counter counts is based on (e.g., equal to) the number of times the counter counts using a multiplier (140) multiplied by (e.g., equal to) the value indicating the number of stages of the ring oscillator.

[0089] Example 3 provides a TDC according to Example 1 or 2, wherein the counter includes a first edge generator and a second edge generator, the first edge generator being configured to generate a first indication when a signal at the output of one of the multiple stages of the ring oscillator switches from a first signal level (e.g., a voltage level corresponding to a logic high) to a second signal level (e.g., a voltage level corresponding to a logic low), and the second edge generator being configured to generate a second indication when a signal at the output of one of the multiple stages of the ring oscillator switches from the second signal level (e.g., a voltage level corresponding to a logic low) to the first signal level (e.g., a voltage level corresponding to a logic high); and the number of times the counter counts is the sum of the number of times the first indication is generated by the first edge generator and the number of times the second indication is generated by the second edge generator during the time period during which the value is converted to a digital value.

[0090] Example 4 provides a TDC according to Example 3, wherein the counter further includes a first multiplier, a second multiplier, and an adder. In such a TDC, the first multiplier is configured to produce a first multiplier output by multiplying a value indicating (e.g., equal to) the stage number of the ring oscillator by the number of times the first edge generator produces a first indication during the time period during which the value is converted to a digital value; the second multiplier is configured to produce a second multiplier output by multiplying a value indicating (e.g., equal to) the stage number of the ring oscillator by the number of times the second edge generator produces a second indication during the time period during which the value is converted to a digital value; the adder is configured to generate an adder output by adding the first multiplier output and the second multiplier output; and a value indicating the number of times counted by the counter is based on (e.g., equal to) the adder output.

[0091] Example 5 provides a TDC according to any of the preceding examples, wherein the counter is configured to be reset after the digital value is generated and before the start of the transition of another time period (i.e., the value of the counter is configured to be set to some reset value (e.g., set to zero)).

[0092] Example 6 provides a TDC according to any of the preceding examples, wherein the margin generation circuit is configured to be reset after the digital value is generated and before the start of the transition in another time period (i.e., the output of the margin generation circuit is configured to be set to a certain reset value (e.g., set to zero)).

[0093] Example 7 provides a TDC according to any of the preceding examples, wherein the ring oscillator is configured to be reset after the digital value is generated and before the start of a transition in another time period (i.e., the outputs of multiple stages of the ring oscillator are configured to be set to their respective reset values ​​(e.g., for the example of a 3-stage ring oscillator, they are set to 1, 0, 1)).

[0094] Example 8 provides a TDC according to any of the preceding examples, wherein the first stage of the margin generation circuit is configured to operate on the output of the first stage of the ring oscillator and the output of the last stage of the ring oscillator, and the second stage of the margin generation circuit is configured to operate on the output of the first stage of the ring oscillator and the output of the second stage of the ring oscillator.

[0095] Example 9 provides a TDC according to any of the preceding examples, wherein the last stage of the margin generation circuit is configured to operate on the output of the one preceding the last stage of the ring oscillator and the output of the last stage of the ring oscillator.

[0096] Example 10 provides a TDC based on any of the preceding examples, wherein each stage of the margin generation circuit includes a separate (i.e., different example) logic circuit with the response of an XOR gate.

[0097] Example 11 provides a TDC according to Example 10, wherein the TDC further includes a respective (i.e., different example) latch circuit corresponding to each stage of the ring oscillator, each latch circuit having an input configured to receive a signal indicating the output of the stage of the ring oscillator corresponding to the latch circuit, and also having an output of logic circuitry coupled to the corresponding stage of the margin generation circuit.

[0098] Example 12 provides a TDC according to Example 11, wherein at least one of the latching circuits has another input configured to receive a control signal that is configured to enable the margin generation circuit to generate its output once the time period for converting to a digital value ends and before resetting the margin generation circuit for another time period conversion. For example, such a control signal could be an enable signal, which could be configured to be at a first signal level (e.g., a voltage level corresponding to a logic high) during the time period for converting to a digital value and at a second signal level (e.g., a voltage level corresponding to a logic low) outside of all time periods for converting to a digital value.

[0099] Example 13 provides a TDC according to any of the preceding examples, wherein each stage of the ring oscillator includes a separate (i.e., different example) logic circuit with a response of NOT gates (in other words, each stage of the ring oscillator contains a digital inverter).

[0100] Example 14 provides a TDC according to any of the preceding examples, further comprising pulse adjustment logic configured to generate an enable signal for the ring oscillator and the margin generation circuitry, such that: if the start signal precedes the stop signal, the enable signal is active (e.g., has a voltage level corresponding to a logic high) when the start signal is active (e.g., has a voltage level corresponding to a logic high) and the stop signal is inactive (e.g., has a voltage level corresponding to a logic low); and if the start signal lags the stop signal, the enable signal is active when the stop signal is active (e.g., has a voltage level corresponding to a logic high) and the start signal is inactive (e.g., has a voltage level corresponding to a logic low). The pulse adjustment logic can be further adjusted to provide an indication to the TDC whether the start signal leads the stop signal or otherwise, allowing test pulses to be provided to calibrate the TDC, etc.

[0101] Example 15 provides a TDC according to any of the preceding examples, further including saturation logic configured to determine whether the digital value is greater than a saturation threshold, and to set the digital value to a predetermined value if the determination is positive.

[0102] Example 16 provides an electronic device comprising: a time-varying clock (TDC) configured to convert a time period indicating a phase difference between a reference clock signal and an input clock signal into a digital value; and further comprising: a PLL circuit configured to generate an output signal having a phase related to the phase of the input clock signal based on the digital value generated by the TDC. In such an electronic device, the TDC comprises: a ring oscillator (110) including multiple stages (e.g., an odd number of stages of three or more); a margin generation circuit (120) wherein the number of stages of the margin generation circuit is equal to the number of stages of the ring oscillator, and wherein each stage of the margin generation circuit is configured to operate on the outputs of two different stages of the ring oscillator; and a combiner (150) configured to generate a digital value based on the output of the margin generation circuit.

[0103] Example 17 provides an electronic device according to Example 16, wherein the electronic device is a digital signal processing chip or a digital signal processing circuit.

[0104] Example 18 provides an electronic device according to Example 16 or 17, wherein the TDC is the TDC according to any of the preceding examples.

[0105] Example 19 provides a method for converting a time period indicating the phase difference between a reference clock signal and an input clock signal into a digital value. The method includes: providing an enable signal to each of a ring oscillator and a margin generation circuit via pulse conditioning logic, wherein the enable signal is valid during the time period (e.g., having a voltage level corresponding to a logic high) and invalid immediately before and immediately after the time period (e.g., having a voltage level corresponding to a logic low), the ring oscillator comprising multiple stages (e.g., an odd number of stages, three or more); the margin generation circuit having a number of stages equal to the number of stages of the ring oscillator, and each stage of the margin generation circuit being configured to operate on the outputs of two different stages of the ring oscillator. The method also includes counting a number of times the outputs of the ring oscillator stages are switched between a first signal level (e.g., a voltage level corresponding to a logic high) and a second signal level (e.g., a voltage level corresponding to a logic low) during the time the enable signal is valid (e.g., counting the number of times the outputs of the ring oscillator stages switch from 0 to 1 or from 1 to 0). The method also includes generating the digital value based on a value indicating the number of times the counter has been counted and the output of the margin generation circuit.

[0106] Example 20 provides a method according to Example 16, further comprising multiplying the number of times counted by the counter by a value indicating (e.g., equal to) the stage of the ring oscillator by one or more multipliers, wherein the numerical value is generated based on the value indicating the multiplication.

[0107] Example 21 provides a method according to Example 19 or 20, further comprising generating an output signal having a phase related to the phase of the input clock signal by means of a PLL circuit generating an output signal based on the digital value.

[0108] Example 22 provides a method based on any of the examples 19-21, wherein the method is executed by a TDC based on any of the preceding examples.

[0109] Example 23 provides a method according to any of Examples 19-22, wherein the method further includes steps for controlling or operating a TDC according to any of the preceding examples.

[0110] Example 24 provides a non-transitory computer-readable storage medium including instructions for execution, which, when executed by a processor, are operable to perform operations according to any of the examples 19-23.

[0111] Changes and Implementation

[0112] Although the above references are as follows Figure 1-7The exemplary embodiments shown describe embodiments of this disclosure, but those skilled in the art will recognize that the various teachings above can be applied to a variety of other embodiments.

[0113] In the discussion of the above embodiments, system components, such as counters, logic elements (e.g., XOR gates), and / or other components, can be readily replaced, substituted, or otherwise modified to suit specific circuit requirements. Furthermore, it should be noted that the use of complementary electronics, hardware, software, etc., provides equally feasible options for implementing the teachings of this disclosure in relation to implementing one or more TDCs with relatively low area and power.

[0114] As presented herein, portions of various systems for implementing one or more TDCs with relatively low area and power may include electronic circuitry performing the functions described herein. In some cases, one or more portions of the system may be provided by a processor specifically configured to perform the functions described herein. For example, the processor may include one or more dedicated components, or may include programmable logic gates configured to perform the functions described herein. The circuitry may operate in the analog domain, digital domain, or mixed-signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0115] In some embodiments, any number of circuits in the present figures can be implemented on a board of the associated electronic device. This board can be a general-purpose circuit board that can house various components of the internal electronic system of the electronic device and may also provide connectors for other peripherals. More specifically, the board can provide electrical connections through which other components of the system can communicate electrically. Any suitable processor (including DSPs, microprocessors, supporting chipsets, etc.), computer-readable non-transitory storage elements, etc., can be appropriately coupled to the board based on specific configuration requirements, processing requirements, computer design, etc. Other components (e.g., external memory, additional sensors, controllers for audio / video displays, and peripherals) can be connected to the board via cables as plug-in cards or integrated onto the board. In various embodiments, the functions described herein can be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure supporting these functions. The emulated software or firmware can be provided on a non-transitory computer-readable storage medium including instructions that allow the processor to perform those functions.

[0116] In some embodiments, the electronic circuitry of this figure may be implemented as a standalone module (e.g., a device having associated components and circuitry configured to perform a particular application or function) or implemented as a plug-in module into the dedicated hardware of an electronic device. Note that specific embodiments of this disclosure can be readily included, partially or entirely, in a system-on-a-chip (SOC) package. SOC stands for IC, which integrates components of a computer or other electronic system into a single chip. It may include digital, analog, mixed-signal, and typical RF functions: all of these functions can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple separate ICs reside within a single electronic package and are configured to interact closely with each other via the electronic package.

[0117] All specifications, dimensions, and relationships outlined herein (e.g., the number of components in a TDC with relatively small area and power, or a portion thereof, as shown in this figure) are provided for illustrative and teaching purposes only. Significant changes may be made to this information without departing from the spirit of this disclosure or the scope of the appended claims. These specifications are merely a non-limiting example and should therefore be interpreted accordingly. In the foregoing description, exemplary embodiments have been described with reference to specific processor and / or component arrangements. Various modifications and changes may be made to these embodiments without departing from the scope of the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0118] Note that, using the numerous examples provided herein, interactions can be described based on two, three, four, or more electronic components. However, this is done merely for clarity and illustrative purposes. It should be understood that systems can be combined in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in this invention can be combined in a variety of possible configurations, all of which are clearly within the broad scope of this disclosure. In some cases, it may be easier to describe one or more functions of a given set of processes by referring only to a limited number of electrical components. It should be understood that the current figures and the circuits they teach are readily expandable and can accommodate a large number of components, as well as more complex or more intricate arrangements and configurations. Therefore, the examples provided should not limit the scope or inhibit the extensive teachings that may potentially be applied to countless other architectures of electronic circuits.

[0119] Furthermore, as presented herein, the functions related to implementing one or more TDCs with relatively low area and power are only some of the possible functions that can be performed by or within the system shown in this figure. Some of these operations can be removed or eliminated where appropriate, or considerable modifications or changes can be made to these operations without departing from the scope of this disclosure. Additionally, the timing of these operations may vary significantly. The preceding operational flow is provided for illustrative and discussion purposes. The embodiments described herein offer considerable flexibility, as any suitable arrangement, timing, configuration, and timing mechanism can be provided without departing from the teachings of this disclosure.

[0120] Note that all optional features of the above-described apparatus may also be implemented with respect to the methods or processes described herein, and the details in the examples may be used anywhere in one or more embodiments.

[0121] Those skilled in the art can identify many other changes, substitutions, variations, alterations and modifications, and it is intended that this disclosure cover all such changes, substitutions, variations, alterations and modifications that fall within the scope of the appended claims.

Claims

1. A time-to-digital converter (TDC), comprising: A ring oscillator with multiple stages; A margin generation circuit has multiple stages, wherein the stages of the margin generation circuit are configured to operate on the outputs of two stages from the ring oscillator; A counter, coupled to the output of one of the multiple stages of the ring oscillator, and configured to count the number of times the signal at the output of one of the multiple stages of the ring oscillator switches from a first signal level to a second signal level and from a second signal level to a first signal level during a time period during which the signal is converted to a digital value; and A combiner is configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate the digital value.

2. The TDC of claim 1, wherein the value indicating the number of times the counter counts is based on the number of times the counter counts by multiplying by a value indicating the stage of the ring oscillator.

3. The TDC according to claim 1, wherein: The counter includes a first edge generator and a second edge generator. The first edge generator is configured to generate a first indication when the signal at the output of one of the multiple stages of the ring oscillator switches from the first signal level to the second signal level. The second edge generator is configured to generate a second indication when the signal at the output of one of the multiple stages of the ring oscillator switches from the second signal level to the first signal level; and The number of times counted by the counter is the sum of the number of times the first edge generator generates the first indication and the number of times the second edge generator generates the second indication during the time period when the values ​​are converted into digital values.

4. The TDC according to claim 3, wherein: The counter also includes a first multiplier, a second multiplier, and an adder. The first multiplier is configured to produce a first multiplier output by multiplying a value indicating the stage of the ring oscillator by the number of times the first edge generator produces the first indication during the time period during which it is converted into a digital value. The second multiplier is configured to produce a second multiplier output by multiplying a value indicating the stage of the ring oscillator by the number of times the second edge generator produces the second indication during the time period during which it is converted into a digital value. The adder is configured to generate an adder output by adding the outputs of the first multiplier and the second multiplier. The value indicating the number of times the counter counts is based on the adder output.

5. The TDC of claim 1, wherein at least one of the counter, the margin generation circuit, and the ring oscillator is configured to be reset after the digital value is generated and before the start of a transition in another time period.

6. The TDC according to claim 1, wherein: The first stage of the margin generation circuit is configured to operate on the output of the first stage of the ring oscillator and the output of the last stage of the ring oscillator. The second stage of the margin generation circuit is configured to operate on the output of the first stage of the ring oscillator and the output of the second stage of the ring oscillator.

7. The TDC of claim 1, wherein the last stage of the margin generation circuit is configured to operate on the outputs of the last two stages of the ring oscillator.

8. The TDC of claim 1, wherein each stage of the margin generation circuit includes logic circuitry having an XOR gate response.

9. The TDC of claim 8, wherein the TDC further comprises a corresponding latch circuit for each stage of the ring oscillator, each latch circuit having an input configured to receive a signal indicating the output of the ring oscillator corresponding to the stage of the latch circuit, and further having an output of logic circuitry coupled to the corresponding stage of the margin generation circuit.

10. The TDC of claim 9, wherein at least one of the latching circuits has another input configured to receive a control signal configured to enable the margin generation circuit to generate its output once the time period converted to a digital value ends and before resetting the margin generation circuit for conversion to another time period.

11. The TDC of claim 1, further comprising pulse adjustment logic configured to generate an enable signal for the ring oscillator and the margin generation circuit, such that: If the start signal precedes the stop signal, then the enable signal is valid when the start signal is valid and the stop signal is invalid; and If the start signal lags behind the stop signal, then the enable signal is valid when the stop signal is valid and the start signal is invalid.

12. The TDC of claim 1 further includes saturation logic configured to determine whether the digital value is greater than a saturation threshold, and to set the digital value to a predetermined value when the determination is affirmative.

13. An electronic device comprising: A time-to-digital converter (TDC) is configured to convert a time period indicating the phase difference between a reference clock signal and an input clock signal into a digital value. and A phase-locked loop (PLL) circuit is configured to generate an output signal with a phase related to the phase of the input clock signal based on a digital value generated by a TDC. The TDC includes: Ring oscillator, comprising multiple stages, A margin generation circuit includes multiple stages, wherein each stage of the margin generation circuit is configured to operate on the outputs of two stages from the ring oscillator. A counter, coupled to the output of one of the multiple stages of the ring oscillator, is configured to count the number of times the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level and a second signal level during the time period. and A combiner is configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate a digital value.

14. The electronic device of claim 13, wherein the electronic device is a digital signal processing chip or a digital signal processing circuit.

15. A time-to-digital converter (TDC) configured to convert a time period into a digital value, the TDC comprising: A ring oscillator with multiple stages; A margin generation circuit is coupled to the output of at least two of the plurality of stages; A counter, coupled to the output of one of the multiple stages of the ring oscillator, is configured to count the number of times the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level and a second signal level during the time period. and A combiner is configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate a digital value.

16. The TDC according to claim 15, wherein: The margin generation circuit has multiple stages, and The last stage of the margin generation circuit is configured to operate on the outputs of the last two stages of the ring oscillator.

17. The TDC according to claim 15, wherein: The margin generation circuit has multiple stages. The first stage of the margin generation circuit is configured to operate on the output of the first stage of the ring oscillator and the output of the last stage of the ring oscillator. The second stage of the margin generation circuit is configured to operate on the output of the first stage of the ring oscillator and the output of the second stage of the ring oscillator.

18. The TDC according to claim 15, wherein, The combiner is configured to generate the digital value based on the number of times the counter counts by multiplying by a value indicating the stage of the ring oscillator.

19. The TDC according to claim 15, wherein: The margin generation circuit has multiple stages. The stage of the margin generation circuit is configured to operate on the outputs of the two stages from the ring oscillator, and At least one stage of the margin generation circuit includes a logic circuit with an XOR gate response.

20. The TDC according to claim 15, further comprising: The pulse adjustment logic is configured to generate an enable signal for the ring oscillator and the margin generation circuit, such that: If the start signal precedes the stop signal, then the enable signal is valid when the start signal is valid and the stop signal is invalid. and If the start signal lags behind the stop signal, then the enable signal is valid when the stop signal is valid and the start signal is invalid.

21. The TDC of claim 1, wherein each stage of the ring oscillator includes logic circuitry with a NOT gate response.

22. A method for converting a time period indicating the phase difference between a reference clock signal and an input clock signal into a digital value, the method comprising: Enable signals are provided for each of the ring oscillator and the margin generation circuit via pulse regulation logic, where: The enable signal is valid during the specified time period and is invalid before and after that time period. The ring oscillator includes multiple stages. The margin generation circuit includes multiple stages, and Each stage of the margin generation circuit is configured to operate on the outputs of the two stages of the ring oscillator; A counter is used to count the number of times the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level and a second signal level during the time the enable signal is active; and The digital value is generated based on the value indicating the number of times the counter counts and the output of the margin generation circuit.

23. The method of claim 22, further comprising multiplying the number of counts by the counter by a value indicating the stage of the ring oscillator by one or more multipliers, wherein, The numerical value is generated based on the value indicating the multiplication.

24. The method of claim 22, further comprising generating an output signal having a phase related to the phase of the input clock signal by generating an output signal based on the digital value via a phase-locked loop (PLL) circuit.

25. An apparatus comprising: Ring oscillator; and Balance generation circuit; At least one of them: The input of the first stage of the margin generation circuit is coupled to the output of the first stage of the ring oscillator and the output of the last stage of the ring oscillator. The input of the second stage of the margin generation circuit is coupled to the output of the first stage of the ring oscillator and the output of the second stage of the ring oscillator, and The input of the last stage of the margin generation circuit is coupled to the output of the stage preceding the last stage of the ring oscillator and the output of the last stage of the ring oscillator.

26. The apparatus according to claim 25, wherein: The ring oscillator includes multiple stages, including a first stage, a second stage, a stage preceding the last stage, and the last stage of the ring oscillator. The device also includes a counter coupled to the output of one of the multiple stages of the ring oscillator, which counts the number of times the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level and a second signal level during a time period during which it is converted into a digital value.

27. The apparatus according to claim 26, wherein: The counter includes a first edge generator and a second edge generator. The first edge generator is configured to generate a first indication when the signal at the output of one of the multiple stages of the ring oscillator switches from the first signal level to the second signal level. The second edge generator is used to generate a second indication when the signal at the output of one of the multiple stages of the ring oscillator switches from the second signal level to the first signal level; and The number of times counted by the counter is based on the number of times the first edge generator generates a first indication and the number of times the second edge generator generates a second indication during the time period during which the values ​​are converted into digital values.

28. The apparatus of claim 26, further comprising a combiner for combining a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate the digital value.

29. The apparatus according to claim 28, wherein, The value indicating the number of times the counter counts is based on the number of times the counter counts by multiplying by the value indicating the stage of the ring oscillator.

30. The apparatus according to claim 25, wherein: The device is used to convert a time period into a digital value based on the output of the margin generation circuit, and The margin generation circuit must be reset after the digital value is generated and before the transition of another time period begins.

31. The apparatus according to claim 25, wherein: The device is used to convert a time period into a digital value based on the output of the margin generation circuit, and The device also includes saturation logic for determining whether the digital value is greater than a saturation threshold, and setting the digital value to a predetermined value when the determination is positive.

32. The apparatus according to claim 25, wherein: The margin generation circuit includes multiple stages, including a first stage, a second stage, and a final stage. A single stage of the plurality of stages of the margin generation circuit includes a logic circuit with an XOR gate response.

33. The apparatus according to claim 32, wherein, The device further includes corresponding latch circuits for different stages of the ring oscillator, each latch circuit having an input for receiving a signal indicating the output of the ring oscillator corresponding to the stage of the latch circuit, and also having an output of logic circuitry coupled to a corresponding single stage of the margin generation circuit.

34. The apparatus of claim 25, further comprising pulse adjustment logic for generating an enable signal for the ring oscillator and the margin generation circuit, such that: If the start signal precedes the stop signal, then the enable signal is valid when the start signal is valid and the stop signal is invalid; and If the start signal lags behind the stop signal, then the enable signal is valid when the stop signal is valid and the start signal is invalid.

35. The apparatus according to claim 25, wherein: This device is used to convert a time period indicating the phase difference between a reference clock signal and an input clock signal into a digital value, and The device also includes a phase-locked loop (PLL) circuit for generating an output signal with a phase related to the phase of the input clock signal based on the digital values ​​generated by the device.

36. The apparatus according to claim 35, wherein, The device is a time-to-digital converter (TDC).

37. The apparatus according to claim 25, wherein, The device is a digital signal processor.

38. An apparatus for converting a time period indicating a phase difference between a reference clock signal and an input clock signal into a digital value, the apparatus comprising: A ring oscillator, comprising multiple stages; A margin generation circuit has multiple stages, wherein the stages of the margin generation circuit are configured to operate on the outputs of two of the multiple stages of the ring oscillator; A counter, coupled to the output of one of the multiple stages of the ring oscillator, and configured to count the number of times the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level and a second signal level during the time period; and A combiner is configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate the digital value. The margin generation circuit is reset after the digital value is generated and before the transition of another time period begins.

39. The apparatus according to claim 38, wherein, The value indicating the number of times the counter counts is based on the number of times the counter counts by multiplying by the value indicating the stage of the ring oscillator.

40. The apparatus of claim 38, wherein a single stage of the margin generation circuit comprises logic circuitry having an XOR gate response.

41. The apparatus according to claim 38, wherein, The device also includes a phase-locked loop (PLL) circuit for generating an output signal having a phase related to the phase of the input clock signal based on the digital value.

42. The apparatus according to claim 41, wherein, The device is a time-to-digital converter (TDC).

43. An apparatus for converting a time period indicating a phase difference between a reference clock signal and an input clock signal into a digital value, the apparatus comprising: A ring oscillator, comprising multiple stages; A margin generation circuit is coupled to the output of at least two of the plurality of stages; A counter, coupled to the output of one of the multiple stages of a ring oscillator, is used to count the number of times the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level and a second signal level during a time period during which it is converted into a digital value. as well as A combiner is configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate the digital value. The value indicating the number of times the counter counts is based on the number of times the counter counts by multiplying by the value indicating the stage of the ring oscillator.

44. The apparatus according to claim 43, wherein: The counter includes a first edge generator and a second edge generator. The first edge generator is configured to generate a first indication when the signal at the output of one of the multiple stages of the ring oscillator switches from the first signal level to the second signal level. The second edge generator is configured to generate a second indication when the signal at the output of one of the multiple stages of the ring oscillator switches from the second signal level to the first signal level, and The number of times counted by the counter is based on the number of times the first edge generator generates a first indication and the number of times the second edge generator generates a second indication during the time period during which the values ​​are converted into digital values.

45. The apparatus according to claim 43, wherein: The input of the first stage of the margin generation circuit is coupled to the output of the first stage of the ring oscillator and the output of the last stage of the ring oscillator, or The input of the second stage of the margin generation circuit is coupled to the output of the first stage of the ring oscillator and the output of the second stage of the ring oscillator.

46. ​​The apparatus according to claim 43, wherein, The input of the last stage of the margin generation circuit is coupled to the output of the stage preceding the last stage of the ring oscillator and the output of the last stage of the ring oscillator.

47. The apparatus of claim 43 further includes a phase-locked loop (PLL) circuit for generating an output signal having a phase related to the phase of the input clock signal based on the digital value.

48. The apparatus according to claim 47, wherein, The device is a time-to-digital converter (TDC).

49. A time-to-digital converter (TDC) for converting a time period indicating the phase difference between a reference clock signal and an input clock signal into a digital value, the TDC comprising: Ring oscillator; A margin generation circuit is coupled to the output of at least two stages of the ring oscillator; A counter, coupled to the output of one of the multiple stages of the ring oscillator, is configured to count the number of times the signal at the output of one of the multiple stages of the ring oscillator switches between a first signal level and a second signal level during the time period. as well as A combiner is configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate the digital value. The margin generation circuit includes a logic circuit with an XOR gate response.

50. The TDC according to claim 49, wherein, The input of the first stage of the margin generation circuit is coupled to the output of the first stage of the ring oscillator and the output of the last stage of the ring oscillator.

51. The TDC according to claim 49, wherein, The input of the second stage of the margin generation circuit is coupled to the output of the first stage of the ring oscillator and the output of the second stage of the ring oscillator.

52. The TDC according to claim 49, wherein, The input of the last stage of the margin generation circuit is coupled to the output of the stage preceding the last stage of the ring oscillator and the output of the last stage of the ring oscillator.

53. The TDC of claim 49 further includes a phase-locked loop (PLL) circuit for generating an output signal having a phase related to the phase of the input clock signal based on the digital value.

54. A time-to-digital converter (TDC) for converting a time period indicating the phase difference between a reference clock signal and an input clock signal into a digital value, the TDC comprising: Ring oscillator; A margin generation circuit is coupled to the outputs of at least two stages of the ring oscillator, wherein the digital value is generated based on the output of the margin generation circuit; as well as Saturation logic is used to set the digital value to a predetermined value when the digital value generated based on the output of the margin generation circuit is greater than a saturation threshold.

55. The TDC according to claim 54, further comprising: A counter, coupled to the output of one of the multiple stages of a ring oscillator, is configured to count the number of times a signal at the output of one of the multiple stages of the ring oscillator switches from a first signal level to a second signal level and from a second signal level to a first signal level during a time period in which the signal is converted into a digital value. as well as A combiner is configured to combine a value indicating the number of times the counter has counted with the output of the margin generation circuit to generate the digital value.

56. The TDC of claim 54 further includes a phase-locked loop (PLL) circuit for generating an output signal having a phase related to the phase of the input clock signal based on the digital value.

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