Driving circuit and electronic equipment

Abstract

The present disclosure provides a driving circuit, comprising: a transimpedance amplifier, N-stage phase compensators, N-stage broadband amplifiers, and a test buffer, wherein the transimpedance amplifier is connected to the first-stage phase compensator, the K-th-stage phase compensator among the N-stage phase compensators is connected to the K-th-stage broadband amplifier among the N-stage broadband amplifiers, and the N-stage broadband amplifier is connected to the test buffer, where 1≤K≤N; the transimpedance amplifier is configured to convert an input signal into a voltage signal and perform signal amplification processing; the K-th-stage phase compensator is configured to provide an input DC bias for the K-th-stage broadband amplifier and provide phase compensation for the output signals of the transimpedance amplifier and the K-th-stage broadband amplifier; the K-th-stage broadband amplifier is configured to amplify the output signal of the K-th-stage phase compensator and provide additional voltage gain; and the test buffer is configured to convert the output signal of the N-stage broadband amplifier into a driving signal and a test signal, respectively. The present disclosure also provides an electronic device.

Description

Technical Field

[0001] The present disclosure relates to the technical field of high-frequency driving circuits, and in particular to a driving circuit and an electronic device. Background Art

[0002] RF MEMS (Micro-Electro-Mechanical System) resonators can output higher reference frequencies than traditional quartz crystal resonators, and have a much higher quality factor than traditional LC resonators. Therefore, it will have good application prospects in RF / millimeter wave / THz transceivers for new generation wireless communications such as 5G, 6G, and WiFi6. As the core component of RF MEMS resonators, MEMS resonators can generally be divided into two categories, namely capacitive and piezoelectric. Compared with piezoelectric resonators, capacitive resonators have the dual advantages of high frequency and high quality factor, so they are more valuable for research. However, their dynamic resistance is very large, which requires an ultra-high gain peripheral drive circuit. How to make the peripheral circuit have both large bandwidth and ultra-high transimpedance gain has always been a research problem in academia and industry. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, the present disclosure provides a drive circuit and electronic device, in which a phase compensator consisting of a resistor-capacitor coupling structure is arranged before a broadband amplifier. While providing an overall phase compensation function for the drive circuit, it also provides a stable input bias voltage for the broadband amplifier. This circuit eliminates the adaptive control loop, effectively ensuring the simplicity and stability of the circuit and reducing the power consumption of the entire circuit.

[0004] A first aspect of the present disclosure provides a driving circuit, comprising: a transimpedance amplifier, an N-stage phase compensator, an N-stage broadband amplifier, and a test buffer, wherein the transimpedance amplifier is connected to the first-stage phase compensator, the K-th stage phase compensator among the N-stage phase compensators is connected to the K-th stage broadband amplifier among the N-stage broadband amplifiers, and the N-stage broadband amplifier is connected to the test buffer, 1≤K≤N; wherein the transimpedance amplifier is used to convert an input signal into a voltage signal and perform signal amplification processing; the K-th stage phase compensator is used to provide an input DC bias for the K-th stage broadband amplifier, and to provide phase compensation for the output signals of the transimpedance amplifier and the K-th stage broadband amplifier; the K-th stage broadband amplifier is used to amplify the output signal of the K-th stage phase compensator and provide additional voltage gain; and the test buffer is used to convert the output signal of the N-stage broadband amplifier into a driving signal and a test signal, respectively.

[0005] Furthermore, the N-stage phase compensators all adopt a passive structure of resistors and capacitors, including: a digital capacitor array, a first digital resistor array and a second digital resistor array, wherein one end of the digital capacitor array in the first-stage phase compensator is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator of the same stage; one end of the digital capacitor array in the K+1-stage phase compensator is connected to an output end of the K-stage broadband amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator of the same stage; the other ends of the first digital resistor array and the second digital resistor array in the N-stage phase compensators are respectively connected to the second power supply and the ground line.

[0006] Furthermore, the digital capacitor array, the first digital resistor array, and the second digital resistor array in the N-stage phase compensator are used to provide phase compensation for output signals of the transimpedance amplifier and its broadband amplifier at the same stage.

[0007] Furthermore, the digital capacitor array, the first digital resistor array and the second digital resistor array are respectively controlled by digital codes stored in a memory, wherein the digital codes are obtained after the drive circuit is factory debugged and stored in the memory for subsequent search and reading.

[0008] Furthermore, the N-stage phase compensators all adopt a passive structure of resistors and capacitors, including: a capacitor, a first digital resistor array, and a second digital resistor array, wherein one end of the capacitor in the first-stage phase compensator is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator of the same stage; one end of the capacitor in the K+1-stage phase compensator is connected to an output end of the K-stage broadband amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator of the same stage; the other ends of the first digital resistor array and the second digital resistor array in the N-stage phase compensators are respectively connected to the second power supply and the ground line.

[0009] Furthermore, the first digital resistor array and the second digital resistor array in the N-stage phase compensator are used to provide phase compensation for output signals of the transimpedance amplifier and the broadband amplifier at the same stage.

[0010] Furthermore, the first digital resistor array and the second digital resistor array are respectively controlled by digital codes stored in a memory, wherein the digital codes are obtained after the drive circuit is debugged at the factory and stored in the memory for subsequent search and reading.

[0011] Furthermore, the N-stage phase compensators all adopt a passive structure of resistors and capacitors, including: a digital capacitor array, a first resistor and a second resistor, wherein one end of the digital capacitor array in the first-stage phase compensator is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first resistor and the second resistor in the phase compensator of the same level; one end of the digital capacitor array in the K+1-stage phase compensator is connected to an output end of the K-stage broadband amplifier, and the other end thereof is connected to the first resistor and the second resistor in the phase compensator of the same level; the other ends of the first resistor and the second resistor in the N-stage phase compensators are respectively connected to the second power supply and the ground line.

[0012] Furthermore, the digital capacitor array in the N-stage phase compensator is used to provide phase compensation for output signals of the transimpedance amplifier and the broadband amplifier at the same stage.

[0013] Furthermore, the digital capacitor array in the N-stage phase compensator is used to provide phase compensation for output signals of the transimpedance amplifier and the broadband amplifier of the same stage.

[0014] Furthermore, the transimpedance amplifier adopts an adjustable common-gate amplification structure, including: a main amplification branch, used to amplify the input signal; an adjustable branch, used to reduce the input equivalent resistance in the transimpedance amplifier; a bias branch, used to provide current bias for the main amplification branch; a source follower, connected in series with the main amplification branch, used to provide isolation and driving effects for the main amplification branch.

[0015] Furthermore, the N-stage broadband amplifiers all adopt a Cherry-Hooper structure, including: a first-stage inverting amplifier and a second-stage inverting amplifier arranged in series, the first-stage inverting amplifier and the second-stage inverting amplifier adopt a current multiplexing structure or a common-source amplifier structure in the form of an inverter, which is used to amplify the output voltage signal of the transimpedance amplifier and provide voltage gain and broadband characteristics.

[0016] Furthermore, the transimpedance amplifier adopts a current mirror amplification structure, a current mirror amplification structure with local negative feedback, or a common-gate amplification structure.

[0017] Furthermore, the transimpedance amplifier is powered by a first power supply, and the N-stage phase compensator and the N-stage broadband amplifier are both powered by a second power supply, wherein the voltage of the first power supply is higher than the voltage of the second power supply.

[0018] Furthermore, the test buffer is powered by a third power supply, and a voltage of the third power supply is higher or lower than a voltage of the first power supply.

[0019] Furthermore, a DC blocking capacitor is provided between the test buffer and the Nth stage broadband amplifier, and the DC blocking capacitor is used to isolate the Nth stage broadband amplifier and the test buffer from mutual interference.

[0020] A second aspect of the present disclosure provides an electronic device, comprising: the driving circuit provided by the first aspect of the present disclosure.

[0021] Compared with the prior art, the present disclosure has at least the following beneficial effects:

[0022] (1) The driving circuit provided by the present disclosure has a passive tunable phase compensator at the input end of the broadband amplifier. The phase compensator not only provides the input bias voltage of the amplifier (resistance-capacitance coupling mechanism), but also compensates for the lag phase shift of the driving circuit (the high-pass characteristics of the capacitor and resistor). Compared with the prior art, the technical solution provided by the present disclosure does not require the design of a broadband transimpedance amplifier with high gain, nor does it require the design of a broadband tunable phase shifter and a high-speed phase-locked loop circuit with high difficulty. The structure is more concise and practical.

[0023] (2) The phase compensator's tuning control is implemented using a digital code derived from the factory commissioning of the drive circuit and stored in a ROM memory for subsequent access. Compared to the prior art, the present disclosure avoids a broadband closed-loop circuit, making the entire drive circuit more stable.

[0024] (3) The driving circuit provided by the present application mainly consists of four parts: a transimpedance amplifier, a phase compensation circuit, a Cherry-Hooper amplifier, and a test buffer. The phase compensation circuit is implemented by only one adjustable capacitor array and / or two adjustable resistor arrays, avoiding the complex circuits such as the adaptive control branch and active tunable phase shifter in the prior art. Therefore, the driving circuit provided by the present application has the significant advantages of circuit simplicity, stability, low noise, and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] For a more complete understanding of the present disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 The schematic diagram shows the structure of a disclosed ultra-high gain broadband circuit with adaptive phase compensation;

[0027] Figure 2 Schematically shows a structural diagram of a driving circuit according to a first embodiment of the present disclosure;

[0028] Figure 3 Schematically shows a structural diagram of a driving circuit according to a second embodiment of the present disclosure;

[0029] Figure 4 Schematically shows a structural diagram of a driving circuit according to a third embodiment of the present disclosure;

[0030] Figure 5Schematically shows a structural diagram of a driving circuit according to a fourth embodiment of the present disclosure;

[0031] Figure 6 Schematically shows a structural diagram of a driving circuit according to a fifth embodiment of the present disclosure;

[0032] Figure 7 The figure schematically shows the structure of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0034] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0035] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0036] Figure 1 The schematic diagram shows the structure of a publicly available ultra-high gain broadband circuit with adaptive phase compensation.

[0037] like Figure 1 As shown, the ultra-high gain broadband circuit includes: a first-stage transimpedance amplifier 211, a second-stage Cherry-Hooper broadband amplifier 212, and a third-stage tunable phase shifter and its adaptive phase control circuit 220, wherein the low-dropout regulator and the test buffer 230 are auxiliary circuit modules.

[0038] like Figure 1In the ultra-high-gain broadband circuit shown, the first-stage transimpedance amplifier 211 sacrifices bandwidth for gain, setting the upper cutoff frequency at the resonant frequency of the MEMS device to achieve a 10-fold gain increase. The approximately -45-degree lag phase shift introduced by the first-stage transimpedance amplifier 211 is compensated by a third-stage tunable phase shifter. For practicality, the phase shift of the phase shifter is adjusted in real time by the Vctrl signal output by an adaptive control branch. The tunable phase shifter is similar to a delayed resonator, adaptively adjusting its phase shift under the Vctrl control of the phase-locked loop. This design concept not only ensures the functionality of the circuit but also enhances its stability. Overall, the insufficient transimpedance gain of the driving circuit is provided by the second-stage Cherry-Hooper broadband amplifier. The first-stage broadband transimpedance amplifier 221 and the second-stage Cherry-Hooper broadband amplifier 222 in the adaptive control branch work together to generate a voltage signal with no phase lag, which serves as a reference signal for the subsequent phase-locked loop. Through the regulation of the phase-locked loop, the phase of the output voltage signal of the tunable phase shifter is locked on the reference signal, thereby achieving accurate phase compensation.

[0039] However, after conducting tape-out tests on the drive circuit, technicians found that the circuit was very prone to self-oscillation due to its closed-loop broadband circuit, which caused the phase shifter and its phase-locked loop to malfunction, and had defects such as high power consumption and high electrical noise in the output voltage.

[0040] Based on the technical problems of the above-mentioned solution, the present disclosure proposes a driving circuit comprising: a transimpedance amplifier, N-stage phase compensators, N-stage broadband amplifiers, and a test buffer, wherein the transimpedance amplifier is connected to the first-stage phase compensator, the K-th-stage phase compensator is connected to the K-th-stage broadband amplifier, and the N-stage broadband amplifier is connected to the test buffer, where 1≤K≤N; wherein the transimpedance amplifier is used to convert the input signal into a voltage signal and perform signal amplification processing; the K-th-stage phase compensator is used to provide an input DC bias for the K-th-stage broadband amplifier and provide phase compensation for the output signals of the transimpedance amplifier and the K-th-stage broadband amplifier; the K-th-stage broadband amplifier is used to amplify the output signal of the K-th-stage phase compensator and provide additional voltage gain; and the test buffer is used to convert the output signal of the N-stage broadband amplifier into a driving signal and a test signal, respectively. This driving circuit has high gain bandwidth, is more stable, and has low power consumption.

[0041] The technical solution of the present disclosure will be described in detail below in conjunction with the structural diagram of the driving circuit in the specific embodiment of the present disclosure. It should be understood that Figures 2 to 6The driving circuit and the structures of each module shown are merely exemplary to help those skilled in the art understand the technical solutions of the present disclosure, and are not intended to limit the scope of protection of the present disclosure.

[0042] Example 1

[0043] Figure 2 The figure schematically shows a structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0044] like Figure 2 As shown, the driving circuit includes: a transimpedance amplifier 100, a phase compensator 200, a broadband amplifier 300 and a test buffer 400. In this embodiment, K=N=1.

[0045] The transimpedance amplifier 100 is used to convert an input signal into a voltage signal and perform signal amplification processing.

[0046] The phase compensator 200 is connected in series with the transimpedance amplifier 100 to provide an input DC bias for the broadband amplifier 300 and provide phase compensation for the output signals of the transimpedance amplifier 100 and the broadband amplifier 300 .

[0047] The broadband amplifier 300 is connected in series with the phase compensator 200 and is used to amplify the output signal of the phase compensator 200 and provide additional voltage gain.

[0048] The test buffer 400 is connected in series with the broadband amplifier 300 and is used to convert the output signal of the broadband amplifier 300 into a driving signal and a test signal respectively.

[0049] In the embodiments of the present disclosure, Figure 2 As shown, in order to adapt to radio frequency applications and larger input parasitic capacitance, the transimpedance amplifier 100 adopts an adjustable common-gate amplification structure, including: a main amplification branch, an adjustable branch, a bias branch and a source follower.

[0050] Specifically, the main amplifier branch is composed of a MOS transistor M1 and a resistor R1, and is used to amplify the input signal. The regulating branch is composed of a MOS transistor M2 and a resistor R2, and is used to reduce the input equivalent resistance in the transimpedance amplifier 100. The bias branch is composed of a constant current source 10μA, a MOS transistor M3, and a MOS transistor M4, and is used to provide current bias for the main amplifier branch. The source follower is composed of a MOS transistor M5 and a MOS transistor M6, and is used to provide isolation and drive for the main amplifier branch. The source follower isolates the parasitic capacitance of the subsequent DC blocking capacitor or digital capacitor array C1 so that it does not affect the bandwidth of the regulated-cascode common-gate amplifier.

[0051] One end of the resistor R1 and the resistor R2 are both connected to the first power supply, the other end of the resistor R1 is respectively connected to the drain of the MOS transistor M1 and the gate of the MOS transistor M5, the other end of the resistor R2 is respectively connected to the gate of the MOS transistor M1 and the drain of the MOS transistor M2, the source of the MOS transistor M1 is respectively connected to the gate of the MOS transistor M2 and the drain of the MOS transistor M4, the drain and source of the MOS transistor M5 are respectively connected to the first power supply and the drain of the MOS transistor M6, wherein the gate and drain of the MOS transistor M3 are connected, the gate of the MOS transistor M3, the gate of the MOS transistor M4, and the gate of the MOS transistor M6 are connected, and the source of the MOS transistor M2, the source of the MOS transistor M3, the source of the MOS transistor M4, and the source of the MOS transistor M6 are all grounded through a ground line.

[0052] In this embodiment, since the transimpedance amplifier 100 needs to provide a certain voltage gain, the resistance of the load resistor R1 is relatively large. Therefore, the transimpedance amplifier 100 needs to use a higher power supply voltage. For example, the first power supply VCC1 may be 1.8V.

[0053] In this embodiment, Figure 2 As shown, the phase compensator 200 adopts a passive structure of resistors and capacitors, including: a digital capacitor array C1, a first digital resistor array R3, and a second digital resistor array R4. One end of the digital capacitor array C1 is connected to an output end of the transimpedance amplifier 100, and the other end thereof is connected to the first digital resistor array R3 and the second digital resistor array R4. The other ends of the first digital resistor array R3 and the second digital resistor array R4 are connected to a second power supply and a ground line, respectively. The digital capacitor array C1, the first digital resistor array R3, and the second digital resistor array R4 are used to provide phase compensation for the output signals of the transimpedance amplifier 100 and the broadband amplifier 300.

[0054] Specifically, the digital capacitor array C1 can be composed of multiple capacitors connected in series or in parallel, and the first digital resistor array R3 and the second digital resistor array R4 can be composed of multiple resistors connected in series or in parallel, which is not limited in the embodiments of the present disclosure. Among them, the digital capacitor array C1, the first digital resistor array R3, and the second digital resistor array R4 are all controlled by a digital code stored in a memory, wherein the digital code is obtained after the driver circuit is debugged at the factory and stored in the memory for subsequent search and reading.

[0055] In the embodiments of the present disclosure, the first digital resistor array C1, the first digital resistor array R3, or the second digital resistor array R4 can be controlled by digital codes to provide phase compensation for the output signals of the transimpedance amplifier 100 and the broadband amplifier 300. Depending on the actual application, to meet the bias requirements provided later, it is sufficient to ensure that the resistance change trends of the first digital resistor array R3 or the second digital resistor array R4 remain the same, that is, the resistance changes of the first digital resistor array R3 or the second digital resistor array R4 increase or decrease simultaneously.

[0056] In the embodiments of the present disclosure, Figure 2 As shown, broadband amplifier 300 employs a Cherry-Hooper structure, comprising a first-stage inverting amplifier and a second-stage inverting amplifier connected in series. These amplifiers employ a current-multiplexing structure in the form of inverters, amplifying the output voltage signal of transimpedance amplifier 100 and providing voltage gain and broadband performance. Because the output bias voltages of both the first-stage and second-stage inverting amplifiers are unstable, the present disclosure addresses this issue by designing the second-stage inverting amplifier as a digitally controlled MOS transistor array, enabling targeted adjustments based on actual process corners and temperature conditions.

[0057] Specifically, the first-stage inverting amplifier is composed of a MOS transistor M7 and a MOS transistor M8, and the second-stage inverting amplifier is composed of a resistor R5, a first MOS transistor array M9, and a second MOS transistor array M10. The source of the MOS transistor M7 and the source of the first MOS transistor array M9 are both connected to the second power supply VCC2, the gate of the MOS transistor M7 is connected to the other end of the digital capacitor array C1 and the gate of the MOS transistor M8, the gate of the first MOS transistor array M9 is respectively connected to the source of the MOS transistor M7, one end of the resistor R5, and the gate of the second MOS transistor array M10, the source of the first MOS transistor array M9 is respectively connected to the other end of the resistor R5 and the drain of the second MOS transistor array M10, and the source of the MOS transistor M8 and the source of the second MOS transistor array M10 are respectively grounded via ground lines.

[0058] In the disclosed embodiments, the Cherry-Hooper broadband amplifier 300 utilizes an inverter structure, which maintains sufficient gain and low power consumption even at relatively low power supply voltages. Therefore, a high power supply voltage is not required. Therefore, the voltage of the second power supply VCC2 can be lower than that of the first power supply, such as 1.6V. This Cherry-Hooper broadband amplifier 300 achieves high gain while maintaining broadband characteristics.

[0059] In the embodiment of the present disclosure, the test buffer 400 is connected in series with the broadband amplifier 300 and is used to convert the output signal of the broadband amplifier 300 into a driving signal and a test signal respectively.

[0060] Specifically, the test buffer 400 includes: a first common-source amplifier and a second common-source amplifier. The first common-source amplifier is composed of a MOS transistor 11 and a resistor R6, and the second common-source amplifier is composed of a MOS transistor 12 and a resistor R7. The first common-source amplifier outputs a driving signal V out To the MEMS resonator, the second common-source amplifier outputs a test signal V test To the external circuit or test instrument. Among them, one end of the resistor R6 and the resistor R7 are connected to the second power supply, and the other end of the resistor R6 is connected to the drive signal V out The output terminal is connected to the drain of MOS tube 11, and the other end of resistor R7 is connected to the test signal V test The output terminal is connected to the drain of MOS tube 12, the gate of MOS tube 11 is connected to the drain of MOS tube 10, and the gate of MOS tube 12 is connected to the drive signal V out The output end is connected, and the source of the MOS transistor 11 and the source of the MOS transistor 12 are both connected to the ground line.

[0061] Specifically, the load resistor R6 of the test buffer is selected and the driving signal V out The total load capacitance at the output is related to the total load capacitance, which is mainly composed of the chip and resonator PAD parasitics and is generally 0.5pF to 2pF. Therefore, the load resistor R6 cannot be too large and is generally 100Ω to 300Ω. The load resistor R7 needs to match the 50Ω load resistance of the external measuring instrument, which is generally 50Ω to 80Ω. The bias current needs to be large to ensure that the output bias voltage of the first common-source amplifier and the second common-source amplifier is within a reasonable range.

[0062] In the embodiment of the present disclosure, the power supply of the driving circuit may be more than two power supplies, and may be replaced by three or more power supplies. For example, the test buffer 400 may be powered by the second power supply VCC2 or the third power supply or the fourth power supply. Specifically, the test buffer 100 adopts a common source amplifier structure, and the load resistors R6 and R7 have relatively small resistance values ​​(in order to ensure the bandwidth of the circuit under a larger load capacitance), so the test buffer 400 does not require a high power supply voltage. This combination of high and low power supplies is conducive to minimizing the power consumption of the overall driving circuit. Preferably, the voltage of the third power supply may be lower than the voltage of the second power supply, such as 1.2V; the voltage of the fourth power supply may be higher than the voltage of the second power supply, such as 3.3V.

[0063] Since it is necessary to prioritize high transimpedance gain and secondly to ensure a wide bandwidth when designing a transimpedance amplifier, it is inevitable that the bandwidth of the output of the transimpedance amplifier does not meet the requirements, thereby introducing a lagging phase shift. In addition, the Cherry-Hooper broadband amplifier itself has a high bandwidth requirement, and it will also lose some bandwidth when it is cascaded with the transimpedance amplifier. The combined effect of these factors will introduce a lagging phase shift. These unfavorable lagging phase shifts need to be further improved by a passive phase compensator to compensate for the advanced phase. Based on this, in an embodiment of the present disclosure, a phase compensator 200 with a passive structure of resistors and capacitors is set in front of the broadband amplifier 300 instead of behind it, and the advanced phase compensation process implemented includes:

[0064] like Figure 2 As shown, the output voltage V in1 Input voltage V to the Cherry-Hooper broadband amplifier out1 The transfer function satisfies the following relationship:

[0065]

[0066] Where s represents the Laplace operator, s=j2πf, and f represents the frequency. From the above transfer function, we can see that there is a zero point at the origin. There is a pole at , and according to the phase-frequency curve of the transfer function, it can be calculated that Hz to In the frequency range of Hz, the passive structure phase compensator 200 can provide an advanced phase amount in the range of 0 to 90 degrees. By adjusting the value of the digital capacitor array C1 or the first digital resistor array R3 and the second digital resistor array R4 (R3||R4) in the phase compensator 200, it is possible to effectively compensate for the total lagging phase amount of the entire driving circuit, so that the driving circuit meets the driving requirements of the MEMS resonator in terms of the phase relationship. Compared with the prior art, the compensation method provided by the embodiment of the present disclosure is simpler and more practical, and the parasitic capacitance and power consumption are also smaller, so it has greater technical advantages.

[0067] Furthermore, the phase compensator 200, which utilizes a passive resistor-capacitor structure, is placed before the broadband amplifier 300 rather than after it. This not only provides overall phase compensation for the entire drive circuit but also provides a stable input bias voltage for the first portion of the broadband amplifier 300. The digital control code for the phase compensator 200 is obtained and stored in memory during factory testing of the drive circuit, automatically loaded each time the circuit is powered on. This design eliminates the adaptive control loop, effectively ensuring the simplicity and stability of the entire circuit, while also reducing power consumption. Finally, the inclusion of the digital capacitor array C1, the first digital resistor array R3, and the second digital resistor array R4 allows for a wider modulation range and a greater phase compensation range. However, the digital capacitor array C1 contributes to a larger parasitic capacitance in the entire drive circuit, which has a certain impact on the broadband.

[0068] Example 2

[0069] The structure of the driving circuit in this embodiment is as follows Figure 3 As shown, the difference between this embodiment and embodiment 1 is:

[0070] In this embodiment, the phase compensator 200 includes: a capacitor C1′, a first digital resistor array R3, and a second digital resistor array R4. One end of the capacitor C1′ is connected to an output end of the transimpedance amplifier 100, and the other end thereof is connected to the first digital resistor array R3 and the second digital resistor array R4. The other ends of the first digital resistor array R3 and the second digital resistor array R4 are connected to a second power supply and a ground line, respectively. The first digital resistor array R3 and the second digital resistor array R4 are used to provide phase compensation for the output signals of the transimpedance amplifier 100 and the broadband amplifier 300.

[0071] In this embodiment, phase compensation is provided for the output signals of the transimpedance amplifier 100 and the broadband amplifier 300 by controlling the first digital resistor array R3 and the second digital resistor array R4 using a digital code stored in memory. The control requirements are the same as those in Example 1 and are not further described here. The digital code is obtained after factory commissioning of the driver circuit and is stored in memory for subsequent retrieval.

[0072] Compared to Example 1, this embodiment has a smaller modulation range and a smaller phase compensation range than the phase compensator provided in Example 1. However, the provision of capacitor C1' reduces the parasitic load-to-ground capacitance seen by MOS transistor M5 in transimpedance amplifier 100, and also reduces the parasitic capacitance from the input node of broadband amplifier 300 to ground, facilitating broadband circuit design.

[0073] Example 3

[0074] The structure of the driving circuit in this embodiment is as follows Figure 4As shown, the difference between this embodiment and embodiment 1 is:

[0075] In this embodiment, the phase compensator 200 includes a digital capacitor array C1, a first resistor R3', and a second resistor R4'. One end of the digital capacitor array C1 is connected to an output end of the transimpedance amplifier 100, and the other end is connected to the first resistor R3' and the second resistor R4'. The other ends of the first resistor R3' and the second resistor R4' are connected to a second power supply and a ground line, respectively. The digital capacitor array C1 is used to provide phase compensation for the output signals of the transimpedance amplifier 100 and the broadband amplifier 300.

[0076] In this embodiment, the digital capacitor array C1 is controlled by a digital code stored in the memory to provide phase compensation for the output signals of the transimpedance amplifier 100 and the broadband amplifier 300. The digital code is obtained after the driver circuit is factory debugged and stored in the memory for subsequent search and reading.

[0077] Compared to Example 1, this embodiment has a smaller modulation range and a smaller phase compensation range than the phase compensator provided in Example 1. However, because the first resistor R3' and the second resistor R4' replace the first digital resistor array R3 and the second digital resistor array R4, respectively, the input bias voltage of the broadband amplifier 300 is more stable. However, because the first digital resistor array R3 and the second digital resistor array R4 are implemented as digitally controlled resistor arrays, process matching becomes more difficult, which worsens the temperature drift of the R3 / R4 resistance ratio and, consequently, prevents the input bias voltage of the broadband amplifier 300 from reaching its optimal value.

[0078] Example 4

[0079] The structure of the driving circuit in this embodiment is as follows Figure 5 As shown, the difference between this embodiment and embodiment 1 is:

[0080] The driving circuit includes: N-stage phase compensators and N-stage transimpedance amplifiers, wherein the transimpedance amplifier 100 is connected to the first-stage phase compensator 200, the K-th stage phase compensator in the N-stage phase compensators 200 is connected to the K-th stage broadband amplifier in the N-stage transimpedance amplifier, the N-stage phase compensator 200N is connected to one end of the N-stage broadband amplifier 300N, and the other end of the N-stage broadband amplifier 300N is connected to the test buffer 400, where 1≤K≤N.

[0081] In this embodiment, the digital capacitor array, the first digital resistor array, and the second digital resistor array in the N-stage phase compensator can be controlled individually or simultaneously in a hierarchical manner, and this is not limited in the embodiments of the present disclosure. Furthermore, the N-stage phase compensator structure in this embodiment can adopt the structure of the phase compensator 200 in Embodiment 1, Embodiment 2, or Embodiment 3, which can similarly meet various practical application requirements and will not be further described herein.

[0082] Specifically, if Figure 5 As shown, when each phase compensator in an N-stage phase compensator adopts the phase compensator structure of Example 1, one end of the digital capacitor array in the first-stage phase compensator 200 is connected to an output end of the transimpedance amplifier 100, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; one end of the digital capacitor array in the K+1-stage phase compensator is connected to an output end of the K-stage broadband amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; and the other ends of the first digital resistor array and the second digital resistor array in the N-stage phase compensator are connected to the second power supply and the ground, respectively. The digital capacitor array, the first digital resistor array, and the second digital resistor array in the N-stage phase compensator are used to provide phase compensation for the output signals of the transimpedance amplifier and the broadband amplifier at the same stage.

[0083] Specifically, when each phase compensator in an N-stage phase compensator employs the phase compensator structure of Example 2, one end of the capacitor in the first-stage phase compensator 200 is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; one end of the capacitor in the K+1-stage phase compensator is connected to an output end of the K-stage broadband amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; and the other ends of the first digital resistor array and the second digital resistor array in the N-stage phase compensator are connected to the second power supply and the ground, respectively. The first digital resistor array and the second digital resistor array in the N-stage phase compensator are used to provide phase compensation for the output signals of the transimpedance amplifier 100 and the broadband amplifier at the same stage.

[0084] Specifically, when each phase compensator in an N-stage phase compensator adopts the phase compensator structure of Example 3, one end of the digital capacitor array in the first-stage phase compensator is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first resistor and the second resistor in the phase compensator at the same stage; one end of the digital capacitor array in the K+1-stage phase compensator is connected to an output end of the K-stage broadband amplifier, and the other end thereof is connected to the first resistor and the second resistor in the phase compensator at the same stage; and the other ends of the first resistor and the second resistor in the N-stage phase compensator are connected to the second power supply and the ground, respectively. The digital capacitor array in the N-stage phase compensator is used to provide phase compensation for the output signals of the transimpedance amplifier and the broadband amplifier at the same stage.

[0085] It should be noted that in some other practical applications, the N phase compensators in the N-stage phase compensator can adopt a combination of the phase compensator 200 structure shown in Example 1, Example 2 and Example 3 to achieve different modulation ranges and accuracy requirements, and the embodiments of the present disclosure do not limit this.

[0086] Compared with the first embodiment, the configuration of the N-stage phase compensator 200 and the N-stage transimpedance amplifier 300 in this embodiment enables the entire driving circuit to have a higher gain while maintaining the bandwidth characteristic.

[0087] It should be noted that, in this embodiment, N can be any positive integer, for example: 2, 3, 4, 5, ..., which is set according to actual application requirements. The embodiment of the present disclosure does not limit the number of stages of the cascaded phase compensator 200 and the transimpedance amplifier 300.

[0088] Example 5

[0089] The structure of the driving circuit in this embodiment is as follows Figure 6 As shown, the difference between this embodiment and embodiment 1 is:

[0090] The broadband amplifier 300 includes a first-stage inverting amplifier and a second-stage inverting amplifier connected in series. The first-stage inverting amplifier and the second-stage inverting amplifier adopt a common-source amplifier structure for amplifying the output voltage signal of the transimpedance amplifier and providing voltage gain and broadband characteristics.

[0091] Specifically, the first-stage inverting amplifier is composed of a resistor R8 and a MOS transistor M8, and the second-stage inverting amplifier is composed of a resistor R5, a resistor R9, and a MOS transistor M10′. One end of each of the resistors R8 and R9 is connected to the second power supply VCC2, the other end of the resistor R8 is connected to the drain of the MOS transistor M8 and one end of the resistor R5, respectively. The other end of the resistor R9 is connected to the other end of the resistor R5 and the drain of the MOS transistor M10′, respectively. The gate of the MOS transistor M8 is connected to the other end of the digital capacitor array C1, the gate of the MOS transistor M10′ is connected to the resistor R8 and one end of the resistor R5, and the sources of the MOS transistors M8 and M10′ are grounded via ground lines.

[0092] Compared with Example 1, in this embodiment, the broadband amplifier inverter structure is replaced by a common-source amplifier structure. The common-source amplifier is not as sensitive to the external environment as the inverter. Therefore, the output stabilization bias measure in the broadband amplifier 300 can be eliminated.

[0093] In some other embodiments of the present disclosure, the transimpedance amplifier 100 may also adopt a current mirror amplification structure, a current mirror amplification structure with local negative feedback, or a common-gate amplification structure.

[0094] In some other embodiments of the present disclosure, a DC blocking capacitor is provided between the test buffer 400 and the Nth-stage broadband amplifier 300 connected in series with the test buffer 400, so that the test buffer 400 and the broadband amplifier 300 do not affect each other, thereby improving the stability of the driving circuit and reducing the power consumption of the entire driving circuit.

[0095] In the above embodiment, although the node voltages of the driving circuit are single-ended, they can also be changed to fully differential node voltages to improve the common mode and interference resistance and effectively increase the signal processing speed of the circuit.

[0096] It should be noted that in the above embodiments, the output signals of the driving circuit provided in the embodiments of the present disclosure can all be described as voltage signals. It can be understood that the input signal of a driving circuit provided in the embodiments of the present disclosure can also be other types of inputs such as current signals, which can be achieved by adding a conversion circuit in the circuit accordingly.

[0097] Another aspect of the embodiments of the present disclosure further provides an electronic device, which includes the driving circuit shown in the above embodiment.

[0098] Specifically, if Figure 7 As shown, the electronic device includes a clock source composed of a driving circuit and a radio frequency MEMS resonator provided by the present disclosure. The clock source can be used as a reference frequency source for a frequency synthesizer, or directly used as a local oscillation source for a mixer, as shown in FIG. Figure 7a; it can also be used as an independent clock source for digital systems, such as Figure 7 b. The output of the clock source can be both single-ended and differential. The drive circuit outputs a drive signal to the RF MEMS resonator and a test signal to an external device or test equipment, such as a CPU, memory, or microcontroller, although this is not limited in the embodiments of the present disclosure.

[0099] The present disclosure provides a driving circuit, which has the following beneficial effects:

[0100] (1) The driving circuit provided by the present disclosure has a passive tunable phase compensator at the input end of the broadband amplifier. The phase compensator not only provides the input bias voltage of the amplifier (resistance-capacitance coupling mechanism), but also compensates for the lag phase shift of the driving circuit (the high-pass characteristics of the capacitor and resistor). Compared with the prior art, the technical solution provided by the present disclosure does not require the design of a broadband transimpedance amplifier with high gain, nor does it require the design of a broadband tunable phase shifter and a high-speed phase-locked loop circuit with high difficulty. The structure is more concise and practical.

[0101] (2) The phase compensator's tuning control is implemented using a digital code derived from the factory commissioning of the drive circuit and stored in a ROM memory for subsequent access. Compared to the prior art, the present disclosure avoids a broadband closed-loop circuit, making the entire drive circuit more stable.

[0102] (3) The driving circuit provided by the present application mainly consists of four parts: a transimpedance amplifier, a phase compensation circuit, a Cherry-Hooper amplifier, and a test buffer. The phase compensation circuit is implemented by only one adjustable capacitor array and / or two adjustable resistor arrays, avoiding the complex circuits such as the adaptive control branch and active tunable phase shifter in the prior art. Therefore, the driving circuit provided by the present application has the significant advantages of circuit simplicity, stability, low noise, and low power consumption.

[0103] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive.

[0104] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in a variety of ways, even if such combinations or couplings are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure may be combined and / or coupled in a variety of ways without departing from the spirit and teachings of this disclosure. All such combinations and / or couplings are intended to fall within the scope of this disclosure.

[0105] Although the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

Claims

1. A driving circuit, characterized in that: include: A transimpedance amplifier, an N-stage phase compensator, an N-stage broadband amplifier, and a test buffer, wherein the transimpedance amplifier is connected to the first-stage phase compensator, the K-th stage phase compensator among the N-stage phase compensators is connected to the K-th stage broadband amplifier among the N-stage broadband amplifiers, and the N-stage broadband amplifier is connected to the test buffer, 1≤K≤N; wherein, The transimpedance amplifier is used to convert the input signal into a voltage signal and perform signal amplification processing; The K-th stage phase compensator is used to provide an input DC bias for the K-th stage broadband amplifier, and to provide phase compensation for the output signals of the transimpedance amplifier and the K-th stage broadband amplifier; The K-th stage broadband amplifier is used to amplify the output signal of the K-th stage phase compensator and provide additional voltage gain; The test buffer is used to convert the output signal of the N-th stage broadband amplifier into a driving signal and a test signal respectively.

2. The driving circuit according to claim 1, wherein: The N-stage phase compensators all adopt a passive structure of resistors and capacitors, including: a digital capacitor array, a first digital resistor array, and a second digital resistor array, wherein one end of the digital capacitor array in the first-stage phase compensator is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; one end of the digital capacitor array in the K+1-th stage phase compensator is connected to an output end of the K-th stage broadband amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; and the other ends of the first digital resistor array and the second digital resistor array in the N-th stage phase compensator are respectively connected to a second power supply and a ground line.

3. The driving circuit according to claim 2, wherein: The digital capacitor array, the first digital resistor array, and the second digital resistor array in the N-stage phase compensator are used to provide phase compensation for output signals of the transimpedance amplifier and the broadband amplifier of the same stage.

4. The driving circuit according to claim 2, wherein: The digital capacitor array, the first digital resistor array, and the second digital resistor array are respectively controlled by digital codes stored in a memory, wherein the digital codes are obtained after the drive circuit is factory debugged and stored in the memory for subsequent search and reading.

5. The driving circuit according to claim 1, wherein: The N-stage phase compensators all adopt a passive structure of resistors and capacitors, including: a capacitor, a first digital resistor array, and a second digital resistor array, wherein one end of the capacitor in the first-stage phase compensator is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; one end of the capacitor in the K+1-th stage phase compensator is connected to an output end of the K-th stage broadband amplifier, and the other end thereof is connected to the first digital resistor array and the second digital resistor array in the phase compensator at the same stage; and the other ends of the first digital resistor array and the second digital resistor array in the N-th stage phase compensator are respectively connected to a second power supply and a ground line.

6. The driving circuit according to claim 5, wherein: The first digital resistor array and the second digital resistor array in the N-stage phase compensator are used to provide phase compensation for output signals of the transimpedance amplifier and the broadband amplifier of the same stage.

7. The driving circuit according to claim 5, wherein: The first digital resistor array and the second digital resistor array are respectively controlled by digital codes stored in a memory, wherein the digital codes are obtained after the drive circuit is debugged at the factory and stored in the memory for subsequent search and reading.

8. The driving circuit according to claim 1, wherein: The N-stage phase compensators all adopt a passive structure of resistors and capacitors, including: a digital capacitor array, a first resistor, and a second resistor, wherein one end of the digital capacitor array in the first-stage phase compensator is connected to an output end of the transimpedance amplifier, and the other end thereof is connected to the first resistor and the second resistor in the phase compensator at the same level; one end of the digital capacitor array in the K+1-th stage phase compensator is connected to an output end of the K-th stage broadband amplifier, and the other end thereof is connected to the first resistor and the second resistor in the phase compensator at the same level; and the other ends of the first resistor and the second resistor in the N-th stage phase compensator are respectively connected to a second power supply and a ground line.

9. The driving circuit according to claim 8, wherein: The digital capacitor array in the N-stage phase compensator is used to provide phase compensation for output signals of the transimpedance amplifier and the broadband amplifier of the same stage.

10. The driving circuit according to claim 8, wherein: The digital capacitor array is controlled by a digital code stored in a memory, wherein the digital code is obtained after the drive circuit is debugged at the factory and stored in the memory for subsequent search and reading.

11. The driving circuit according to claim 1, wherein: The transimpedance amplifier adopts an adjustable common-gate amplification structure, including: A main amplifying branch, used for amplifying the input signal; An adjustable branch, used to reduce the input equivalent resistance in the transimpedance amplifier; A bias branch, configured to provide a current bias for the main amplifying branch; The source follower is connected in series with the main amplifying branch and is used to provide isolation and driving effects for the main amplifying branch.

12. The driving circuit according to claim 1, wherein: The transimpedance amplifier adopts a current mirror amplification structure, a current mirror amplification structure with local negative feedback, or a common-gate amplification structure.

13. The driving circuit according to claim 1, wherein: The N-stage broadband amplifiers all adopt a Cherry-Hooper structure, including: A first-stage inverting amplifier and a second-stage inverting amplifier are arranged in series, and the first-stage inverting amplifier and the second-stage inverting amplifier adopt a current multiplexing structure or a common-source amplifier structure in the form of an inverter, which is used to amplify the output voltage signal of the transimpedance amplifier and provide voltage gain and broadband characteristics.

14. The driving circuit according to claim 1, wherein: The transimpedance amplifier is powered by a first power supply, and the N-stage phase compensator and the N-stage broadband amplifier are both powered by a second power supply, wherein the voltage of the first power supply is higher than the voltage of the second power supply.

15. The driving circuit according to claim 1, wherein: The transimpedance amplifier is powered by a first power supply, and the test buffer is powered by a third power supply. The voltage of the third power supply is higher or lower than the voltage of the first power supply.

16. The driving circuit according to claim 1, wherein: A DC blocking capacitor is provided between the test buffer and the N-th stage broadband amplifier, and the DC blocking capacitor is used to isolate mutual interference between the N-th stage broadband amplifier and the test buffer.

17. An electronic device, characterized in that: include: The drive circuit according to any one of claims 1 to 16.

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