A content addressable storage device, method and related equipment

Abstract

The embodiment of the present application discloses a content-addressable storage device, method and related equipment, wherein the content-addressable storage device may include: a memory for storing data to be matched; a comparator including N comparison units, the N comparison units are respectively coupled to the memory; a scheduler for acquiring K search data and scheduling the K search data to K target comparison units among the N comparison units, the target comparison units being comparison units in an idle state; a controller for controlling the memory to read out the data to be matched and send them to the K target comparison units respectively; each of the K target comparison units is used to compare the corresponding search data with the data to be matched, and output the corresponding matching result according to the comparison result. By adopting the present application, the low power consumption and flexibility of the content-addressable storage device can be guaranteed.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a content addressable storage device, method and related equipment. Background Art

[0002] Content Addressable Memory (CAM) is a memory that is addressed by content. It is a special storage array Random Access Memory (RAM). In addition to being able to read and write like traditional RAM, it can also perform search operations. Its search mechanism is to compare an input data item with all the data items stored in the CAM, determine whether the input data item matches the data items stored in the CAM, and output the matching information corresponding to the data item. Figure 1A As shown, Figure 1A The figure is a schematic diagram showing the functional difference between a RAM and a CAM in the prior art. The RAM searches for corresponding data according to an input address, while the CAM searches for corresponding addresses according to input data.

[0003] like Figure 1B As shown, Figure 1B FIG. 4 is a schematic diagram of a typical CAM structure in the prior art. The CAM mainly consists of the following parts: a CAM array (M array), a sensitive amplifier (SA), search line drivers (SLdrivers) and an encoder. Figure 1B The CAM array includes (W×K) CAM storage units M, each of which is responsible for storing data and comparing the stored data with external search data. Among them, a row of storage units M (W in the figure as an example) constitutes a word (also called data item, data table item, table item, etc.) of the CAM, W is the "word width or bit width", the number of all words in the CAM array (K in the figure as an example) is called "depth", and the capacity of the CAM is represented by (K words×W bits). When performing a search operation, the search data (Search Key) is loaded into the search line SL through the search line driver SL drivers, and the data stored in the storage unit M is matched with the SL. The matching result is reflected on the match line (Match Line, ML) in the form of level change. The voltage change on ML is amplified by the sensitive method SA and finally output to the priority encoder (encoder). The address with the highest priority of the data item that matches the search data is encoded and output.

[0004] It can be seen that when CAM searches for content, it uses the comparison circuit in each storage unit M to compare the search data with the data stored in all storage units at the same time, so that all data items in the entire CAM array can be queried in one clock cycle at the fastest, achieving fast matching, high parallelism, and the search speed is not affected by the CAM capacity. Compared with ordinary memory, which can only read out the data in the memory one by one in address order under the control of software, CAM realizes the function of high-speed search through hardware circuits, greatly improving the search efficiency and performance of the search system, and is widely used in network communications, pattern recognition and other fields.

[0005] However, due to the characteristics of CAM using dedicated circuits for parallel comparison, it inevitably has the problems of large chip area and high power consumption, and has the disadvantages of poor portability and low flexibility, which reduces the performance and reliability of the CAM chip.

[0006] Application Contents

[0007] The embodiments of the present application provide a content addressable storage device, method and related equipment, which can realize the content addressable function while ensuring the low power consumption and flexibility of the content addressable storage device.

[0008] In a first aspect, an embodiment of the present application provides a content-addressable storage device, which may include: a memory for storing data to be matched; a comparator including N comparison units, the N comparison units being respectively coupled to the memory, N being an integer greater than 1; a scheduler for acquiring K search data, and respectively scheduling the K search data to K target comparison units among the N comparison units, the target comparison unit being a comparison unit in an idle state, K being an integer greater than or equal to 1 and less than or equal to N; a controller for controlling the memory to read out the data to be matched and send them to the K target comparison units respectively; each of the K target comparison units being used to compare the corresponding search data with the data to be matched, and output a corresponding matching result based on the comparison result.

[0009] In the embodiment of the present application, in a content addressable storage device, multiple comparison units in the comparator are used as dynamically flexible and callable comparison resources. When there is input search data that needs to be searched, the idle comparison units in the multiple comparison units are called to compare the search data with the data to be matched in the memory in sequence. Since the comparator includes N comparison units, a maximum of N search data can be searched in parallel at the same time. Different from the CAM of the prior art, each storage unit in the CAM array has a comparison circuit. Although the search data can be compared with all the storage data in the storage array at the same time, so that the comparison result can be obtained in less or even one clock cycle, due to the characteristics of each storage unit having a dedicated comparison circuit, it leads to problems such as large chip area, high power consumption, and high cost. In addition, once the CAM leaves the factory, its physical structure and related parameters are fixed, so the portability and flexibility are poor. In the embodiment of the present application, the comparison unit of the comparator in the content addressable storage device is shared, and the parallel search function of the search data can be realized according to the actual search requirements, which can multiply the processing capacity of the device, meet the low and high instantaneous network throughput scenarios, avoid the use of high-cost, high-power CAM structure, ensure performance, reduce cost and power consumption. Furthermore, since the memory in the device does not require a dedicated CAM structure, a relatively general memory structure can be used, and other functional structures in the device (scheduler, controller, etc.) can be implemented based on general description languages ​​such as hardware description language Verilog, so that it is more portable and flexible, thereby greatly ensuring the high availability, low cost and low power consumption of the content addressable storage device.

[0010] In a possible implementation, the device also includes a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items; each of the K target comparison units is also used to send the corresponding matching result to the result output register, and the matching result includes one or more of matching indication information, matching data items of the corresponding search data, and addresses of the matching data items, wherein the matching indication information is used to indicate whether there are matching data items; the result output register is used to receive and store the matching results sent by the K target comparison units respectively. The N comparison units in the embodiment of the present application are also respectively coupled to the result output register in the content addressable storage device, and when any one of the N comparison units completes the matching of the search data, the matching result can be sent to the result output register, wherein the matching result can be one or more of whether the match is successful, specific matching data, or the address of the matching data.

[0011] In a possible implementation, the data to be matched includes M data items. M is an integer greater than 1; the controller is specifically used to control the memory to read out the M data items in sequence and send them to the K target comparison units respectively in an address traversal manner; each of the K target comparison units is specifically used to compare the corresponding search data with the M data items in sequence to determine the matching data items of the corresponding search data. In an embodiment of the present application, the M data items stored in the memory are serially read out by address traversal, and are gradually sent to the corresponding target comparison units for comparison to obtain corresponding matching results.

[0012] In a possible implementation, the data to be matched includes M data items; the controller is specifically used to control the memory to read out L data items in each clock cycle through address polling, and broadcast the read L data items to the N comparison units, where L is a positive integer less than or equal to M; each of the K comparison units is used to compare the L data items received each time with the corresponding search data. In the embodiment of the present application, when there are multiple search data being searched, there are multiple comparison units performing search operations at the same time, which can be specifically that the controller controls the reading of L data items in the memory and sends them in parallel to the comparison unit currently performing the search operation, and the comparison unit currently performing the search operation compares the L data received each time with the stored search data to obtain the corresponding matching result. For example, the comparator includes 8 comparison units, and currently 4 comparison units are performing data comparison. The controller reads out 2 data items from the 64 data items to be matched in each clock cycle and sends them in parallel to the above 4 comparison units. Each comparison unit compares the 2 data items received each time with the search data stored in itself. For each comparison unit, if it obtains a matching result (compared with all or part of all 64 data items to be matched), the search operation of the comparison unit can be stopped. At this time, the controller controls the data items read from the memory to no longer be sent to the comparison unit that has completed the search operation.

[0013] In a possible implementation, the bit width of each of the N comparison units is L times the bit width of each of the M data items. In an embodiment of the present application, the bit width of each comparison unit in the comparator can be L times the bit width of each data item in the data to be matched stored in the memory. In this case, the comparison unit can compare L data items in each clock cycle. For example, if the bit width of each data item is W, and the comparison bit width of the comparison unit is L*W, then the comparison unit can complete the comparison of L*W bits / bit data in one clock cycle.

[0014] In a possible implementation, the controller is further used to control the memory to write the data to be matched in a preset manner. In the embodiment of the present application, the controller can complete the initial configuration control of the data to be matched in a preset manner under the control of an external or internal processor of the device in the initial stage, for example, enumerate the addresses of all the data to be matched, and write the data to be matched corresponding to the address into the memory accordingly, and the content of the data to be matched depends on the specific business needs.

[0015] In a possible implementation, the scheduler is also used to control the target comparison unit to be determined from the N comparison units after a preset time interval when the search data received within a preset time period exceeds a preset amount, or when there are no idle comparison units at present. In an embodiment of the present application, when the throughput in the network is high, such as when the maximum pps of the instantaneous burst is large, or when there are no idle comparison units at present, the adaptability of the content addressable storage device in the embodiment of the present application can be improved by traffic shaping, that is, controlling the comparison to be performed after a certain time, so as to reduce the demand for instantaneous comparison resources.

[0016] In a possible implementation, the controller is also used to control the memory to write new data to be matched or modify the data to be matched in the process of controlling the memory to read the data to be matched. In the embodiment of the present application, the controller can write the data to be matched into the memory by reading and writing. For example, for a system with a demand for online refreshing of the data to be matched, the data to be matched can be updated or modified by selecting a memory with two independent read / write ports; if a single-port memory is selected, the controller needs to insert some additional refresh time to complete the refresh of the data to be matched when controlling the reading of the data to be matched, which may reduce the speed of some queries. The refresh time refers to the pause of querying (reading table items / data items) when refreshing (writing table items / data items) and increasing the address sequence (while write enable is invalid), and after the writing is completed, the query is re-enabled (read enable, read address sequence increases).

[0017] In a possible implementation, the data to be matched includes M data items, wherein each data item includes content to be matched, query control information, and output results; each of the K target comparison units is specifically used to compare the corresponding search data with the content to be matched in each data item according to the query control information of the M data items, and output the output results in the matched data items as the matching results of the corresponding search data. In an embodiment of the present application, by carrying query control information and corresponding output results (for example, the output result is the address corresponding to the content to be matched) in the data items contained in the data to be matched, the query method and related parameters of the comparison unit when performing search data query are controlled to meet business needs in various scenarios.

[0018] In a second aspect, an embodiment of the present application provides a content-addressable storage method, which can be applied to a content-addressable storage device, the device comprising: a comparator and a memory, the comparator comprising N comparison units, the N comparison units being respectively coupled to the memory, and N being an integer greater than 1; the method comprising: storing data to be matched in the memory; acquiring K search data, and respectively dispatching the K search data to K target comparison units among the N comparison units, the target comparison unit being a comparison unit in an idle state, and K being an integer greater than or equal to 1 and less than or equal to N; controlling the memory to read out the data to be matched and sending them to the K target comparison units respectively; comparing the corresponding search data with the data to be matched through each of the K target comparison units, and outputting the corresponding matching result according to the comparison result.

[0019] In a possible implementation, the device also includes a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items; the method also includes: sending the matching result corresponding to each of the K target comparison units to the result output register, the matching result including one or more of matching indication information, matching data items of the corresponding search data, and addresses of the matching data items, wherein the matching indication information is used to indicate whether there are matching data items; receiving and storing the matching results respectively sent by the K target comparison units through the result output register.

[0020] In a possible implementation, the data to be matched includes M data items, where M is an integer greater than 1; controlling the memory to read out the data to be matched and sending them to the K target comparison units respectively includes: controlling the memory to read out the M data items in sequence and sending them to the K target comparison units respectively in an address traversal manner; comparing the corresponding search data with the data to be matched through each of the K target comparison units, and outputting the corresponding matching result based on the comparison result, includes: comparing the corresponding search data with the M data items in sequence through each of the K target comparison units, and determining the matching data items of the corresponding search data.

[0021] In a possible implementation, the data to be matched includes M data items, where M is an integer greater than 1; the controlling the memory to read out the data to be matched and sending them to the K target comparison units respectively includes: controlling the memory to read out L data items in each clock cycle through an address polling method, and broadcasting the read L data items to the N comparison units, where L is a positive integer less than or equal to M; comparing the corresponding search data with the data to be matched through each of the K target comparison units, including: comparing the L data items received each time with the corresponding search data through each of the K comparison units.

[0022] In a possible implementation manner, a bit width of each of the N comparing units is L times a bit width of each of the M data items.

[0023] In a possible implementation manner, the method further includes: controlling the memory to write the data to be matched in a preset manner.

[0024] In a possible implementation, the method further includes: when the search data received within a preset time period exceeds a preset amount, or there is currently no idle comparison unit, controlling to determine the target comparison unit from the N comparison units after a preset time interval.

[0025] In a possible implementation manner, the method further includes: in the process of controlling the memory to read the data to be matched, controlling the memory to write new data to be matched or modifying the data to be matched.

[0026] In a possible implementation, the data to be matched includes multiple data items, wherein each data item includes content to be matched, query control information and output results; the corresponding search data is compared with the data to be matched through each of the K target comparison units, and the corresponding matching result is output according to the comparison result, including: through each of the K target comparison units, the corresponding search data is compared with the content to be matched in each data item according to the query control information of the M data items, and the output result in the matched data item is output as the matching result of the corresponding search data.

[0027] In a third aspect, the present application provides a semiconductor chip, which may include:

[0028] The first aspect and any one implementation manner in combination with the first aspect provide a content addressable storage device.

[0029] In a fourth aspect, the present application provides a semiconductor chip, which may include:

[0030] The first aspect and any one of the implementations of the first aspect provide a content addressable storage device, a processor coupled to the content addressable storage device, and a memory outside the content addressable storage device.

[0031] In a fifth aspect, the present application provides a system-on-chip (SoC) chip, the SoC chip comprising the first aspect and the content addressable storage device provided in combination with any one of the implementations of the first aspect, a processor coupled to the content addressable storage device, and an external memory of the content addressable storage device. The chip system may be composed of a chip, or may include a chip and other discrete devices.

[0032] In a sixth aspect, the present application provides a chip system, the chip system comprising: a content addressable storage device provided in the first aspect and in combination with any one of the implementations of the first aspect, and a chip comprising a processor coupled to the content addressable storage device and an external memory of the content addressable storage device. The chip system may be composed of a chip, or may include a chip and other discrete devices.

[0033] In a seventh aspect, the present application provides an electronic device, which includes the content addressable storage device provided in the first aspect and in combination with any one of the implementations in the first aspect, an external memory of the content addressable storage device, and a processor coupled to the content addressable storage device. The external memory is used to store necessary program instructions and data, the processor is used to run a general operating system necessary for the electronic device, and is used to couple with the content addressable storage device to complete relevant processing functions in the content addressable storage device. The electronic device may also include a communication interface for the electronic device to communicate with other devices or a communication network.

[0034] In an eighth aspect, the present application provides a computer storage medium storing a computer program. When the computer program is executed by a processor, the process of the content-addressable storage method provided in the second aspect and in combination with any one of the implementation methods in the second aspect can be implemented.

[0035] In the ninth aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute the process in the content-addressable storage method provided in the above-mentioned second aspect and in combination with any one of the implementation methods in the above-mentioned second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A A schematic diagram showing the functional differences between a RAM and a CAM in the prior art;

[0037] Figure 1B A typical CAM structure schematic diagram in the prior art;

[0038] Figure 2 A processing schematic diagram of a simulated CAM based on memory address traversal provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of an extended bit width analog CAM processing based on memory address traversal provided in an embodiment of the present application;

[0040] Figure 4 It is a structural diagram of a content-addressable storage device provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of the structure of another content-addressable storage device provided in an embodiment of the present application;

[0042] Figure 6 A schematic diagram of the structure of another content-addressable device provided in an embodiment of the present application;

[0043] Figure 7 A timing diagram of comparison by a comparison unit provided in an embodiment of the present application;

[0044] Figure 8 It is a flowchart of a content-addressable storage method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0046] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0047] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0049] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0050] (1) System on Chip (SoC), SoC is also called system on chip, which means it is a product, an integrated circuit with a dedicated purpose, which contains the complete system and all the embedded software. At the same time, it is a technology that is used to realize the entire process from determining the system function to the software / hardware division and completing the design.

[0051] (2) Random Access Memory (RAM) is used to store and save data. It can be read and written at any time. RAM is usually used as a temporary storage medium for the operating system or other running programs (also known as system memory). RAM cannot retain data when the power is turned off. If data needs to be saved, it must be written to a long-term storage device (such as a hard disk).

[0052] (3) Random Access Memory RAM can be further divided into two categories: static random access memory (SRAM) and dynamic random access memory (DRAM). The two have the same basic principle, both of which store charge inside the memory. Among them, SRAM has a more complex structure, a smaller capacity per unit area, and a faster access speed; DRAM has a simpler structure, a larger capacity per unit area, and a slower access time than SRAM. At the same time, because DRAM has a simpler structure, the stored charge will gradually disappear over time, so it needs to be recharged (Refresh) regularly to maintain the data stored in the capacitor.

[0053] (4) Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), referred to as DDR, is developed based on SDRAM and still uses the SDRAM production system. Therefore, for memory manufacturers, they only need to slightly improve the equipment for manufacturing ordinary SDRAM to realize the production of DDR memory, which can effectively reduce costs. Compared with the traditional single data rate, DDR technology realizes two read / write operations in one clock cycle, that is, a read / write operation is performed on the rising edge and falling edge of the clock respectively.

[0054] (5) Read Only Memory (ROM) is a solid-state semiconductor memory that can only read previously stored data. Its characteristic is that once the data is stored, it cannot be changed or deleted. It is usually used in electronic or computer systems where data does not need to be changed frequently, and the data will not disappear when the power is turned off.

[0055] (6) Field Programmable Gate Array (FPGA) is a product that is further developed on the basis of programmable devices such as programmable array logic (PAL), general array logic (GAL), and complex programmable logic device (CPLD). It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0056] (7) Emulator (Emulator, Emu) refers to a device or program that can simulate almost 100% of all the characteristics and behaviors of a hardware or software system. Its purpose is to completely simulate the response of the simulated hardware when it receives various external information.

[0057] (8) The Round Robin Scheduling algorithm is to request scheduling / processing of ready task queues or processes in a cyclic manner.

[0058] (9) A look-up table (LUT) is essentially a RAM. Currently, FPGAs mostly use 4-input LUTs, so each LUT can be seen as a RAM with 4 address lines. When a user describes a logic circuit using a schematic or HDL language, the PLD / FPGA development software will automatically calculate all possible results of the logic circuit and write the truth table (i.e., the result) into the RAM in advance. In this way, each input of a signal for a logic operation is equivalent to inputting an address to look up the table, find the content corresponding to the address, and then output it.

[0059] (10) Packets per second (pps) is a commonly used unit of network throughput (i.e., how many packets are sent per second). Network performance is usually measured by throughput. The packet forwarding rate indicates the switch's ability to forward packets. Generally, the packet forwarding rate of a switch ranges from tens of Kpps to hundreds of Mpps. The packet forwarding rate refers to how many millions of packets (Mpps) a switch can forward per second, that is, the number of packets that the switch can forward simultaneously. The packet forwarding rate reflects the switch's switching capacity in units of packets.

[0060] (11) Throughput: Throughput refers to the amount of data (measured in bits, bytes, etc.) successfully transmitted per unit time by a network, device, port, or other facility. In other words, throughput refers to the maximum data rate that a device can receive and forward without frame loss. The size of throughput is mainly determined by the hardware of the internal and external network ports of the network device, and the efficiency of the program algorithm, especially the program algorithm. For devices that require a large amount of calculations, the inefficiency of the algorithm will greatly reduce the communication volume.

[0061] In order to facilitate the understanding of the embodiments of the present application, the following further analyzes the technical problems to be solved by the embodiments of the application and the corresponding practical application scenarios. Since the highly parallel search feature of CAM when performing content search is based on the comparison circuit in each storage unit in the CAM array, that is to say, the CAM array structure in CAM is different from the data storage array structure in ordinary memory (such as memory, RAM, etc.), that is, CAM cannot use the general Memory structure to implement the content-addressable function. The following provides two solutions that can use the general Memory structure to implement the content-addressable storage function:

[0062] Solution 1: Analog CAM based on memory address traversal:

[0063] This solution can be simply described as follows: initially, the table item data to be matched is stored in the memory. After each subsequent query is started, all table item data of the memory depth are read in an address traversal manner. During the reading process, the target matching data (i.e., the search input data in this application) and the read table item data (i.e., the data item in this application) are compared one by one. When the address traversal is completed, a simulated CAM process is completed; the next query startup needs to wait for the previous query to end, and then repeat the above complete address traversal process. Figure 2 As shown, Figure 2 A processing diagram of an analog CAM based on memory address traversal provided in an embodiment of the present application, assuming that the addresses corresponding to all table data in the memory are 0, 1, 2, 3, 4, 5, 6, 7, T 0 Represents the time when the first query is started, T 1 Represents the time when the second query is started, T 3 Represents the start time of the third query. It can be seen that the second query can only be started after the first query is completed, there is no overlap between the single query time slices, and only one query request is processed at the same time. The above solution is a serial comparison method and uses a common memory structure. The cost and power consumption are relatively low, the back-end risk is small (that is, the feasibility risk of converting the logic design into the physical circuit is small), and the flexibility is high.

[0064] The disadvantages of the above processing structure are: since a single query needs to wait for the processing delay of address traversal, it results in low throughput and low performance.

[0065] Solution 2: Extended bit width analog CAM based on memory address traversal:

[0066] This solution can be simply described as increasing the storage word width of Memroy based on the above solution 1, for example, widening it to the word width of 2 table items, and comparing 2 table items at a time, so that the memory depth can be reduced to 1 / 2 of the original, and the processing delay is reduced accordingly. The single query time is reduced to half of the original, and two table items are compared in one clock cycle. Figure 3 As shown, Figure 3 A schematic diagram of an extended bit width analog CAM processing based on memory address traversal provided in an embodiment of the present application, assuming that the addresses corresponding to all table data in the memory are 0, 1, 2, 3, 4, 5, 6, 7, T 0 Represents the time when the first query is started, T 1 Represents the time when the second query is started, T 3 Represents the start time of the third query. It can be seen that two table items can be compared in each clock cycle, and the single query time is reduced to half of the original. However, the second query can only be started after the first query is completed. There is still no overlap between the single query time slices, and only one query request is processed at the same time. That is, the above solution can also be understood as a serial comparison method, and a general memory structure can also be used, with relatively low cost and power consumption, small back-end risk, and high flexibility.

[0067] The disadvantages of the above processing structure are: it makes the word width of memory significantly wider and the depth significantly smaller, but the memory shape with actual resource optimization generally has certain constraints. The above changes may lead to the degradation of memory selection. In extreme scenarios, the high integration storage advantage of memory may be lost, which is ultimately reflected in the increase of chip area and power consumption.

[0068] However, through analyzing the application scenarios of general network systems, it is found that it is usually not necessary to meet the extreme performance requirement of initiating a query request in each system clock cycle. Typically, such as Ethernet message processing, it is generally sufficient to query by packet instead of by byte, and the packet rate is much smaller than the byte rate of the packet. Therefore, there are usually not a large number of query requests in a short period of time; however, in the short packet burst scenario, if the table entry depth is long (the number of data items to be matched is large), the pps performance of the above-mentioned solution 1 may not be able to meet the performance requirements, because the table entry depth is long, resulting in a long single query time, and there is no time overlap between the single queries, resulting in the scenario of short packet burst, and the network throughput cannot be guaranteed; the CAM in the prior art and the above-mentioned solution 2 will optimize the network throughput compared with the above-mentioned solution 1, but there are problems with resource and power consumption degradation or matching flexibility.

[0069] In summary, the existing content-based addressing scheme cannot meet the performance of the network. Therefore, the present application provides a flexible CAM with low power consumption, small area, strong portability and strong scalability to solve the above technical problems.

[0070] Based on the above, the content addressable storage device and related devices provided by the embodiment of the present application are described below. Figure 4 , Figure 4 4 is a schematic diagram of the structure of a content addressable storage device provided by an embodiment of the present application. The content addressable storage device 40 may include a scheduler 401, a comparator 402, a memory 403 and a memory 404, wherein the comparator 402 includes N comparison units 4021, and the N comparison units are respectively coupled to the memory 403, where N is an integer greater than 1; optionally, the above scheduler 401, comparator 402, memory 403 and memory 404 may be located on an integrated circuit substrate. Among them,

[0071] The memory 404 is used to store the data to be matched, which is a plurality of data items that need to be matched by the K search data obtained by the scheduler 401, that is, each search data needs to be matched with the data to be matched, so as to obtain the corresponding matching result. The data to be matched can be obtained in a variety of ways, such as static configuration, dynamic learning, etc. Before any target comparison unit 4021 starts to compare the search data, the controller 404 controls the memory 404 to write the data to be matched. Optionally, the controller 403 can also control the memory 404 to write new data to be matched or modify the data to be matched in the process of controlling the memory 404 to read the data to be matched. That is, the controller 403 can control the memory 404 to write the data to be matched into the memory 403 in a read-while-write manner. For example, for a system that needs to refresh the data to be matched online, a memory with two independent read / write ports can be selected to perform read-while-update or read-while-modify of the data to be matched; if a single-port memory is selected, the controller 403 can insert some additional refresh time to complete the refresh of the data to be matched when controlling the memory 404 to read out the data to be matched. At this time, the query speed may be partially reduced, and the refresh time refers to the pause of query (reading table entries / data items) and the increase of address sequence (while write enable is invalid) when refreshing (writing table entries / data items), and re-enabling query (reading enable, increasing read address sequence) after writing is completed.

[0072] In one possible implementation, the storage structure of memory 404 may be in the form of a storage array, which is composed of many basic storage units, each of which stores a binary digit (1 or 0), called a bit, and a row of storage units constitutes a word (also called a data item, data table item, table item, etc.) of memory 403, W is the "word width or bit width", the number K of all words in the memory array is called the "depth", and the capacity of memory 403 is represented by (K words × W bits). Different from the CAM in the prior art, the memory 403 itself does not have a data comparison function, that is, it does not include a comparison circuit, so a general memory structure can be adopted. For example, the memory 403 can be a general random access memory (Random Access Memory, RAM) or a power-off volatile storage device, such as a static random access memory (Static Random Access Memory, SRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a synchronous dynamic random access memory (Synchronous DRAM, SDRAM), a double data rate SDRAM (Dual Data Rate SDRAM, DDR SDRAM), etc.; the memory 403 can also be a general read-only memory (Read Only Memory, ROM) or a non-power-off volatile memory, such as a programmable ROM (Programmable ROM, PROM), an erasable programmable ROM (Erasable Programmable ROM, EPROM), an electrically erasable programmable ROM (Electrically Erasable Programmable ROM, EEPROM), a fast erasable ROM (FLASH ROM), etc.; the memory 403 may also be a general register on the processor, a flash memory, or any other suitable type of memory. It is understandable that if the memory 403 is a RAM, the data to be matched can be changed, and if the memory 403 is a ROM, the data to be matched is the data solidified in the memory 403. It should be noted that the present application does not specifically limit the specific form in which the memory 404 stores the data to be matched, and relevant changes can be made according to actual needs or business conditions.

[0073] The scheduler 401 is used to obtain K search data and schedule the K search data to K target comparison units among the N comparison units respectively. The target comparison unit is a comparison unit in an idle state, and K is an integer greater than or equal to 1 and less than or equal to N. For example, when the scheduler 401 receives a query request, and the query request includes search data, search type, etc., it indicates that the content addressable storage device 40 needs to perform a search operation on the search data. At this time, the scheduler 401 needs to allocate corresponding comparison units to the search data to search for matching results. When there are multiple query requests, the scheduler 401 needs to allocate different target comparison units to different query requests respectively; the scheduler 401 dynamically selects idle and available target comparison units (which can be Figure 4 Any comparison unit 4021 in the scheduler 401), start or enable the query function of the target comparison unit, and send the search data to the target comparison unit 4021, so as to complete the allocation and scheduling of the query request to the query resource. Among them, the K search data obtained by the scheduler 401 can be obtained at the same time or at different times, that is, the K search data can be scheduled to the K target comparison units at the same time, or they can be scheduled to the K target comparison units in sequence, which can depend on the order in which the K search data reach the scheduler, or it can depend on the preset or flexible scheduling rules of the scheduler 401, which is not specifically limited in the embodiments of the present application. For example, the scheduler 401 can schedule a certain search data to a certain target comparison unit immediately after receiving it, or the scheduler 401 can schedule it to the corresponding target comparison unit uniformly after receiving a certain number of search data. It should be noted that the scheduler 401 may receive a large number of query requests at a certain moment or time period, that is, receive a large amount of search data. At this time, since the number of comparison units in the comparator 402 is limited, the scheduler 401 can be based on a certain traffic shaping control, that is, currently only K of the search data are obtained for query, and other search data will be scheduled after there are idle comparison units in the future, so as to avoid congestion or discard of search data as much as possible.

[0074] The controller 403 is used to control the memory 404 to read out the data to be matched and send them to the K target comparison units respectively. When a comparison unit in the comparator 402 is selected as a target comparison unit, that is, one or more comparison units need to perform a search operation, the comparator 402 can notify the controller 403 of the state information (idle state or use state) of the target comparison unit to complete the read-write enable merging control of the comparator 402 to the controller 403, and finally control the output of the memory 404. In other words, when at least one comparison unit in the comparator 402 is selected as a target comparison unit, then the controller 403 needs to control the memory 404 to continue to read out the data items to be matched, because it is necessary to control the port of the memory 404 to remain in a readable state, thereby realizing the read operation. Optionally, the scheduler 401 can also notify the controller 403 of the state information of the target comparison unit to complete the read-write enable merging control of the comparator 402 to the controller 403, and the embodiment of the present application does not specifically limit this. Figure 4 The structure in is based on the example of the controller 403 being notified by the comparator 402. It can be understood that if the controller 403 is notified by the scheduler 401, there needs to be a communication connection between the scheduler 401 and the controller 403, which will not be repeated here. The memory 403, under the control of the controller 403, sends the read data to be matched to the K target comparison units respectively, which can be broadcast to N comparison units (including the K target comparison units), or optionally, it can also be sent only to the K target comparison units. For example, when the controller 403 learns through the scheduler 401 or the comparator 402 that there are currently comparison units 4021-2 and comparison units 4021-4 as target comparison units, and performs a comparison operation of the search data, the controller 403 controls the memory 404 to broadcast the read data to be matched to the N comparison units, or only send it to the comparison units 4021-2 and the comparison units 4021-4. It should be noted that if the memory 404 sends the read data to be matched only to the K target comparison units, then the memory 404 needs to know which comparison units are currently the target comparison units. At this time, the output of the memory 404 can be controlled by the status information of each comparison unit obtained by the controller 403 (notified by the scheduler 401 or the comparator 402).

[0075] Furthermore, before the search operation begins, the controller 403 is also used to control the memory 404 to write the data to be matched in a preset manner. The controller 403 can complete the initial configuration control of the data to be matched in a preset manner under the control of the external or internal processor of the device in the initial stage. For example, after the content addressable storage device 40 is powered on, before entering the data search operation, the controller 403, under the control of the external processor, first completes the initialization process of the memory 404, such as including defining the matching word width and the output result bit width, selecting the read / write mode of the data table item (data to be matched), enumerating the addresses of all the data to be matched, and writing the data to be matched corresponding to the address into the memory 404, etc., and the content of the data to be matched depends on the specific business needs.

[0076] The comparator 402 includes N comparison units 4021 for searching data, namely Figure 4 Since the N comparison units in the comparator 402 are respectively coupled to the memory 404, such as Figure 4 As shown in , each comparison unit 4021 is physically connected to the memory 404, that is, the N comparison units 4021 are in a parallel comparison structure, and the search process does not interfere with each other. The start time of the search and the search data to be searched can be unrelated. When an idle comparison unit 4021 is selected as a target comparison unit, the target comparison unit compares the search data sent by the scheduler 401 with the data to be matched sent by the memory 404, and determines the matching result of the search data according to the comparison result. Among them, the matching result includes one or more of the matching indication information, the matching data item of the corresponding search data, and the address of the matching data item, wherein the matching indication information is used to indicate whether there is a matching data item. For example, in actual applications, it may not be necessary to completely traverse all data items, such as only taking the result of the first match or only judging whether there is a matching item. At this time, it is not necessary to completely traverse all data items to speed up the response speed or reduce the flip power consumption; the corresponding matching result can maintain a fixed delay, or be output immediately, which can be determined according to the requirements of other components of the system. That is, in some cases, it is only necessary to find whether there is a hit match, and in some cases, it is necessary to find a specific match or the address corresponding to the match. It can be understood that each comparison unit 4021 includes not only logic resources such as comparison circuits, but also maintenance control of necessary information such as its own comparison status, and a register for storing search data sent by the scheduler 401.

[0077] In a possible implementation, when the search data received by the scheduler 401 within a preset time period exceeds a preset amount, or there is no idle comparison unit at present, the scheduler 401 further controls to determine an idle target comparison unit from the N comparison units after a preset time interval. That is, when the throughput in the network is high, such as when the instantaneous burst maximum pps is large, or there is no idle comparison unit at present, the traffic shaping processing method can be used, that is, the comparison is controlled to be performed after a certain time, to improve the adaptability of the content addressable storage device in the embodiment of the present application to reduce the demand for instantaneous comparison resources.

[0078] In the embodiment of the present application, in a content addressable storage device, multiple comparison units in the comparator are used as dynamically flexible and callable comparison resources. When there is input search data that needs to be searched, the idle comparison units in the multiple comparison units are called to compare the search data with the data to be matched in the memory in sequence. Since the comparator includes N comparison units, a maximum of N search data can be searched in parallel at the same time. Different from the CAM of the prior art, each storage unit in the CAM array has a comparison circuit. Although the search data can be compared with all the storage data in the storage array at the same time, so that the comparison result can be obtained in less or even one clock cycle, due to the characteristics of each storage unit having a dedicated comparison circuit, it leads to problems such as large chip area, high power consumption, and high cost. In addition, once the CAM leaves the factory, its physical structure and related parameters are fixed, so the portability and flexibility are poor. In the embodiment of the present application, the comparison unit of the comparator in the content addressable storage device is shared, and the parallel search function of the search data can be realized according to the actual search requirements, which can multiply the processing capacity of the device, meet the low and high instantaneous network throughput scenarios, avoid the use of high-cost, high-power CAM structure, ensure performance, reduce cost and power consumption. Furthermore, since the memory in the device does not require a dedicated CAM structure, a relatively general memory structure can be used, and other functional structures in the device (scheduler, controller, etc.) can be implemented based on general description languages ​​such as hardware description language Verilog, so that it is more portable and flexible, thereby greatly ensuring the high availability, low cost and low power consumption of the content addressable storage device.

[0079] Above Figure 4In the process, the scheduler 401 selects an idle target comparison unit from N comparison units 4021, or before the controller 403 determines to which comparison unit the currently read data to be matched is sent, each comparison unit 4021 in the comparator 402 can directly send its own status information (idle or in use status) to the scheduler 401 and / or the controller 403, or each comparison unit 4021 can send the status information uniformly to a status merging module in the comparator 402 for aggregation, and then the status merging module sends all the aggregated status information to the scheduler 401 and / or the controller 403. The embodiments of the present application do not make specific limitations on this.

[0080] like Figure 5 As shown, Figure 5 A schematic diagram of the structure of another content-addressable storage device provided in an embodiment of the present application, wherein a scheduler 401 and N comparison units 4021 are connected in parallel via N physical lines 001, and the idle state or use state of the N comparison units 4021 can be reflected on the physical line 001 in the form of level changes, and the scheduler 401 can sense the current idle or use state of each comparison unit 4021 based on the voltage change on the physical line 001. For example, when the comparison unit 4021 is in an idle state, the scheduler 401 keeps the physical line 001 between it and the comparison unit at a low level, and when the comparison unit 4021 is in use, the scheduler 401 pulls up the physical line 001 between it and the comparison unit to a high level. When an idle comparison unit 4021 is selected as a target comparison unit, the target comparison unit (such as Figure 5 The target comparison units 4021-2, 4021-4 and 4021-5 in the scheduler 401 can receive the corresponding physical connection ( Figure 5 001a, 001b, 001c) in the search data (search data a, search data b, search data c) sent, and store the corresponding search data.

[0081] Furthermore, each comparison unit 4021 in the comparator 402 can feed back its current state information (idle state or use state) to the controller 403 through the physical connection 002. The controller 403 obtains and counts the comparison units that are currently performing the search operation through the physical connection 002, and controls the data to be matched in the memory 404 to be gradually sent in parallel to the corresponding target comparison units through the physical connection 003.

[0082] Assume that there are three search data: search data a, search data b and search data c, and the comparison units selected by the scheduler 401 are the target comparison unit 4021-2, the target comparison unit 4021-4 and the target comparison unit 4021-5 respectively, and after the search operation functions of 4021-2, 4021-4 and 4021-5 are turned on, the comparator 402 notifies the controller 403 (which may also be notified by the scheduler 401) of the enabled state of the target comparison unit. After the controller 403 learns the state information of the comparison unit, it merges the states of N comparison units, that is, 4021-2, 4021-4 and 4021-5 are all enabled, and the other comparison units are disabled. The controller 403 combines the states of the above-mentioned comparison units and the initialization control of the memory 404, and sends the merged control information to the memory 404, thereby controlling the step-by-step reading of the data items and sending them in parallel to the target comparison units 4021-2, 4021-4 and 4021-5 in the enabled state. For example, according to the address polling method, one data item (or multiple data items, depending on the bit width relationship between the comparison unit 4021 and the memory 404) is sent to the target comparison units 4021-2, 4021-4 and 4021-5 in parallel in each clock cycle. Finally, the target comparison units 4021-2, 4021-4 and 4021-5 read the stored search data from the memory 404 step by step under the control of the controller 403 and transmit them to the target comparison units 4021-2, 4021-4 and 4021-5 through the corresponding physical connections ( Figure 5 The data items sent by 003a, 003b, and 003c in the search data are gradually compared until the final matching result of the search data is obtained. It can be understood that the time when each comparison unit 4021 starts searching can be at the same time or at different times, that is, the search data between different comparison units 4021 do not affect each other and do not interfere with each other.

[0083] In a possible implementation, the data to be matched includes M data items; the controller 403 is specifically used to control the memory to read out the M data items in sequence and send them to the K target comparison units respectively according to the address traversal method, which may be sent only to the K target comparison units (such as Figure 5 The comparison units 4021-2, 4021-4, 4021-5 in FIG. 4021-1 can also be broadcast to N comparison units (such as Figure 5The comparison units 4021-1, 4021-2, ... 4021-N in the K target comparison units); each of the K target comparison units is specifically used to compare the corresponding search data with the M data items in sequence to determine the matching data items of the corresponding search data. In the embodiment of the present application, the M data items stored in the memory are serially read out by address traversal, and are gradually sent to the corresponding target comparison units for comparison to obtain corresponding matching results. Optionally, they can be read out one by one, that is, one data item is read out, or two by two, that is, two data items are read out, or multiple data items are read out.

[0084] like Figure 6 As shown, Figure 6 A schematic diagram of the structure of another content addressable device provided in an embodiment of the present application, Figure 6 The content addressable device 40 also includes a result output register 405, and N comparison units 4021 are respectively coupled to the result output register 405; the target comparison unit also sends the matching result to the result output register 405, and the result output register 405 receives and stores the matching result. Since the N comparison units 4021 are also respectively coupled to the result output register 405 in the content addressable storage device 40 through the physical connection 004, when any one of the N comparison units 4021 completes the matching of the search data, the matching result can be sent to the result output register 405 in parallel through the corresponding physical connection 004. Optionally, the data read out by the memory 404 in an address polling manner under the control of the controller 403 can realize that the read data can participate in the independent query of multiple comparison units at the same time. In one possible implementation, Figure 6 The comparator 402 of the content addressable device 40 also includes a state merging module 4022, and each comparison unit 4021 sends the state information to the state merging module 4022 in the comparator 402 for aggregation, and then the state merging module 4022 sends all the aggregated state information to the controller 403. Optionally, the number of comparison units N is greater than or equal to (instantaneous burst maximum pps)*(static table lookup cycle), where the instantaneous burst maximum pps can be determined by the minimum cycle of the actual query request, and the static table lookup cycle refers to the time to traverse the query table address (the address of the data to be matched). In actual applications, it can be combined with the existing traffic shaping module of the system to reduce the peak pps.

[0085] For example, Figure 7 As shown, Figure 7 The timing diagram of the comparison unit comparison provided in the embodiment of the present application is shown in FIG. Figure 7In the example, the time sequence is T0, T1, T2, T3, T4, and T5, which correspond to the first query, the second query, the third query, the fourth query, the fifth query, and the sixth query, respectively. The first query and the fourth query (T0 and T3) are executed by the comparison unit 402-2, the second query and the fifth query (T1 and T4) are executed by the comparison unit 402-4, and the third query and the sixth query (T2 and T5) are executed by the comparison unit 402-5. That is, each comparison unit can perform search data queries in parallel, and each comparison unit returns to an idle state after a single query is completed, and can perform the next round of search data queries. For example, the comparison unit 402-2 starts to search for data a at time T0, and after completing the search for data a, it can start a new search for data d. While the comparison unit 402-2 is performing the comparison of the search for data a, the comparison unit 402-4 starts to search for data b, and then starts to search for data e. It should be noted that all the data to be matched in the memory 404 are read out in the form of address polling, which is Figure 7 The address of the data to be matched in the memory 404 is read out in a loop in the manner of address polling. As long as there is a comparison unit currently querying the corresponding search data, the controller 403 will control the data in the memory 404 to keep reading out in a loop, and each comparison unit does not start comparison from the data item with the lowest or highest address when starting comparison. For example, comparison starts from address 6 at time T1 and from address 2 at time T3, that is, the data items that all target comparison units start to compare depend on the data currently read out from the memory 404. Figure 7 In the time period corresponding to the middle address 5 (hold), since no comparison unit is currently executing the query task, if the data to be matched is output at this time, resources will be wasted, and if the comparison unit indicates the controller 403 through the high and low levels, then the N comparison units are all in the low level state at this time, and the controller 403 will control the reading and matching of the paused data. When the search data is sent to the comparison unit 402-5 again at time T5, the controller 403 continues to read out from the paused data item and sends it to the comparison unit 402-5 for comparison.

[0086] In a possible implementation, among the N comparison units, K comparison units are currently performing comparison of search data, and different comparison units correspond to different search data, wherein K is a positive integer less than or equal to M; the data to be matched includes M data items; the controller 403 is specifically used to control the memory 404 to read out L data items in each clock cycle through address polling, and broadcast the read L data items to the N comparison units, wherein L is a positive integer less than or equal to M; each comparison unit among the K comparison units is used to compare the L data items received each time with the corresponding search data. That is, when there are multiple search data being searched, there are correspondingly multiple comparison units performing search operations at the same time, which can be specifically that the controller 403 controls the memory 404 to read out L data items in each clock cycle and broadcast them to the N comparison units, and optionally, it can also be sent in parallel only to the target comparison unit currently performing the search operation, and each target comparison unit performing the search operation compares the L data received each time with the search data stored in itself, so as to obtain the corresponding matching result. For example, assuming that M=64, N=8, L=2, and K=4, the comparator 402 includes 8 comparison units, and currently 4 target comparison units are performing data comparison. The controller 403 reads out 2 data items from the 64 data items to be matched in each clock cycle and sends them in parallel to the above 4 target comparison units (or broadcasts them to the above 8 comparison units). Each target comparison unit compares the 2 data items received each time with the search data stored in itself. For each target comparison unit, after obtaining the matching result (compared with all or part of all 64 data items to be matched), the search operation of the comparison unit can be stopped. At this time, the controller 403 can control the data items read out from the memory to no longer be sent to the comparison unit that has completed the search operation task.

[0087] In one possible implementation, the bit width of each of the N comparison units is L times the bit width of each of the M data items. That is, the bit width of each comparison unit in the comparator 402 can be L times the bit width of each data item in the data to be matched stored in the memory 404. At this time, the comparison unit can compare L data items in each clock cycle. For example, if the bit width of each data item is W, and the comparison bit width of the comparison unit is L*W, then the comparison unit can complete the comparison of L*W bits / bit data in one clock cycle. The embodiment of the present application can further balance performance and cost by expanding the word width within the range permitted by the selection and reasonable evaluation of the back-end impact, and speed up the query speed by performing multiple comparisons simultaneously in one clock cycle within a relatively low cost and power consumption impact range.

[0088] In one possible implementation, when multiple matching results appear, a priority encoder may be added to the content addressable device 40, located between the comparison unit 4021 and the result output register 40, and the priority encoder encodes and outputs the matching result with the highest priority (for example, the data item at the lowest address position).

[0089] In a possible implementation, a matching address history register may be added to the content addressable device 40. When a match occurs for the first time, the address where the match occurs is recorded. When a match occurs again, the relative size of the recorded address and the new matching address is compared to determine whether to update the matching result and the matching address history register. For example, when the low address priority strategy is used, the old large matching address and result may always be updated with the new small matching address and result.

[0090] In a possible implementation, the data to be matched includes M data items, wherein each data item includes content to be matched, query control information and output results; each of the K target comparison units is specifically used to compare the corresponding search data with the content to be matched in each data item according to the query control information of the M data items, and output the output results in the matched data items as the matching results of the corresponding search data. That is, in the above search, the query control information and the corresponding output results (for example, the output result is the address corresponding to the content to be matched) can be carried in the data items contained in the data to be matched, wherein the query control information can include: the min max range or bit mask used in the specific comparison or combined with other logical operations, which can be determined according to system requirements. For example, the data items stored in the memory can be defined as a three-dimensional data set of {content to be matched, query control information, output result}, such as a multi-dimensional data group of one or more data items = {min, max, mask, item_en, result}, to indicate that when the search data to be queried satisfies min=<(d0&mask)<=max and item__en is equal to 1, then the data item is the matching data item of the search data, and the result can be output at this time, that is, the matching result in this application.

[0091] It should be noted that the above Figure 4-Figure 6The scheduler 401 of the content addressable storage device 40 in the content addressable storage device 40 can be a hardware circuit module or a functional device running software. Similarly, the controller 403 can also be a hardware circuit module or a functional device running software. It can be understood that, under normal circumstances, the use of hardware circuit modules is faster than the use of software to implement the corresponding functions. The above-mentioned scheduler 401 can be deployed inside the controller 403, that is, it is considered to be a part of the controller 403 or integrated with the controller 403 in physical form; alternatively, the scheduler 401 can also be deployed outside the controller 403, of course, it can also be partially deployed inside the controller 403 and the other part can be deployed outside the controller 403, and the embodiment of the present application does not make specific limitations on this.

[0092] It should be noted that the content addressable storage device in this application can have three operating modes: read mode, write mode and matching mode. In read and write modes, the way of accessing and operating data in the memory is the same as in ordinary memory. Matching mode can achieve the above Figure 4-Figure 6 The content-based search function implemented by the content-addressable storage device in the content-addressable storage device.

[0093] The data search function of the content addressable storage device in the present application can be used in various application scenarios such as virtual memory, data compression, pattern recognition, image processing, cache, table lookup application, etc. For example, when performing a media access control (MAC) address search, the switch (the switch may include any of the content addressable storage devices described in the present application) first uses the MAC address as a keyword (search data) to retrieve the corresponding index value through the MAC-CAM table (that is, the data to be matched in the present application), wherein, on the Ethernet, the MAC-CAM table maintains an address table for layer 2 switching for the switch (usually referred to as a "CAM table"), which maintains the correspondence between the MAC address and the outbound interface. In this way, whenever the switch receives an Ethernet data frame, the switch will make a judgment. The destination MAC address of the data frame is extracted. If the data frame is not sent to itself, the CAM table is queried according to the destination MAC address of the data frame; if it can be hit (the so-called hit is to find the forwarding item corresponding to the MAC address in the CAM table), it is forwarded according to the query result (usually an outbound interface list); if it cannot be hit, the data frame is broadcast to all ports. The CAM table of the switch can be obtained in many ways, such as static configuration and dynamic learning.

[0094] The content addressable storage device in the present application can use only one set of table storage resources (data to be matched) when only general CAM operations need to be simulated. By adding a small amount of control logic, the throughput (pps) performance can be linearly doubled, and there is no need to significantly change the shape of the memory (relative to the original table lookup matching requirements). While ensuring throughput and feasibility, it does not lose the cost and power consumption advantages. If a more flexible dynamic table lookup requirement is required, some operation information about the table items can be conveniently stored in the memory at the same time, which can more conveniently support the implementation of additional features such as table item enable, bit mask, value range mask, and out-of-order table item priority, greatly improving the flexibility of the table lookup matching process itself. At the same time, combined with specific scenarios, it can also be combined with word width expansion to further balance performance and area power consumption and further improve energy efficiency. In general, the content addressable storage device provided by the present application includes at least the following advantages:

[0095] 1. Low cost and power consumption, matching application scenarios for relatively low pps peak scenarios, avoiding the use of high-cost and high-power CAM structures, reducing costs (area) and power consumption (including average and peak); at the same time, since the circuit is simpler, it can also reduce the risk of back-end engineering processes;

[0096] 2. Strong portability. Since the general memory (such as Memory) structure can be used, the logic scheme is highly portable. Emu, FPGA and other scenarios can be directly integrated and implemented, and the occupation of logic resources such as LUT is low, which greatly reduces the cost of suppression or verification;

[0097] 3. Strong scalability. TCAM and other complex fuzzy CAM processing methods can be easily implemented through a small amount of control and modification of table entry content. For example, table entry enablement, fuzzy methods with min and max, etc. can all be planned into the Memory table entry content for dynamic matching processing; it is easier to achieve fixed processing delay and form a pipeline structure in the overall system processing; it is easier to combine with the extended word width dimension to further improve the cost-performance balance; it is easier to expand and implement online dynamic table entry update operations to meet business scenarios with high online requirements; in some applications, other non-coexisting scene storage (such as Memory) resources can also be reused to further reduce costs.

[0098] See also Figure 8 , Figure 8 is a flow chart of a content addressable storage method provided in an embodiment of the present application, the content addressable storage method is applicable to the above Figure 4-Figure 7Any one of the content addressable storage devices and the equipment comprising the content addressable storage device, the content addressable storage device comprises: a comparator and a memory, the comparator comprises N comparison units, the N comparison units are respectively coupled to the memory, and N is an integer greater than 1; the method may include the following steps S801-S804.

[0099] S801: Storing data to be matched in the memory.

[0100] S802: Acquire K search data, and dispatch the K search data to K target comparison units among the N comparison units respectively, where the target comparison unit is an idle comparison unit, and K is an integer greater than or equal to 1 and less than or equal to N.

[0101] S803: Read the data to be matched from the memory and send it to the target comparison unit.

[0102] S804: Compare the corresponding search data with the data to be matched through each of the K target comparison units, and output a corresponding matching result according to the comparison result.

[0103] In a possible implementation, the device also includes a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items; the method also includes: sending the matching result corresponding to each of the K target comparison units to the result output register, the matching result including one or more of matching indication information, matching data items of the corresponding search data, and addresses of the matching data items, wherein the matching indication information is used to indicate whether there are matching data items; receiving and storing the matching results respectively sent by the K target comparison units through the result output register.

[0104] In a possible implementation, the data to be matched includes M data items, where M is an integer greater than 1; and controlling the memory to read out the data to be matched and sending them to the K target comparison units respectively includes:

[0105] According to the address traversal method, the memory is controlled to read out the M data items in sequence and send them to the K target comparison units respectively; each of the K target comparison units compares the corresponding search data with the data to be matched, and outputs the corresponding matching result according to the comparison result, including: each of the K target comparison units compares the corresponding search data with the M data items in sequence to determine the matching data item of the corresponding search data.

[0106] In a possible implementation, the data to be matched includes M data items, where M is an integer greater than 1; and controlling the memory to read out the data to be matched and sending them to the K target comparison units respectively includes:

[0107] Through address polling, the memory is controlled to read out L data items in each clock cycle, and the read L data items are broadcast to the N comparison units, where L is a positive integer less than or equal to M; through each of the K target comparison units, the corresponding search data is compared with the data to be matched, including: through each of the K comparison units, the L data items received each time are compared with the corresponding search data.

[0108] In a possible implementation manner, a bit width of each of the N comparing units is L times a bit width of each of the M data items.

[0109] In a possible implementation manner, the method further includes: controlling the memory to write the data to be matched in a preset manner.

[0110] In a possible implementation, the method further includes: when the search data received within a preset time period exceeds a preset amount, or there is currently no idle comparison unit, controlling to determine the target comparison unit from the N comparison units after a preset time interval.

[0111] In a possible implementation manner, the method further includes: in the process of controlling the memory to read the data to be matched, controlling the memory to write new data to be matched or modifying the data to be matched.

[0112] In a possible implementation, the data to be matched includes multiple data items, wherein each data item includes content to be matched, query control information and output results; the corresponding search data is compared with the data to be matched through each of the K target comparison units, and the corresponding matching result is output according to the comparison result, including: through each of the K target comparison units, the corresponding search data is compared with the content to be matched in each data item according to the query control information of the M data items, and the output result in the matched data item is output as the matching result of the corresponding search data.

[0113] It should be noted that the specific process of the content addressable storage method described in the embodiment of the present application can be found in the above Figure 4-Figure 7The relevant descriptions in the application embodiments described in will not be repeated here.

[0114] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium may store a program, and when the program is executed, the program includes part or all of the steps of any one of the steps recorded in the above method embodiments.

[0115] The present application also provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can perform some or all steps of any content addressable storage method. In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0116] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, some steps may be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0117] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0118] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0120] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

Claims

1. A content addressable storage device, It is characterized in that include: A memory, used for storing data to be matched; A comparator, comprising N comparison units, wherein the N comparison units are respectively coupled to the memory, and N is an integer greater than 1; wherein the N comparison units are in a parallel comparison structure, and each of the comparison units is physically connected to the memory; A scheduler, used to obtain K search data, and schedule the K search data to K target comparison units among the N comparison units for parallel comparison, wherein the target comparison unit is a comparison unit in an idle state, and K is an integer greater than or equal to 1 and less than or equal to N; A controller, used for controlling the memory to read out the data to be matched and send the data to the K target comparison units respectively; Each of the K target comparison units is used to compare the corresponding search data with the data to be matched, and output a corresponding matching result according to the comparison result.

2. The device according to claim 1, It is characterized in that The device further comprises a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched comprises a plurality of data items; Each of the K target comparison units is further used to send a corresponding matching result to the result output register, wherein the matching result includes one or more of matching indication information, a matching data item of the corresponding search data, and an address of the matching data item, wherein the matching indication information is used to indicate whether there is a matching data item; The result output register is used to receive and store the matching results respectively sent by the K target comparison units.

3. The device according to claim 1 or 2, It is characterized in that The data to be matched includes M data items, where M is an integer greater than 1; The controller is specifically used to control the memory to read out the M data items in sequence and send them to the K target comparison units respectively according to the address traversal method; Each of the K target comparison units is specifically configured to compare the corresponding search data with the M data items in sequence to determine a matching data item of the corresponding search data.

4. The device according to claim 1 or 2, It is characterized in that The data to be matched includes M data items; The controller is specifically used to control the memory to read out L data items in each clock cycle through an address polling method, and broadcast the read L data items to the N comparison units, where L is a positive integer less than or equal to M; Each of the K comparing units is used to compare the L data items received each time with the corresponding search data.

5. The device as claimed in claim 4, It is characterized in that The bit width of each of the N comparing units is L times the bit width of each of the M data items.

6. The device according to any one of claims 1 to 2, It is characterized in that The controller is further used to control the memory to write the data to be matched in a preset manner.

7. The device according to any one of claims 1 to 2, It is characterized in that The scheduler is further configured to control, when the search data received within a preset time period exceeds a preset amount, or when there is no idle comparison unit at present, to determine a target comparison unit from the N comparison units after a preset time interval.

8. The device according to any one of claims 1 to 2, It is characterized in that The controller is further used to control the memory to write new data to be matched or modify the data to be matched during the process of controlling the memory to read the data to be matched.

9. The device according to claim 1, It is characterized in that The data to be matched includes M data items, wherein each data item includes content to be matched, query control information and output results; Each of the K target comparison units is specifically used to compare the corresponding search data with the content to be matched in each data item according to the query control information of the M data items, and output the output result in the matching data item as the matching result of the corresponding search data.

10. A content-addressable storage method, It is characterized in that Applied to a content addressable storage device, the device comprises: a comparator and a memory, the comparator comprises N comparison units, the N comparison units are respectively coupled to the memory, N is an integer greater than 1; wherein the N comparison units are in a parallel comparison structure, and each comparison unit is physically connected to the memory; the method comprises: storing the data to be matched in the memory; Acquire K search data, and dispatch the K search data to K target comparison units among the N comparison units for parallel comparison, respectively, where the target comparison unit is an idle comparison unit, and K is an integer greater than or equal to 1 and less than or equal to N; Controlling the memory to read out the data to be matched and sending them to the K target comparison units respectively; Through each of the K target comparison units, the corresponding search data is compared with the data to be matched, and a corresponding matching result is output according to the comparison result.

11. The method according to claim 10, It is characterized in that The device further includes a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items; and the method further includes: Sending a matching result corresponding to each of the K target comparison units to the result output register, the matching result comprising one or more of matching indication information, a matching data item of the corresponding search data, and an address of the matching data item, wherein the matching indication information is used to indicate whether there is a matching data item; The matching results respectively sent by the K target comparison units are received and stored through the result output register.

12. The method according to claim 10 or 11, It is characterized in that The data to be matched includes M data items, where M is an integer greater than 1; and the controlling the memory to read out the data to be matched and send them to the K target comparison units respectively, including: According to the address traversal method, the memory is controlled to read out the M data items in sequence and send them to the K target comparison units respectively; The step of comparing the corresponding search data with the data to be matched by each of the K target comparison units, and outputting a corresponding matching result according to the comparison result, includes: Each of the K target comparison units compares the corresponding search data with the M data items in sequence to determine matching data items of the corresponding search data.

13. The method according to claim 10 or 11, It is characterized in that The data to be matched includes M data items, where M is an integer greater than 1; and the controlling the memory to read out the data to be matched and send them to the K target comparison units respectively, including: By address polling, the memory is controlled to read out L data items in each clock cycle, and the read L data items are broadcast to the N comparison units, where L is a positive integer less than or equal to M; By each of the K target comparison units, the corresponding search data is compared with the data to be matched, including: Each of the K comparing units compares the L data items received each time with the corresponding search data.

14. The method according to claim 13, It is characterized in that The bit width of each of the N comparing units is L times the bit width of each of the M data items.

15. The method according to any one of claims 10 to 11, It is characterized in that The method further comprises: The memory is controlled to write the data to be matched in a preset manner.

16. The method according to any one of claims 10 to 11, It is characterized in that The method further comprises: When the search data received within the preset time period exceeds the preset amount, or there is no idle comparison unit at present, the control determines the target comparison unit from the N comparison units after the preset time interval.

17. The method according to any one of claims 10 to 11, It is characterized in that The method further comprises: In the process of controlling the memory to read the data to be matched, the memory is controlled to write new data to be matched or to modify the data to be matched.

18. The method of claim 10, It is characterized in that The data to be matched includes M data items, where M is an integer greater than 1; wherein each data item includes content to be matched, query control information, and output results; The step of comparing the corresponding search data with the data to be matched by each of the K target comparison units, and outputting a corresponding matching result according to the comparison result, includes: Through each of the K target comparison units, the corresponding search data is compared with the content to be matched in each data item according to the query control information of the M data items, and the output result in the matching data item is output as the matching result of the corresponding search data.

19. A semiconductor chip, It is characterized in that include: A content addressable storage device as claimed in any one of claims 1 to 9, a processor coupled to the content addressable storage device, and a memory external to the content addressable storage device.

20. An electronic device, It is characterized in that include: A content addressable storage device as claimed in any one of claims 1 to 9, and a discrete device coupled to the content addressable storage device.

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