Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device that does not reduce reliability and can achieve high-speed writing sequences. The semiconductor memory device according to the embodiment includes a storage transistor and a word line connected to the gate electrode of the storage transistor. When the writing sequence is interrupted after the k-th verification operation of the n-th writing cycle of the writing sequence and before the (k + 1)-th verification operation is completed, a verification voltage corresponding to the first verification operation or a voltage greater than it is supplied to the word line after the writing sequence is restarted and before the (k + 1)-th verification operation is started. The time from restarting the writing sequence to starting the (k + 1)-th verification operation is shorter than the time from the start of the first verification operation of the n-th writing cycle to the end of the k-th verification operation.

Description

[0001] [Related Application]

[0002] This application claims priority based on Japanese Patent Application No. 2020-87180 (filing date: May 19, 2020). This application incorporates all the contents of the base application by reference thereto. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] There is known a semiconductor memory device including a substrate, a plurality of gate electrodes stacked in a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of gate electrodes, and a gate insulating film provided between the gate electrodes and the semiconductor layer. The gate insulating film includes, for example, an insulating charge storage layer such as silicon nitride (Si3N4) or a conductive charge storage layer such as a floating gate, which is a memory portion capable of storing data. Summary of the Invention

[0005] An embodiment provides a semiconductor memory device that can achieve high-speed writing sequence without reducing reliability.

[0006] A semiconductor memory device according to an embodiment includes a memory transistor and a word line connected to a gate electrode of the memory transistor. Further, the semiconductor memory device is configured to execute a writing sequence in which a plurality of writing cycles are performed on the memory transistor. The writing cycle includes a programming operation of supplying a programming voltage to the word line and at least one verification operation of supplying a verification voltage to the word line. During the period from the start to the end of the writing sequence, when the writing sequence is not interrupted, in the nth (n is a natural number) writing cycle, one programming operation is performed and m (m is a natural number of 2 or more) verification operations are performed. When the writing sequence is interrupted after the kth (k is a natural number less than m) verification operation and before the (k + 1)th verification operation in the nth writing cycle of the writing sequence, a verification voltage corresponding to the first verification operation or a voltage higher than that is supplied to the word line after restarting the writing sequence and before starting the (k + 1)th verification operation. The time from restarting the writing sequence to starting the (k + 1)th verification operation is shorter than the time from the start of the first verification operation to the end of the kth verification operation in the nth writing cycle. Brief Description of the Drawings

[0007] Figure 1 is a schematic block diagram showing the configuration of a storage system 10 according to the first embodiment.

[0008] Figure 2 is a schematic side view showing a configuration example of the storage system 10.

[0009] Figure 3 is a schematic top view showing the described configuration example.

[0010] Figure 4 is a schematic block diagram showing the configuration of the memory die MD of the first embodiment.

[0011] Figure 5 is a schematic circuit diagram showing a part of the configuration of the memory die MD.

[0012] Figure 6 is a schematic circuit diagram showing a part of the configuration of the memory die MD.

[0013] Figure 7 is a schematic perspective view of the memory die MD.

[0014] Figure 8 is Figure 7 a schematic enlarged view of a part of the shown structure.

[0015] Figure 9 is a schematic histogram for explaining the threshold voltage of the memory cell MC.

[0016] Figure 10 is a schematic waveform diagram for explaining the read operation.

[0017] Figure 11 is a schematic cross-sectional view for explaining the read operation.

[0018] Figure 12 is a schematic waveform diagram for explaining the write sequence.

[0019] Figure 13 is a schematic flowchart for explaining the write sequence.

[0020] Figure 14 is a schematic cross-sectional view for explaining the programming operation.

[0021] Figure 15 is a schematic cross-sectional view for explaining the verification operation.

[0022] Figure 16 is a schematic waveform diagram for explaining the verification operation.

[0023] Figure 17 is a schematic table for explaining the verification operation.

[0024] Figure 18 is a schematic waveform diagram for explaining the interruption and restart of the write sequence.

[0025] Figure 19 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence.

[0026] Figure 20 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence.

[0027] Figure 21 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the first comparative example.

[0028] Figure 22 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the second comparative example.

[0029] Figure 23 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the second embodiment.

[0030] Figure 24 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the third embodiment.

[0031] Figure 25 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the fourth embodiment.

[0032] Figure 26 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the fifth embodiment.

[0033] Figure 27 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the sixth embodiment.

[0034] Figure 28 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the seventh embodiment.

[0035] Figure 29 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the eighth embodiment.

[0036] Figure 30 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the eighth embodiment.

[0037] Figure 31 It is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the eighth embodiment. Detailed implementation manners

[0038] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. In addition, the following embodiments are merely examples and are not intended to limit the present invention. In addition, the following drawings are schematic diagrams, and in order to facilitate explanation, there are cases where a part of the configuration is omitted. In addition, there are cases where the same reference numerals are attached to common parts in a plurality of embodiments and the description thereof is omitted.

[0039] In addition, in this specification, when referring to a "semiconductor memory device", it sometimes refers to a memory die, sometimes refers to a memory chip, a memory card, a storage system including a controller die such as an SSD (Solid State Drive), etc. Moreover, it sometimes refers to a configuration including a host such as a smartphone, a tablet terminal, or a personal computer.

[0040] In addition, in this specification, when referring to a case where a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, in the case of connecting three transistors in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0041] In addition, in this specification, when referring to a case where a first configuration is "connected between" a second configuration and a third configuration, there is a case where the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0042] In addition, in this specification, when referring to a case where a circuit causes two wirings or the like to be "conductive", for example, it refers to a case where the circuit includes transistors or the like, the transistors or the like are provided on a current path between two wirings, and the transistors or the like are in an ON state.

[0043] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0044] In addition, in this specification, sometimes a direction along a specific plane is referred to as the first direction, a direction intersecting the first direction along the specific plane is referred to as the second direction, and a direction intersecting the plane is referred to as the third direction. The first direction, the second direction, and the third direction may correspond to any one of the X direction, the Y direction, and the Z direction, or may not correspond.

[0045] In addition, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as upper, and the direction approaching the substrate along the Z direction is referred to as lower. In addition, when referring to the lower surface or lower end of a certain component, it means the surface or end on the substrate side of the component, and when referring to the upper surface or upper end, it means the surface or end on the side opposite to the substrate of the component. In addition, a surface intersecting the X direction or Y direction is referred to as a side surface.

[0046] [First Embodiment]

[0047] [Storage System 10]

[0048] Figure 1 is a schematic block diagram showing the configuration of the storage system 10 according to the first embodiment.

[0049] The storage system 10 reads, writes, deletes, etc. user data according to signals sent from the host 20. The storage system 10 is, for example, a memory chip, a memory card, an SSD, or other systems capable of storing user data. The storage system 10 includes a plurality of memory dies MD for storing user data, and a controller die CD connected to the plurality of memory dies MD and the host 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), etc., and performs processing such as conversion between logical addresses and physical addresses, error detection / correction, garbage collection (compression), wear leveling, etc.

[0050] Figure 2 is a schematic side view showing a configuration example of the storage system 10 according to this embodiment. Figure 3 is a schematic top view showing the configuration example. For ease of explanation, in Figure 2 and Figure 3 a part of the configuration is omitted.

[0051] As Figure 2 shown, the storage system 10 according to this embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided in the end regions in the Y direction on the upper surface of the mounting substrate MSB, and other part regions are bonded to the lower surface of the memory dies MD via an adhesive or the like. Pad electrodes P are provided in the end regions in the Y direction on the upper surface of the memory dies MD, and other regions are bonded to the lower surface of other memory dies MD or the controller die CD via an adhesive or the like. Pad electrodes P are provided in the end regions in the Y direction on the upper surface of the controller die CD.

[0052] As Figure 3As shown, the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD each have a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P provided on the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are connected to each other via bonding wires B, respectively.

[0053] In addition, as shown in FIGS. 2 and Figure 3 The configuration shown is merely an example, and the specific configuration can be adjusted as appropriate. For example, in the example shown in Figure 2 and Figure 3 the controller die CD is stacked on the plurality of memory dies MD, and the configuration is connected by the bonding wires B. In this configuration, the plurality of memory dies MD and the controller die CD are included in one package. However, the controller die CD may also be included in a package different from the memory die MD. In addition, the plurality of memory dies MD and the controller die CD may be connected to each other via through electrodes or the like instead of the bonding wires B.

[0054] [Circuit Configuration of Memory Die MD]

[0055] Figure 4 is a schematic block diagram showing the configuration of the memory die MD of the first embodiment. Figure 5 and Figure 6 are schematic circuit diagrams showing a partial configuration of the memory die MD.

[0056] In addition, Figure 4 illustrates a plurality of control terminals and the like. The plurality of control terminals may be described as control terminals corresponding to a high-active signal (positive logic signal), as control terminals corresponding to a low-active signal (negative logic signal), or as control terminals corresponding to both a high-active signal and a low-active signal. Figure 4 In, the symbol of the control terminal corresponding to the low-active signal includes an overline. In this specification, the symbol of the control terminal corresponding to the low-active signal includes a slash (" / ").

[0057] As shown in Figure 4 the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. In addition, the peripheral circuit PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. In addition, the peripheral circuit PC includes an input / output control circuit I / O and an AND logic circuit CTR.

[0058] [Circuit Configuration of Memory Cell Array MCA]

[0059] The memory cell array MCA is Figure 5 As shown, there are multiple memory blocks BLK. Each of the multiple memory blocks BLK has multiple string units SU. Each of the multiple string units SU has multiple memory strings MS. One end of each of the multiple memory strings MS is connected to the peripheral circuit PC via a bit line BL. In addition, the other ends of each of the multiple memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0060] The memory string MS includes: a drain side selection transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC (memory transistors), a source side selection transistor STS, and a source side selection transistor STSb. Hereinafter, the drain side selection transistor STD, the source side selection transistor STS, and the source side selection transistor STSb are sometimes referred to as selection transistors (STD, STS, STSb).

[0061] The memory cell MC is a field effect transistor having a semiconductor layer functioning as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. The memory cell MC stores 1-bit or multi-bit data. In addition, a word line WL is connected to each gate electrode of a plurality of memory cells MC corresponding to a memory string MS. The word lines WL are respectively connected to all memory strings MS in a memory block BLK in common.

[0062] The selection transistors (STD, STS, STSb) are field effect transistors having a semiconductor layer, a gate insulating film, and a gate electrode that function as a channel region. The gate electrodes of the selection transistors (STD, STS, STSb) are connected to the selection gate lines (SGD, SGS, SGSb), respectively. The drain-side selection gate line SGD is set corresponding to the string unit SU and is commonly connected to all storage strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all storage strings MS in multiple string units SU. The source-side selection gate line SGSb is commonly connected to all storage strings MS in multiple string units SU.

[0063] [Circuit Configuration of Voltage Generating Circuit VG]

[0064] Voltage generating circuit VG( Figure 4 ) For example Figure 5 As shown, the voltage generating circuit VG includes a voltage step-down circuit such as a regulator and a voltage step-up circuit such as a charge pump circuit 32. The voltage step-down circuit and the voltage step-up circuit are connected to the supply voltage V CC and ground voltage V SS ( Figure 4)'s voltage supply line. The voltage supply line is connected to a reference, for example. Figure 2 , Figure 3 The pad electrode P described. The voltage generation circuit VG generates, for example, a plurality of operation voltages applied to the bit lines BL, source lines SL, word lines WL, and selection gate lines (SGD, SGS, SGSb) during the read operation, write sequence, and erase sequence for the memory cell array MCA in accordance with a control signal from the sequencer SQC, and outputs them to a plurality of voltage supply lines 31 at the same time. The operation voltages output from the voltage supply lines 31 are appropriately adjusted in accordance with the control signal from the sequencer SQC.

[0065] [Circuit configuration of row decoder RD]

[0066] The row decoder RD ( Figure 4 ) has, for example, as Figure 5 shown: an address decoder 22 that decodes the address data D ADD ; and a block selection circuit 23 and a voltage selection circuit 24 that transfer the operation voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0067] The address decoder 22 has a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22 sequentially refers to the row address RA of the address register ADR ( Figure 4 ) in accordance with a control signal from the sequencer SQC, decodes the row address RA, sets the specific block selection transistor 35 and voltage selection transistor 37 corresponding to the row address RA to the ON state, and sets the other block selection transistors 35 and voltage selection transistors 37 to the OFF state. For example, the voltages of the specific block selection line BLKSEL and the voltage selection line 33 are set to the "H" state, and the other voltages are set to the "L" state. In addition, when using P-channel transistors instead of N-channel transistors, the opposite voltage is applied to the wiring.

[0068] In addition, in the illustrated example, in the address decoder 22, the block selection lines BLKSEL are set one by one for each memory block BLK. However, the configuration can be appropriately changed. For example, the block selection lines BLKSEL can also be set one by one for two or more memory blocks BLK.

[0069] The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory blocks BLK. Each of the plurality of block selection units 34 includes a plurality of block selection transistors 35 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). The block selection transistors 35 are, for example, field effect withstand voltage transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb) respectively. The source electrodes are electrically connected to the voltage supply line 31 via the wirings CG and the voltage selection circuit 24 respectively. The gate electrodes are commonly connected to the corresponding block selection lines BLKSEL.

[0070] In addition, the block selection circuit 23 further includes a plurality of transistors (not shown). The plurality of transistors are field effect transistors connected between the selection gate lines (SGD, SGS, SGSb) and the voltage supply line supplied with the ground voltage V SS The plurality of transistors supply the ground voltage V SS to the selection gate lines (SGD, SGS, SGSb) included in the non-selected memory block BLK.

[0071] The voltage selection circuit 24 includes a plurality of voltage selection units 36 corresponding to the word lines WL and the selection gate lines (SGD, SGS, SGSb). Each of the plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistors 37 are, for example, field effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or selection gate lines (SGD, SGS, SGSb) via the wirings CG and the block selection circuit 23 respectively. The source terminals are electrically connected to the corresponding voltage supply lines 31 respectively. The gate electrodes are connected to the corresponding voltage selection lines 33 respectively.

[0072] In addition, in the illustrated example, an example in which the wiring CG is connected to the voltage supply line 31 via one voltage selection transistor 37 is shown. However, this configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, the wiring CG may also be connected to the voltage supply line 31 via two or more voltage selection transistors 37.

[0073] [Circuit Configuration of the Sense Amplifier Module SAM]

[0074] The sense amplifier module SAM, for example, includes a plurality of sense amplifier units SAU corresponding to a plurality of bit lines BL. The sense amplifier unit SAU is as Figure 6As shown, each includes a sense amplifier SA connected to a bit line BL, a wiring LBUS connected to the sense amplifier SA, a latch circuit SDL connected to the wiring LBUS, a plurality of latch circuits DL connected to the wiring LBUS, and a charging transistor 55 for precharging connected to the wiring LBUS. The wiring LBUS in the sense amplifier unit SAU is connected to the wiring DBUS via a switching transistor DSW.

[0075] The sense amplifier SA is as Figure 6 shown and includes a sense transistor 41 that discharges the charge of the wiring LBUS according to the current flowing in the bit line BL. The source electrode of the sense transistor 41 is connected to a voltage supply line to which the ground voltage V SS is supplied. The drain electrode is connected to the wiring LBUS via a switching transistor 42. The gate electrode is connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamping transistor 44, and a breakdown voltage transistor 45. In addition, the sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

[0076] In addition, the sense amplifier SA includes a voltage transfer circuit that selectively conducts the node COM and the sense node SEN to a voltage supply line to which the voltage V DD is supplied or a voltage supply line to which the voltage V SRC is supplied according to the data latched in the latch circuit SDL. The voltage transfer circuit includes: a node N1; a charging transistor 46 connected between the node N1 and the sense node SEN; a charging transistor 49 connected between the node N1 and the node COM; a charging transistor 47 connected between the node N1 and the voltage supply line to which the voltage V DD is supplied; and a discharge transistor 50 connected between the node N1 and the voltage supply line to which the voltage V SRC is supplied. In addition, the gate electrodes of the charging transistor 47 and the discharge transistor 50 are commonly connected to the node INV_S of the latch circuit SDL.

[0077] In addition, the sense transistor 41, the switching transistor 42, the discharge transistor 43, the clamping transistor 44, the charging transistor 46, the charging transistor 49, and the discharge transistor 50 are, for example, enhancement-type NMOS transistors. The breakdown voltage transistor 45 is, for example, a depletion-type NMOS transistor. The charging transistor 47 is, for example, a PMOS transistor.

[0078] In addition, the gate electrode of the switching transistor 42 is connected to the signal line STB. The gate electrode of the discharge transistor 43 is connected to the signal line XXL. The gate electrode of the clamping transistor 44 is connected to the signal line BLC. The gate electrode of the breakdown voltage transistor 45 is connected to the signal line BLS. The gate electrode of the charging transistor 46 is connected to the signal line HLL. The gate electrode of the charging transistor 49 is connected to the signal line BLX. The signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC.

[0079] The latch circuit SDL includes: nodes LAT_S, INV_S, an inverter 51 having an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S, an inverter 52 having an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S, a switching transistor 53 connected to the node LAT_S and the wiring LBUS, and a switching transistor 54 connected to the node INV_S and the wiring LBUS. The switching transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of the switching transistor 53 is connected to the sequencer SQC via the signal line STL. The gate electrode of the switching transistor 54 is connected to the sequencer SQC via the signal line STI.

[0080] A plurality of latch circuits DL are each configured almost identically to the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is electrically connected to the gate electrodes of the charging transistor 47 and the discharge transistor 50 in the sense amplifier SA. The latch circuit DL differs from the latch circuit SDL in this regard.

[0081] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switching transistor DSW is connected to the sequencer SQC via the signal line DBS.

[0082] In addition, the signal lines STB, HLL, XXL, BLX, BLC, and BLS are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. In addition, the voltage supply line supplied with the voltage V DD and the voltage supply line supplied with the voltage V SRC are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. In addition, the signal line STI and the signal line STL of the latch circuit SDL are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines corresponding to the signal line STI and the signal line STL among the plurality of latch circuits DL are commonly connected among all the sense amplifier units SAU included in the sense amplifier module SAM.

[0083] [Circuit Configuration of Cache Memory CM]

[0084] Cache memory CM ( Figure 4 ) has a plurality of latch circuits connected to the latch circuit in the sense amplifier module SAM via the wiring DBUS. The data DAT contained in the plurality of latch circuits is sequentially transmitted to the sense amplifier module SAM or the input / output control circuit I / O.

[0085] In addition, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA stored in the address register ADR ( Figure 4 ). The switching circuit conducts the latch circuit corresponding to the column address CA to the bus DB ( Figure 4 ) according to the output signal of the decoding circuit.

[0086] [Circuit Configuration of Sequencer SQC]

[0087] Sequencer SQC ( Figure 4 ) outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG according to the command data D stored in the command register CMR CMD . In addition, the sequencer SQC outputs status data D ST appropriately representing its own state to the status register STR. In addition, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. In addition, the terminal RY / / BY is realized by, for example, the pad electrode P described in reference Figure 2 , Figure 3 .

[0088] [Circuit Configuration of Input / Output Control Circuit I / O]

[0089] The input / output control circuit I / O has data signal input / output terminals DQ0 to DQ7, clock signal input / output terminals DQS, / DQS, input circuits such as comparators connected to the data signal input / output terminals DQ0 to DQ7, and output circuits such as OCD (OffChip Driver) circuits. In addition, the input / output circuit I / O has a shift register and a buffer circuit connected to the input circuit and the output circuit. The input circuit, the output circuit, the shift register, and the buffer circuit are respectively connected to the terminals supplied with the power supply voltage V CCQ and the ground voltage V SS . The data signal input / output terminals DQ0 to DQ7, the clock signal input / output terminals DQS, / DQS, and the terminals supplied with the power supply voltage V CCQ are realized by, for example, the references Figure 2 , Figure 3The described pad electrode P is implemented. The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR according to the internal control signal from the logic circuit CTR. In addition, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0090] [Circuit configuration of the logic circuit CTR]

[0091] The logic circuit CTR ( Figure 4 ) receives an external control signal from the controller die CD via the external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and correspondingly outputs an internal control signal to the input / output control circuit I / O. In addition, the external control terminals / CEn, CLE, ALE, / WE, RE, / RE are implemented, for example, by the pad electrode P described with reference to Figure 2 , Figure 3 The described pad electrode P is implemented.

[0092] [Structure of the memory die MD]

[0093] Figure 7 is a schematic perspective view of the memory die MD. Figure 8 is Figure 7 A partial schematic enlarged view of the structure shown. In addition, Figure 7 and Figure 8 are diagrams for explaining the schematic configuration of the memory die MD, and do not show the quantity, shape, arrangement, etc. of the specific configuration.

[0094] The memory die MD includes, for example, as shown in Figure 7 : a semiconductor substrate 100, a transistor layer L provided on the semiconductor substrate 100 TR , a wiring layer D0, D1, D2 provided above the transistor layer L TR , a memory cell array layer L provided above the wiring layer D0, D1, D2 MCA , and a plurality of wiring layers provided above the memory cell array layer L MCA .

[0095] The semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si), and the P-type silicon contains P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, semiconductor regions and insulation regions STI are provided. The semiconductor regions respectively function as channel regions and the like of the plurality of transistors Tr constituting the peripheral circuit PC.

[0096] The transistor layer L TRGate electrodes of multiple transistors Tr and contacts CS connected to the multiple transistors Tr. These gate electrodes and contacts CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0097] The wiring layers D0, D1, D2 include multiple wirings. The multiple wirings are electrically connected to at least one of the components in the memory cell array MCA and the components in the peripheral circuit PC. The multiple wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0098] Memory cell array layer L MCA It includes multiple conductive layers 110 arranged in the Z direction, multiple semiconductor pillars 120 extending in the Z direction, and multiple gate insulating films 130 respectively provided between the multiple conductive layers 110 and the multiple semiconductor pillars 120.

[0099] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. One or more of the conductive layers 110 located at the lowermost layer among the multiple conductive layers 110 function as gate electrodes of the source-side selection gate lines SGS, SGSb ( Figure 5 ) and the multiple source-side selection transistors STS, STSb connected thereto. In addition, the multiple conductive layers 110 located further above function as word lines WL ( Figure 5 ) and gate electrodes of the multiple memory cells MC ( Figure 5 ) connected thereto. In addition, one or more of the conductive layers 110 located further above function as a drain-side selection gate line SGD and gate electrodes of the multiple drain-side selection transistors STD ( Figure 5 ) connected thereto. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 110 may include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). Between the multiple conductive layers 110 arranged in the Z direction, an insulating layer 101 such as silicon dioxide (SiO2) is provided.

[0100] Below the conductive layer 110, a conductive layer 140 is provided. The conductive layer 140 functions as a source line SL ( Figure 5 ). The conductive layer 140 includes a semiconductor layer 141 connected to the lower end of the semiconductor pillar 120 and a conductive layer 142 connected to the lower surface of the semiconductor layer 141. The semiconductor layer 141 may include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 142 may include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon dioxide (SiO2) is provided between the conductive layer 140 and the conductive layer 110.

[0101] In the conductive layers 110 and 140, contact members CC extending in the Z direction are connected. The contact member CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0102] The semiconductor pillars 120 are arranged in a specific pattern in the X direction and the Y direction. The semiconductor pillar 120 functions as a channel region of a plurality of memory cells MC and selection transistors (STD, STS, STSb) included in one memory string MS( Figure 5 ). The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 has a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. In addition, the outer peripheral surfaces of the semiconductor pillars 120 are respectively surrounded by the conductive layer 110 and face the conductive layer 110.

[0103] An impurity region 121 containing an N-type impurity such as phosphorus (P) is provided at the upper end portion of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via the contact member Ch and the contact member Cb.

[0104] An impurity region 122 containing an N-type impurity such as phosphorus (P) is provided at the lower end portion of the semiconductor pillar 120. The impurity region 122 is connected to the semiconductor layer 141 of the conductive layer 140. The portion of the semiconductor pillar 120 directly above the impurity region 122 functions as a channel region of the source-side selection transistor STSb.

[0105] The gate insulating film 130 has a substantially bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 is, for example, as Figure 8 shown, and includes a tunneling insulating film 131, a charge storage film 132, and a barrier insulating film 133 laminated between the semiconductor pillar 120 and the conductive layer 110. The tunneling insulating film 131 and the barrier insulating film 133 are insulating films such as silicon oxide (SiO2), for example. The charge storage film 132 is a film capable of storing charges such as silicon nitride (Si3N4), for example. The tunneling insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

[0106] In addition, Figure 8 an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride has been shown. However, the gate insulating film 130 may also include a floating gate such as polysilicon containing an N-type or P-type impurity, for example.

[0107] The plurality of wiring layers provided above the memory cell array layer L MCA include the bit line BL( Figure 7 ), and the pad electrode P( Figure 2 , Figure 3 ).

[0108] Bit line BL( Figure 7 ) may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). The bit lines BL are arranged in the X direction and extend in the Y direction. In addition, each of the plurality of bit lines BL is connected to one semiconductor pillar 120 included in each string unit SU( Figure 5 ).

[0109] Pad electrode P( Figure 2 , Figure 3 ) may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as aluminum (Al).

[0110] [Threshold voltage of memory cell MC]

[0111] Next, with reference to Figure 9 , the threshold voltage of the memory cell MC will be described.

[0112] As described above, the memory cell array MCA includes a plurality of memory cells MC. When a write sequence is performed on the plurality of memory cells MC, the threshold voltages of these memory cells MC are controlled to multiple states.

[0113] Figure 9 is a schematic histogram for explaining the threshold voltage of the memory cell MC that stores 4-bit data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC in the memory cell array MCA.

[0114] Figure 9 In the example of , the threshold voltage of the memory cell MC is controlled to 16 states. For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erased state). Data "1111" can be assigned to the memory cell MC corresponding to the Er state, for example. In addition, the S1 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. Data "1110" can be assigned to the memory cell MC corresponding to the S1 state, for example. Similarly, the S2 state to S15 states in the figure respectively correspond to threshold voltages higher than the threshold voltages corresponding to the S1 state to S14 states. Different 4-bit data are assigned to the memory cells MC corresponding to these distributions respectively.

[0115] For example, the threshold voltage of the memory cell MC controlled to the Er state is less than Figure 9 read voltage V CGS1R and verification voltage V VFYS1 . In addition, for example, the threshold voltage of the memory cell MC controlled to the S1 state is greater than Figure 9 read voltage V CGS1R and verification voltage V VFYS1, less than the read voltage V CGS2R and the verification voltage V VFYS2 . Additionally, for example, the threshold voltage of the memory cell MC controlled to the S2 state is greater than Figure 9 the read voltage V CGS2R and the verification voltage V VFYS2 , less than the read voltage V CGS3R and the verification voltage V VFYS3 . Similarly hereinafter, the threshold voltages of the memory cells MC controlled to the S3 state to S15 states in the figure are controlled within a specific range. Additionally, the threshold voltages of all the memory cells MC are less than Figure 9 the read path voltage V READ .

[0116] [Read Operation]

[0117] Next, with reference to Figure 10 and Figure 11 , the read operation of the semiconductor memory device of the present embodiment will be described.

[0118] Figure 10 is a schematic waveform diagram for explaining the read operation. Figure 10 The signal waveforms shown represent the signals of the terminal RY / / BY ( Figure 4 ) of the memory die MD.

[0119] At time t101, the terminal RY / / BY ( Figure 4 ) of the memory die MD is in the “H” state. The controller die CD inputs the command C01 to the memory die MD at time t101, then inputs the address A01, and then inputs the command C02. The command C01 is a command meaning to execute the read operation. When the command C01 is input, for example, 8-bit data corresponding to the command C01 is set to the data signal input / output terminals DQ0 to DQ7, and “L, H, L” is set to the external control terminals / CEn, CLE, ALE. In this state, the external control terminal / WE is raised from the L state to the H state. Thus, the command C01 is latched into the command register CMR as the command data D CMD ( Figure 4 ). When the address A01 is input, for example, 8-bit data included in the address A01 is sequentially set to the data signal input / output terminals DQ0 to DQ7, and “L, L, H” is set to the external control terminals / CEn, CLE, ALE. In this state, the external control terminal / WE is raised from the L state to the H state multiple times. Thus, the address A01 is latched into the address register ADR as the address data D ADD ( Figure 4 ). The command C02 is a command meaning to start the read operation. The input of the command C02 is performed in the same manner as the input of the command C01.

[0120] At time t102, the read operation of the memory die MD starts, and the terminal RY / / BY ( Figure 4 ) of the memory die MD is in the "L" state.

[0121] At time t103, the read operation of the memory die MD ends, and the terminal RY / / BY ( Figure 4 ) of the memory die MD is in the "H" state.

[0122] At time t104, the controller die CD inputs command C03 to the memory die MD, then inputs address A01, and then inputs command C04. Command C03 is a command meaning to output the data read by the read operation. Command C04 is a command meaning to start outputting data. The input of commands C03 and C04 is performed in the same way as the input of command C01. Then, the controller die CD reads data D01 from the memory die MD. When reading data D01, for example, the 8-bit data output from the data signal input / output terminals DQ0 to DQ7 and the signal switching input to the external control terminals RE and / RE are alternately executed. The controller die CD performs error detection / correction, etc. on the data, and then transfers it to the host 20. In addition, although Figure 10 is omitted here, when reading data D01, commands and addresses may also be input again.

[0123] Figure 11 is a schematic cross-sectional view for explaining the read operation. In addition, in the following description, the word line WL that becomes the operation object is referred to as the selected word line WL S , and the word line WL other than this is referred to as the non-selected word line WL U . In addition, in the following description, among the multiple memory cells MC included in the string unit SU, those connected to the selected word line WL S are referred to as "selected memory cells MC" in some cases.

[0124] When the memory die MD is in the read operation, for example, charging of the bit line BL is performed. For example, Figure 6 the latch circuit SDL is latched to "H", and the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, H, H". Thereby, voltage V is supplied to the bit line BL and the sense node SEN DD , and charging of them starts. In addition, for example, voltage V is supplied to the source line SL ( Figure 5 ), and charging of them starts. Voltage V SRC has, for example, a magnitude similar to that of the ground voltage V SRC . Voltage V SS is, for example, greater than the ground voltage V SRC For example, it has a magnitude similar to that of the ground voltage VSS , less than the voltage V DD .

[0125] In addition, for example, as Figure 11 shown, a plurality of selected memory cells MC are connected to the bit line BL and the source line SL. For example, a voltage V is supplied to the select gate lines (SGD, SGS0, SGSb). SG , and the select transistors (STD, STS, STSb) are set to the ON state. In addition, a read path voltage V is supplied to the unselected word line WL U , and all the memory cells MC connected to the unselected word line WL READ are set to the ON state. U

[0126] In addition, as Figure 11 shown, any one of the read voltages V corresponding to the data to be read is supplied to the selected word line WL S . CGSR ( Figure 9 any one of the read voltages V CGS1R ~V CGS15R ). Thus, the memory cells MC corresponding to any state of Figure 9 become the ON state, and the memory cells MC corresponding to any state become the OFF state.

[0127] In addition, the sense amplifier module SAM( Figure 5 ) detects the ON / OFF state of the selected memory cell MC. For example, the wiring LBUS is charged via the charging transistor 55 of Figure 6 . In addition, the states of the signal lines STB, XXL, BLC, BLS, HLL, BLX are set to "L, H, H, H, L, H", and the charge of the sense node SEN is released to the bit line BL. Here, the voltage of the sense node SEN connected to the bit line BL corresponding to the memory cell MC in the ON state decreases significantly relatively. On the other hand, the voltage of the sense node SEN connected to the bit line BL corresponding to the memory cell MC in the OFF state does not decrease much. Therefore, at a specific moment, the signal line STB is set to the "H" state, the charge of the wiring LBUS is released or maintained, the signal line STL is set to the "H" state, and thus, the data representing the state of the selected memory cell MC is latched into the latch circuit SDL. In addition, the data can also be latched into any latch circuit DL other than the latch circuit SDL.

[0128] When it is necessary to perform a read operation using a plurality of read voltages V CGSR , if necessary, the supply of the read voltage V to the selected word line WL is repeated multiple times S . CGSR ​, detect and select the on / off state of the memory cell MC, and latch the detected data. In addition, perform arithmetic processing on the latched data to calculate Figure 10 data D01.

[0129] After that, according to the command C04 described in Figure 10 , output data D01 ( Figure 10 ). For example, the data D01 detected and calculated by the sense amplifier module SAM is transmitted to the controller die CD ( Figure 4 ) via the cache memory CM ( Figure 1 ), the bus DB, and the input / output control circuit I / O.

[0130] [Write Sequence]

[0131] Next, refer to Figures 12 to 17 to describe the write sequence of the semiconductor memory device.

[0132] Figure 12 is a schematic waveform diagram for explaining the write sequence. Figure 12 The signal waveforms shown represent the signals of the terminal RY / / BY ( Figure 4 ) of the memory die MD.

[0133] At time t111, the terminal RY / / BY ( Figure 4 ) of the memory die MD is in the "H" state. The controller die CD inputs the command C11 to the memory die MD at time t111, then inputs the address A11, then inputs the data D11, and then inputs the command C12. The commands C11 and C12 are commands meaning to execute and start the write sequence. The input of the commands C11 and C12 is performed in the same way as the input of the command C01. The input of the address A11 is performed in the same way as the input of the address A01. When inputting the data D11, for example, the 8-bit data included in the data D11 is sequentially set to the data signal input / output terminals DQ0 to DQ7, and the external control terminals / CEn, CLE, and ALE are set to "L, L, L". In this state, the external control terminal / WE is raised from the L state to the H state multiple times. Thus, the data D11 is latched into the cache memory CM as the data DAT ( Figure 4 ).

[0134] At time t112, the write sequence of the memory die MD starts, and the terminal RY / / BY ( Figure 4 ) of the memory die MD becomes the "L" state.

[0135] At time t1113, the write sequence of the memory die MD ends, and the terminal RY / / BY ( Figure 4 ) of the memory die MD becomes the "H" state.

[0136] At time t114, the controller die CD inputs command C13 to the memory die MD. Command C13 is a command meaning to output status data. The input of command C13 is performed in the same manner as the input of command C01. Next, the controller die CD reads data D12 from the memory die MD. Data D12 is, for example, status data D ST ( Figure 4 ). The reading of data D12 is performed in the same manner as the reading of data D01.

[0137] Figure 13 is a schematic flowchart for explaining a write sequence. Figure 14 is a schematic cross-sectional view for explaining a programming operation included in the write sequence. Figure 15 is a schematic cross-sectional view for explaining a verification operation included in the write sequence. Figure 16 is a schematic waveform diagram for explaining the verification operation. Figure 17 is a schematic table for explaining the verification operation, showing which state among states S1 to S11 the verification operation performed in each write cycle corresponds to. In addition, Figure 17 in the exemplified table, only the part corresponding to states S1 to S11 is shown, and the part corresponding to states S12 to S15 is omitted.

[0138] In step S101( Figure 13 ), the loop count n W is set to 1. The loop count n W is recorded in a register or the like. In addition, in step S101, 4-bit data corresponding to the data written to each memory cell MC can be latched in a plurality of latch circuits DL in the sense amplifier unit SAU.

[0139] In step S102, a programming operation is performed.

[0140] During the programming operation, for example, as Figure 14 shown, it is determined whether to adjust the threshold voltage of a plurality of selected memory cells MC (hereinafter, sometimes referred to as "writing to memory cell MC") or not to adjust the threshold voltage of a plurality of selected memory cells MC (hereinafter, sometimes referred to as "prohibiting memory cell MC"). The determination can be made, for example, based on the data latched in a plurality of latch circuits DL in the sense amplifier unit SAU( Figure 6 ). In addition, voltage V SRC is supplied to the bit line BL connected to the memory cell MC to be written, and voltage V DD is supplied to the bit line BL connected to the prohibited memory cell MC. For example, the latch circuit SDL corresponding to the memory cell MC to be written( Figure 6)Latch “L” to enable the latch circuit SDL corresponding to the prohibited memory cell MC Figure 6 )Latch “H”. Additionally, set the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX to “L, L, H, H, L, H”.

[0141] Additionally, connect the write memory cell MC to the bit line BL and disconnect the prohibited memory cell MC from the bit line BL. For example, supply voltage V SGD to the drain - side select gate line SGD. Voltage V SGD For example, is less than Figure 11 voltage V SG . Thus, the drain - side select transistor STD corresponding to the bit line BL supplied with voltage V SRC becomes in the on - state, and the drain - side select transistor STD corresponding to the bit line BL supplied with voltage V DD is in the off - state. Additionally, supply the write path voltage V U to the non - selected word line WL PASS . The write path voltage V PASS For example, is greater than Figure 11 the read path voltage V READ .

[0142] Additionally, supply the programming voltage V S to the selected word line WL PGM . The programming voltage V PGM is greater than the write path voltage V PASS . Thus, electrons are accumulated in the charge storage film 132( Figure 8 ) of the desired memory cell MC, and the threshold voltage of the memory cell MC increases.

[0143] In step S103( Figure 13 ), a verification operation is performed. Additionally, in step S104( Figure 13 ), it is determined whether the verification operation has ended. If the verification operation has not ended, the process proceeds to step S103. If the verification operation has ended, the process proceeds to step S105.

[0144] For example, in the case of Figure 16 , the verification operation corresponding to state S1 starts at time t121 (step S103). Along with this, supply the verification voltage V S to the selected word line WL VFYS1 . Additionally, the states of the signal lines BLC, HLL, XXL, STB( Figure 6 ) become “H, H, L, L”. Along with this, supply voltage V DD to the bit line BL connected to the memory cell MC corresponding to state S1, and supply voltage V SRC to the other bit lines BL。In addition, for example, as Figure 15 shown, the selected memory cell MC is turned on to the bit line BL and the source line SL.

[0145] In addition, at time t122, the states of the signal lines BLC, HLL, XXL, STB ( Figure 6 ) are "H, L, H, L".

[0146] In addition, at time t123, the states of the signal lines BLC, HLL, XXL, STB ( Figure 6 ) are "H, L, L, H", the on-state / off-state of the selected memory cell MC is detected, and the data representing the state of the selected memory cell MC is latched into any one of the latch circuits DL.

[0147] In addition, at time t124, the verification operation (step S103) corresponding to the state S1 ends. In step S104, a determination is made that the verification operation has not ended, and the verification operation (step S103) corresponding to the state S2 is started. Along with this, a verification voltage V is supplied to the selected word line WL S . In addition, the states of the signal lines BLC, HLL, XXL, STB ( VFYS2 ) are "H, L, L, L". Figure 6

[0148] In addition, at time t125, the states of the signal lines BLC, HLL, XXL, STB ( Figure 6 ) are "H, H, L, L". Along with this, a voltage V is supplied to the bit line BL connected to the memory cell MC corresponding to the state S2 DD , and a voltage V is supplied to the other bit lines BL SRC .

[0149] In addition, at time t126, the states of the signal lines BLC, HLL, XXL, STB ( Figure 6 ) are "H, L, H, L".

[0150] In addition, at time t127, the states of the signal lines BLC, HLL, XXL, STB ( Figure 6 ) are "H, L, L, H", the on-state / off-state of the selected memory cell MC is detected, and the data representing the state of the selected memory cell MC is latched into any one of the latch circuits DL.

[0151] In addition, at time t128, the states of the signal lines BLC, HLL, XXL, STB ( Figure 6 ) are "H, L, L, L".

[0152] ​In addition, at time t129, the verification operation (step S103) corresponding to state S2 ends, and in step S104, a determination indicating the end of the verification operation is made. Along with this, a ground voltage V is supplied to the selected word line WL S is supplied to the selected word line WL SS . In addition, the states of the signal lines BLC, HLL, XXL, STB( Figure 6 ) are "L, L, L, L".

[0153] In addition, in steps S103 and S104, based on the data indicating the states of the memory cells MC obtained at times t123, t127, etc., it is determined whether each memory cell MC has reached the target threshold voltage. For the memory cells MC determined to have reached the target threshold voltage, the data in the multiple latch circuits DL in the sense amplifier unit SAU corresponding to the memory cells MC is updated. For example, the data in the latch circuit DL is updated to a value indicating write inhibition. Thus, in subsequent write sequences, the memory cells MC are treated as prohibited memory cells MC. For the memory cells MC determined not to have reached the target threshold voltage, the data in the multiple latch circuits DL in the sense amplifier unit SAU corresponding to the memory cells MC is maintained.

[0154] In addition, the number of verification operations performed in each write cycle, etc., is adjusted according to the cycle number n W .

[0155] For example, in the example shown in Figure 17 , when the cycle number n W is 1, in steps S103 and S104, the verification operation corresponding to the state S1 is performed. In the verification operation corresponding to the state S1, for example, the bit line BL connected to the write memory cell MC corresponding to the state S1 is charged, and a verification voltage V S is supplied to the selected word line WL VFYS1 .

[0156] In addition, when the cycle number n W is 2, in steps S103 and S104, the verification operations corresponding to the states S1 and S2 are sequentially performed. In the verification operation corresponding to the state S2, for example, the bit line BL connected to the write memory cell MC corresponding to the state S2 is charged, and a verification voltage V S is supplied to the selected word line WL VFYS2 .

[0157] In addition, when the cycle number n WWhen it is 3, in steps S103 and S104, verification actions corresponding to the states S1 to S3 are sequentially executed. In the verification action corresponding to state S3, for example, the bit line BL connected to the write memory cell MC corresponding to state S3 is charged, and the select word line WL S is supplied with the verification voltage V VFYS3 .

[0158] In step S105( Figure 13 ), the result of the verification action is determined. For example, when it is determined that the number of memory cells MC that have reached the target threshold voltage is less than a certain number, it is determined that the verification has failed (FAIL), and the process proceeds to step S106. On the other hand, when it is determined that the number of memory cells MC that have reached the target threshold voltage is equal to or more than a certain number, it is determined that the verification has passed (PASS), and the process proceeds to step S108.

[0159] In step S106, it is determined whether the loop count n W has reached a specific number N W . If it has not reached, the process proceeds to step S107. If it has reached, the process proceeds to step S109.

[0160] In step S107, the loop count n W is incremented by 1, and the process proceeds to step S102. Also, in step S107, for example, a specific voltage ΔV is added to the programming voltage V PGM .

[0161] In step S108, the status data D ST indicating the normal end of the write sequence is stored in the status register STR( Figure 2 ), and the write sequence ends.

[0162] In step S109, the status data D ST indicating that the write sequence has not ended normally is stored in the status register STR( Figure 2 ), and the write sequence ends.

[0163] [Interruption and Restart of Write Sequence]

[0164] Next, with reference to Figures 18 to 20 , the interruption and restart of the write sequence of the semiconductor memory device will be described.

[0165] Figure 18 is a schematic waveform diagram for explaining the interruption and restart of the write sequence. Figure 18 The signal waveform shown represents the signal of the terminal RY / / BY( Figure 4 ) of the memory die MD.

[0166] In Figure 18In the example, at time t115 when the write operation is being performed, the controller die CD inputs command C21 to the memory die MD. Command C21 is a command that means to interrupt the write operation. The input of command C21 is performed in the same way as the input of command C01.

[0167] In addition, in Figure 18 the example, at the subsequent time t106, the write operation is interrupted, and the terminal RY / / BY of the memory die MD ( Figure 4 ) becomes the "H" state.

[0168] In addition, in Figure 18 the example, the subsequent read operation described with reference to Figure 10 and Figure 11 is performed.

[0169] In addition, in Figure 18 the example, at the subsequent time t117, the controller die CD inputs command C22 to the memory die MD. Command C22 is a command that means to restart the write operation. The input of command C22 is performed in the same way as the input of command C01.

[0170] In addition, in Figure 18 the example, the write operation is restarted at the subsequent time t118.

[0171] Next, with reference to Figure 19 and Figure 20 , the voltage etc. supplied to the select word line WL S when the write sequence is interrupted and restarted is explained. In addition, Figure 19 and Figure 20 explain Figure 13 the number of cycles n W is 8, and as shown in Figure 17 , an example of performing 6 verification operations is given.

[0172] First, for comparison, with reference to Figure 19 , an example where the write sequence is not interrupted is explained.

[0173] In Figure 19 the example shown, the programming operation starts at time t131. That is, a programming voltage V S is supplied to the select word line WL PGM . In addition, the states of the signal lines HLL, XXL, STB ( Figure 6 ) become "L, L, L".

[0174] In addition, at time t132, the programming operation ends. That is, a ground voltage V S is supplied to the select word line WL SS . In addition, the signal lines HLL, XXL, STB (Figure 6 ) becomes "L, L, L".

[0175] In addition, at time t133, the verification operation corresponding to state S3 starts. That is, a verification voltage V is supplied to the selected word line WL S . In addition, the states of the signal lines HLL, XXL, STB( VFYS3 ) become "H, L, L". Figure 6 ) becomes "H, L, L".

[0176] In addition, at time t134, the states of the signal lines HLL, XXL, STB( Figure 6 ) become "L, H, L".

[0177] In addition, at time t135, the states of the signal lines HLL, XXL, STB( Figure 6 ) become "L, L, H".

[0178] In addition, at time t136, the verification operation corresponding to state S3 ends, and the verification operation corresponding to state S4 starts. That is, a verification voltage V is supplied to the selected word line WL S . In addition, the states of the signal lines HLL, XXL, STB( VFYS4 ) become "H, L, L". Figure 6 ) become "H, L, L".

[0179] In addition, at time t137, the states of the signal lines HLL, XXL, STB( Figure 6 ) become "L, H, L".

[0180] In addition, at time t138, the states of the signal lines HLL, XXL, STB( Figure 6 ) become "L, L, H".

[0181] In addition, at time t139, the verification operation corresponding to state S4 ends, and the verification operation corresponding to state S5 starts. That is, a verification voltage V is supplied to the selected word line WL S . In addition, the states of the signal lines HLL, XXL, STB( VFYS5 ) become "H, L, L". Figure 6 ) become "H, L, L".

[0182] In addition, at time t140, the states of the signal lines HLL, XXL, STB( Figure 6 ) become "L, H, L".

[0183] In addition, at time t141, the states of the signal lines HLL, XXL, STB( Figure 6 ) become "L, L, H".

[0184] In addition, at time t142, the verification operation corresponding to state S5 ends, and the verification operation corresponding to state S6 starts. That is, a verification voltage V is supplied to the selected word line WL S Supply the verification voltage V VFYS6 . In addition, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "H, L, L".

[0185] In addition, at time t143, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "L, H, L".

[0186] In addition, at time t144, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "L, L, H".

[0187] In addition, at time t145, the verification operation corresponding to state S6 ends, and the verification operation corresponding to state S7 starts. That is, a verification voltage V is supplied to the selected word line WL S Supply the verification voltage V VFYS7 . In addition, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "H, L, L".

[0188] In addition, at time t146, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "L, H, L".

[0189] In addition, at time t147, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "L, L, H".

[0190] In addition, at time t148, the verification operation corresponding to state S7 ends, and the verification operation corresponding to state S8 starts. That is, a verification voltage V is supplied to the selected word line WL S Supply the verification voltage V VFYS8 . In addition, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "H, L, L".

[0191] In addition, at time t149, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "L, H, L".

[0192] In addition, at time t150, the states of the signal lines HLL, XXL, and STB( Figure 6 ) become "L, L, H".

[0193] In addition, at time t151, the verification operation corresponding to state S8 ends. That is, for the selected word line WL SSupply ground voltage V SS . In addition, the states of signal lines HLL, XXL, and STB ( Figure 6 ) become "L, L, L".

[0194] Next, with reference to Figure 20 , an example of interrupting and restarting a write sequence will be described. In the semiconductor memory device of the present embodiment, when the write sequence is interrupted after the k-th (k is a natural number less than m) verification operation in the write sequence is completed and before the (k + 1)-th verification operation is completed, after the write sequence is restarted, a virtual verification operation corresponding to the k-th verification operation is executed, and then, the operations after the (k + 1)-th verification operation are executed. In addition, Figure 17 and Figure 20 show an example where k = 4. In Figure 17 , the verification operation corresponding to the confirmation flag corresponds to the verification operation that has been executed, and the verification operation corresponding to the circle corresponds to the verification operation before execution. In addition, in the example of Figure 17 , the number of loop times n W is 8, and the state where k = 4 corresponds to the state where 4 verification operations corresponding to states S3 to S6 have been executed and 2 verification operations corresponding to states S7 and S8 have not been executed.

[0195] In addition, the virtual verification operation can be performed in the same manner as the verification operation. However, in the virtual verification operation, the data indicating whether the selected memory cell MC is in the on state or the off state may not be latched into the latch circuit. In addition, in the virtual verification operation, a voltage may or may not be supplied to the bit line BL. In addition, in the virtual verification operation, the sense amplifier module SAM may be operated in the same form as the verification operation, or a part or all of the sense amplifier module SAM may not be operated.

[0196] In the example shown in Figure 20 , from time t131 to time t144, the write sequence is executed in the same manner as the example shown in Figure 19 .

[0197] In addition, at time t245, the verification operation corresponding to state S6 is completed, and the write sequence is interrupted. That is, the selected word line WL S is supplied with the ground voltage V SS . In addition, the states of signal lines HLL, XXL, and STB ( Figure 6 ) become "L, L, L".

[0198] In addition, at time t242, the write sequence is restarted, and the virtual verification operation corresponding to state S6 is started. That is, the selected word line WL supplied with the ground voltage V SS ​S Supply verification voltage V VFYS6 . Further, the states of signal lines HLL, XXL, and STB ( Figure 6 ) become "H, L, L".

[0199] Further, at time t243, the states of signal lines HLL, XXL, and STB ( Figure 6 ) become "L, H, L".

[0200] Further, at time t244, the states of signal lines HLL, XXL, and STB ( Figure 6 ) become "L, L, H".

[0201] Thereafter, the virtual verification operation corresponding to state S6 ends, and an operation corresponding to after time t145 of the write sequence is executed.

[0202] [First Comparative Example]

[0203] Next, with reference to Figure 21 , the interruption and restart of the write sequence of the semiconductor memory device of the comparative example will be described.

[0204] In the semiconductor memory device of the first comparative example, when the write sequence is interrupted after the k-th verification operation of the write sequence ends and before the (k + 1)-th verification operation ends, after the write sequence restarts, virtual verification operations corresponding to the 1st to k-th verification operations are sequentially executed, and thereafter, an operation after the (k + 1)-th verification operation is executed. Further, in Figure 21 , an example where k = 4 is shown.

[0205] Figure 21 In the example shown, from time t131 to time t144, the write sequence is executed in the same manner as the example shown in Figure 19 .

[0206] Further, at time t245, the verification operation corresponding to state S6 ends, and the write sequence is interrupted. That is, a ground voltage V is supplied to the selected word line WL S . SS . Further, the states of signal lines HLL, XXL, and STB ( Figure 6 ) become "L, L, L".

[0207] Further, the write sequence restarts at time t233. Further, from time t233 to time t145, virtual verification operations corresponding to states S3 to S6 are executed.

[0208] Thereafter, an operation corresponding to after time t145 of the write sequence is executed.

[0209] [Second Comparative Example]

[0210] Next, with reference to Figure 22 , the interruption and restart of the write sequence of the semiconductor memory device of the comparative example will be described.

[0211] In the semiconductor memory device of the second comparative example, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after the write sequence is restarted, the virtual verification operation is not executed, and the operations after the (k + 1)-th verification operation are executed immediately after the write sequence is restarted. In addition, Figure 22 shows an example where k = 4.

[0212] In Figure 22 In the example shown, from time t131 to time t144, the write sequence is executed in the same manner as in the example shown in Figure 19 .

[0213] In addition, at time t245, the verification operation corresponding to state S6 is completed and the write sequence is interrupted. That is, a ground voltage V S is supplied to the selected word line WL SS . In addition, the states of the signal lines HLL, XXL, STB( Figure 6 ) become "L, L, L".

[0214] In addition, at time t145, the write sequence is restarted, and the operations corresponding to after time t145 of the write sequence are executed.

[0215] [Effect of the First Embodiment]

[0216] As described above, in the semiconductor memory device of the first comparative example, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after the write sequence is restarted, the virtual verification operations corresponding to the first to k-th verification operations are executed, and thereafter, the operations after the (k + 1)-th verification operation are executed.

[0217] In this method, the time from restarting the write sequence to the (k + 1)-th verification operation ( Figure 21 the time from time t233 to time t145 in

[0218] Therefore, as described above, in the semiconductor memory device of the second comparative example, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after the write sequence is restarted, the virtual verification operation is not executed, and the operations after the (k + 1)-th verification operation are executed immediately after the write sequence is restarted.

[0219] In this method, since the (k + 1)-th verification operation starts immediately after the write sequence restarts, high-speed operation of the write sequence can be achieved.

[0220] However, in this method, compared with the method of the first comparative example, there is a case where the reliability of the verification operation executed immediately after the write sequence restarts decreases. It is considered that this is due to the following phenomenon.

[0221] That is, as the semiconductor memory device becomes more highly integrated, the film thickness of the conductive layer 110 that functions as the word line WL becomes smaller, and the conductive layer 110 becomes more highly resistive. In addition, the distance between the conductive layers 110 in the Z direction becomes shorter, and the capacitance in the conductive layer 110 becomes larger. As a result, the time constant in the conductive layer 110 becomes larger, and the time required for the voltage of the entire word line WL to reach the voltage supplied to the word line WL becomes longer.

[0222] When performing the verification operation in the above state, for example, it is also possible to consider supplying a voltage to the word line WL until the voltage of the entire word line WL is saturated, and obtaining data indicating whether the memory cell MC is in an on state or an off state in the above state. However, in this method, the time required for the verification operation is prolonged, which may hinder the high-speed operation of the write sequence. Therefore, in order to achieve high-speed operation of the write sequence, for example, it is considered to obtain the above data before the voltage of the entire word line WL is saturated.

[0223] Here, in the first comparative example, whether the write sequence is interrupted or not, immediately before the (k + 1)-th verification operation, a verification voltage V S is supplied to the selected word line WL VFYS6 , and in the (k + 1)-th verification operation, a verification voltage V S is supplied to the selected word line WL VFYS7 . Therefore, it can be considered that the voltage of the selected word line WL S in the (k + 1)-th verification operation is of the same magnitude regardless of whether the write sequence is interrupted.

[0224] On the other hand, in the second comparative example, when the write sequence is interrupted, immediately before the (k + 1)-th verification operation, a ground voltage V S is supplied to the selected word line WL SS , and in the (k + 1)-th verification operation, a verification voltage V S is supplied to the selected word line WL VFYS7 . Therefore, it is considered that the voltage of the selected word line WL S in the (k + 1)-th verification operation when the write sequence is interrupted is lower than the voltage of the selected word line WL S in the (k + 1)-th verification operation when the write sequence is not interrupted.

[0225] Here, as described above, in the semiconductor memory device of the first embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, a virtual verification operation corresponding to the k-th verification operation is executed, and then, the operations after the (k + 1)-th verification operation are executed.

[0226] In this method, the time from restarting the write sequence to the (k + 1)-th verification operation ( Figure 20 the time from time t242 to time t145 in

[0227] is shorter than that in the first comparative example. S In addition, in this method, immediately before the (k + 1)-th verification operation, a verification voltage V VFYS6 is supplied to the selected word line WL S and a verification voltage V VFYS7 is supplied to the selected word line WL S in the (k + 1)-th verification operation. Therefore, it is considered that the voltage of the selected word line WL

[0228] in the (k + 1)-th verification operation is of the same magnitude regardless of whether the write sequence is interrupted.

[0229] [Second Embodiment]

[0230] Next, with reference to Figure 23 , the semiconductor memory device of the second embodiment will be described. The semiconductor memory device of the second embodiment is basically configured in the same manner as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the second embodiment, the operations executed after interrupting and then restarting the write sequence are different from those of the semiconductor memory device of the first embodiment.

[0231] In the semiconductor memory device of the second embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, virtual verification operations corresponding to the (k - 1)-th and k-th verification operations are sequentially executed, and then, the operations after the (k + 1)-th verification operation are executed. In addition, Figure 23 shows an example where k = 4.

[0232] Figure 23 In the example shown in Figure 20 , the write sequence and the read operation are executed in substantially the same manner as the operations described with reference to

[0233] However, in Figure 23In the example shown, the write sequence is restarted not at time t242 but at time t239.

[0234] In addition, from the time t239 when the write sequence is restarted to the time t145 when the verification operation corresponding to state S7 starts, the dummy verification operations corresponding to state S5 and state S6 are sequentially executed.

[0235] [Third Embodiment]

[0236] Next, with reference to Figure 24 , a semiconductor memory device according to the third embodiment will be described. The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the third embodiment, the operations performed after the write sequence is interrupted and then restarted are different from those of the semiconductor memory device according to the first embodiment.

[0237] In the semiconductor memory device according to the third embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence ends and before the (k + 1)-th verification operation ends, after restarting the write sequence, two dummy verification operations corresponding to the k-th verification operation are executed, and then the operations after the (k + 1)-th verification operation are executed. In addition, Figure 24 shows an example where k = 4.

[0238] Figure 24 In the example shown, the write sequence and the read operation are basically executed in the same manner as the operations described with reference to Figure 20 .

[0239] However, in Figure 24 the example shown, the write sequence is restarted not at time t242 but at time t239.

[0240] In addition, from the time t239 when the write sequence is restarted to the time t145 when the verification operation corresponding to state S7 starts, two dummy verification operations corresponding to state S6 are executed.

[0241] [Fourth Embodiment]

[0242] Next, with reference to Figure 25 , a semiconductor memory device according to the fourth embodiment will be described. The semiconductor memory device according to the fourth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the fourth embodiment, the operations performed after the write sequence is interrupted and then restarted are different from those of the semiconductor memory device according to the first embodiment.

[0243] In the semiconductor memory device according to the fourth embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, virtual verification operations corresponding to the (k + 1)-th and k-th verification operations are sequentially executed, and then, operations after the (k + 1)-th verification operation are executed. In addition, Figure 25 shows an example where k = 4.

[0244] Figure 25 In the example shown, the write sequence and the read operation are basically executed in the same manner as the operations described with reference to Figure 20 However, in the example shown in

[0245] the write sequence is restarted not at time t242 but at time t239. Figure 25 In addition, from the time t239 when the write sequence is restarted to the time t145 when the verification operation corresponding to state S7 starts, virtual verification operations corresponding to state S7 and state S6 are sequentially executed.

[0246] In addition, from the time t239 when the write sequence is restarted to the time t145 when the verification operation corresponding to state S7 starts, virtual verification operations corresponding to state S7 and state S6 are sequentially executed.

[0247] [Fifth Embodiment]

[0248] Next, with reference to Figure 26 , the semiconductor memory device according to the fifth embodiment will be described. The semiconductor memory device according to the fifth embodiment has basically the same configuration as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the fifth embodiment, the operations executed after the write sequence is interrupted and then restarted are different from those of the semiconductor memory device according to the first embodiment.

[0249] In the semiconductor memory device according to the fifth embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, a virtual verification operation corresponding to the (k + 1)-th verification operation is executed, and then, operations after the (k + 1)-th verification operation are executed. In addition, Figure 26 shows an example where k = 4.

[0250] Figure 26 In the example shown, the write sequence and the read operation are basically executed in the same manner as the operations described with reference to Figure 20 However, in the example shown in

[0251] from the time t242 when the write sequence is restarted to the time t145 when the verification operation corresponding to state S7 starts, a virtual verification operation corresponding to state S7 is executed. Figure 26 In the example shown, from the time t242 when the write sequence is restarted to the time t145 when the verification operation corresponding to state S7 starts, a virtual verification operation corresponding to state S7 is executed.

[0252] [Sixth Embodiment]

[0253] Next, with reference to Figure 27 , a semiconductor memory device according to the sixth embodiment will be described. The semiconductor memory device according to the sixth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the sixth embodiment, the operations performed after interrupting and then restarting the write sequence are different from those of the semiconductor memory device according to the first embodiment.

[0254] In the semiconductor memory device according to the sixth embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence and before the (k + 1)-th verification operation is completed, after restarting the write sequence, a dummy verification operation is performed in which a voltage higher than the verification voltage V corresponding to the (k + 1)-th verification operation is supplied to the selected word line WL S . Then, a dummy verification operation corresponding to the (k + 1)-th verification operation is performed, and thereafter, the operations after the (k + 1)-th verification operation are performed. Additionally, VFYS7 shows an example where k = 4. Figure 27 In the example shown in

[0255] Figure 27 , the write sequence and the read operation are basically performed in the same manner as the operations described with reference to Figure 20 .

[0256] However, in the example shown in Figure 27 , the write sequence is restarted not at time t242 but at time t239.

[0257] Additionally, from the time t239 when the write sequence is restarted to the time t145 when the verification operation corresponding to state S7 starts, the two dummy verification operations are sequentially performed. Further, in the example of Figure 27 , from time t239 to time t242, a verification voltage V corresponding to state S8 is supplied to the selected word line WL S . VFYS8

[0258] [Seventh Embodiment]

[0259] Next, with reference to Figure 28 , a semiconductor memory device according to the seventh embodiment will be described. The semiconductor memory device according to the seventh embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the seventh embodiment, the operations performed after interrupting and then restarting the write sequence are different from those of the semiconductor memory device according to the first embodiment.

[0260] In the semiconductor memory device according to the seventh embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, a virtual verification operation for supplying a voltage larger than the verification voltage V corresponding to the (k + 1)-th verification operation to the selected word line WL is performed, and then, the operations after the (k + 1)-th verification operation are performed. In addition, S an example in which k = 4 is shown. VFYS7 In the example shown in Figure 28 the write sequence and the read operation are basically performed in the same manner as the operations described with reference to

[0261] Figure 28 However, in the example shown in Figure 20 the virtual verification operation is performed from the time t242 when the write sequence is restarted to the time t145 when the verification operation corresponding to the state S7 is started. In addition, in the example shown in

[0262] the verification voltage V corresponding to the state S8 is supplied to the selected word line WL from the time t242 to the time t145. Figure 28 Figure 28 S VFYS8

[0263] [Eighth Embodiment]

[0264] Next, with reference to Figures 29 to 31 the semiconductor memory device according to the eighth embodiment will be described. The semiconductor memory device according to the eighth embodiment has basically the same configuration as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the eighth embodiment, the execution order of the verification operations is different from that of the semiconductor memory device according to the first embodiment.

[0265] For example, in the first embodiment, as described with reference to Figure 17 Figure 19 etc., when the number of cycles n W is 8, the verification operation corresponding to the state S3 is performed at the time t133 to the time t136, the verification operation corresponding to the state S4 is performed at the time t136 to the time t139, and so on. Similarly, the verification operations corresponding to the states S5, S6, S7, and S8 are sequentially performed at the time t139 to the time t151. That is, when multiple verification operations are performed in each write cycle, the verification operations are performed in the order from the verification operation corresponding to the low threshold voltage state to the verification operation corresponding to the high threshold voltage state.

[0266] On the other hand, in the eighth embodiment, as exemplified in Figure 29 Figure 30 when the number of cycles n​​​​​​W When it is 8, from time t333 to time t336, the verification operation corresponding to state S8 is executed, and from time t336 to time t339, the verification operation corresponding to state S7 is executed. Similarly hereinafter, from time t339 to time t351, the verification operations corresponding to states S6, S5, S4, and S3 are sequentially executed. That is, when the verification operation is executed multiple times in each write cycle, the verification operations are executed in the order from the verification operation corresponding to the high threshold voltage state to the verification operation corresponding to the low threshold voltage state.

[0267] In addition, in the eighth embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence ends and before the (k + 1)-th verification operation ends, similar to the first embodiment, after the write sequence restarts, the virtual verification operation corresponding to the k-th verification operation is executed, and thereafter, the operations after the (k + 1)-th verification operation are executed.

[0268] In Figure 31 the example shown, from time t131 to time t344, the write sequence is executed in the same manner as Figure 30 the example shown.

[0269] In addition, at time t445, the verification operation corresponding to state S5 ends and the write sequence is interrupted. That is, a ground voltage V S is supplied to the selected word line WL SS . In addition, the states of the signal lines HLL, XXL, and STB ( Figure 6 ) become "L, L, L".

[0270] In addition, at time t442, the write sequence restarts and the virtual verification operation corresponding to state S5 starts. That is, a verification voltage V SS is supplied to the selected word line WL S to which the ground voltage V VFYS5 is supplied. In addition, the states of the signal lines HLL, XXL, and STB ( Figure 6 ) become "H, L, L".

[0271] In addition, at time t443, the states of the signal lines HLL, XXL, and STB ( Figure 6 ) become "L, H, L".

[0272] In addition, at time t444, the states of the signal lines HLL, XXL, and STB ( Figure 6 ) become "L, L, H".

[0273] Thereafter, the virtual verification operation corresponding to state S5 ends, and the operations after time t345 of the write sequence are executed.

[0274] In addition, in the above example, similar to the first embodiment, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, a virtual verification operation corresponding to the k-th verification operation is executed, and then, the operations after the (k + 1)-th verification operation are executed. However, this functional method is merely an illustration, and the specific form can be appropriately adjusted.

[0275] For example, similar to the second embodiment ( Figure 23 ), when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, virtual verification operations corresponding to the (k - 1)-th and k-th verification operations are sequentially executed.

[0276] In addition, for example, similar to the third embodiment ( Figure 24 ), when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, two virtual verification operations corresponding to the k-th verification operation are executed.

[0277] In addition, for example, similar to the fourth embodiment ( Figure 25 ), when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, virtual verification operations corresponding to the (k + 1)-th and k-th verification operations are sequentially executed.

[0278] In addition, for example, similar to the fifth embodiment ( Figure 26 ), when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, after restarting the write sequence, a virtual verification operation corresponding to the (k + 1)-th verification operation is executed.

[0279] [Other Embodiments]

[0280] As described above, the semiconductor memory devices of the first to eighth embodiments have been described. However, the semiconductor memory devices of the above embodiments are merely illustrations, and the specific configuration, operation, etc. can be appropriately adjusted.

[0281] For example, in the first to eighth embodiments, when the write sequence is interrupted after the k-th verification operation of the write sequence is completed and before the (k + 1)-th verification operation is completed, before starting the (k + 1)-th verification operation after restarting the write sequence, a verification voltage V S corresponding to states S1 to S15 is supplied to the select word line WL VFYS1 ~ verification voltage VVFYS15 any one of the voltages. However, this method is merely illustrative, and the specific method can be appropriately adjusted. For example, it can be considered to supply a voltage to the selection word line WL at this time S is a voltage above the verification voltage corresponding to the first verification operation. Additionally, for example, it can be considered to set the voltage supplied to the selection word line WL at this time S to a voltage above the verification voltage corresponding to the k-th verification operation. Thus, the voltage of the selection word line WL can be adjusted more appropriately S voltage. Additionally, it can be considered that the voltage supplied to the selection word line WL at this time S is at least less than the programming voltage V PGM voltage.

[0282] Additionally, for example, in the first to eighth embodiments, it has been shown that the execution time of the verification operation is the same as the execution time of the dummy verification operation, and the number of dummy verification operations executed after restarting the write sequence is less than that of the first comparative example ( Figure 21 ). However, this form is merely illustrative, and the specific form can be appropriately adjusted. For example, the execution time of the dummy verification operation can be made shorter than the execution time of the verification operation. Thus, further speeding up of the write sequence can be achieved.

[0283] Additionally, for example, as described above, in the dummy verification operation, a voltage can be supplied to the bit line BL or not. Additionally, when a voltage is supplied to the bit line BL, which bit line BL to supply the voltage to can be appropriately adjusted. For example, in the above example, for the memory cell MC determined to reach the target threshold voltage in the verification operation, the data in the plurality of latch circuits DL in the sense amplifier unit SAU corresponding to the memory cell MC is updated to a value indicating write prohibition. In this case, it is considered that the number of bit lines BL supplied with a voltage in the dummy verification operation is less than the number of bit lines BL supplied with a voltage in the verification operation.

[0284] However, this form is merely illustrative, and the specific method can be appropriately adjusted. For example, for the memory cell MC determined to reach the target threshold voltage in the verification operation, the verification path flag can be latched individually in the sense amplifier unit SAU corresponding to the memory cell MC, and the 4-bit data corresponding to the memory cell MC can be maintained. Additionally, the number of bit lines BL supplied with a voltage in the dummy verification operation can be set to the same number as the number of bit lines BL supplied with a voltage in the verification operation.

[0285] [Others]

[0286] Several embodiments of the present invention have been described, but the embodiments are merely presented as examples and are not intended to limit the scope of the invention. The new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. The embodiments or their variations are included within the scope or gist of the invention, and at the same time, are included within the scope of the invention described in the claims and equivalents thereof.

[0287] [Description of Symbols]

[0288] MC storage unit

[0289] WL word line

[0290] BL bit line.

Claims

1. A semiconductor memory device includes: a memory transistor, and a word line connected to a gate electrode of the memory transistor, and is configured to execute a write sequence for performing a plurality of write cycles on the memory transistor, the write cycle includes a programming operation for supplying a programming voltage to the word line, and at least one verification operation for supplying a verification voltage to the word line, during a period from the start to the end of the write sequence, when the write sequence is not interrupted, in the nth (n is a natural number) write cycle, one programming operation is executed, and m (m is a natural number of 2 or more) verification operations are executed, when the write sequence is interrupted after the kth (k is a natural number less than m) verification operation and before the (k + 1)th verification operation in the nth write cycle of the write sequence, before starting the (k + 1)th verification operation after restarting the write sequence, a verification voltage corresponding to the first verification operation or a voltage greater than it is supplied to the word line, the time from restarting the write sequence to starting the (k + 1)th verification operation is shorter than the time from the start of the first verification operation to the end of the kth verification operation in the nth write cycle.

2. The semiconductor memory device according to claim 1, wherein m is a natural number of 3 or more, k is a natural number of 2 or more, before starting the (k + 1)th verification operation after restarting the write sequence, a first verification voltage is supplied to the word line, the first verification voltage is a verification voltage corresponding to any one of the kth to mth verification operations in the nth write cycle of the write sequence.

3. The semiconductor memory device according to claim 2, wherein m is a natural number of 4 or more, k is a natural number of 3 or more, before supplying the first verification voltage to the word line after restarting the write sequence, a second verification voltage is supplied to the word line, the second verification voltage is a verification voltage corresponding to any one of the (k - 1)th to mth verification operations in the nth write cycle of the write sequence.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein m is a natural number of 3 or more, k is a natural number of 2 or more, before starting the (k + 1)th verification operation after restarting the write sequence, a verification voltage corresponding to the kth verification operation in the nth write cycle of the write sequence or a voltage greater than it is supplied to the word line.

5. The semiconductor memory device according to any one of claims 1 to 3, includes: a bit line electrically connected to the memory transistor; a sense transistor having a gate electrode electrically connected to the bit line; and a first transistor electrically connected to the sense transistor; and at a first time of the verification operation, the voltage supplied to the gate electrode of the first transistor rises, and at a second time later than it, the voltage supplied to the gate electrode of the first transistor drops, After restarting the writing sequence and before starting the (k + 1)-th verification operation, at the third moment, the voltage supplied to the gate electrode of the first transistor rises, and at the fourth moment, which is later than that, the voltage supplied to the gate electrode of the first transistor drops.

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