Chip packaging structure

Abstract

The present application provides a chip packaging structure. The chip packaging structure includes: a packaging substrate, on the first surface of which a driving chip is electrically connected; a stress dispersion layer, disposed on the first surface and located on the outer periphery of the driving chip, and in a direction perpendicular to the first surface, the thickness of the stress dispersion layer is greater than or equal to the thickness of the driving chip; a stress buffer layer, covering the stress dispersion layer and wrapping the driving chip; and a semiconductor chip group, disposed on the stress buffer layer and electrically connected to the first surface. By providing the above stress dispersion layer, the present application can be used to disperse the downward stress generated by the semiconductor chip group due to external force application during the packaging process, thereby effectively avoiding the damage of the bottom chip in the semiconductor chip group caused by stress concentration in the area corresponding to the edge of the driving chip in the stress buffer layer in the prior art, and further reducing the risk of short circuit caused by chip failure in the semiconductor chip group, and improving the performance of the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a chip packaging structure. Background Art

[0002] In the prior art, the main function of a flash memory is to maintain the stored information for a long time without power supply. It has the advantages of high integration, fast access speed, easy erasure and rewriting, etc., and thus has been widely used in electronic products. In order to further improve the bit density of the flash memory and reduce the bit cost at the same time, a three-dimensional NAND flash memory has been further proposed.

[0003] Packaging is an important step in the manufacturing process of 3D NAND memories. At present, the chip packaging structure usually electrically connects a chipset to a packaging substrate through wires and fixes the chipset by a packaging shell. However, the chips in the prior art are prone to short-circuit problems after packaging. Summary of the Invention

[0004] The main purpose of this application is to provide a chip packaging structure to solve the problem that the chips in the prior art are prone to short-circuit after packaging.

[0005] To achieve the above object, according to one aspect of this application, there is provided a chip packaging structure, including: a packaging substrate, on the first surface of which a driving chip is electrically connected; a stress dispersion layer, disposed on the first surface and located on the outer periphery of the driving chip, and in the direction perpendicular to the first surface, the thickness of the stress dispersion layer is greater than or equal to the thickness of the driving chip; a stress buffer layer, covering the stress dispersion layer and wrapping the driving chip; and a semiconductor chipset, disposed on the stress buffer layer and electrically connected to the first surface.

[0006] Further, the difference in Young's modulus between the driving chip and the stress dispersion layer is Y1, and the difference in Young's modulus between the driving chip and the stress buffer layer is Y2, where Y1 < Y2.

[0007] Further, the material forming the stress dispersion layer includes silicon dioxide and / or silicon.

[0008] Further, the material forming the stress buffer layer includes epoxy resin and / or silicon dioxide composite.

[0009] Further, the stress dispersion layer includes a plurality of sub-dispersion parts, each sub-dispersion part is located on at least one side of the driving chip, and adjacent sub-dispersion parts are connected and surround the stress dispersion layer.

[0010] Further, each sub-dispersion part is located on a different side of the driving chip, and the projected areas of the sub-dispersion parts located on the opposite sides on the first surface are equal.

[0011] Further, the stress dispersion layer includes a first sub-dispersion part and a second sub-dispersion part. The two ends of the first sub-dispersion part are correspondingly connected to the two ends of the second sub-dispersion part one by one, and the projected areas of the first sub-dispersion part and the second sub-dispersion part on the first surface are equal.

[0012] Further, the first sub-dispersion part and the second sub-dispersion part are of a U-shaped structure or an L-shaped structure.

[0013] Further, the semiconductor chip group includes a plurality of semiconductor chips sequentially stacked in a direction away from the stress buffer layer. The projected area of the first semiconductor chip in the direction away from the stress buffer layer on the first surface is S1, and the projected area of the stress buffer layer on the first surface is S2, and S1 ≤ S2.

[0014] Further, the chip packaging structure further includes: a packaging housing, mounted on the packaging substrate, and the semiconductor chip group is packaged inside the packaging housing.

[0015] Applying the technical solution of the present application provides a chip packaging structure, including a packaging substrate, a stress dispersion layer, a stress buffer layer, and a semiconductor chip group. Among them, a driving chip is electrically connected to the first surface of the packaging substrate. The stress dispersion layer is disposed on the first surface and is located on the outer periphery of the driving chip, and in a direction perpendicular to the first surface, the thickness of the stress dispersion layer is greater than or equal to the thickness of the driving chip. The stress buffer layer covers the stress dispersion layer and wraps the driving chip, and the semiconductor chip group is disposed on the stress buffer layer and is electrically connected to the first surface. By providing the above stress dispersion layer, the present application can be used to disperse the downward stress generated by the semiconductor chip group due to external force application during the packaging process, thereby effectively avoiding the damage of the bottom chip in the semiconductor chip group caused by stress concentration in the area corresponding to the edge of the driving chip in the stress buffer layer in the prior art, and further reducing the risk of short circuit caused by chip failure in the semiconductor chip group, and improving the performance of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The specification drawings forming a part of the present application are used to provide a further understanding of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0017] Figure 1 shows a schematic cross-sectional structure diagram of a chip packaging structure provided by an embodiment of the present application;

[0018] Figure 2 shows a schematic cross-sectional structure diagram of a stress dispersion layer provided by an embodiment of the present application;

[0019] Figure 3 Shows a schematic cross-sectional structure diagram of a stress dispersion layer provided by another embodiment of the present application;

[0020] Figure 4 Shows a schematic cross-sectional structure diagram of a stress dispersion layer provided by still another embodiment of the present application;

[0021] Figure 5 Shows a schematic cross-sectional structure diagram of a chip package structure with a package housing provided by an embodiment of the present application.

[0022] Wherein, the above-mentioned drawings include the following reference numerals:

[0023] 10. Package substrate; 20. Driving chip; 30. Stress dispersion layer; 310. Sub-dispersion part; 311. First sub-dispersion part; 312. Second sub-dispersion part; 40. Stress buffer layer; 50. Semiconductor chip group; 510. Semiconductor chip; 520. Second bonding layer; 60. First bonding layer; 70. Electrical contact; 80. Package housing; 90. Protective layer. Detailed embodiments

[0024] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present application described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0027] As introduced in the background art, in the prior art, the chip packaging structure usually electrically connects a chipset to a packaging substrate through wires, and encapsulates and fixes the chipset through a packaging shell. However, the chips are prone to short - circuit problems after packaging.

[0028] The inventors of the present application studied the above problems and proposed a chip packaging structure, as Figure 1 shown, including: a packaging substrate 10, a driving chip 20 is electrically connected to the first surface of the packaging substrate 10; a stress - dispersion layer 30, disposed on the first surface and located on the outer periphery of the driving chip 20, and in a direction perpendicular to the first surface, the thickness of the stress - dispersion layer 30 is greater than or equal to the thickness of the driving chip 20; a stress - buffer layer 40, covering the stress - dispersion layer 30 and wrapping the driving chip 20; a semiconductor chipset 50, disposed on the stress - buffer layer 40 and electrically connected to the first surface.

[0029] Through research, the present application found that the short - circuit problem of chips in the prior art after packaging is due to directly wrapping the driving chip with a stress - buffer layer, which causes uneven distribution of the external force generated during the packaging of the semiconductor chipset in the stress - buffer layer, and is prone to concentration at positions corresponding to the edges of the driving chip, resulting in easy cracking of the semiconductor chips at the bottom of the semiconductor chipset, and further leading to failure. By providing the above - mentioned stress - dispersion layer 30, the present application can be used to disperse the downward stress generated by the semiconductor chipset 50 due to the application of external force during the packaging process, thus effectively avoiding the stress concentration in the region corresponding to the edge of the driving chip 20 in the stress - buffer layer 40 in the prior art, which causes damage to the bottom chips in the semiconductor chipset 50, and further reducing the risk of chip failure and short - circuit in the semiconductor chipset 50, and improving the performance of the chip packaging structure.

[0030] The material of the above - mentioned packaging substrate 10 can be a conventional insulating material. For example, an epoxy - based laminated substrate, a resin - based bismaleimide triazine (BT) substrate, etc. The packaging substrate 10 can also have rigidity to provide mechanical support for the driving chip 20 and the semiconductor chipset 50.

[0031] The above - mentioned packaging substrate 10 can also provide electrical support for the driving chip 20 and the semiconductor chipset 50. Exemplarily, the above - mentioned packaging substrate 10 has multiple layers of metal traces, with insulating materials located therebetween. The metal traces on different layers can be connected through vias. The material of the above - mentioned metal traces can include but is not limited to metal wiring materials such as gold, silver, copper, and aluminum.

[0032] The above - mentioned driving chip 20 can be fixedly disposed on the packaging substrate 10 through a first bonding layer 60 and electrically connected to the packaging substrate 10 through wires, as Figure 1As shown. Exemplarily, the above-mentioned first bonding layer 60 is a Die Attach Film (DAF).

[0033] In an optional embodiment of the present application, the difference in Young's modulus between the driving chip 20 and the stress dispersion layer 30 is Y1, and the difference in Young's modulus between the driving chip 20 and the stress buffer layer 40 is Y2, where Y1 < Y2. By adopting the above embodiment, by adding the stress dispersion layer 30, and compared with the stress buffer layer 40, the stress dispersion layer 30 has a Young's modulus closer to that of the driving chip 20, so that the stress generated during the encapsulation of the semiconductor chip group 50 can be more evenly distributed in the stress buffer layer 40, thereby reducing the risk of the semiconductor chip 510 cracking. It should be noted that the mechanical properties of the added stress buffer layer 40 in the present application that are close to those of the driving chip 20 are not limited to Young's modulus, and may also have other mechanical properties close to those of the driving chip 20, such as Poisson's ratio, which is not specifically limited in the present application.

[0034] In the above embodiment of the present application, since the control chip in the prior art is usually a silicon-based chip, in order to make the stress dispersion layer 30 have a Young's modulus closer to that of the driving chip 20, preferably, the material forming the stress dispersion layer 30 includes silicon dioxide and / or silicon. However, it is not limited to the above preferred types, and those skilled in the art can reasonably select materials that meet the above Young's modulus according to the prior art.

[0035] In the above embodiment of the present application, the material forming the stress buffer layer 40 may include epoxy resin and / or silica composite. The above materials usually have fluidity, so that during the molding process, they can not only better cover the driving chip 20 and the stress dispersion layer 30, but also better fill the gaps between the driving chip 20 and the stress dispersion layer 30, thereby improving the uniformity of the stress generated during the encapsulation of the semiconductor chip group 50 distributed in the stress buffer layer 40. It should be noted that the material forming the stress buffer layer 40 in the present application is not limited to the above types, and may also be other insulating materials with fluidity in the prior art, which is not specifically limited in the present application.

[0036] In order to facilitate the stress dispersion layer 30 to be disposed on the outer periphery of the driving chip 20 on the encapsulation substrate 10, the stress dispersion layer 30 may include a plurality of sub-dispersion portions 310, each sub-dispersion portion 310 is located on at least one side of the driving chip 20, and adjacent sub-dispersion portions 310 are connected and surround the stress dispersion layer 30, such as Figures 2 to 4 As shown.

[0037] In an optional embodiment of the present application, each sub-dispersion portion 310 is respectively located on different sides of the driving chip 20, and the projected areas of the sub-dispersion portions 310 located on the opposite sides on the first surface are equal, such asFigure 2 As shown. By adopting the above implementation manner, the strip-shaped sub-dispersion parts 310 can be respectively arranged on different sides of the driving chip 20, so that the sub-dispersion parts 310 are adjacent to each other to form the stress dispersion layer 30, reducing the difficulty of the manufacturing process of the stress dispersion layer 30. At the same time, it is convenient to arrange the stress dispersion layer 30 around the driving chip 20 on the packaging substrate 10.

[0038] In another optional implementation manner of the present application, the stress dispersion layer 30 includes a first sub-dispersion part 311 and a second sub-dispersion part 312. The two ends of the first sub-dispersion part 311 are correspondingly connected to the two ends of the second sub-dispersion part 312 one by one, and the projected areas of the first sub-dispersion part 311 and the second sub-dispersion part 312 on the first surface are equal. The above-mentioned first sub-dispersion part 311 and the above-mentioned second sub-dispersion part 312 can be U-shaped structures, as Figure 3 shown; the above-mentioned first sub-dispersion part 311 and the above-mentioned second sub-dispersion part 312 can also be L-shaped structures, as Figure 4 shown. By adopting the above implementation manner, the difficulty of the manufacturing process of the stress dispersion layer 30 can also be reduced. At the same time, it is convenient to arrange the stress dispersion layer 30 around the driving chip 20 on the packaging substrate 10.

[0039] In an optional implementation manner of the present application, the semiconductor chip group 50 includes a plurality of semiconductor chips 510 sequentially stacked in a direction away from the stress buffer layer 40. The projected area of the first semiconductor chip 510 in the direction away from the stress buffer layer 40 on the first surface is S1, and the projected area of the stress buffer layer 40 on the first surface is S2, and S1≤S2. By adopting the above implementation manner, it can be ensured that the contact area between the semiconductor chip 510 at the bottom layer of the semiconductor chip group 50 and the stress buffer layer 40 is less than or equal to the upper surface area of the stress buffer layer 40, so that the stress generated during the packaging of the semiconductor chip group 50 is more evenly distributed in the stress buffer layer 40.

[0040] The above-mentioned semiconductor chip group 50 of the present application includes a plurality of semiconductor chips 510. The adjacent semiconductor chips 510 are stacked through a second bonding layer 520, and the adjacent semiconductor chips 510 are connected by wires. The above-mentioned semiconductor chips 510 can form a multi-layer stepped structure or be arranged in a staggered manner, as Figure 1 shown. Exemplarily, the above-mentioned semiconductor chip 510 is a memory chip with a memory structure for providing a storage function. It should be noted that the above-mentioned semiconductor chip 510 of the present application can also be a chip with other functions, such as including a chip for providing a computing function and / or a processing function.

[0041] The material of the above-mentioned connection lines may include, but is not limited to, metal connection line materials such as gold, silver, copper, and aluminum. Exemplarily, the above-mentioned second bonding layer 520 is a Die Attach Film (DAF).

[0042] The number of the above-mentioned semiconductor chip sets 50 may be one or more. Exemplarily, only one semiconductor chip set 50 is encapsulated on the above-mentioned packaging substrate 10, as Figure 1 shown. In another example, multiple semiconductor chip sets are encapsulated on the packaging substrate, and the multiple semiconductor chip sets are arranged and distributed on the packaging substrate. It should be noted that the number of chips, the stacking structure, and the circuit structure within the chips in different semiconductor chip sets 50 may be the same or different.

[0043] The above-mentioned chip packaging structure of the present application may further include a packaging housing 80 for improving the reliability of the device, as Figure 5 shown. The packaging housing 80 is mounted on the packaging substrate 10, and the semiconductor chip set 50 is encapsulated inside the packaging housing 80. The material of the above-mentioned packaging housing 80 may be conventional materials used for semiconductor packaging in the prior art, including but not limited to Epoxy Molding Compound (EMC).

[0044] Optionally, the above-mentioned chip packaging structure of the present application may further include a protective layer 90 disposed outside the semiconductor chip set 50, as Figure 5 shown. The above-mentioned protective layer 90 may be made of a material with certain shock absorption ability, such as silica gel, resin, or other adhesive materials. By disposing the protective layer 90 outside the semiconductor chip set 50 and the corresponding connection lines, on the one hand, it can prevent the chips or connection lines from being damaged during the manufacture of the packaging housing 80, and on the other hand, it can absorb part of the deformation and external force when the packaging housing 80 is externally squeezed. Exemplarily, the above-mentioned protective layer 90 includes Epoxy Molding Compound (EMC).

[0045] The above-mentioned chip packaging structure of the present application may further include electrical contacts 70, and each semiconductor chip 510 in the semiconductor chip set 50 is electrically connected to the electrical contacts 70 through connection lines. The above-mentioned electrical contacts 70 may be disposed at any position exposed outside the packaging housing 80. Exemplarily, the above-mentioned electrical contacts 70 are solder balls, and the solder balls are disposed on the side of the packaging substrate 10 away from the semiconductor chip set 50, as Figure 1 and Figure 5 shown.

[0046] Exemplarily, the method for encapsulating the semiconductor chip set 50 to obtain the above-mentioned chip packaging structure includes:

[0047] Provided is a packaged substrate 10, on one side of which there is a driving chip 20 fixedly arranged by DAF glue, and the driving chip 20 is electrically connected to the packaged substrate 10 through a wire;

[0048] A silicon dioxide layer is arranged on the outer periphery of the driving chip 20 on the packaged substrate 10 to serve as a stress dispersion layer 30, and the height of the stress dispersion layer 30 is not lower than the height of the driving chip 20;

[0049] An epoxy resin with fluidity is coated on the surface of the packaged substrate 10 so that the epoxy resin wraps the driving chip 20 and covers the stress dispersion layer 30, and after the epoxy resin is cured, a stress buffer layer 40 is obtained;

[0050] A plurality of semiconductor chips 510 are sequentially arranged on the stress buffer layer 40 through DAF glue to form a semiconductor chip group 50, and each semiconductor chip 510 is electrically connected to the packaged substrate 10 through a wire;

[0051] Silicone is used to form a protective layer 90 on the packaged substrate 10 to wrap the semiconductor chip group 50, and a packaging shell 80 is formed outside the protective layer 90 so that the semiconductor chip group 50 is packaged inside the packaging shell 80;

[0052] An electrical contact 70 is formed on the side of the packaged substrate 10 away from the driving chip 20 through solder, so that the semiconductor chip group 50 is electrically connected to the electrical contact 70 on the packaged substrate 10 through a wire.

[0053] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0054] By providing the above stress dispersion layer, the present application can be used to disperse the downward stress generated by the semiconductor chip group during the packaging process due to external force application, thereby effectively avoiding the damage of the bottom chips in the semiconductor chip group caused by stress concentration in the area corresponding to the edge of the driving chip in the stress buffer layer in the prior art, and further reducing the risk of short circuit caused by chip failure in the semiconductor chip group, and improving the performance of the chip packaging structure.

[0055] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that, Comprising: A packaging substrate, on the first surface of which a driving chip is electrically connected; A stress dispersion layer, disposed on the first surface and located on the outer periphery of the driving chip, and in a direction perpendicular to the first surface, the thickness of the stress dispersion layer is greater than or equal to the thickness of the driving chip; A stress buffer layer, covering the stress dispersion layer and wrapping the driving chip; The difference in Young's modulus between the driving chip and the stress dispersion layer is Y1, and the difference in Young's modulus between the driving chip and the stress buffer layer is Y2, where Y1 < Y2; A semiconductor chip group, disposed on the stress buffer layer and electrically connected to the first surface.

2. The chip packaging structure according to claim 1, wherein The material forming the stress dispersion layer includes silicon dioxide and / or silicon.

3. The chip package structure according to claim 1, wherein The material forming the stress buffer layer includes epoxy resin and / or silicon dioxide composite.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that The stress dispersion layer includes a plurality of sub-dispersion parts, each of the sub-dispersion parts is located on at least one side of the driving chip, and adjacent sub-dispersion parts are connected and surround the stress dispersion layer.

5. The chip packaging structure according to claim 4, wherein, Each of the sub-dispersion parts is located on different sides of the driving chip, and the projected areas of the sub-dispersion parts on the opposite sides on the first surface are equal.

6. The chip packaging structure according to claim 4, wherein, The stress dispersion layer includes a first sub-dispersion part and a second sub-dispersion part, the two ends of the first sub-dispersion part are connected to the two ends of the second sub-dispersion part in a one-to-one correspondence, and the projected areas of the first sub-dispersion part and the second sub-dispersion part on the first surface are equal.

7. The chip packaging structure according to claim 6, characterized in that, The first sub-dispersion part and the second sub-dispersion part are of U-shaped structure or L-shaped structure.

8. The chip packaging structure according to any one of claims 1 to 3, characterized in that, The semiconductor chip group includes a plurality of semiconductor chips sequentially stacked in a direction away from the stress buffer layer. The projected area of the first semiconductor chip in the direction away from the stress buffer layer on the first surface is S1, and the projected area of the stress buffer layer on the first surface is S2, where S1 ≤ S2.

9. The chip packaging structure according to any one of claims 1 to 3, characterized in that, The chip packaging structure further includes: A packaging housing, mounted on the packaging substrate, and the semiconductor chip group is packaged inside the packaging housing.

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