Package and manufacturing method

Abstract

In an embodiment, the interposer has: a first side; a first integrated circuit device attached to the first side of the interposer by a first set of conductive connectors, each of the first set of conductive connectors having a first height; a first die package attached to the first side of the interposer by a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height and the second conductive connector having a third height, the third height being different from the second height; a first pseudo-conductive connector located between the first side of the interposer and the first die package; an underfill disposed under the first integrated circuit device and the first die package; and a sealant disposed around the first integrated circuit device and the first die package. Embodiments of the present application relate to packages and manufacturing methods.

Description

Technical Field

[0001] Embodiments of the present application relate to a package and a manufacturing method thereof. Background Art

[0002] Due to the continuous increase in the integration level of many electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid development. For the most part, this improvement in integration density comes from the continuous reduction of the minimum component size, which enables more components to be integrated into a given area. With the growing demand for shrinking electronic devices, there has emerged a need for smaller and more innovative semiconductor die packaging technologies. An example of such a packaging system is the Package on Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. The PoP technology can generally produce semiconductor devices with enhanced functions and small occupied areas on a printed circuit board (PCB). Summary of the Invention

[0003] Some embodiments of the present application provide a package, including: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer through a first group of conductive connectors, each of the first group of conductive connectors having a first height; a first die package attached to the first side of the interposer through a second group of conductive connectors, the second group of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different from the second height; a first pseudo-conductive connector located between the first side of the interposer and the first die package; an underfill disposed under the first integrated circuit device and the first die package; and a sealant disposed around the first integrated circuit device and the first die package.

[0004] Some other embodiments of the present application provide a method of manufacturing a package, including: forming a first redistribution structure on a first side of an interposer, the first redistribution structure including metal lines and vias in a dielectric layer, the first redistribution structure including active pads and dummy pads on a first surface of the first redistribution structure, the active pads being electrically coupled to the metal lines and vias, the dummy pads being electrically isolated from the metal lines and vias; forming active connectors on the active pads; forming dummy connectors on the dummy pads; attaching a first integrated circuit device to a first subset of the active connectors; attaching a second integrated circuit device to a second subset of the active connectors, the dummy connectors being located between the interposer and the second integrated circuit device; forming an underfill on the first side of the interposer, the underfill having a first portion under the first integrated circuit device and a second portion under the second integrated circuit device; and sealing the first integrated circuit device and the second integrated circuit device with a sealant.

[0005] Some further embodiments of the present application provide a method of manufacturing a package, including: attaching a first integrated circuit device to a first side of an interposer through a first set of connectors having the same height; attaching a die package to the first side of the interposer through a second set of connectors having multiple heights, a first set of dummy connectors being located between the interposer and the die package, the first set of dummy connectors being electrically isolated from the die package and the first integrated circuit device; forming an underfill on the first side of the interposer under the first integrated circuit device and the die package; and sealing the first integrated circuit device and the die package with a sealant. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] As will be best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0007] Figure 1 A cross-sectional view of an integrated circuit die according to some embodiments is shown.

[0008] Figures 2 to 6 A cross-sectional view of an intermediate step during a process for forming a die package according to some embodiments is shown.

[0009] Figures 7 to 12B and Figures 19 to 26 are a cross-sectional view and a top view of an intermediate step during a process for forming a semiconductor device according to some embodiments.

[0010] Figures 13 to 18D Cross-sectional and top views of the configuration of active and pseudo-connectors according to some embodiments.

[0011] Figure 27 and Figure 28 Cross-sectional view of the configuration of active and pseudo-connectors according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming the first component above or on the second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numerals and / or letters in various examples. This repetition is only for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Except for the orientation shown in the figures, the spatial relationship terms are intended to include different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0014] According to some embodiments, an integrated circuit device is attached to a wafer using connectors with variable heights to address any warping of the integrated circuit die and / or the wafer. In some embodiments, the connectors are micro-bumps formed by a plating method. In those embodiments, during the formation process, the pattern density of the micro-bumps in a specific region is adjusted by inserting pseudo micro-bumps on one or both of the integrated circuit device and the wafer to achieve variable-height micro-bumps. For example, if it is desired that the micro-bumps in the first region have a shorter height than those in the second region, the pattern density of the micro-bumps in the first region will be increased by inserting pseudo micro-bumps in the first region. This formation of variable-height connectors can prevent cold welding or connector damage, and thus can improve the reliability and yield of the device.

[0015] Embodiments will now be described with respect to a system-on-chip (“SoC”). However, the embodiments are not intended to be limited and may be employed in a variety of embodiments. In some embodiments, a die package is formed that includes a plurality of dies bonded together. For example, the dies may be bonded together using hybrid bonding. The die package may include through-substrate vias and / or through-dielectric vias. In addition to another semiconductor device such as a memory die, an I / O die, etc., a package incorporating the die package may also be formed. The die package and the semiconductor device may include conductive components of different sizes for electrical connection to a single redistribution structure. By forming a die package that bonds the dies and by incorporating the die package and the semiconductor device in the same package, the size of the package may be reduced and the high-speed operation of the package may be improved.

[0016] Figure 1 is a cross-sectional view of an integrated circuit device 50 according to some embodiments. The integrated circuit device 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. The integrated circuit device 50 may be formed in a wafer that may include different device regions that are divided in subsequent steps to form a plurality of integrated circuit devices 50. The integrated circuit device 50 includes a substrate 52 and an interconnect structure 54.

[0017] The substrate 52 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layer semiconductor substrate, etc. The semiconductor material of the substrate 52 may be: silicon; germanium; a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates such as multi-layer or gradient substrates may also be used. The substrate 52 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, etc. may be formed in and / or on the active surface (e.g., the upward-facing surface) of the substrate 52.

[0018] An interconnect structure 54 having one or more dielectric layers and corresponding metallization patterns is formed on the active surface of a substrate 52. The dielectric layer can be an intermetal dielectric (IMD) layer. For example, the IMD layer can be formed of a low-k dielectric material such as undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon carbide material, its compounds, its composites, its combinations, etc. by any suitable method known in the art such as spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), etc. The metallization pattern in the dielectric layer can transfer electrical signals between devices by using vias and / or traces, for example, and can also include various electrical devices such as capacitors, resistors, inductors, etc. Various devices and metallization patterns can be interconnected to perform one or more functions. The functions can include memory structures, processing structures, sensors, amplifiers, power distribution, input / output circuits, etc. Additionally, die connectors such as conductive pillars or contact pads are formed in and / or on the interconnect structure 54 to provide external electrical connections to the circuits and devices. Those of ordinary skill in the art will understand that the above examples are provided for illustrative purposes. Other circuits can be appropriately used for a given application.

[0019] In some embodiments, the integrated circuit device 50 is a stacked device including a plurality of substrates 52. For example, the integrated circuit device 50 can be a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. including a plurality of memory dies. In such embodiments, the integrated circuit device 50 includes a plurality of substrates 52 interconnected by vias. Each substrate 52 can have (or can not have) a separate interconnect structure 54.

[0020] Figures 2 to 6 A cross-sectional view showing the formation of a die package 100 (see Figure 6 ) according to some embodiments is shown. In some embodiments, the die package 100 is, for example, a system-on-chip (SoC) package, a system-on-integrated circuit (SoIC) package, etc. Now referring to Figure 1 , a semiconductor device 102 is shown. The semiconductor device 102 can be a semiconductor device such as a memory device, a logic device, a power device, a combination of these devices, etc., which is designed to work in cooperation with other devices within the die package 100. However, any suitable function can be utilized.

[0021] In an embodiment, the semiconductor device 102 includes a first substrate 104, a first active device (not shown separately), a first metallization layer 106, a bonding layer 108, and a bonding metal 110 within the bonding layer 108. The first substrate 104 may include doped or undoped bulk silicon, or the active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of semiconductor material such as silicon, germanium, silicon-germanium, SOI, silicon-germanium-on-insulator (SGOI), or a combination thereof. Other substrates that may be used include multi-layer substrates, gradient substrates, or hybrid-orientation substrates.

[0022] The first active device, which includes various active devices, and passive devices such as transistors, capacitors, resistors, inductors, etc. can be used to generate the desired structural and functional requirements for the design of the semiconductor device 102. The first active device can be formed using any suitable method within or on the first substrate 104.

[0023] The first metallization layer 106 is formed over the first substrate 104 and the first active device and is designed to connect the various active devices to form a functional circuit. In an embodiment, the first metallization layer 106 is formed of alternating layers of a dielectric material and a conductive material and can be formed by any suitable process such as deposition, damascene, dual damascene, etc. In an embodiment, there may be four metallization layers separated from the first substrate 104 by at least one interlayer dielectric layer (ILD), but the exact number of the first metallization layer 106 depends on the design.

[0024] The bonding layer 108 is deposited over the first metallization layer 106. The bonding layer 108 can be used for fusion bonding (also known as oxide-oxide bonding or dielectric-dielectric bonding). According to some embodiments, the bonding layer 108 is formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, etc. Any suitable method such as CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), etc. can be used to deposit the bonding layer 108. The bonding layer 108 can be planarized, for example, using a chemical mechanical polishing (CMP) process.

[0025] The bonding metal 110 can be formed within the bonding layer 108. In an embodiment, the bonding metal 110 can be formed by first applying a photoresist over the top surface of the bonding layer 108 and patterning it to first form an opening within the bonding layer 108. Then the patterned photoresist is used as an etch mask to etch the bonding layer 108 to form the opening. The bonding layer 108 can be etched using a suitable process such as dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE), etc.), wet etching, etc. The bonding metal 110 can also be referred to as a "bonding pad" or a "metal pad".

[0026] Once the opening is formed, the bonding metal 110 is filled in the opening within the bonding layer 108. In an embodiment, the bonding metal 110 may include a seed layer and a metal plate. The seed layer may be deposited blanketly over the top surface of the bonding layer 108 and may include, for example, a copper layer. Depending on the desired material, processes such as sputtering, evaporation, or plasma enhanced chemical vapor deposition (PECVD) may be used to deposit the seed layer. The plate-like metal may be deposited over the seed layer by a plating process such as electroplating or electroless plating. The plate-like metal may include copper, copper alloy, etc. In some embodiments, the plate-like metal may be a filling material. A barrier layer (not shown separately) may be deposited blanketly over the top surface of the bonding layer 108 before the seed layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0027] Still referring to Figure 2 , the semiconductor device 102 may include through-substrate vias (TSVs) 112 that extend through the substrate 104 to facilitate electrical signal transmission. In other embodiments, the semiconductor device 102 does not include TSVs 112. In an embodiment, the TSVs 112 may be formed by first forming through-substrate via (TSV) openings in the substrate 104. The TSV openings may be formed by applying and patterning a photoresist (not shown) to expose an area of the substrate 104 and then etching the exposed portion of the substrate 104 to a desired depth. The TSV openings may be formed to extend at least further into the substrate 104 than the active devices formed within and / or on the substrate 104 and may extend to a depth greater than the final desired height of the substrate 104. Thus, although the depth depends on the overall design, the depth from the active devices on the substrate 104 may be between about 20 μm and about 200 μm, such as about 50 μm from the active devices on the substrate 104.

[0028] Once the TSV openings are formed in the substrate 104, the TSV openings may be lined with a liner (not shown). The liner may be, for example, an oxide formed of tetraethyl orthosilicate (TEOS) or silicon nitride, but any suitable dielectric material may alternatively be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, but other suitable processes such as physical vapor deposition or thermal processes may optionally be used. Additionally, the liner may be formed to a thickness between about 0.1 μm and about 5 μm, such as about 1 μm.

[0029] Once a liner is formed along the sidewalls and bottom of the TSV opening, a barrier layer (not shown separately) can be formed, and the remaining portion of the TSV opening can be filled with a first conductive material to form the TSV 112. The first conductive material can include copper, but other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, etc. can be optionally utilized. The first conductive material can be formed by electroplating copper onto a seed layer (not shown), filling and overfilling the TSV opening. Once the TSV opening is filled, the excess liner, barrier layer, seed layer, and first conductive material outside the TSV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process can be used. In some embodiments, the TSV 112 can be formed to have a width between about 0.5 μm and 10 μm, such as about 2 μm. In some embodiments, the TSV 112 can be formed to have a pitch between about 1 μm and 40 μm, such as about 10 μm. However, any appropriate dimensions can be utilized.

[0030] In some embodiments, multiple semiconductor devices 102 are formed on the same substrate 104 and then diced to form individual semiconductor devices 102. A sawing process, a laser process, an etching process, etc. or a combination thereof can be used to dice the semiconductor devices 102. In some embodiments, after dicing, the thickness of the semiconductor device 102 can be between about 30 μm and about 200 μm, such as about 100 μm. In some embodiments, the semiconductor device 102 can have an area between about 1 mm 2 and about 850 mm 2 such as about 30 mm 2 . The semiconductor device 102 can have other dimensions than these. In some embodiments, known good dies (KGD) can be separated from defective dies before or after dicing.

[0031] Figure 3 The semiconductor device 102 is shown bonded to the first wafer 120. In some embodiments, the first wafer 120 can be an application processor wafer, where semiconductor dies (not shown separately) are formed to work in cooperation with the semiconductor device 102. However, any appropriate function can also be utilized, such as additional memory or other functions. The first wafer 120 can include a second substrate 122 and second active devices (not shown separately in Figure 3 ). In an embodiment, the second substrate 122 and the second active devices can be similar to the first substrate 104 and the first active devices described above with respect to Figure 2 . For example, the second substrate 122 can be a semiconductor substrate, and the second active devices can be active and passive devices formed on or in the second substrate 122. However, any suitable substrate and active devices can be utilized.

[0032] The first wafer 120 may further include a second metallization layer 124, a second bonding layer 126, and a second bonding metal 128. In one embodiment, the second metallization layer 124, the second bonding layer 126, and the second bonding metal 128 may be similar to the first metallization layer 106, the first bonding layer 108, and the first bonding metal 110. For example, the second bonding metal 128 may be a metal placed in the second bonding layer 126 after the second bonding layer 126 has been formed.

[0033] In another embodiment, the second bonding metal 128 and the second bonding layer 126 are formed as part of the second metallization layer 124. For example, the second bonding layer 126 may be formed as an initial dielectric layer over the active devices, while the second bonding metal 128 may be formed within the second bonding layer 126 and adjacent to the active devices, but is referred to as a "via0" configuration. However, any suitable arrangement for the second bonding metal 128 and the second bonding layer 126 may be utilized.

[0034] After forming the second bonding layer 126 and the second bonding metal 128, the semiconductor device 102 may be bonded to the first wafer 120. In some embodiments, the semiconductor device 102 may be bonded to the first wafer 120 using, for example, a hybrid bonding process, where the first bonding layer 108 is bonded to the second bonding layer 126, and the first bonding metal 110 is bonded to the second bonding metal 128. In some embodiments, the top surfaces of the first wafer 120 and the semiconductor device 102 may first be activated using, for example, dry processing, wet processing, plasma processing, exposure to inert gases, exposure to H2, exposure to N2, exposure to O2, etc. or a combination thereof. However, any suitable activation process may be used.

[0035] After the activation process, the first wafer 120 and the semiconductor device 102 can be cleaned using, for example, a chemical rinse, and then the semiconductor device 102 is aligned and physically contacted with the first wafer 120. For example, the semiconductor device 102 can be placed on the first wafer 120 using a pick-and-place process. Then, the first wafer 120 and the semiconductor device 102 are subjected to a heat treatment and contact pressure to hybrid bond the first wafer 120 to the semiconductor device 102. For example, the pressure that the first wafer 120 and the semiconductor device 102 can be subjected to is about 200 kPa or less, and the temperature is between about 200 °C and about 400 °C to fuse the first bonding layer 108 and the second bonding layer 126. Then, the first wafer 120 and the semiconductor device 102 can be subjected to a temperature at or above the eutectic point of the materials of the first bonding metal 110 and the second bonding metal 128, for example, between about 150 °C and about 650 °C, to fuse the metal bonding pads. In this way, the fusion of the first wafer 120 and the semiconductor device 102 forms a hybrid bonding device. In some embodiments, the bonded die is baked, annealed, pressurized, or otherwise processed to strengthen or complete the bond.

[0036] Additionally, although the above description describes the second bonding metal 128 as being within the second metallization layer 124 and the first bonding metal 110 as being above the first metallization layer 106, this is merely exemplary and not restrictive. Rather, any suitable combination, including the first bonding metal 110 being within the first metallization layer 106 (e.g., within the via0 layer). In other embodiments, the first wafer 120 can be bonded to the semiconductor device 102 by direct surface bonding, metal-to-metal bonding, or another bonding process. The direct surface bonding process creates a dielectric-dielectric bond or a substrate-substrate bond by the steps of: a cleaning and / or surface activation process, subsequent application of pressure, heating, and / or other bonding process steps to the joined surfaces. In some embodiments, the first wafer 120 and the semiconductor device 102 are bonded by a metal-to-metal bonding achieved by fusing conductive elements. Any suitable bonding process can be utilized.

[0037] Figure 4 Thinning of the semiconductor device 102 is shown to expose the TSV 112. In an embodiment, the thinning of the semiconductor device 102 can be performed using a planarization process such as a chemical mechanical planarization (CMP) process, where an etchant and an abrasive are used with a polishing platen to react and abrade away the material until a flat surface is formed and the TSV 112 is exposed. However, any other suitable method of exposing the TSV 112 can also be utilized, such as a series of one or more etching processes.

[0038] Figure 5A through dielectric via (TDV) 130 is shown formed on the second bonding metal 128. In other embodiments, the TDV 130 is not formed. In an embodiment, the TDV 130 can be formed by first placing and patterning a photoresist ( Figure 5 not shown separately) above the second bonding metal 128 (or above a separately placed seed layer if desired). In an embodiment, the pattern formed in the photoresist is the pattern for the TDV 130. The TDV 130 can be formed on different sides of the semiconductor device 102. However, any suitable arrangement of the pattern for the TDV 130 can also be utilized. In some embodiments, the pitch of the TDV130 can be greater than the pitch of the TSV 112.

[0039] Once the photoresist is placed and patterned, the TDV 130 can be formed within the photoresist. In an embodiment, the TDV 130 includes one or more conductive materials such as copper, tungsten, other conductive metals, etc., and can be formed, for example, by electroplating, electroless plating, etc. After the conductive material of the TDV 130 has been formed, the photoresist can be removed using a suitable removal process such as a plasma ashing process or wet chemical stripping. In some embodiments, the TDV 130 can be formed to have a width between about 10 μm and about 200 μm, such as about 150 μm. Additionally, the TDV 130 can be formed to have a height between about 35 μm and about 250 μm, such as about 180 μm. However, any suitable dimensions can be utilized.

[0040] In some embodiments, after the TDV 130 is formed, the first substrate 104 of each semiconductor device 102 can be recessed. The first substrate 104 can be recessed using, for example, one or more etching processes such as a wet etching process or a dry etching process. However, any suitable method for recessing the first substrate 104 such that the TSV 112 extends away from the first substrate 104 can be used. In this way, the TSV 112 can protrude from the first substrate 104 of the die package 100 to facilitate external connection in subsequent processing steps.

[0041] Reference Figure 6 , a dielectric layer 132 is formed and a dicing process is performed to form separate die packages 100. Figure 6 Separate die packages 100 are shown in. After the first substrate 104 is recessed, a dielectric layer 132 can be formed above the semiconductor device 102 and the TDV 130. In some embodiments, the dielectric layer 132 can be a material such as a low temperature polyimide material, but any other suitable dielectric such as PBO, another polymer, resin, epoxy resin, etc. or a combination thereof can also be utilized. In some cases, the dielectric layer 132 can be cured.

[0042] After forming the dielectric layer 132, the first wafer 120 can be thinned, and then a dicing process can be performed to dice the individual die packages 100. In an embodiment, a planarization process such as a CMP process or a grinding process can be utilized to thin the back side of the first wafer 120. However, any suitable process for thinning the first wafer 120 can also be utilized, such as a combination of a series of one or more etching or polishing and etching.

[0043] In some embodiments, the dielectric layer 132 can be formed to cover the TDV 130 and the TSV 112, and can subsequently be recessed to expose the TDV 130 and the TSV 112. For example, a planarization process such as a CMP process or a grinding process or one or more etching processes such as a wet etching process or a dry etching process can be used to recess the dielectric layer 132. However, any suitable method for recessing the dielectric layer 132 can be used. In this way, the TDV 130 and the TSV 112 are exposed to facilitate external connection in subsequent processing steps.

[0044] In some embodiments, after forming the dielectric layer 132 (and after an optional recessing step), within process variations, the surfaces of the dielectric layer 132, the TDV 130, and the TSV 112 are coplanar. A sawing process, a laser process, an etching process, etc., or a combination thereof can be used to dice the first wafer 120.

[0045] Figures 7 to 12B and Figures 19 to 26 are a cross-sectional view and a top view of an intermediate step during a process for forming a semiconductor device according to some embodiments. Figures 13 to 18D are a cross-sectional view and a top view of configurations of active and dummy connectors according to various embodiments. In Figures 7 to 12A and Figures 19 - 25 a device package 200 is formed by bonding various integrated circuit devices 50 and die packages 100 to the front side of an interposer 170. In some embodiments, the device package 200 is a chip-on-wafer (CoW) package, but it should be understood that the embodiments can be applied to other three-dimensional integrated circuit (3DIC) packages. In Figure 25 a device package 400 is formed by mounting the device package 200 onto a package substrate. In an embodiment, the device package 400 is a chip-on-wafer-on-substrate package, but it should be understood that the embodiments can be applied to other 3DIC packages.

[0046] Figure 7FIG. 0 is a cross-sectional view of an interposer 170 according to some embodiments. Although only one interposer 170 is shown, it should be understood that the interposer 170 may be formed in a wafer having a plurality of device regions, each device region for forming an interposer 170. The interposer 170 includes a substrate 172, vias 174, and interconnect structures 176.

[0047] The substrate 172 may be a bulk semiconductor substrate, an SOI substrate, a multi-layer semiconductor substrate, etc. The semiconductor material of the substrate 172 may be: silicon; germanium; compound semiconductors including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multi-layer or gradient substrates may also be used. The substrate 172 may be doped or undoped. Active devices such as transistors may (or may not) be in and / or on the front surface (e.g., the upward-facing surface) of the substrate 172. Passive devices such as capacitors, resistors, diodes, etc. may (or may not) be in and / or on the front surface of the substrate 172.

[0048] The vias 174 are formed to extend from the front surface of the substrate 172 into the substrate 172. When the substrate 172 is a silicon substrate, the vias 174 are sometimes also referred to as substrate vias or through-silicon vias (TSVs). The vias 174 may be formed by, for example, forming grooves in the substrate 172 by etching, milling, laser techniques, combinations thereof, etc. A thin dielectric material may be formed in the grooves, for example, by using an oxidation technique. A thin barrier layer may be conformally deposited over the front side of the substrate 172 and in the openings by, for example, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The barrier layer may be formed of a nitride or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, etc. A conductive material may be deposited over the thin barrier layer and in the openings. The conductive material may be formed by an electroless plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of the conductive material are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and the barrier layer are removed from the front side of the substrate 172 by, for example, chemical mechanical polishing (CMP). Thus, the vias 174 may include a conductive material, and the thin barrier layer is between the conductive material and the substrate 172.

[0049] An interconnect structure 176 is formed over a front surface of a substrate 172 and is configured to electrically connect devices (if any) and / or vias 174 of the substrate 172 together and / or to an external device. The interconnect structure 176 may include one or more dielectric layers 178 and corresponding metallization patterns 180 located within the dielectric layers. The metallization patterns 180 may include vias and / or traces to interconnect any devices and / or vias 174 together and / or to an external device. The dielectric layers 178 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k dielectric materials such as PSG, BPSG, FSG, SiO x C y , spin-on glass, spin-on polymer, silicon carbide materials, their compounds, their composites, their combinations, etc. The dielectric layers 178 may be deposited by any suitable method such as spin coating, CVD, PECVD, HDP-CVD, etc. The metallization patterns 180 may be formed in the dielectric layers 178, for example, by depositing and patterning a photoresist material over the dielectric layer to expose portions of the dielectric layer that are to become the metallization patterns. An etching process such as an anisotropic dry etching process may be used to create trenches and / or openings in the dielectric layers 178 corresponding to the exposed portions of the dielectric layers 178. The trenches and / or openings may be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may be formed of one or more layers of TaN, Ta, TiN, Ti, CoW, etc. deposited by ALD, etc., and the conductive material may be formed of copper, aluminum, tungsten, silver, their combinations, etc., and may be deposited by CVD, PVD, etc. Any excess diffusion barrier layer and / or conductive material over the dielectric layers 178 may be removed, for example, by using CMP.

[0050] Figures 8 to 10 Shown in Figure 7 is a detailed view of a portion of forming an electrical connection on the interconnect 176. In Figure 8 , it is shown that the dielectric layer 178 extends and covers over the topmost metallization pattern 180. However, in some embodiments, the top surface of the dielectric layer 178 and the topmost metallization pattern 180 are coplanar within process variations. In Figure 8 , the metallization pattern 180A is electrically coupled to other metallization patterns in the interconnect structure and may subsequently be electrically coupled to an integrated circuit device 50 and / or a die package 100 (also referred to as an active metallization pattern 180A). The metallization pattern 180B is electrically isolated from other metallization patterns in the interconnect structure (also referred to as a dummy metallization pattern 180B) and will not subsequently be electrically coupled to the integrated circuit device 50 and / or the die package 100. In some embodiments, the topmost metallization pattern 180 (of which 180A and 180B shown are a part) may be referred to as a pad 180 or an under bump metallization (UBM) 180.

[0051] Although a single dummy pad 180B is shown, in some embodiments, more dummy pads 180B may be included as needed. For example, depending on the design of the interposer 170 and the overall package structure, a single interconnect structure 176 may include hundreds, thousands, or more dummy pads 180B. As discussed in more detail below, the dummy pads 180B are placed in specific regions / zones of the interconnect 176 to increase the pattern density of the pads 180, and conductive bumps 204 are formed in those specific regions / zones such that the difference in the pattern density of the pads 180 and the formation of the conductive bumps 204 change the formation rate of the conductive bumps 204 in those specific regions / zones. For example, the conductive bumps 204 may be formed by a plating process such as electroplating, and the pattern density of the pads 180 and the conductive bumps 204 affects and changes the plating rate. Specifically, the plating rate is slower in regions / zones with a higher pattern density of the pads 180 and the conductive bumps 204, and the plating rate is higher in regions / zones with a lower pattern density of the pads 180 and the conductive bumps 204. As further discussed below, this difference in plating rate can be used to adjust the height of the conductive bumps 204 in different regions / zones of the interposer 170 to address warping of the interposer 170 and / or the integrated circuit device 50 and die package 100 subsequently attached to the interposer 170.

[0052] In Figure 9 a photoresist material 182 is deposited and patterned on the interconnect structure 176 to expose portions of the dielectric layer 178, where the exposed dielectric layer 178 will be patterned using subsequent patterning processes. An etching process such as an anisotropic dry etching process may be used to create trenches and / or openings in the dielectric layer 178 to expose portions of the pads 180 corresponding to the exposed portions of the dielectric layer 178.

[0053] In Figure 10 an electrical connection including the conductive bumps 204 and conductive connectors 206 is formed on the exposed pads 180. The conductive bumps 204A and conductive connectors 206A (which may also be referred to as active conductive bumps 204A and active conductive connectors 206A) are electrically coupled to the active metallization pattern 180A and may subsequently be electrically coupled to the integrated circuit device 50 and / or die package 100. The conductive bumps 204B and conductive connectors 206B (which may also be referred to as dummy conductive bumps 204B and dummy conductive connectors 206B) are electrically coupled to the dummy metallization pattern 180B and are electrically isolated from other metallization patterns in the interconnect structure and will not subsequently be electrically coupled to the integrated circuit device 50 and / or die package 100.

[0054] The conductive bump 204 is formed of a conductive material such as copper, aluminum, gold, nickel, palladium, or combinations thereof, and can be formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The conductive bump 204 can be solderless and have substantially vertical sidewalls, and can be referred to as a pillar. The conductive bump 204 is electrically and physically connected to the interconnect structure 176. The active conductive connector 206A joins the conductive bump 204 to a connector on other devices (such as the subsequently joined devices 100 and 50) (see Figures 12A - 12B ). The pseudo-conductive connector 206B does not join the conductive bump 204 to any other device (see Figures 12A - 12B ). The conductive connector 206 can be formed of a conductive material such as solder and can be referred to as a solder cap. The conductive connector 206 can be formed by methods such as evaporation, electroplating, printing, solder transfer, solder ball placement, etc., by first forming a solder layer on the conductive bump 204. Once the solder layer is formed, a reflow process can be performed to shape the conductive connector 206 into a desired bump shape. The conductive bump 204 and the conductive connector 206 together form a microbump.

[0055] Figure 11 Shown Figure 7 in the structure where, as discussed in the detailed view of Figures 8 to 10 , the conductive bump 204 and the conductive connector 206 are formed on the pad 180.

[0056] In Figure 12A , a plurality of integrated circuit devices 50 and one or more die packages 100 are attached to the interposer 170. The plurality of integrated circuit devices 50 and one or more die packages 100 can be attached to the interconnect structure 176, for example, using a pick-and-place tool.

[0057] The various integrated circuit devices 50 can include a plurality of devices with different functions. The interconnect structures 54 and 176 are connected to physically and electrically connect the integrated circuit devices 50 and the interposer 170. Each of the integrated circuit devices 50 can have a single function (e.g., a logic device, a memory die, etc.) or can have multiple functions (e.g., an SoC). In an embodiment, the integrated circuit device 50 is a memory device such as an HBM module. The integrated circuit device 50 can also include a logic device such as a CPU.

[0058] The die package 100 (an exemplary die package 100 is shown in Figure 6 ) includes a plurality of devices. The TDV 130 and the vias 112 of the die package 100 are connected to the conductive connector 206 to physically and electrically connect the die package 100 and the interposer 170.

[0059] The height of the back surface of one or more die packages 100 from the interconnect structure 176 is H1, and the height of the back surface of the integrated circuit device 50 from the interconnect structure 176 is H2. The heights H1 and H2 may be the same or may be different. In some embodiments, the height H1 is in the range of about 50 μm to about 800 μm, and the height H2 is in the range of about 50 μm to about 800 μm.

[0060] In embodiments where the interposer 170 is formed in a wafer, multiple integrated circuit devices 50 and one or more die packages 100 may be attached in different device regions of the wafer, which will be diced in subsequent steps to form multiple device packages 200. Figure 12B is Figure 12A An exemplary top view of the structure of, showing regions 200A and 200B. Each of the regions 200A and 200B contains multiple devices 50 and a single die package 100. In some embodiments, such as Figure 12B In embodiments of, the integrated circuit devices 50 are symmetrically arranged near the die package 100. In some embodiments, the integrated circuit devices 50 are asymmetrically arranged near the die package 100. The asymmetric layout may allow the integrated circuit devices 50 to be located closer to the input / output (I / O) connection regions of the die package 100.

[0061] In the illustrated embodiment, multiple integrated circuit devices 50 and one or more die packages 100 are attached to the interconnect structure 176 through a connection including conductive bumps 202 (which may also be referred to as active conductive bumps 202), active conductive bumps 204A, and conductive connectors 206. The active conductive bumps 202 are electrically and physically connected to the interconnect structure 54, and the active conductive bumps 204A are electrically and physically connected to the interconnect structure 176. The conductive connectors 206 join the active conductive bumps 202 and 204A.

[0062] The dummy conductive bumps 204B and dummy conductive connectors 206B on the interconnect structure 176 are not connected to the multiple integrated circuit devices 50 or one or more die packages 100 joined to the interconnect structure. In the illustrated embodiment, no corresponding active conductive bumps 202 are joined to the dummy conductive bumps 204B and dummy conductive connectors 206B. In some embodiments, the multiple integrated circuit devices 50 and one or more die packages 100 may also include dummy conductive bumps 202, which may be joined to the dummy conductive bumps 204B and dummy conductive connectors 206B.

[0063] Figure 13 and Figure 14 Shows a simplified form of a portion of the package 300 before and after joining the die package 100 and the interposer 170. In Figure 13In [the figure], a portion of the die package 100 and the interposer 170 is shown before being joined together. As Figure 13 shown, the die package 100 is warped or bent such that the bonding surface of the active conductive connector 206A on the active conductive bump 202 formed on the die package 100 follows the curved profile 310A. In this example, the die package 100 is bent such that the edges extend higher than the central region (sometimes referred to as a smiling profile). In some embodiments, the die package is bent such that the edges extend lower than the central region (sometimes referred to as a frowning profile) (see, for example, Figure 17 ). If the bonding surface of the active conductive connector 206A on the active conductive bump 204A formed on the interposer 170 does not have a similar curved profile, the curved profile 310A of the bonding surface of the active conductive connector 206A on the active conductive bump 202 formed on the die package 100 may cause problems such as cold welding or connector damage.

[0064] As described above and discussed in more detail below, the pseudo-conductive bumps 204B are placed in specific zones / regions of the interposer 170 to increase the pattern density of the conductive bumps 204 in those specific zones / regions such that the difference in the pattern density of the conductive bumps 204 changes the formation rate of the conductive bumps 204 in those specific zones / regions. This difference in the formation rate can be used to adjust the height of the conductive bumps 204 in different zones / regions of the interposer 170 to address the warping of the interposer 170 and / or the integrated circuit device 50 and the die package 100 subsequently attached to the interposer 170. Thus, as Figure 13 shown, the bonding surface of the active conductive connector 206A on the active conductive bump 204A formed on the interposer 170 follows a curved profile 310B similar to the curved profile 310A of the die package 100. In Figure 13 the illustrated embodiment, the active conductive bumps 204A on the interposer 170 are formed to be shorter in the central region of the interposer 170 and become taller as they move away from the central region. For example, the outer active conductive bumps 204A may be formed to a height H3, the central active conductive bumps 204A may be formed to a height H5, and the active conductive bumps 204A between the outer and central bumps may be formed to a height H4. In some embodiments, the height H3 is greater than H4 and H5, the height H4 is greater than H5 and less than H3, and the height H5 is less than H4 and H5. In some other embodiments, the relationship of these heights may be reversed such that H5 is the largest and H3 is the smallest. In other embodiments, the height H4 may be the maximum height.

[0065] In some embodiments, the die package 100 can be bent at the lower surface of the die package 100 such that the lower surface at the edge of the die package 100 is higher than the lower surface of the central region of the die package 100 by a distance D1. In some embodiments, the distance D1 is in the range from 20 μm to 50 μm.

[0066] In Figure 14 , the die package 100 is bonded to the interposer 170, wherein the active conductive bumps 204A on the interposer 170 have varying heights to address warping and / or bending of the die package 100.

[0067] Figure 15 An exemplary layout of active and dummy conductive pads 180A and 180B (and the layout of active and dummy conductive bumps 204A and 204B) on a portion of the interposer 170 is shown. In the portion shown, the interposer 170 is divided into regions 402 and 404, where region 402 is the region where dummy pads 180B can be formed, and region 404 is the region where dummy pads 180B cannot be formed. In some embodiments, region 402 is separated from the active pads 180A by a distance D2. In some embodiments, the distance D2 is in the range from 15 μm to 50 μm. The distance D2 ensures that the dummy conductive bumps 204B do not interfere with the active conductive bumps 204A. Although, Figure 15 a checkerboard pattern of regions 402 and 404 is shown, other patterns, such as rows, columns, concentric circles, etc. of region 402 or combinations thereof, are within the scope of the present disclosure.

[0068] Figure 16A , Figure 16B , Figure 16C and Figure 16D are embodiments of the layout of region 200A or 200B (see Figure 12B ) to enable the active conductive bumps 204A to achieve Figure 13 and Figure 14 the smile bending profile 310B in Figure 16A . As Figures 16A - 16D shown, the layout configuration of the active and dummy pads 180A and 180B within the occupied area of the die package 100 is in multiple partitions or zones (labeled as partitions 1 - 3 in Figures 16A - 16D ) such that the configuration of the dummy pads 180B can be different in each different partition. In Figures 16A - 16DIn it, partition 1 is at the center of the occupied area of the die package 100, partition 2 is a ring surrounding area 1, and partition 3 is the remaining part of the occupied area of the die package 100 that is not in partition 1 or partition 2.

[0069] As described above, the pattern density of the active and dummy pads 180A and 180B affects the formation height of the active conductive bumps 204A, such that a larger pattern density of the active and dummy pads 180A and 180B results in shorter active conductive bumps 204A. To achieve Figure 13 and Figure 14 the smile bending profile 310B in, where the higher active conductive bumps 204A are towards the outer edge of the occupied area of the die package 100, while the shorter active conductive bumps 204A are in the central area of the occupied area of the die package 100. Therefore, in the central area of the occupied area of the die package 100, the pattern density of the active and dummy pads 180A and 180B needs to be greater. In this embodiment, the pattern density of the active and dummy pads 180A and 180B in partition 1 is greater than both partition 2 and 3, the pattern density of the active and dummy pads 180A and 180B in partition 3 is less than both partition 2 and 1, and the pattern density of the active and dummy pads 180A and 180B in partition 2 is between partition 2 and 1.

[0070] In Figure 16A it, the shape of the dummy pad 180B is circular and has different sizes in different partitions. For example, the dummy pad 180B is the largest in partition 1, smaller in partition 2, and the smallest (or non - existent) in partition 3. Figure 16B shows a configuration similar to Figure 16A except that the dummy pad 180B has a different shape and is square or rectangular.

[0071] In Figure 16C it, the shape of the dummy pad 180B is circular and has similar sizes in each partition, where different partitions have different numbers of dummy pads 180B in each area 402. For example, partition 1 has the most dummy pads 180B per area 402, partition 2 has fewer dummy pads 180B per area 402 than partition 1, and partition 3 has fewer dummy pads 180B per area 402 than partition 2 (possibly zero). Figure 16D shows a configuration similar to Figure 16C except that the dummy pad 180B has a different shape and is square or rectangular.

[0072] Although only four configurations with various sizes and shapes are shown, the present disclosure contemplates more sizes and shapes of the dummy pads 180B to achieve varying pattern density goals for partitions 1-3. Additionally, the occupied area of the die package 100 (or even the occupied area of the entire interposer 170) can be divided into more or fewer partitions, such as 2 partitions, 4 partitions, 5 partitions, or even more partitions.

[0073] Although the dummy pads, dummy bumps, and dummy connectors have been described as being only within the occupied area of the die package 100, in some embodiments, there are dummy pads, dummy bumps, and dummy connectors. For example, within the occupied area of the integrated circuit device 50 or outside the occupied areas of the integrated circuit device 50 and the die package 100, there can be dummy pads, dummy bumps, and dummy connectors.

[0074] In an embodiment where the dummy pads, dummy bumps, and dummy connectors are formed only within the occupied area of the die package 100, the conductive bumps 204 and 202 within the occupied area of the integrated circuit device 50 are formed to have the same height, while the conductive bumps 204 and / or 202 within the occupied area of the die package 100 are formed to have different heights.

[0075] Figure 17 A simplified form of a portion of the package 300 before bonding the die package 100 and the interposer 170 is shown. This embodiment is similar to Figure 13 and Figure 14 in the embodiments, except that this embodiment has frown bending profiles 312A and 312B. For example, in this embodiment, the taller active conductive bumps 204A are in the central region of the interposer 170, while the shorter active conductive bumps 204A are outside the central region. Details regarding this embodiment are similar to the details of the previously described embodiments and will not be elaborated herein.

[0076] Figure 18A 、 Figure 18B 、 Figure 18C and Figure 18D are embodiments of the layout of the region 200A or 200B (see Figure 12B ) to enable the active conductive bumps 204A to achieve the Figure 17 frown bending profile 312B in Figures 16A - 16B . This embodiment is similar to the embodiments in

[0077] except that this embodiment has frown bending profiles 312A and 312B. Details regarding this embodiment are similar to the details of the previously described embodiments and will not be elaborated herein. Figure 17the frowning bend profile 312B therein, where the taller active conductive bumps 204A are in the central region of the occupied area of the die package 100, while the shorter active conductive bumps 204A are outside the central region of the occupied area of the die package 100. Thus, outside the central region of the occupied area of the die package 100, a greater pattern density of the active and dummy pads 180A and 180B is required. In this embodiment, the pattern density of the active and dummy pads 180A and 180B in partition 1 is less than both partition 2 and partition 3, the pattern density of the active and dummy pads 180A and 180B in partition 3 is greater than both partition 2 and partition 1, and the pattern density of the active and dummy pads 180A and 180B in partition 2 is between partition 2 and partition 1.

[0078] In Figure 18A it, the dummy pad 180B is circular in shape and has different sizes in different partitions. For example, the dummy pad 180B is the largest in partition 3, smaller in partition 2, and the smallest (or non-existent) in partition 1. Figure 18B shows a configuration similar to Figure 18A except that the dummy pad 180B has a different shape and is square or rectangular.

[0079] In Figure 18C it, the dummy pad 180B is circular in shape and has similar sizes in each partition, where different partitions have different numbers of dummy pads 180B in each region 402. For example, partition 3 has the most dummy pads 180B per region 402, partition 2 has fewer dummy pads 180B per region 402 than partition 3, and partition 1 has fewer dummy pads 180B per region 402 than partition 2 (possibly zero). Figure 18D shows a configuration similar to Figure 16C except that the dummy pad 180B has a different shape and is square or rectangular.

[0080] The interposer 170 has connectors with variable heights, which can address the warping of the integrated circuit die and / or wafer. In some embodiments, the connectors are micro-bumps formed by a plating method. In those embodiments, during the formation process, the pattern density of the micro-bumps in a specific region is adjusted by inserting dummy micro-bumps on one or both of the integrated circuit device and the wafer to achieve micro-bumps with variable heights. For example, if it is desired that the micro-bump height in the first region is shorter than that in the second region, the pattern density of the micro-bumps in the first region will be increased by inserting dummy micro-bumps in the first region. This formation of variable height connectors can prevent cold welding or connector damage, thus improving the reliability and yield of the device.

[0081] In Figure 19In [description], a bottom-fill material 210 is dispensed between the integrated circuit device 50 and the die package 100 and the interconnect structure 176. The bottom-fill material 210 surrounds the active and conductive bumps 202A / B and 204A / B, and the active and pseudo-conductive connectors 206A / B. The bottom-fill material 210 has a chamfer that extends upward along the sides of the integrated circuit device 50 and the die package 100. The bottom-fill material 210 can be any acceptable material, such as a polymer, an epoxy resin, a molded underfill, etc. The bottom-fill material 210 can be formed by a capillary flow process. The bottom-fill 210 separates and isolates the pseudo-conductive bump 204B and the pseudo-conductive connector 206B from the die package 100.

[0082] In Figure 20 [description], a sealant 212 is formed on each component. The sealant 212 can be a molding compound, an epoxy resin, etc., and can be applied by compression molding, transfer molding, etc. The sealant 212 can be formed above the interconnect structure 176 such that the integrated circuit device 50, the die package 100, and the bottom-fill material 210 are buried or covered. Then the sealant 212 is cured. In some embodiments, the sealant 212 is thinned such that the top surfaces of the sealant 212, the integrated circuit device 50, and the die package 100 are flush.

[0083] In Figure 21 [description], the intermediate structure is flipped to prepare for processing the back side of the substrate 172. The intermediate structure can be placed on a carrier substrate 214 or other suitable support structure for subsequent processing. For example, the carrier substrate 214 can be attached to the sealant 212. The intermediate structure can be attached to the carrier substrate 214 through a release layer 216. The release layer 216 can be formed of a polymer-based material, and the release layer can be removed from the overlying structure together with the carrier substrate 214. In some embodiments, the carrier substrate 214 is a substrate such as a bulk semiconductor or a glass substrate, and can have any thickness, such as a thickness of about 300 mm. In some embodiments, the release layer 216 is an epoxy-based thermal release material such as a light-to-thermal conversion (LTHC) release coating that loses its adhesiveness when heated.

[0084] In Figure 22Therein, the substrate 172 is thinned to expose the vias 174. In some embodiments, the exposed surfaces of the substrate 172 and the vias 174 are flush. The exposure of the vias 174 can be achieved by a thinning process such as a grinding process, chemical mechanical polishing (CMP), or other acceptable removal processes. In some embodiments (not shown), a recessing process may be performed to recess the substrate 172 such that the vias 174 protrude from the back side of the substrate 172. The recessing process can be, for example, an appropriate etch-back process. An insulating layer can be formed on the back side of the substrate 172 that surrounds and protects the protruding portions of the vias 174.

[0085] In Figure 23 therein, a redistribution structure 220 is formed over the back side of the substrate 172. The redistribution structure 220 includes a dielectric layer 222, an UBM 224, and conductive bumps 226. The redistribution structure 220 is shown as an example. More or fewer dielectric layers and conductive layers can be formed in the redistribution structure 220. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0086] As an example of forming the redistribution structure 220, the dielectric layer 222 is deposited over the back side of the substrate 172 and the vias 174. In some embodiments, the dielectric layer 222 is formed of a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., and can be patterned using a photolithography mask. The dielectric layer 222 can be formed by spin coating, lamination, CVD, etc. or a combination thereof. Then the dielectric layer 222 is patterned. The patterning forms openings to expose a portion of the vias 174. When the dielectric layer 222 is a photosensitive material, the patterning is implemented by an acceptable process such as exposing the dielectric layer 222 to light, or, for example, by etching using anisotropic etching. If the dielectric layer 222 is a photosensitive material, the dielectric layer 222 can be developed after exposure.

[0087] Then, the UBM 224 is formed. The UBM 224 includes wires on and extending along the main surface of the dielectric layer 222. The UBM 224 also includes conductive vias extending through the dielectric layer 222 to physically and electrically connect to the vias 174. A seed layer (not shown) is formed over the dielectric layer 222 and in the openings extending through the dielectric layer 222. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, the seed layer can be formed using PVD, etc.

[0088] Then, a dielectric layer 228 is formed and patterned on the seed layer. In some embodiments, the dielectric layer 228 is formed of a photosensitive material such as photoresist, PBO, polyimide, BCB, etc. that can be patterned using a photolithography mask. The dielectric layer 228 can be formed by spin coating, lamination, CVD, etc. or a combination thereof, and can be exposed to light for patterning. The pattern of the dielectric layer 228 corresponds to the UBM 224. Patterning forms openings through the dielectric layer 228 to expose the seed layer. Then, a conductive material is formed in the openings of the dielectric layer 228 and on the exposed portions of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the portion below the seed layer forms the UBM 224.

[0089] Then, conductive bumps 226 are formed. A dielectric layer 230 is formed and patterned on the UBM 224 and the dielectric layer 228. The dielectric layer 230 can be similar to the dielectric layer 228. The dielectric layer 230 can be exposed to light for patterning. The pattern of the dielectric layer 230 corresponds to the conductive bumps 226. Patterning forms openings through the dielectric layer 230 to expose a portion of the UBM 224. Then, a conductive material is formed in the openings of the dielectric layer 230 and on the exposed portion of the UBM 224. The conductive material can be formed by plating such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. Since the UBM 224 is exposed by the openings in the dielectric layer 230, no seed layer is formed in the openings. Instead, the conductive material is formed directly and physically on the UBM 224. The conductive material is formed by performing a plating process that has the same plating process parameters as the plating process for the conductive material of the UBM 224. In particular, no seed layer is formed between the UBM 224 and the conductive bumps 226. Instead, the conductive material of the conductive bumps 226 is formed by performing a plating process using the seed layer of the UBM 224.

[0090] In Figure 24 this, a conductive connector 232 is formed on the conductive bumps 226. The conductive connector 232 can be formed of a conductive material such as solder, and can be formed by methods such as evaporation, electroplating, printing, solder transfer, solder ball placement, etc., by first forming a solder layer on the conductive bumps 226. Once the solder layer is formed, a reflow process can be performed to shape the conductive connector 232 into a desired bump shape. The conductive connector 232 can be a ball grid array (BGA) connector, a solder ball, a controlled collapse chip connection (C4) bump, etc. The UBM 224 is laterally offset from the conductive connector 232 by the via hole 174. Since no seed layer is formed between the UBM 224 and the conductive bumps 226, the conductive bumps 226 are conductive materials that continuously extend from the UBM 224 to the conductive connector 232.

[0091] In Figure 25 it, carrier debonding is performed to separate the carrier substrate 214 from the sealant 212 (debonding). According to some embodiments, the debonding includes projecting light such as laser or extreme ultraviolet (UV) light onto the release layer 216 such that the release layer 216 decomposes under the heat of the light and the carrier substrate 214 can be removed. Then the structure is flipped and placed on a tape. Subsequently, the interposer 170 is divided along a scribed area between adjacent device regions to form a device package 200. The division can be performed by sawing, cutting, etc. As a result of the division process, the edges of the interposer 170 and the sealant 212 are adjacent. In other words, the outer sidewall of the interposer 170 has the same width as the outer sidewall of the sealant 212. The dielectric layer 228 and the dielectric layer 230 can be optionally removed before or after the carrier debonding.

[0092] In Figure 26 it, the device package 300 is formed by mounting the device package 200 onto a package substrate 410. The package substrate 410 can be made of a semiconductor material such as silicon, germanium, etc. Alternatively, a compound material such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon carbide germanium, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, etc. can also be used. Additionally, the package substrate 410 can be a SOI substrate. In some embodiments, the SOI substrate includes a semiconductor material layer such as epitaxially grown silicon, germanium, silicon germanium, SOI, or combinations thereof. In an alternative embodiment, the package substrate 410 is based on an insulating core such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin such as FR4. Alternative materials for the core material include bismaleimide-triazine (BT) resin, or other printed circuit board (PCB) materials or films. A build-up film such as Ajinomoto build-up film (ABF) or other laminates can be used for the package substrate 410.

[0093] The package substrate 410 can include active and passive devices. As will be appreciated by one of ordinary skill in the art, various devices such as transistors, capacitors, resistors, combinations thereof, etc. can be used to meet the structural and functional requirements of the device package 400 design. Any suitable method can be used to form the devices.

[0094] The encapsulation substrate 410 may further include a metallization layer and vias, and bonding pads 412 located above the metallization layer and vias. The metallization layer may be formed over active and passive devices and is designed to connect the respective devices to form a functional circuit. The metallization layer may be formed of alternating layers of a dielectric (such as a low-k dielectric material) and a conductive material (such as copper), having vias that interconnect the conductive material layers, and may be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the encapsulation substrate 410 is substantially free of active and passive devices.

[0095] The conductive connectors 232 are reflowed to attach the device package 200 to the bonding pads 412, thereby bonding the interposer 170 to the encapsulation substrate 410. The conductive connectors 232 electrically and physically couple the encapsulation substrate 410 (including the metallization layer located in the encapsulation substrate 410) to the device package 200. As described above, physically separated portions of the underfill material 210 may reduce warping of the device package 200. Thus, the standoff height variation between the encapsulation substrate 410 and the interposer 170 can be reduced, which can help avoid cold soldering and bridging during reflow of the conductive connectors 232. Therefore, the manufacturing yield can be improved.

[0096] An epoxy flux may be formed on the conductive connectors 232 before their reflow, and at least some epoxy portions of the remaining epoxy flux after attaching the device package 200 to the encapsulation substrate 410. The remaining epoxy portions may be used as an underfill to reduce stress and protect the joints caused by reflow of the conductive connectors 232.

[0097] In some embodiments, passive devices (e.g., surface mount devices (SMDs) not shown) are attached to the device package 400 (e.g., bonded to the bonding pads 412) before being mounted onto the encapsulation substrate 410. In some embodiments, the passive devices may be bonded to the same surface of the encapsulation substrate 410 as the conductive connectors 232.

[0098] An underfill 414 may be formed between the device package 200 and the encapsulation substrate 410, surrounding the conductive connectors 232, conductive bumps 226, and UBM 224. Due to the process of forming the UBM 224, they are not surrounded by a dielectric or insulating layer after formation. In this way, the underfill 414 directly contacts and extends along the sides of the UBM 224. In addition, the underfill 414 is a continuous material extending from the encapsulation substrate 410 to the dielectric layer 222. The underfill 414 may be formed by a capillary flow process after attaching the device package 200, or may be formed by a suitable deposition method before attaching the device package 200.

[0099] Optionally, a heat sink may be attached to the device package 400, covering and surrounding the device package 200. The heat sink may be formed of a material having a high thermal conductivity, such as steel, stainless steel, copper, etc. or a combination thereof. The heat sink protects the device package 200 and forms a thermal path to conduct heat from the various components of the device package 400.

[0100] Figure 27 A simplified form of a portion of the package 300 prior to bonding the die package 100 and the interposer 170 is shown. This embodiment is similar to Figure 13 and Figure 14 the embodiments in, except that this embodiment includes dummy conductive bumps 202A located on the die package 100 instead of dummy conductive bumps 204A located on the interposer 170. Figures 13 - 15 、 Figures 16A - 16D 、 Figure 17 and Figures 18A - 18D The various configurations of active and dummy bumps disclosed in Figure 27 are applicable to the embodiments in. Details regarding this embodiment are similar to the details of the previously described embodiments and will not be repeated herein.

[0101] Figure 28 A simplified form of a portion of the package 300 prior to bonding the die package 100 and the interposer 170 is shown. This embodiment is similar to Figure 13 、 Figure 14 and Figure 27 the embodiments in, except that this embodiment includes dummy conductive bumps 202A located on the die package 100 and dummy conductive bumps 204A located on the interposer 170. Figures 13 - 15 、 Figures 16A - 16D 、 Figure 17 and Figures 18A - 18D The various configurations of active and dummy bumps disclosed in Figure 28 are applicable to the embodiments in. Details regarding this embodiment are similar to the details of the previously described embodiments and will not be repeated herein.

[0102] Other components and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate (which allow testing of the 3D package or 3DIC), using probes and / or probe cards, etc. The verification testing may be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in combination with test methods incorporating intermediate verification of known good dies to increase yield and reduce cost.

[0103] The embodiments described herein can achieve advantages. According to some embodiments, the embodiments include a connector with variable height, which can address the warping of integrated circuit dies and / or interposers. In some embodiments, the connector is a microbump formed by a plating method. In those embodiments, during the formation process, the pattern density of the microbumps in a specific region is adjusted by inserting pseudo microbumps on one or both of the integrated circuit device and the wafer, to achieve microbumps with variable height. For example, if it is desired that the first region has a shorter microbump height than the second region, the pattern density of the microbumps in the first region will be increased by inserting pseudo microbumps in the first region. This formation of the variable height connector can prevent cold welding or connector damage, and thus can improve the reliability and yield of the device.

[0104] In addition, the packages described herein are capable of integrating devices with different functions or technologies, which can increase functionality and reduce costs. By bonding semiconductor devices to form a bonded die package (e.g., a system-on-chip (SoC), etc.) within the package, the size of the package can be reduced. The package can include a bonded die package and another semiconductor die, such as a memory die, an I / O die, etc. The bonded die package and the semiconductor die can be connected to the same redistribution structure, which can allow for shorter wiring between the bonded die package and the semiconductor die. The redistribution structure can have vias of different sizes to connect to different devices, such as through vias connecting to the bonded die package or contact pads connecting to the semiconductor die. In cases where the pitch of the connections (e.g., through vias or conductive pads) of the device is small, a single via of the redistribution structure can be connected to multiple connections. Using a bonded die package or shorter wiring in this way can improve the high-frequency or high-speed operation of the package. The bonded die package can include multiple semiconductor devices or a stack of semiconductor devices, which can allow for reduced costs and greater design flexibility. In some cases, using different protective materials within the bonded die package can reduce the likelihood of defects occurring, such as due to CTE mismatch or dopant diffusion into the bonded die package.

[0105] In an embodiment, the interposer has: a first side; a first integrated circuit device attached to the first side of the interposer by a first set of conductive connectors, each of the first set of conductive connectors having a first height. The package further includes: a first die package connected to the first side of the interposer by a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height and the second conductive connector having a third height, the third height being different from the second height. The package further includes a first pseudo-conductive connector located between the first side of the interposer and the first die package. The package further includes an underfill disposed under the first integrated circuit device and the first die package. The package further includes a sealant disposed around the first integrated circuit device and the first die package.

[0106] The embodiment may include one or more of the following features. A package, wherein the first die package includes: a first die connected to a second die by a metal-to-metal bond and a dielectric-to-dielectric bond; a first dielectric material located over the first die and the second die, wherein the first dielectric material surrounds the first die; and a first via extending through the first dielectric material, wherein the first via is connected to the first die. The first die package further includes a second via extending through the first dielectric material, wherein the second via is connected to the second die. The first die package further includes a third via extending through the first dielectric material, wherein the third via is connected to the second die. The footprint of the first die package on the first side of the interposer includes a first region, a second region, and a third region, the first conductive connector and the first pseudo-conductive connector being located in the first region, the second conductive connector being located in the second region, the second height being less than the third height. The second region surrounds the first region. The first region surrounds the second region. The second region includes a second pseudo-conductive connector, and the third region has no pseudo-conductive connector. The package further includes: a third conductive connector located in the second region, the third conductive connector having a height greater than the second height; and a fourth conductive connector located in the third region, the fourth conductive connector having a height greater than the height of the third conductive connector. The underfill separates the first pseudo-conductive connector from the first die package.

[0107] In one embodiment, a first redistribution structure is formed on a first side of an interposer. The first redistribution structure includes metal lines and vias in a dielectric layer. The first redistribution structure includes active pads and dummy pads on a first surface of the first redistribution structure. The active pads are electrically connected to the metal lines and vias, and the dummy pads are electrically isolated from the metal lines and vias. The method further includes forming active connectors on the active pads. The method further includes forming dummy connectors on the dummy pads. The method further includes attaching a first integrated circuit device to a first subset of the active connectors. The method further includes attaching a second integrated circuit device to a second subset of the active connectors, with the dummy connectors being between the interposer and the second integrated circuit device. The method further includes forming an underfill on the first side of the interposer, the underfill having a first portion under the first integrated circuit device and a second portion under the second integrated circuit device. The method further includes sealing the first integrated circuit device and the second integrated circuit device with a sealant.

[0108] The embodiment may include one or more of the following features. The method further includes forming a second integrated circuit device, the forming including: bonding a first die to a second die by metal-metal bonding and dielectric-dielectric bonding; forming a first dielectric material over the first die and the second die, the first dielectric material surrounding the first die; and forming a first via hole extending through the first dielectric material and connected to the first die. The footprint of the second integrated circuit device on the first redistribution structure includes a first region, a second region, and a third region. The first region and the second region include dummy connectors. The first region, the second region, and the third region include active connectors. The third region has no dummy connectors. The active connectors in the third region are taller than the active connectors in the first region and the second region. The active and dummy connectors in the first region have a first pattern density, and the active connectors in the third region have a second pattern density, with the second pattern density being less than the first pattern density. The second region surrounds the first region, and the second region separates the first region from the third region. The first subset of the active connectors has the same height, and the second subset of the active connectors has multiple heights. The method further includes forming a via hole extending through a substrate of the interposer, with the first redistribution structure being electrically coupled to the via hole.

[0109] In an embodiment, a first integrated circuit device is attached to a first side of an interposer using a first set of connectors having the same height. The method further includes attaching a die package to the first side of the interposer using a second set of connectors having multiple heights, with a first set of dummy connectors being between the interposer and the die package and the first set of dummy connectors being electrically isolated from the die package and the first integrated circuit device. The method further includes forming an underfill on the first side of the interposer under the first integrated circuit device and the die package. The method further includes sealing the first integrated circuit device and the die package with a sealant.

[0110] The embodiments may include one or more of the following features. In the method, the occupied area of the die package on the first side of the intermediate layer includes a first region, a second region, and a third region, the second region surrounds the first region, the second region is located between the first region and the third region, the first region and the second region include a first set of dummy connectors, and the first region, the second region, and the third region include active connectors.

[0111] The components of several embodiments have been described above so that those skilled in the art can better understand the various embodiments of the present invention. Those skilled in the art should understand that it is easy to use the present invention as a basis to design or change other processes and structures for achieving the same purpose and / or realizing the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. An encapsulation, comprising: An interposer having a first side; A first integrated circuit device attached to the first side of the interposer by a first set of conductive connectors, each of the first set of conductive connectors having a first height; A first die package attached to the first side of the interposer by a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different from the second height; A first pseudo-conductive connector located between the first side of the interposer and the first die package, the first pseudo-conductive connector being located between the first conductive connector and the second conductive connector; An underfill disposed under the first integrated circuit device and the first die package; And A sealant disposed around the first integrated circuit device and the first die package.

2. The package according to claim 1, wherein The first die package includes: A first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding; A first dielectric material located above the first die and the second die, wherein the first dielectric material surrounds the first die; and A first via hole extending through the first dielectric material, wherein the first via hole is connected to the first die.

3. The package according to claim 2, wherein, The first die package further includes a second via hole extending through the first dielectric material, wherein the second via hole is connected to the second die.

4. The package according to claim 2, wherein The first die package further includes a third via hole extending through the first dielectric material, wherein the third via hole is connected to the second die.

5. The package according to claim 1, wherein, The occupied area of the first die package on the first side of the interposer includes a first area, a second area, and a third area, the first conductive connector and the first pseudo-conductive connector being located in the first area, the second conductive connector being located in the second area, the second height being less than the third height.

6. The package according to claim 5, wherein, The second area surrounds the first area.

7. The package according to claim 5, wherein, The first area surrounds the second area.

8. The package according to claim 5, wherein, The second area includes a second pseudo-conductive connector, and the third area has no pseudo-conductive connector.

9. The encapsulation according to claim 8, further comprising: A third conductive connector located in the second area, the third conductive connector having a height greater than the second height; And A fourth conductive connector located in the third area, the fourth conductive connector having a height greater than the height of the third conductive connector.

10. The package according to claim 1, wherein, The underfill separates the first pseudo-conductive connector from the first die package.

11. A method of manufacturing an encapsulation, comprising: Forming a first redistribution structure on a first side of an interposer, the first redistribution structure including metal lines and vias in a dielectric layer, the first redistribution structure including active pads and pseudo-pads on a first surface of the first redistribution structure, the active pads being electrically coupled to the metal lines and vias, the pseudo-pads being electrically isolated from the metal lines and vias; Forming active connectors on the active pads; Form a pseudo-connector on the pseudo-pad; Attach a first integrated circuit device to a first subset of the active connectors; Attach a second integrated circuit device to a second subset of the active connectors, the pseudo-connector being located between the interposer and the second integrated circuit device; Form an underfill on a first side of the interposer, the underfill having a first portion located under the first integrated circuit device and a second portion located under the second integrated circuit device; And Seal the first integrated circuit device and the second integrated circuit device with a sealant; Wherein the first subset of the active connectors has the same height, and wherein the second subset of the active connectors has multiple heights.

12. The method according to claim 11, further comprising: Forming the second integrated circuit device, the forming including: Bonding a first die to a second die by metal-metal bonding and dielectric-dielectric bonding; Forming a first dielectric material over the first die and the second die, the first dielectric material surrounding the first die; and Forming a first viaduct extending through the first dielectric material and connected to the first die.

13. The method according to claim 11, wherein, The occupied area of the second integrated circuit device on the first redistribution structure includes a first region, a second region, and a third region, the first region and the second region include pseudo-connectors, the first region, the second region, and the third region include active connectors, and the third region has no pseudo-connectors.

14. The method according to claim 13, wherein, The active connectors in the third region are higher than the active connectors in the first region and the second region.

15. The method according to claim 13, wherein, The active connectors and pseudo-connectors in the first region have a first pattern density, the active connectors in the third region have a second pattern density, and the second pattern density is less than the first pattern density.

16. The method according to claim 13, wherein, The second region surrounds the first region, and wherein the second region separates the first region from the third region.

17. The method according to claim 11, wherein, The underfill is an epoxy resin.

18. The method according to claim 11, further comprising: Forming a viaduct extending through the substrate of the interposer, the first redistribution structure being electrically coupled to the viaduct.

19. A method of manufacturing a package, comprising: Attaching a first integrated circuit device to a first side of an interposer through a first set of connectors, the first set of connectors having the same height; Attaching a die package to the first side of the interposer through a second set of connectors, the second set of connectors having multiple heights, the second set of connectors including a first connector and a second connector, the height of the first connector being different from the height of the second connector, a first set of pseudo-connectors being located between the interposer and the die package, the first set of pseudo-connectors being electrically isolated from the die package and the first integrated circuit device, the first set of pseudo-connectors having pseudo-connectors located between the first connector and the second connector; Forming an underfill on the first side of the interposer under the first integrated circuit device and the die package; And Seal the first integrated circuit device and the die package with a sealant.

20. The method according to claim 19, wherein, The occupied area of the die package on the first side of the interposer includes a first region, a second region, and a third region. The second region surrounds the first region and is located between the first region and the third region. The first region and the second region include the first set of dummy connectors, and the first region, the second region, and the third region include active connectors.

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