Preparation Method of 3D Memory and Lithography Mask

Abstract

The present application provides a method for fabricating a three-dimensional memory and a photolithography mask. The method includes: forming a first stacked structure on a substrate; forming a first channel hole penetrating therethrough and extending to the substrate, and filling the first channel hole with a sacrificial layer; forming a second stacked structure on the first stacked structure, and forming an etching mask layer on a surface of the second stacked structure away from the substrate; patterning the etching mask layer to form at least two of a pattern of a second channel hole, a pattern of a gate gap, a pattern of a virtual channel hole, and a pattern of a conductive contact hole; etching to form at least two of a second channel hole, a gate gap, a virtual channel hole, and a conductive contact hole with the patterned etching mask layer as a mask. The fabrication method provided by the present application simplifies process steps and saves fabrication costs, and can improve the overlay accuracy in the etching process and the overall performance of the three-dimensional memory by pre-embedding an etching mask layer including a plurality of etching patterns on the upper surface of the multi-stacked structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a method for manufacturing a three-dimensional memory (3D NAND) and a photolithography mask. Background Art

[0002] Photolithography is an important process in the method for manufacturing a three-dimensional memory. Photolithography can transfer the mask pattern on the photolithography mask (Mask) to the wafer (Wafer) through a series of steps such as alignment and exposure. In the process of manufacturing a three-dimensional memory, usually multiple photolithography processes are required to complete the entire manufacturing process.

[0003] With the development of semiconductor manufacturing technology and the development of integrated circuit design and manufacturing, the feature size of three-dimensional memory devices is continuously shrinking. Therefore, in order to achieve good product performance and high yield, how to improve the position alignment of local structures with very small pitch in three-dimensional memory devices, such as channels, conductive contacts, virtual channels, and gate gaps, and reduce the overlay error during their formation, and improve the overlay accuracy is a crucial issue in the method for manufacturing a three-dimensional memory. Summary of the Invention

[0004] The present application provides a three-dimensional memory and a method for manufacturing the same that can at least partially solve the above problems existing in the related art.

[0005] On the one hand, the present application provides a method for manufacturing a three-dimensional memory, the method comprising: forming a first stacked structure on a substrate; forming a first channel hole penetrating the first stacked structure and extending to the substrate, and filling the first channel hole with a sacrificial layer; forming a second stacked structure on the first stacked structure, and forming an etching mask layer on a surface of the second stacked structure away from the substrate; patterning the etching mask layer to form at least two of a pattern of a second channel hole, a pattern of a gate gap, a pattern of a virtual channel hole, and a pattern of a conductive contact hole; and etching to form at least two of the second channel hole, the gate gap, the virtual channel hole, and the conductive contact hole with the patterned etching mask layer as a mask.

[0006] In one embodiment of the present application, patterning the etching mask layer includes: covering a first photoresist layer on the etching mask layer; transferring the pattern of a photomask to the first photoresist layer by means of a photolithography process, wherein the pattern of the photomask includes at least two of the pattern of the second channel hole, the pattern of the gate gap, the pattern of the dummy channel hole, and the pattern of the conductive contact hole; etching the etching mask layer with the patterned first photoresist layer as a mask to remove the portion of the etching mask layer corresponding to the pattern of the first photoresist layer and form a plurality of first hollow windows; and filling the plurality of first hollow windows with an oxide layer to form the patterned etching mask layer.

[0007] In one embodiment of the present application, after filling the plurality of first hollow windows with an oxide layer to form the patterned etching mask layer, the method further includes: planarizing the surface of the patterned etching mask layer away from the substrate.

[0008] In one embodiment of the present application, the radial dimension of the pattern of the second channel hole in the patterned first photoresist layer is greater than the radial dimension of the pattern of the second channel hole in the patterned etching mask layer; the width of the pattern of the gate gap in the patterned first photoresist layer is greater than the width of the pattern of the gate gap in the patterned etching mask layer; the radial dimension of the pattern of the dummy channel hole in the patterned first photoresist layer is greater than the radial dimension of the pattern of the dummy channel hole in the patterned etching mask layer; and the radial dimension of the pattern of the conductive contact hole in the patterned first photoresist layer is greater than the radial dimension of the pattern of the conductive contact hole in the patterned etching mask layer.

[0009] In one embodiment of the present application, etching to form the second channel hole with the patterned etching mask layer as a mask includes: forming a second photoresist layer on the patterned etching mask layer; removing the portion of the second photoresist layer corresponding to the pattern of the second channel hole in the patterned etching mask layer to form a second hollow window in the second photoresist layer; etching through the second stack structure to form the second channel hole via the second hollow window; and removing the sacrificial layer in the first channel hole through the second channel hole.

[0010] In an embodiment of the present application, with the patterned etching mask layer as a mask, etching to form the virtual channel hole includes: forming a third photoresist layer on the patterned etching mask layer; removing a portion of the third photoresist layer corresponding to the pattern of the virtual channel hole in the patterned etching mask layer to form a third hollow window in the third photoresist layer; and etching through the first stacked structure and the second stacked structure and extending to the substrate to form the virtual channel hole via the third hollow window.

[0011] In an embodiment of the present application, with the patterned etching mask layer as a mask, etching to form the gate gap includes: forming a fourth photoresist layer on the patterned etching mask layer; removing a portion of the fourth photoresist layer corresponding to the pattern of the gate gap in the patterned etching mask layer to form a fourth hollow window in the fourth photoresist layer; and etching through the first stacked structure and the second stacked structure and extending to the substrate to form the gate gap via the fourth hollow window.

[0012] In an embodiment of the present application, where the conductive contact hole includes a word line contact hole and a peripheral contact hole, with the patterned etching mask layer as a mask, etching to form the conductive contact hole includes: forming a fifth photoresist layer on the patterned etching mask layer; removing a portion of the fifth photoresist layer corresponding to the pattern of the conductive contact hole in the patterned etching mask layer to form a fifth hollow window in the fifth photoresist layer, where the pattern of the conductive contact hole includes the pattern of the word line contact hole and the pattern of the peripheral contact hole; and etching to form the conductive contact hole via the fifth hollow window.

[0013] In an embodiment of the present application, after etching to form at least two of the second channel hole, the gate gap, the virtual channel hole, and the conductive contact hole with the patterned etching mask layer as a mask, the method further includes: filling the second channel hole formed by etching, the gate gap formed by etching, the virtual channel hole formed by etching, or the conductive contact hole formed by etching; and retaining the etching mask layer.

[0014] In an embodiment of the present application, the etching mask layer is a hard mask layer.

[0015] In an embodiment of the present application, the thickness range of the etching mask layer is between 20 microns and 30 microns.

[0016] In an embodiment of the present application, before filling the first channel hole with a sacrificial layer, the method further includes: forming a barrier layer on a portion of the inner wall of the channel hole located in the substrate.

[0017] On the other hand, the present application provides a three-dimensional memory, which includes: a substrate; a stacked structure including a first stacked structure and a second stacked structure, wherein the first stacked structure is disposed on the substrate, and the second stacked structure is disposed on the first stacked structure; an etching mask retention layer disposed on the surface of the second stacked structure away from the substrate; and a channel structure including a channel hole and a functional layer and a channel layer sequentially disposed on the inner wall of the channel hole. Among them, the channel hole includes a first channel hole and a second channel hole. The first channel hole penetrates the first stacked structure and extends to the substrate, and the second channel hole penetrates the second stacked structure and the etching mask retention layer and is at least partially aligned with the first channel hole.

[0018] In one embodiment of the present application, the memory further includes: a gate gap structure including a gate gap and a filling dielectric layer filled in the gate gap, wherein the gate gap penetrates the etching mask retention layer and the stacked structure and extends to the substrate.

[0019] In one embodiment of the present application, the memory further includes: a virtual channel structure including a virtual channel hole and an insulating dielectric filling layer filled in the virtual channel hole, wherein the virtual channel hole penetrates the etching mask retention layer and the stacked structure and extends to the substrate.

[0020] In one embodiment of the present application, wherein the stacked structure includes alternately stacked gate layers and insulating layers forming a plurality of stepped steps, the memory further includes: a stepped region dielectric layer covering the stepped steps; and an outer contact and a plurality of word line contacts. Among them, the outer contact includes an outer contact hole and a conductive layer filled in the outer contact hole. The outer contact hole penetrates the etching mask retention layer and the stepped region dielectric layer and extends to the substrate, and the word line contact includes a word line contact hole and a conductive layer filled in the word line contact hole. The word line contact hole penetrates the etching mask retention layer and the stepped region dielectric layer and extends to the stepped steps.

[0021] In one embodiment of the present application, the stacked structure includes a storage area and a stepped area located at the periphery of the storage area. Among them, the stepped area includes a plurality of the stepped steps, and the storage area includes a plurality of channel structures.

[0022] In one embodiment of the present application, the stacked structure includes a first storage area, a second storage area and a stepped area. Among them, the stepped area is located between the first storage area and the second storage area and includes a plurality of the stepped steps; and the first storage area and the second storage area respectively include a plurality of channel structures.

[0023] According to at least one embodiment of the present application, the preparation method provided by the present application, while simplifying the process steps and saving preparation costs, can improve the overlay accuracy of the etching process by pre-embedding an etching mask layer including multiple etching patterns on the upper surface of the multi-layer structure, reduce the overlay error, and improve the overall performance of the three-dimensional memory.

[0024] In addition, compared with the conventional preparation method using multiple layers of etching mask layers, the preparation method provided in the present application only pre-buries one layer of etching mask layer. Since the etching mask layer is relatively thin, the pattern of the etching mask layer under the photoresist layer can be directly observed during the photolithography process, and can therefore be directly exposed.

[0025] In addition, according to at least one embodiment of the present application, the present application also provides a photolithography mask that can be used in the preparation of a three-dimensional memory, which can simplify the steps of the three-dimensional memory preparation process and save its preparation cost. Furthermore, the photolithography mask can also be used to pre-embed an etching mask layer including multiple etching patterns on the upper surface of the multi-layer structure to improve the overlay accuracy of the etching process during the preparation of the three-dimensional memory, reduce its overlay error, and improve the overall performance of the three-dimensional memory.

[0026] In addition, according to at least one embodiment of the present application, the three-dimensional memory provided by the present application has relatively high overall performance and relatively low preparation cost because it can improve the overlay accuracy of the etching process and reduce the overlay error by pre-burying an etching mask layer including multiple etching patterns on the upper surface of the multi-layer structure during the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0028] Figure 1 is a flow chart of a method for preparing a three-dimensional memory according to one embodiment of the present application;

[0029] Figures 2A to 13B They are respectively process schematic diagrams of a preparation method according to one embodiment of the present application;

[0030] Figure 14 is a schematic top view of a stacked structure according to one embodiment of the present application;

[0031] Figure 15 is a schematic top view of a stacked structure according to another embodiment of the present application;

[0032] Figure 16 is a schematic top view of a photolithography mask according to another embodiment of the present application; and

[0033] Figure 17 A top view schematic diagram of a three-dimensional memory according to an embodiment of the present application. Detailed Embodiments

[0034] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to separate one feature from another feature region and do not represent any limitation on the features, especially do not represent any order. Therefore, without departing from the teachings of the present application, the first channel structure discussed in the present application can also be referred to as the second structure, and vice versa.

[0036] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, terms such as "substantially", "about", and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0037] It should also be understood that expressions such as "comprising", "including", "having", "containing", and / or "including having" are open-ended rather than closed-ended expressions in this specification, which mean that there are the stated features, elements, and / or components, but do not exclude the existence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0038] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which the present application belongs. It should also be understood that unless there is a clear statement in the present application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the related art and should not be interpreted in an idealized or overly formal sense.

[0039] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. In addition, unless explicitly defined or inconsistent with the context, the specific steps included in the methods described in the present application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0040] In addition, in the present application, when using "connect" or "couple", it can mean that there is direct contact or indirect contact between the corresponding components, unless there are other explicit limitations or can be deduced from the context.

[0041] Figure 1 is a flowchart of a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application. As Figure 1 shown, the present application provides a method 1000 for manufacturing a three-dimensional memory, including:

[0042] S1, forming a first stacked structure on a substrate.

[0043] S2, forming a first channel hole penetrating the first stacked structure and extending to the substrate, and filling the first channel hole with a sacrificial layer.

[0044] S3, forming a second stacked structure on the first stacked structure, and forming an etching mask layer on the surface of the second stacked structure away from the substrate.

[0045] S4, patterning the etching mask layer to form at least two of a pattern of a second channel hole, a pattern of a gate gap, a pattern of a virtual channel hole, and a pattern of a conductive contact hole.

[0046] S5, using the patterned etching mask layer as a mask to etch and form at least two of a second channel hole, a gate gap, a virtual channel hole, and a conductive contact hole.

[0047] The following will be combined with Figures 2A to 13A to detail the specific processes of each step of the above manufacturing method 1000.

[0048] Step S1

[0049] Figure 2A A cross-sectional schematic view of the structure formed after forming the first channel hole 311 in the first stacked structure 201 according to the manufacturing method of an embodiment of the present application. Figure 2B A top view schematic view of the structure formed after forming the first channel hole 311 in the first stacked structure 201 according to the manufacturing method of an embodiment of the present application. As Figure 2A and Figure 2BAs shown, step S1 of forming the first stacked structure on the substrate may, for example, include: preparing the substrate 100; and forming the first stacked structure 201 on one side of the substrate 100.

[0050] Specifically, in one embodiment of the present application, the material for preparing the substrate 100 may be selected from any suitable semiconductor material, such as single-crystalline silicon (Si), single-crystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or group III-V compounds such as gallium arsenide. Further, the substrate 100 may be selected as single-crystalline silicon.

[0051] In one embodiment of the present application, the substrate 100 may be, for example, a composite substrate for supporting the device structure thereon. Multiple layers made of different materials may be sequentially provided by a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate 100.

[0052] The substrate 100 may include a substrate sacrificial layer, and the substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high-k dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer provided in sequence, where the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, in one embodiment of the present application, an exemplary material for forming the substrate sacrificial layer may be polysilicon.

[0053] In addition, well regions doped with N-type or P-type dopants by ion implantation or diffusion processes may also be formed in some regions of the substrate 100. The dopants may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions may be prepared with the same dopant or different dopants. Further, the doping concentrations of the well regions may be the same or different, and the present application does not limit this.

[0054] The substrate 100 has opposite first and second sides. After forming the substrate 100, a first stacked structure 201 can be formed on one side of the substrate 100 through one or more thin-film deposition processes, which may include but are not limited to CVD, PVD, ALD, or any combination thereof, and this application does not limit this. The first stacked structure 201 may include multiple pairs of insulating layers 210 and gate sacrificial layers 220 stacked alternately with each other. For example, the first stacked structure 201 may include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 210 and gate sacrificial layers 220. In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may respectively include a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials for forming the insulating layer 210 and the gate sacrificial layer 220 may include silicon oxide and silicon nitride respectively. The silicon oxide layer can be used as an isolation stacked layer, while the silicon nitride layer can be used as a sacrificial stacked layer. In subsequent steps of fabricating the three-dimensional memory, the sacrificial stacked layer can be etched away and replaced with a conductor layer including a conductive material.

[0055] In addition, as Figure 2B shown, the first stacked structure 201 may have a stepped area 01' and a storage array area 02', where the stepped area 01' can be used as part of the stepped area of the subsequently formed stacked structure to form multiple stepped steps 500, and the storage array area 02' can be used as part of the storage array area of the subsequently formed stacked structure to form a storage array. Subsequently, the gate layers in the storage array can be connected and conducted one by one through word line contacts formed on each stepped step. Step S2

[0056] Referring back to Figure 2A and Figure 2B , step S2 of forming a first channel hole that penetrates the first stacked structure and extends to the substrate, and filling the first channel hole with a sacrificial layer may include, for example: forming a first channel hole 311 in the first stacked structure 201, the first channel hole 311 penetrating the first stacked structure 201 and extending into the substrate 100; and filling the first channel hole 311 with a sacrificial layer.

[0057] In an embodiment of this application, the first channel hole 311 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing. In some embodiments of this application, the first channel hole 311 has a cylindrical or columnar shape that penetrates the first stacked structure 201 in the thickness direction (Z direction) of the first stacked structure 201 and extends to the substrate 100.

[0058] In addition, as Figure 2BAs shown, in an embodiment of the present application, a plurality of first channel holes 311 can be formed not only in the storage array region 02' of the first stacked structure 201, but also in the step region 01' of the first stacked structure 201.

[0059] Referring again to Figure 2A , after forming the first channel holes 311, a sacrificial layer 340 can be filled in the first channel holes 311 through one or more thin film deposition processes. The thin film deposition processes can include but are not limited to CVD, PVD, ALD, or any combination thereof. The present application does not limit this.

[0060] As an option, the sacrificial layer 340 can be a material with a high deposition rate to quickly fill the first channel holes 311, and the sacrificial layer 340 should be any material with a high dry etching selectivity relative to the insulating layer 210 and the gate sacrificial layer 220 to facilitate the removal of the sacrificial layer 340 in the first channel holes 311 in subsequent steps. In an embodiment of the present application, the sacrificial layer 340 can be polysilicon.

[0061] In addition, in an embodiment of the present application, a chemical mechanical polishing process with a relatively low polishing rate (Buffer CMP) or a chemical mechanical polishing process (CMP) can be performed on the top surface of the first stacked structure 201 (the surface of the first stacked structure 201 away from the substrate 100) and the top surface of the sacrificial layer 340 (the surface of the sacrificial layer 340 away from the substrate 100). Through the above processes, the top surface of the first stacked structure 201 and the top surface of the sacrificial layer 340 can be made flat and at the same height, thereby obtaining a flat surface, and a second stacked structure can be formed on this flat surface in subsequent steps, improving the overall performance of the 3D memory.

[0062] Furthermore, in an embodiment of the present application, before filling the first channel holes 311 with the sacrificial layer 340, the method for manufacturing a 3D memory further includes: forming a barrier layer on the part of the inner wall of the channel hole located on the substrate.

[0063] Forming a barrier layer on the inner wall of the portion of the first channel hole 311 located within the substrate 100 may include, for example: before filling the first channel hole 311, forming the barrier layer 350 on the bottom surface of the first channel hole 311 and the side walls adjacent to the bottom surface. In other words, forming the barrier layer 350 on the inner wall of the portion of the first channel hole 311 located within the substrate 100. The barrier layer 350 can be formed by one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof; as an option, an oxidation process can also be performed on the portion of the substrate 100 in contact with the first channel hole 311 to form an oxide layer as the barrier layer 350. The barrier layer 350 can provide insulation protection for the subsequently formed channel structure to prevent leakage and other situations that may cause a decrease in electrical performance in the fabricated three-dimensional memory. However, those skilled in the art should understand that without departing from the technical solutions claimed in the present application, the structure, composition, and generation process of the barrier layer can be changed to obtain the various results and advantages described in this specification.

[0064] Step S3

[0065] Figure 3 Schematic cross-sectional view of a structure formed after forming a second stacked structure 202 on a first stacked structure 201 according to a preparation method of an embodiment of the present application. Figure 4 According to a preparation method of an embodiment of the present application, after forming a patterned initial etching mask layer on the second stacked structure 202 (as Figure 3 shown), schematic cross-sectional view of the formed structure.

[0066] As Figure 3 and Figure 4 shown, step S3 of forming a second stacked structure on the first stacked structure and forming an etching mask layer on the surface of the second stacked structure away from the substrate may include, for example: forming a second stacked structure 202 on the first stacked structure 201; forming a plurality of stepped steps 500 in the stacked structure 200; forming an initial etching mask layer (not shown) on the second stacked structure 202.

[0067] Specifically, in an embodiment of the present application, after filling the first channel hole 311, a second stacked structure 202 can be formed on the side of the first stacked structure 201 away from the substrate 100 through one or more thin film deposition processes. The thin film deposition processes can include but are not limited to CVD, PVD, ALD, or any combination thereof, and the present application does not limit this.

[0068] The second stacked structure 202 may include multiple pairs of insulating layers 210' and gate sacrificial layers 220' stacked alternately with each other. For example, the second stacked structure 202 may include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 210' and gate sacrificial layers 220'. In some embodiments, the insulating layer 210' and the gate sacrificial layer 220' may respectively include a third dielectric material and a fourth dielectric material different from the third dielectric material. Exemplary materials for forming the insulating layer 210' and the gate sacrificial layer 220' may include silicon oxide and silicon nitride respectively. As an option, the insulating layers and the gate sacrificial layers included in the second stacked structure 202 may be the same as those included in the first stacked structure 201; as another option, the insulating layers and the gate sacrificial layers included in the second stacked structure 202 may also be different from those included in the first stacked structure 201. The difference means that the materials constituting the insulating layers and the gate sacrificial layers are different, or the numbers of the insulating layers and the gate sacrificial layers are different from each other, or both of the above situations exist.

[0069] After the second stacked structure 202 is formed, it and the first stacked structure 201 together constitute the stacked structure 200 of the 3D memory. However, those skilled in the art should understand that without departing from the technical solutions claimed in the present application, the stacked structure 200 can be prepared by using a dual stack technology or a multi-stack technology. In other words, the structure, composition, and generation process of the stacked structure 200 can be changed to obtain the various results and advantages described in this specification.

[0070] Figure 14 is a top view schematic diagram of the stacked structure 200 according to an embodiment of the present application. Figure 15 is a top view schematic diagram of the stacked structure 200 according to another embodiment of the present application.

[0071] As Figure 3 , Figure 14 and Figure 15 shown, the stacked structure 200 may have a stepped area 01 and a storage array area 02. The stepped area 01 may be used to form multiple stepped steps 500, and the storage array area 02 may be used to form a storage array. Subsequently, the gate layers in the storage array can be connected and conducted in one-to-one correspondence through word line contacts formed on each stepped step.

[0072] In one embodiment of the present application, a plurality of stepped steps 500 may be formed in the stepped area 01 of the stacked structure 200. The plurality of stepped steps 500 may include a plurality of stepped dielectric layer pairs (e.g., the insulating layer 210' and the gate sacrificial layer 220'). Specifically, the plurality of stepped steps 500 may be formed by performing a plurality of "trim-etch" cycles on the edge portion of the stacked structure 200 including, for example, the first stacked structure 201 and the second stacked structure 202, so that the stacked structure 200 has one or more inclined edges and a top (away from the substrate 100) dielectric layer pair that is shorter than the bottom (close to the substrate 100) dielectric layer pair. Any suitable etching process (including any one or combination of dry etching processes and wet etching processes) may be used in the step formation process. Further, a stepped area dielectric layer 510 may also be formed to cover the stepped dielectric layer pair.

[0073] As Figure 14 shown, according to some embodiments, the storage array area 02 may be disposed in the center of the stacked structure 200, and the stepped area 01 may be disposed on one side edge or multiple side edges of the stacked structure 200. As Figure 15 shown, according to some embodiments, the stepped area 01 may be disposed in the center of the stacked structure 200, and the storage array area 02 may be disposed on the edge of the stacked structure 200. The present application does not limit the relative positions and specific structures of the stepped area 01 and the storage array area 01. In addition, the stacked structure 200 may further include a peripheral circuit area for forming peripheral circuits.

[0074] Referring again to Figure 3 and Figure 4 , after forming the plurality of stepped steps 500, an initial etch mask layer may be formed on the second stacked structure 202. The initial etch mask layer may be formed on the surface of the second stacked structure 202 away from the substrate 100 through one or more thin film deposition processes, and the thin film deposition processes may include but are not limited to CVD, PVD, ALD, or any combination thereof.

[0075] In some embodiments of the present application, the initial etch mask layer may be a hard mask layer. The hard mask layer may be, for example, a composite layer of silicon nitride, silicon oxide, carbon, silicon oxynitride, etc., or a combination thereof. The present application does not limit the structure, composition, and generation process of the etch mask layer.

[0076] In addition, in an embodiment of the present application, the initial etching mask layer may also be a hard mask layer doped with a specific substance, such as an amorphous carbon layer doped with hydrogen, and the transparency of the initial etching mask layer can be improved by adjusting the doping concentration of hydrogen therein. Higher transparency is beneficial for aligning the stacked structure 200 under the initial etching mask layer in subsequent processes. Further, multiple sub-etching mask layers with different doping concentrations may be formed in the initial etching mask layer including multiple composite layers, and the different doping concentrations may also vary according to a certain rule, such as increasing or decreasing in a gradient, etc., to improve the transparency of the initial etching mask layer.

[0077] Further, in some embodiments of the present application, the thickness range of the initial etching mask layer may be between 20 micrometers and 30 micrometers.

[0078] Step S4

[0079] Refer again to Figure 4 , step S4 patterns the etching mask layer to form at least two of the patterns of the second channel holes, the gate gaps, the dummy channel holes, and the conductive contact holes. For example, it may include: covering a first photoresist layer (not shown) on the initial etching mask layer; transferring the pattern of the photomask to the first photoresist layer by a photolithography process, where the pattern of the photomask includes at least two of the patterns of the second channel holes, the gate gaps, the dummy channel holes, and the conductive contact holes; etching the initial etching mask layer with the patterned first photoresist layer as a mask to remove the part of the initial etching mask layer corresponding to the pattern of the first photoresist layer and form multiple hollow windows; and filling the multiple hollow windows with the oxide layer 610 to form the patterned etching mask layer 600.

[0080] Photolithography is an important process in the method for manufacturing three-dimensional memories. Photolithography can transfer the mask pattern on the photomask to the wafer through a series of steps such as alignment and exposure. In the process of manufacturing three-dimensional memories, usually multiple photolithography processes are required to complete the entire manufacturing process. For example, multiple photolithography processes are needed to form the channel holes, gate gaps, dummy channel holes, word line contact holes, and peripheral contact holes of the three-dimensional memory on the wafer respectively.

[0081] However, with the development of semiconductor manufacturing technology and the development of integrated circuit design and manufacturing, the characteristic size of three-dimensional memory devices is constantly shrinking. The characteristic sizes of the above-mentioned multiple structures in the three-dimensional memory device are constantly shrinking, and the spacing between them is also gradually shrinking, so it is easy to cause leakage due to mutual contact caused by overlay error, or alignment difficulties caused by stress, offset of overlay accuracy, etc., which ultimately affects the yield and overall performance of the three-dimensional memory product.

[0082] In order to achieve good product performance and high yield, the present application provides a method for preparing a three-dimensional memory, which can reduce the overlay error of multiple local structures with very small spacing in the device during the formation process and improve the overlay accuracy of its etching process.

[0083] Specifically, an etching mask layer is pre-buried on the upper surface (the surface away from the substrate) of the double (or multi-) stacked structure, wherein the etching mask layer may include a plurality of hole patterns pre-formed by etching in subsequent steps. By forming a plurality of etching patterns in one etching mask layer, not only can the process steps be simplified and the preparation cost be saved, but also the overlay error between the plurality of holes formed by the subsequent etching process can be reduced, the overlay accuracy of the etching process can be improved, and the overall performance of the three-dimensional memory can be improved.

[0084] In addition, compared with the conventional preparation method using multiple layers of etching mask layers, the preparation method provided in the present application only pre-buries one layer of etching mask layer. Since the etching mask layer is relatively thin, the pattern of the etching mask layer under the photoresist layer can be directly observed during the photolithography process, and can therefore be directly exposed.

[0085] Furthermore, in some embodiments of the present application, after the oxide layer 610 is used to fill the plurality of hollow windows to form a patterned etch mask layer 600, the method for preparing a three-dimensional memory further includes: performing a planarization process on the surface of the patterned etch mask layer 600 that is away from the substrate 100. As an option, a chemical mechanical polishing process (Buffer CMP) with a low grinding rate may be performed on the surface of the patterned etch mask layer 600. Through the Buffer CMP process, the patterned etch mask layer 600 may obtain a flat surface to facilitate the etching process in subsequent steps.

[0086] In addition, in some embodiments of the present application, the radial dimensions of the patterns of the second channel holes, the gate gaps, the dummy channel holes, and the conductive contact holes in the patterned first photoresist layer are all larger than the radial dimensions of their corresponding portions in the patterned etching mask layer 600. Specifically, the radial dimension of the pattern of the second channel holes in the patterned first photoresist layer is larger than the radial dimension of the pattern of the second channel holes in the patterned etching mask layer 600; the width of the pattern of the gate gaps in the patterned first photoresist layer is larger than the width of the pattern of the gate gaps in the patterned etching mask layer 600; the radial dimension of the pattern of the dummy channel holes in the patterned first photoresist layer is larger than the radial dimension of the pattern of the dummy channel holes in the patterned etching mask layer 600; and the radial dimension of the pattern of the conductive contact holes in the patterned first photoresist layer is larger than the radial dimension of the pattern of the conductive contact holes in the patterned etching mask layer 600.

[0087] Step S5

[0088] Figure 5 Schematic cross-sectional view of a structure formed after forming a second photoresist layer 701 on the surface of a patterned etching mask layer 600 according to a preparation method of an embodiment of the present application. Figure 6A Schematic cross-sectional view of a structure formed after forming second channel holes 312 in a stacked structure 200 according to a preparation method of an embodiment of the present application. Figure 6B Schematic top view of a structure formed after forming second channel holes 312 in a stacked structure 200 according to a preparation method of an embodiment of the present application. Figure 7 Schematic cross-sectional view of a structure formed after forming a channel structure 300 according to a preparation method of an embodiment of the present application. Figure 8 Schematic cross-sectional view of a structure formed after forming dummy channel holes 810 according to a preparation method of an embodiment of the present application. Figure 9A Schematic cross-sectional view of a structure formed after forming a dummy channel structure 800 according to a preparation method of an embodiment of the present application. Figure 9B Schematic top view of a structure formed after forming a dummy channel structure 800 according to a preparation method of an embodiment of the present application. Figure 10 Schematic cross-sectional view of a structure formed after forming gate gaps 410 according to a preparation method of an embodiment of the present application. Figure 11A Schematic cross-sectional view of a structure formed after forming a gate gap structure 400 according to a preparation method of an embodiment of the present application. Figure 11B Schematic top view of a structure formed after forming a gate gap structure 400 according to a preparation method of an embodiment of the present application. Figure 12Schematic cross-sectional view of a structure formed after forming conductive contact holes 911 and 912 according to a preparation method of an embodiment of the present application. Figure 13A Schematic cross-sectional view of a structure formed after forming conductive contacts 901 and 902 according to a preparation method of an embodiment of the present application. Figure 13B Schematic cross-sectional view of a structure formed after forming conductive contact 902 according to a preparation method of an embodiment of the present application.

[0089] As Figures 5 to 13B shown, step S5 uses the patterned etching mask layer as a mask to etch and form at least two of the second channel hole, the gate gap, the dummy channel hole, and the conductive contact hole. For example, it may include: forming a second photoresist layer 701 on the surface of the patterned etching mask layer 600; forming a second channel hole 312 in the second stacked structure 202; forming a channel structure 300; forming a third photoresist layer 702 on the surface of the patterned etching mask layer 600; forming a dummy channel hole 810; forming a dummy channel structure 800; forming a fourth photoresist layer 703 on the surface of the patterned etching mask layer 600; forming a gate gap 410; forming a gate gap structure 400; forming a fifth photoresist layer 704 on the surface of the patterned etching mask layer 600; forming conductive contact holes 911 and 912; and forming conductive contacts 901 and 902.

[0090] Specifically, as Figures 5 to 7 shown, in an embodiment of the present application, a second photoresist layer 701 is formed on the patterned etching mask layer 600; the portion of the second photoresist layer 701 corresponding to the pattern 601 of the second channel hole in the patterned etching mask layer 600 is removed to form a second hollow window 01 in the second photoresist layer 701; through the second hollow window 01, a second channel hole 312 penetrating the second stacked structure 202 is etched; the sacrificial layer 340 in the first channel hole 311 is removed through the second channel hole 312, so that the first channel hole 311 and the second channel hole 312 are at least partially aligned to form a channel hole 310; the second photoresist layer 701 is removed; and a channel structure 300 is formed in the channel hole 310.

[0091] As Figure 5 shown, the second photoresist layer 701 can be formed on the etching mask layer 600 by processes such as spin coating, and the portion of the second photoresist layer 701 corresponding to the pattern 601 of the second channel hole in the patterned etching mask layer 600 is correspondingly removed to form a second hollow window 01 in the second photoresist layer 701.

[0092] As Figure 6AAs shown, the second channel hole 312 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, in some embodiments of the present application, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc. As Figure 2B and Figure 6B shown, the second channel hole 312 can be formed in a portion of the second stacked structure 202 (it can be understood that the second stacked structure 202 formed on the first stacked structure 201 has jointly formed the stacked structure 200 with the first stacked structure 201) corresponding to the first channel hole 311, and is at least partially aligned with the first channel hole 311. The second channel hole 312 can also have a cylindrical or columnar shape in the Z direction.

[0093] Further, as Figure 6A and Figure 7 shown, the sacrificial layer 340 can be removed based on the second channel hole 312 of the second stacked structure 202, so that the second channel hole 312 and the first channel hole 311 are at least partially connected to form the channel hole 310.

[0094] As Figure 6B shown, in an embodiment of the present application, multiple channel holes 310 can be formed not only in the storage array region 02 of the stacked structure 200, but also in the stepped region 01 of the stacked structure 200.

[0095] As Figure 7 shown, the channel structure 300 includes a channel hole 310 filled with a semiconductor layer and a composite dielectric layer. A functional layer 320 and a channel layer 330 can be formed on the inner wall of the channel hole 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0096] Specifically, a barrier layer, a charge trapping layer, and a tunneling layer can be sequentially formed on the inner wall of the channel hole 310 and the surface of the barrier layer 350, and a channel layer 330 can be formed on the surface of the tunneling layer.

[0097] The functional layer 320 may include a blocking layer that blocks the outflow of charges, a charge trapping layer on the surface of the blocking layer that stores charges during the operation of the three-dimensional memory, and a tunneling layer on the surface of the charge trapping layer. The blocking layer may include one or more layers, and the one or more layers may include one or more materials. The materials for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. The charge trapping layer may include one or more layers, and the one or more layers may include one or more materials. The materials for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide-bandgap material, etc. The tunneling layer may include one or more layers, and the one or more layers may include one or more materials. The materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc.

[0098] In some embodiments, the functional layer may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer may have a structure different from the ONO configuration. For example, the functional layer may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0099] The channel layer 330 can be used to transport the required charges (electrons or holes). According to an exemplary embodiment of the present application, the channel layer 330 can be formed on the surface of the tunneling layer by a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0100] In some embodiments, the channel layer 330 may include silicon, such as amorphous silicon, polysilicon, or single-crystalline silicon. The material of the channel layer 330 includes but is not limited to p-type doped polysilicon. Similar to the channel holes 310, the channel layer 330 also extends through the stacked structure 200 and into the substrate 100.

[0101] In one embodiment of the present application, the functional layer 320 including the blocking layer, the charge trapping layer, the tunneling layer, and the channel layer 330 penetrates the stacked structure 200 and extends into the substrate 100.

[0102] The method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application further includes: forming a channel plug (not shown) at the top of the channel hole 310 away from the substrate 100. Specifically, the channel hole 310 can be filled with a filling dielectric layer. The filling dielectric layer can include an oxidation dielectric layer, such as silicon oxide. Further, during the filling process, multiple insulating gaps can be formed in the filling dielectric layer by controlling the channel filling process to relieve the structural stress. Then, a channel plug is formed in the portion of the filling dielectric layer located at the top of the channel hole 310. The material of the channel plug can be selected to be the same as that of the channel layer 330, such as p-type doped polysilicon.

[0103] As Figures 8 to 9B shown, in an embodiment of the present application, an etching mask layer 600 can also be used to form a virtual channel hole 810, and further form a virtual channel structure 800.

[0104] Specifically, as Figure 8 shown, a third photoresist layer 702 can be formed on the etching mask layer 600 by processes such as spin coating, and correspondingly, the portion of the third photoresist layer 702 corresponding to the pattern 602 of the virtual channel hole in the patterned etching mask layer 600 (as Figure 7 shown) is removed to form a third hollow window 02 in the third photoresist layer 702.

[0105] The virtual channel hole 810 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, in some embodiments of the present application, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing. The virtual channel hole 810 is formed in the multiple stepped steps 500 of the stacked structure 200. The virtual channel hole 810 and the channel hole 310 are arranged at intervals in the X direction (the X direction can be understood as being approximately perpendicular to the Z direction and being the extending direction of the insulating layer 210 or the gate sacrificial layer 220, and can also be understood as the extending direction of the subsequently formed gate layer). The virtual channel hole 810 can also have a cylindrical or columnar shape in the Z direction and can extend into the substrate 100. After the virtual channel hole 810 is formed, the third photoresist layer 702 can be removed.

[0106] As an option, the virtual channel hole 810 can be prepared simultaneously with the second channel hole 312 (as Figure 5 shown).

[0107] Further, as Figure 9A and Figure 9BAs shown, an insulating dielectric filling layer can be used to fill the virtual channel holes through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form a virtual channel structure 800. The virtual channel structure 800 can provide strong structural support for the operation of removing the gate sacrificial layer during the subsequent gate formation process. The virtual channel structure 800 can also have a cylindrical or columnar shape in the Z direction and can extend into the substrate 100.

[0108] As Figure 9B shown, as an option, the virtual channel structure 800 can be formed in the step region 01 of the stacked structure 200.

[0109] As Figures 10 to 11B shown, in an embodiment of the present application, an etching mask layer 600 can also be used to form a gate gap 410 and further form a gate gap structure 400.

[0110] Specifically, as Figure 10 shown, a fourth photoresist layer 703 can be formed on the etching mask layer 600 by processes such as spin coating, and the corresponding part of the fourth photoresist layer 703 that corresponds to the pattern 603 of the gate gap in the patterned etching mask layer 600 (as Figure 9A shown) can be removed to form a fourth hollow window 03 in the fourth photoresist layer 703.

[0111] The gate gap 410 is formed in the stacked structure 200 and has a certain spacing from the channel hole 310 in the X direction. The gate gap 410 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate gap 410 can extend through the stacked structure 200 and penetrate the stacked structure 200 along the thickness direction (Z direction) of the stacked structure 200 and extend into the substrate 100. After the gate gap 410 is formed, the fourth photoresist layer 703 can be removed.

[0112] Further, the gate gap 410 can be used as a path for providing an etchant and a chemical precursor, and all the gate sacrificial layers 220 in the stacked structure 200 can be removed by processes such as wet etching to form a sacrificial gap.

[0113] As Figure 11A shown, in some embodiments of the present application, a gate layer 230 can be formed in the sacrificial gap by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 can be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

[0114] In addition, before forming the gate layer 230, the method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application further includes forming a dielectric layer (not shown) on the inner wall of the sacrificial gap and on the inner side wall of the gate gap 410 by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the dielectric layer can be a high-k dielectric layer. Further, a bonding layer (e.g., a titanium nitride TiN layer, not shown) can also be formed between the insulating layer 210 and the gate layer 230 or between the dielectric layer and the gate layer 230 by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0115] The gate layer 230 can extend horizontally (perpendicular to the thickness direction of the stacked structure 200) as a word line and terminate at one or more stepped structures 500 (as Figure 3 shown) of the stacked structure 200. After forming the gate layer 230, the step region 01 (as Figure 3 shown) correspondingly includes a plurality of stepped layer pairs, and each layer pair includes a gate layer 230 and an insulating layer 210.

[0116] In addition, as Figure 11A and 11B shown, in some embodiments of the present application, after forming the gate layer 230, a gate gap structure 400 can also be formed by filling the gate gap 410. Specifically, a dielectric layer can be filled in the gate gap 410 by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form the gate gap structure 400.

[0117] As Figures 11A to 13B shown, in an embodiment of the present application, conductive contact holes 911 and 912 can also be formed by using an etching mask layer 600.

[0118] Specifically, the method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application further includes: forming a word line contact 902 electrically connected to the gate layer 230 at a plurality of stepped steps 500; and forming a peripheral contact 901 that forms an ohmic contact with the well layer of the substrate 100 in the stacked structure 200. A fifth photoresist layer 704 can be formed on the etching mask layer 600 by using a process such as spin coating, and correspondingly, the portions of the fifth photoresist layer 704 corresponding to the patterns 604 and 605 of the conductive contact holes in the patterned etching mask layer 600 are removed to form a fifth hollow window 04 in the fifth photoresist layer 704.

[0119] A peripheral contact hole 911 penetrating the stacked etch layer structure 200 and extending to the periphery of the substrate 100 is formed by, for example, a dry etching process or a combination of dry and wet etching processes, and a word line contact hole 912 penetrating the stepped dielectric layer and correspondingly extending to a plurality of stepped levels (a stepped-level layer pair, each layer pair including a gate layer 230 and an insulating layer 210) is formed simultaneously by the above processes. After forming the peripheral contact hole 911 and the word line contact hole 912, the fifth photoresist layer 704 can be removed.

[0120] When forming the peripheral contact hole 911 and the word line contact hole 912, since the peripheral contact hole 911 has a greater depth than the word line contact hole 912. Therefore, the gate layer 230 can be used as an etch stop layer to ensure that the word line contact hole 912 with different depths can stop on the corresponding gate layer 230 during the etching process, so that the depth of the word line contact hole 912 no longer increases.

[0121] As Figure 13A and 13B shown, then, the peripheral contact hole 911 and the word line contact hole 912 are filled with a conductive material by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material for forming the peripheral contact 901 and the word line contact 902 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, when fabricating the peripheral contact 901 and the word line contact 902, a conductive material (e.g., titanium nitride TiN) layer may be deposited as a contact layer before depositing another conductive material.

[0122] As an option, the etch mask layer 600 (as Figure 12 shown) can be removed after forming the peripheral contact 901 and the word line contact 902. However, as another option, as Figure 13A shown, the etch mask layer 600 (as Figure 12 shown) can also be retained after forming the peripheral contact 901 and the word line contact 902. In other words, after the step of forming the functional holes or functional gaps through the above-mentioned multiple etching processes using the etch mask layer 600, the remaining etch mask retention layer 600' can be used as part of the top surface protection layer of the ultimate three-dimensional memory.

[0123] According to at least one embodiment of the present application, the manufacturing method provided by the present application simplifies the process steps and saves the manufacturing cost. At the same time, by pre-embedding an etch mask layer including a plurality of etch patterns on the upper surface of the multi-stack structure, the alignment accuracy of the etching process can be improved, the alignment error can be reduced, and the overall performance of the three-dimensional memory can be improved.

[0124] In addition, compared with the conventional preparation method that uses a multi-layer etching mask layer, the preparation method provided by this application only embeds one etching mask layer. Since the etching mask layer is relatively thin, the pattern of the etching mask layer under the photoresist layer can be directly observed during the photolithography process, so direct exposure can be performed.

[0125] Figure 16 FIG. 18 is a top view schematic diagram of a photolithography mask according to another embodiment of this application. FIG. 17 is a top view schematic diagram of a three-dimensional memory according to an embodiment of this application.

[0126] As Figure 16 shown, on the other hand, this application also provides a photolithography mask 2000. The photolithography mask 2000 may be provided with at least two of the patterns 2001 for forming the second channel holes of the three-dimensional memory, the pattern 2002 of the gate gap, the pattern 2003 of the virtual channel holes, and the pattern 2004 of the conductive contact holes. As an option, for example, a photolithography process may be used to transfer the pattern of the photolithography mask 2000 to the first photoresist layer (covering the Figure 4 surface of the etching mask layer 600 shown).

[0127] In an embodiment of this application, the pattern of the conductive contact holes 2004 includes the pattern of the word line contact holes and the pattern of the peripheral contact holes.

[0128] After that, an etching mask layer is embedded on the upper surface (the surface away from the initial substrate) of the double (or multi)-stacked structure, and a first photoresist layer is covered on the etching mask layer. Using the patterned first photoresist layer as a mask, the etching mask layer is etched. The etching mask layer may include the patterns of a plurality of holes that are pre-etched in subsequent steps. Forming a plurality of etching patterns in one etching mask layer can not only simplify the process steps and save the preparation cost, but further reduce the overlay error between the plurality of holes formed by the subsequent etching process, improve the overlay accuracy of the etching process, and improve the overall performance of the three-dimensional memory.

[0129] As Figure 15 and Figure 17As shown, the three-dimensional memory can be formed by means of the above-mentioned lithography mask 2000, and may include a stepped area 01 and a memory array area 02. As an option, the stepped area 01 may be disposed at the center of the stacked structure 200, and the memory array area 02 may be disposed at the edge of the stacked structure 200. A plurality of channel structures 300 can be formed not only in the memory array area 02 of the stacked structure 200, but also in the stepped area 01 of the stacked structure 200. The virtual channel structure 800 can be formed in the stepped area 01 of the stacked structure 200. In addition, the peripheral contacts and word line contacts 902 can also be formed in the stepped area 01 of the stacked structure 200. The channel structure 300, the virtual channel structure 800, the peripheral contacts and the word line contacts 902 may also have a cylindrical or columnar shape in the Z direction, but the above structures have different radial dimensions in a plane perpendicular to the Z direction. The gate gap structure 400 extends in a direction perpendicular to the X direction in a plane perpendicular to the Z direction, and has an extension width in the X direction. In addition, in some embodiments of the present application, the radial dimensions of the pattern of the second channel hole, the pattern of the gate gap (which can be understood as the width of the pattern), the pattern of the virtual channel hole, and the pattern of the conductive contact hole in the patterned first photoresist layer (which can be understood as Figure 16 the radial dimensions of the corresponding patterns in the lithography mask 2000 as shown) are all larger than the radial dimensions of the corresponding portions in the patterned etch mask layer 600. Specifically, the radial dimension of the pattern of the second channel hole in the patterned first photoresist layer is larger than the radial dimension of the pattern of the second channel hole in the patterned etch mask layer 600; the width of the pattern of the gate gap (the width of the pattern) in the patterned first photoresist layer is larger than the width of the pattern of the gate gap (the width of the pattern) in the patterned etch mask layer 600; the radial dimension of the pattern of the virtual channel hole in the patterned first photoresist layer is larger than the radial dimension of the pattern of the virtual channel hole in the patterned etch mask layer 600; and the radial dimension of the pattern of the conductive contact hole in the patterned first photoresist layer is larger than the radial dimension of the pattern of the conductive contact hole in the patterned etch mask layer 600.

[0130] According to at least one embodiment of the present application, the lithography mask provided by the present application can be applied to the preparation of three-dimensional memories, can simplify the steps of the three-dimensional memory preparation process, save its preparation cost. Further, an etch mask layer including a plurality of etch patterns can be pre-buried on the upper surface of the multi-stacked structure through the lithography mask, so as to improve the alignment accuracy of the etching process in the preparation of three-dimensional memories, reduce its alignment error, and improve the overall performance of three-dimensional memories.

[0131] Refer again to Figure 13A and Figure 17, on the other hand, the present application also provides a three-dimensional memory, the memory comprising: a substrate 100, a stacked structure 200, an etched mask retention layer 600', and a channel structure 300. The stacked structure 200 includes a first stacked structure and a second stacked structure, the first stacked structure is disposed on the substrate 100, and the second stacked structure is disposed on the first stacked structure. The etched mask retention layer 600' is disposed on the surface of the second stacked structure away from the substrate 100. In other words, after the above-mentioned multiple etching processes of forming functional holes or functional gaps by means of the etched mask layer 600, the remaining etched mask retention layer 600' can be used as part of the top surface protection layer of the ultimate three-dimensional memory. The channel structure 300 includes a channel hole 310 and a functional layer and a channel layer sequentially disposed on the inner wall of the channel hole 310. The channel hole 310 includes a first channel hole and a second channel hole. The first channel hole penetrates the first stacked structure and extends to the substrate 100, and the second channel hole penetrates the second stacked structure and the etched mask retention layer 600' and is at least partially aligned with the first channel hole.

[0132] As Figure 17 shown, the three-dimensional memory may include a stepped area 01 and a memory array area 02. As an option, the stepped area 01 may be disposed in the center of the stacked structure 200, and the memory array area 02 may be disposed at the edge of the stacked structure 200. According to other embodiments, the memory array area 02 may be disposed in the center of the stacked structure 200, and the stepped area 01 may be disposed at one or more side edges of the stacked structure 200. A plurality of channel structures 300 may be formed not only in the memory array area 02 of the stacked structure 200, but also in the stepped area 01 of the stacked structure 200. As an option, a virtual channel structure 800 may be formed in the stepped area 01 of the stacked structure 200. In addition, peripheral contacts and word line contacts 902 may also be formed in the stepped area 01 of the stacked structure 200. The channel structure 300, the virtual channel structure 800, the peripheral contacts and the word line contacts 902 may also have a cylindrical or columnar shape in the Z direction, but the above structures have different radial dimensions in a plane perpendicular to the Z direction. The gate gap structure 400 extends in a direction perpendicular to the X direction in a plane perpendicular to the Z direction and has an extension width in the X direction. As Figure 5 shown, in one embodiment of the present application, the second channel hole 312 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, and via the pattern 601 of the etched mask layer 600.

[0133] In one embodiment of the present application, the 3D memory further includes a gate gap structure 400, which includes a gate gap 410 and a filling dielectric layer filled in the gate gap 410, wherein the gate gap 410 penetrates through the etching mask retention layer 600' and the stacked structure 200 and extends to the substrate 100.

[0134] As Figure 9A and Figure 10 shown, in one embodiment of the present application, the gate gap 410 is formed in the stacked structure 200 and has a certain distance from the channel hole 310 in the X direction. The gate gap 410 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, and via the pattern 603 of the etching mask layer 600.

[0135] In one embodiment of the present application, the 3D memory further includes a virtual channel structure 800, which includes a virtual channel hole 810 and an insulating dielectric filling layer filled in the virtual channel hole 810, wherein the virtual channel hole 810 penetrates through the etching mask retention layer 600' and the stacked structure 200 and extends to the substrate 100.

[0136] As Figure 7 and Figure 8 shown, in one embodiment of the present application, the virtual channel hole 810 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as a patterning process including lithography, cleaning, and chemical mechanical polishing, and via the pattern 602 of the etching mask layer 600. As an option, the virtual channel hole 810 can be prepared simultaneously with the second channel hole 312 (as Figure 5 shown).

[0137] In one embodiment of the present application, the 3D memory further includes conductive contacts, which include word line contacts 902 and peripheral contacts 901. As Figure 13A shown, the stacked structure 200 includes alternately stacked gate layers 230 and insulating layers 210 that form a plurality of stepped steps. Thus, the 3D memory further includes a stepped area dielectric layer 510 covering the above stepped steps. The peripheral contact 901 includes a peripheral contact hole 911 and a conductive layer filled in the peripheral contact hole 911. The peripheral contact hole 911 penetrates through the etching mask retention layer 600' and the stepped area dielectric layer 510 and extends to the substrate 100. And the word line contact 902 includes a word line contact hole 912 and a conductive layer filled in the word line contact hole 912. Each word line contact hole 912 penetrates through the etching mask retention layer 600' and the stepped area dielectric layer 510 and extends to the corresponding stepped step.

[0138] According to at least one embodiment of the present application, the three-dimensional memory provided by the present application has relatively high overall performance and relatively low preparation cost because, during the preparation process, an etching mask layer including multiple etching patterns is pre-buried on the upper surface of the multi-layer structure, which can improve the overlay accuracy of the etching process and reduce the overlay error.

[0139] Although an exemplary method and structure of manufacturing a three-dimensional memory are described herein, it is understood that one or more features may be omitted, replaced, or added to the structure of the three-dimensional memory. For example, a conductive layer connected to the channel layer is formed in a subsequent step. In addition, the materials of the various layers exemplified are merely exemplary.

[0140] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, The method includes: forming a first stacked structure on a substrate; forming a first channel hole penetrating the first stacked structure and extending to the substrate, and filling the first channel hole with a sacrificial layer; forming a second stacked structure on the first stacked structure, and forming an etching mask layer on a surface of the second stacked structure away from the substrate; patterning the etching mask layer to form at least two of a pattern of a second channel hole, a pattern of a gate gap, a pattern of a dummy channel hole, and a pattern of a conductive contact hole in the etching mask layer, wherein patterning the etching mask layer includes: covering a first photoresist layer on the etching mask layer; and transferring a pattern of a photomask to the first photoresist layer by a photolithography process, and radial dimensions of the pattern of the second channel hole, the pattern of the gate gap, the pattern of the dummy channel hole, and the pattern of the conductive contact hole in the patterned first photoresist layer are all larger than radial dimensions of corresponding portions in the etching mask layer; and etching to form at least two of the second channel hole, the gate gap, the dummy channel hole, and the conductive contact hole using the patterned etching mask layer as a mask; wherein the second channel hole penetrates the second stacked structure and is at least partially aligned with the first channel hole to form a channel hole for accommodating a channel structure.

2. The method according to claim 1, wherein Patterning the etching mask layer further includes: etching the etching mask layer using the patterned first photoresist layer as a mask to remove portions of the etching mask layer corresponding to the pattern of the first photoresist layer and form a plurality of first hollow windows; and filling the plurality of first hollow windows with an oxide layer to form the patterned etching mask layer.

3. The method according to claim 2, wherein After filling the plurality of first hollow windows with an oxide layer to form the patterned etching mask layer, the method further includes: performing a planarization process on a surface of the patterned etching mask layer away from the substrate.

4. The method according to claim 1, wherein Etching to form the second channel hole using the patterned etching mask layer as a mask includes: forming a second photoresist layer on the patterned etching mask layer; removing a portion of the second photoresist layer corresponding to the pattern of the second channel hole in the patterned etching mask layer to form a second hollow window in the second photoresist layer; etching through the second hollow window to form the second channel hole penetrating the second stacked structure and exposing the sacrificial layer; and removing the sacrificial layer in the first channel hole through the second channel hole.

5. The method according to claim 1, wherein Etching to form the dummy channel hole using the patterned etching mask layer as a mask includes: forming a third photoresist layer on the patterned etching mask layer; removing a portion of the third photoresist layer corresponding to the pattern of the dummy channel hole in the patterned etching mask layer to form a third hollow window in the third photoresist layer; and etching through the third hollow window to form the dummy channel hole penetrating the first stacked structure and the second stacked structure and extending to the substrate.

6. The method according to claim 1, characterized in that, Etching to form the gate gap using the patterned etching mask layer as a mask includes: Form a fourth photoresist layer on the patterned etching mask layer; Remove a portion of the fourth photoresist layer corresponding to the pattern of the gate gap in the patterned etching mask layer to form a fourth hollow window in the fourth photoresist layer; and Via the fourth hollow window, etch to form the gate gap that penetrates the first stacked structure and the second stacked structure and extends to the substrate.

7. The method according to claim 1, wherein the conductive contact holes include word line contact holes and peripheral contact holes, characterized in that, Etching to form the conductive contact holes with the patterned etching mask layer as a mask includes: Form a fifth photoresist layer on the patterned etching mask layer; Remove a portion of the fifth photoresist layer corresponding to the pattern of the conductive contact hole in the patterned etching mask layer to form a fifth hollow window in the fifth photoresist layer, wherein the pattern of the conductive contact hole includes the pattern of the word line contact hole and the pattern of the peripheral contact hole; and Via the fifth hollow window, etch to form the conductive contact holes.

8. The method according to any one of claims 1 to 7, characterized in that After etching to form at least two of the second channel hole, the gate gap, the dummy channel hole, and the conductive contact hole with the patterned etching mask layer as a mask, the method further includes: Fill the second channel hole formed by etching, the gate gap formed by etching, the dummy channel hole formed by etching, or the conductive contact hole formed by etching; and Retain the etching mask layer.

9. The method according to any one of claims 1 to 7, wherein The etching mask layer is a hard mask layer.

10. The method according to any one of claims 1 to 7, wherein The thickness range of the etching mask layer is between 20 microns and 30 microns.

11. The method according to any one of claims 1 to 7, characterized in that Before filling the first channel hole with a sacrificial layer, the method further includes: Form a barrier layer on a portion of the inner wall of the channel hole located on the substrate.

12. A three-dimensional memory, characterized in that, The memory includes: A substrate; A stacked structure including a first stacked structure and a second stacked structure, wherein the first stacked structure is disposed on the substrate, and the second stacked structure is disposed on the first stacked structure; An etching mask retention layer disposed on a surface of the second stacked structure away from the substrate; and A channel structure including a channel hole and a functional layer and a channel layer sequentially disposed on the inner wall of the channel hole, Wherein, the channel hole includes a first channel hole and a second channel hole, the first channel hole penetrates the first stacked structure and extends to the substrate, and The second channel hole penetrates the second stacked structure and the etching mask retention layer and is at least partially aligned with the first channel hole.

13. The memory according to claim 12, wherein The memory further includes: A gate gap structure including a gate gap and a filling dielectric layer filled in the gate gap, wherein the gate gap penetrates the etching mask retention layer and the stacked structure and extends to the substrate.

14. The memory according to claim 12, wherein The memory further includes: A dummy channel structure including a dummy channel hole and an insulating dielectric filling layer filled in the dummy channel hole, wherein the dummy channel hole penetrates the etching mask retention layer and the stacked structure and extends to the substrate.

15. The memory according to claim 12, wherein the stacked structure includes alternately stacked gate layers and insulating layers forming a plurality of stepped levels, characterized in that, The memory further includes: A step region dielectric layer covering the stepped steps; and Peripheral contacts and a plurality of word line contacts, wherein the peripheral contacts include peripheral contact holes and a conductive layer filled in the peripheral contact holes, the peripheral contact holes penetrate through the etching mask retention layer and the step region dielectric layer and extend to the substrate, and the word line contacts include word line contact holes and a conductive layer filled in the word line contact holes, the word line contact holes penetrate through the etching mask retention layer and the step region dielectric layer and extend to the stepped steps.

16. The memory according to claim 15, wherein the stacked structure includes a storage area and a step area located at the periphery of the storage area, wherein the step area includes a plurality of the stepped steps; and the storage area includes a plurality of channel structures.

17. The memory according to claim 15, wherein the stacked structure includes a first storage area, a second storage area and a step area, wherein the step area is located between the first storage area and the second storage area and includes a plurality of the stepped steps; and the first storage area and the second storage area respectively include a plurality of channel structures.

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