A radio frequency amplifier with adjustable bias and gain

Abstract

The invention discloses a radio frequency amplifier with adjustable bias and gain, comprising: a bandgap reference, which generates a reference current voltage and outputs it to an adjustable bias current circuit; the adjustable bias current circuit, which converts the reference current voltage into an adjustable bias current required by an adjustable bias mirror module under the control of an n-k-bit digital control signal; the adjustable bias mirror module, which converts the adjustable bias current into an adjustable bias voltage required by an output stage bias adjustment circuit and an input stage under the control of a k-bit digital control signal; the output stage bias adjustment circuit, which converts the adjustable bias voltage into an output stage bias voltage required by the output stage; radio frequency input and output stages, which, under the control of the input and output stage bias voltages, cascade amplify radio frequency input signals through input and output stages to obtain radio frequency output signals; and a low voltage difference voltage stabilizing circuit.

Description

Technical Field

[0001] The invention relates to a radio frequency amplifier, in particular to a radio frequency amplifier with adjustable bias and gain. Background Art

[0002] As a key module for system signal reception, the power consumption and gain of the amplifier are crucial, affecting the minimum signal reception sensitivity and maximum signal reception capability, thus affecting the system signal reception dynamic range and energy efficiency. Therefore, the amplifier is designed with adjustable bias power consumption and gain optimization to achieve adjustable gain. By adjusting the bias and gain according to the strength of the received signal, the signal sensitivity and the maximum strength of the received signal can be improved to improve the system dynamic range, and the gain power consumption and energy efficiency can be optimized to extend the battery life.

[0003] like Figure 1 As shown, a conventional RF amplifier includes a bandgap reference (BGR) 10 , a bias mirror module 20 , a fixed bias circuit 30 , an RF input stage 40 , an RF output stage 50 and a low dropout voltage regulator (LDO) 60 .

[0004] Among them, the bandgap reference (BGR, BandGap Reference) 10 is used to generate a reference current Iref and output it to the bias mirror module 20 to generate the bias voltage required by the RF input stage 40, and the fixed bias circuit 30 is used to generate the output stage bias voltage required by the RF output stage 50; the RF input stage 50 is used to complete the preliminary amplification of the RF signal IN, and the RF output stage 50 is used to further amplify the RF signal IN amplified by the RF input stage 40 to obtain the RF output signal OUT, and the low voltage difference regulator circuit (LDO) 60 is used to generate a stable voltage Va to supply the bias mirror module 20, the fixed bias circuit 30, the RF input stage 40, and the RF output stage 50 to obtain stable performance.

[0005] Depend on Figure 1 It can be seen that both the RF input stage 40 and the RF output stage 50 use fixed bias circuits, their power consumption and gain are fixed, and they do not have variable gain. Their gain-power-consumption energy efficiency ratio cannot be adjusted, which affects energy efficiency, and the dynamic range of the received signal is fixed and cannot be expanded and adjusted. Summary of the invention

[0006] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a RF amplifier with adjustable bias and gain, which realizes variable adjustment of the bias voltage of the RF input and RF output stages, and the power consumption and gain can be digitally variable adjusted and optimized, thereby improving the energy efficiency ratio of gain and power consumption, and improving and expanding the receiving dynamic range of the adjustable system signal.

[0007] To achieve the above and other purposes, the present invention provides a radio frequency amplifier with adjustable bias and gain, comprising:

[0008] A bandgap reference, used to generate a reference current (Iref) and a reference voltage (Vref) and output them to an adjustable bias current circuit;

[0009] An adjustable bias current circuit, used for converting a reference current (Iref) and a reference voltage (Vref) into an adjustable bias current (Ipc) required by an adjustable bias mirror module under the control of an nk-bit digital control signal (CT[k+1,n]);

[0010] The adjustable bias mirror module is used to convert the adjustable bias current (Ipc) into the adjustable bias voltage (Vg) required by the output stage bias adjustment circuit and the RF input stage under the control of the k-bit digital control signal (CT[1,k]). Nin );

[0011] The output stage bias adjustment circuit is used to adjust the adjustable bias voltage (Vg Nin ) is converted into the output stage bias voltage (Vpcb) required by the output stage and transmitted to the output stage to provide the output stage gate bias voltage (Vg No );

[0012] RF input stage, for the adjustable bias voltage (Vg Nin ) to complete the initial amplification of the RF input signal (IN);

[0013] A radio frequency output stage, used for further amplifying the radio frequency input signal (IN) amplified by the radio frequency input stage to obtain a radio frequency output signal (OUT) under the control of the output stage bias voltage (Vpcb);

[0014] The low voltage difference voltage stabilizing circuit is used to generate a stable voltage to supply the adjustable bias current circuit, the adjustable bias mirror module, the output stage bias adjustment circuit, the radio frequency input stage and the radio frequency output stage.

[0015] Preferably, the adjustable bias current circuit is configured to adjust the current sampling load resistance (R cs ) adjustment to achieve adjustable output current.

[0016] Preferably, the adjustable bias current circuit includes an error amplifier, a first NMOS bias tube (N ind ), the first adjustable resistor (R cs) and a first PMOS bias tube (MPc), the output reference current (Iref) of the bandgap reference is connected to the current reference input terminal of the error amplifier, the output reference voltage (Vref) of the bandgap reference is connected to the inverting input terminal of the error amplifier, the output terminal of the error amplifier is connected to the gate of the first PMOS bias tube (MPc), the drain of the first PMOS bias tube (MPc) is connected to the first NMOS bias tube (N ind ) of the gate, the first adjustable resistor (R cs ) and the non-inverting input terminal of the error amplifier, the source and substrate of the first PMOS bias tube (MPc) are connected to the regulated power supply output by the low voltage difference voltage regulator circuit, and the first adjustable resistor (R cs ) is connected to the first NMOS bias tube (N ind ) of the drain, the first NMOS bias tube (N ind ) is connected to the adjustable bias mirror module, and the first adjustable resistor (R cs ) are respectively connected to nk-bit digital control signals (CT[k+1,n]), the positive power supply terminal of the error amplifier is connected to a regulated power supply, and the negative power supply terminal of the error amplifier is grounded.

[0017] Preferably, the adjustable bias mirror module introduces a second adjustable resistor (R T ) voltage divider feedback fine-tunes the mirror branch current and generates the adjustable bias voltage, i.e., the input stage bias voltage (Vg Nin ) is output to the output stage bias adjustment circuit and the RF input stage.

[0018] Preferably, the adjustable bias mirror module provides charge storage by adding a third NMOS bias tube (Mc), thereby improving the transient stability of the adjustable bias voltage output.

[0019] Preferably, the adjustable bias mirror module includes a second NMOS bias tube (N inb ), the second adjustable resistor (R T ), bias resistor (Rb) and third NMOS bias tube (Mc), k-bit digital control signal (CT[1,k]) is connected to the second adjustable resistor (R T ) of k control terminals, the second adjustable resistor (R T ) is connected to the second NMOS bias tube (N inb ) of the drain, the second adjustable resistor (R T ) is connected to one end of a bias resistor (Rb), and the other end of the bias resistor (Rb) is connected to the second NMOS bias tube (N inb) and the gate of the third NMOS bias tube (Mc) are connected to the output stage bias adjustment circuit and the RF input stage to form the input stage bias voltage (Vg Nin ) node, the second NMOS bias tube (N inb ) is grounded, and the drain, source and substrate of the third NMOS bias tube (Mc) are grounded and used as a MOS capacitor.

[0020] Preferably, the output stage bias adjustment circuit includes a fourth NMOS bias tube (N inm )、The third variable resistor (R p ) and a second PMOS bias tube (MPv), the fourth NMOS bias tube (N inm ) is connected to the drain of the third variable resistor (R p ) one end, the third variable resistor (R p ) is connected to the RF output stage and then connected to the gate and drain of the second PMOS bias tube (MPv) to form an output stage bias voltage (Vpcb) node, the source and substrate of the second PMOS bias tube (MPv) are connected to a regulated power supply, and the fourth NMOS bias tube (N inm )'s source is grounded.

[0021] Preferably, the RF input stage adopts an inductive negative feedback common source structure, and the RF output stage adopts a common gate structure.

[0022] Preferably, the RF input stage includes a first gate isolation resistor (Rg1), an input matching inductor (L g )、Input matching capacitor (C g ), input NMOS amplifier (N in ) and the emitter degeneration inductor (L s ), one end of the first gate isolation resistor (Rg1) is connected to the input stage bias voltage (Vg Nin ) node, and the other end is connected to the input NMOS amplifier tube (N in ) of the gate and input matching capacitors (C g ) and the input matching capacitor (C g ) through the input matching inductor (L g ) is connected to the RF input signal, the input NMOS amplifier tube (N in ) through the emitter negative feedback inductor (L s ) is grounded, the input NMOS amplifier tube (N in ) has a drain connected to the RF output stage.

[0023] Preferably, the RF output stage includes an output load inductor (L d )、output coupling capacitor (Co ), output NMOS amplifier (N o ), gate decoupling capacitor (C b ) and a second gate isolation resistor (Rg2), one end of the second isolation resistor (Rg2) is connected to the output stage bias voltage (Vpcb) node, and the other end is connected to the output NMOS amplifier tube (N o ) of the gate and gate decoupling capacitance (C b ) is connected to form the output stage gate bias voltage Vg No Node, output NMOS amplifier (N o ) of the drain connected output load inductor (L d ) and the output coupling capacitor (C o ) at one end, the output coupling capacitor (C o ) is the RF output signal, the gate decoupling capacitor (C b ) and the output load inductor (L d ) is connected to a regulated power supply.

[0024] Compared with the prior art, the bias and gain adjustable RF amplifier of the present invention can adjust the current sampling load resistance R of the voltage feedback by changing the current sampling load resistance R of the voltage feedback. cs Adjust the output current of the adjustable bias current circuit to be adjustable, and introduce a second adjustable resistor R in the self-bias path of the mirror tube through the adjustable bias mirror module. T The voltage divider feedback fine-tunes the mirror branch current to generate an adjustable bias voltage, namely the input stage bias voltage VgNin, which is output to the output stage bias adjustment circuit and the RF input stage. By adding a third NMOS bias tube Mc in the adjustable bias mirror module to provide charge storage, the transient stability of the adjustable bias voltage output is improved, and the variable adjustment of the bias voltage of the RF input and RF output stages, the power consumption and gain can be digitally variably adjusted and optimized, thereby improving the gain and power consumption energy efficiency ratio, and improving and expanding the receiving dynamic range of the adjustable system signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a circuit diagram of a traditional radio frequency amplifier;

[0026] Figure 2 The circuit structure diagram of a radio frequency amplifier with adjustable bias and gain according to the present invention;

[0027] Figure 3 It is a circuit structure diagram of a radio frequency amplifier with adjustable bias and gain in a specific embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of simulation analysis of adjustable gain and power consumption in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following describes the implementation of the present invention through specific examples and in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Figure 2 The circuit structure diagram of a radio frequency amplifier with adjustable bias and gain of the present invention is shown in FIG. Figure 3 FIG. 1 is a circuit diagram of a RF amplifier with adjustable bias and gain in a specific embodiment of the present invention. Figure 2 and Figure 3 As shown, the present invention is a radio frequency amplifier with adjustable bias and gain, including a bandgap reference (BGR) 10, an adjustable bias current circuit 20, an adjustable bias mirror module 30, an output stage bias adjustment circuit 40, a radio frequency input stage 50, a radio frequency output stage 60 and a low dropout voltage regulator circuit (LDO) 70.

[0031] The bandgap reference (BGR, BandGap Reference) 10 is used to generate a reference current Iref and a reference voltage Vref and output them to an adjustable bias current circuit 20; the adjustable bias current circuit 20 is composed of an error amplifier, a first NMOS bias transistor N ind , the first adjustable resistor (current sampling load resistor) R cs and a first PMOS bias tube MPc, which is used to convert the reference current Iref and the reference voltage Vref into the adjustable bias current Ipc required by the adjustable bias mirror module 30 under the control of the nk-bit digital control signal CT[k+1,n]; the adjustable bias mirror module 30 is composed of a second NMOS bias tube N inb , the second adjustable resistor R T , a bias resistor Rb and a third NMOS bias tube Mc, which is used to convert the adjustable bias current Ipc into an adjustable bias voltage required by the output stage bias adjustment circuit 40 and the input stage 50, that is, the input stage bias voltage Vg under the control of the k-bit digital control signal CT[1,k]. Nin Output stage bias adjustment circuit 40, by the fourth NMOS bias tube N inm , the third variable resistor R p The second PMOS bias tube MPv is used to adjust the output of the adjustable bias mirror module 30, that is, the input stage bias voltage Vg Nin The output stage bias voltage Vpcb is converted into the output stage bias voltage Vpcb required by the output stage 60 and transmitted to the output stage 60 to provide the output stage gate bias voltage Vg required by the output stage NoRF input stage 50 is an inductive-degenerated common source structure, consisting of a first gate isolation resistor Rg1, an input matching inductor L g , input matching capacitor C g , Input NMOS amplifier tube N in and emitter degeneration inductor L s The RF output stage 60 is a common-gate structure, which is composed of an output load inductor L d , output coupling capacitor C o , output NMOS amplifier tube N o , gate decoupling capacitor C b and a second gate isolation resistor Rg2, which is used to further amplify the RF input signal IN amplified by the input stage 50 to obtain the RF output signal OUT under the control of the output stage bias voltage Vpcb; a low voltage difference regulator circuit (LDO) 70 is used to generate a stable voltage Va to supply the adjustable bias current circuit 20, the adjustable bias mirror module 30, the output stage bias adjustment circuit 40, the RF input stage 50 and the RF output stage 60 to obtain a more stable gain control effect.

[0032] The input power supply Vdd is connected to the power supply input terminal of the bandgap reference (BGR) 10 and the low voltage dropout regulator circuit (LDO) 70, the output reference current Iref of the bandgap reference (BGR) 10 is connected to the current reference input terminal of the error amplifier, the output reference voltage Vref of the bandgap reference (BGR) 10 is connected to the inverting input terminal of the error amplifier, the output terminal of the error amplifier is connected to the gate of the first PMOS bias tube MPc, and the drain of the first PMOS bias tube MPc is connected to the first NMOS bias tube N ind The gate, the first adjustable resistor R cs and the non-inverting input terminal of the error amplifier, the source and substrate of the first PMOS bias tube MPc are connected to the regulated power supply Va output by the low voltage difference regulator circuit (LDO) 70, and the first adjustable resistor R cs The other end is connected to the first NMOS bias tube N ind The drain of the first NMOS bias tube N ind The source and substrate of the first adjustable resistor R cs The nk control terminals are respectively connected to the nk-bit digital control signals CT[k+1,n], the positive terminal of the power supply of the error amplifier is connected to the voltage-stabilized power supply Va, and the negative terminal of the power supply of the error amplifier is grounded. cs Adjustment is performed to achieve the adjustable output current of the adjustable bias current circuit 20.

[0033] The k-bit digital control signal CT[1,k] is connected to the second adjustable resistor R T k control terminals, the second adjustable resistor R T The other end is connected to the second NMOS bias tube N inb The drain of the second adjustable resistor R T The third end of is connected to one end of the bias resistor Rb, that is, in the present invention, the adjustable bias mirror module introduces a second adjustable resistor R in the self-bias path of the mirror tube. T The voltage divider feedback fine-tunes the mirror branch current and generates an adjustable bias voltage, namely the input stage bias voltage VgNin, which is output to the output stage bias adjustment circuit 40 and the RF input stage 50. The other end of the bias resistor Rb is connected to the second NMOS bias tube N inb The gate of the third NMOS bias tube Mc, the gate of the fourth NMOS bias tube N inm The gate of the first gate isolation resistor Rg1 is connected to form an input stage bias voltage Vg Nin Node, the second NMOS bias tube N inb The source of the third NMOS bias tube Mc is grounded, and the drain, source and substrate of the third NMOS bias tube Mc are grounded to be used as a MOS capacitor. The present invention improves the transient stability of the adjustable bias voltage output by adding the third NMOS bias tube Mc to provide charge storage.

[0034] The fourth NMOS bias tube N inm The drain of the third variable resistor R p One end of the third variable resistor R p The other end of the fourth NMOS bias tube MPv is connected to one end of the second gate isolation resistor Rg2, the gate and drain of the second PMOS bias tube MPv to form an output stage bias voltage Vpcb node, the source and substrate of the second PMOS bias tube MPv are connected to the regulated power supply Va, and the fourth NMOS bias tube N inm The source of the input stage bias voltage Vg is grounded. In the present invention, the output stage bias adjustment circuit 40 dynamically adapts the voltage output by the adjustable bias mirror module 30, that is, the input stage bias voltage Vg Nin Further generate an adjustable output stage bias voltage, namely the output stage gate bias voltage Vg No .

[0035] The other end of the first gate isolation resistor Rg1 is connected to the input NMOS amplifier tube N in The gate and input matching capacitor C g One end of the input matching capacitor C g The other end is connected through the input matching inductor L g Connected to the RF input signal IN, input NMOS amplifier tube N in The source of the emitter is negatively fed back to the inductor L s Ground, input NMOS amplifier tube Nin The drain of the output NMOS amplifier tube M o The source and substrate;

[0036] The other end of the second isolation resistor Rg2 is connected to the output NMOS amplifier tube N o The gate and gate decoupling capacitor C b One end is connected to form the output stage gate bias voltage Vg No Node, output NMOS amplifier tube N o The drain connected output load inductor L d One end and the output coupling capacitor C o One end of the output coupling capacitor C o The other end is the RF output signal OUT, the gate decoupling capacitor C b The other end of and the other end of the output load inductor Ld are connected to the regulated power supply Va.

[0037] The principle of the present invention is as follows:

[0038] 1. By changing the current sampling load resistance R of the voltage feedback cs Adjusting the output current of the adjustable bias current circuit 20 to be adjustable;

[0039] 2. The present invention introduces a second adjustable resistor R in the self-bias path of the mirror tube through an adjustable bias mirror module T The voltage divider feedback fine-tunes the mirror branch current and generates an adjustable bias voltage, namely the input stage bias voltage Vg Nin Output to the output stage bias adjustment circuit 40 and the RF input stage 50;

[0040] 3. The present invention improves the transient stability of the adjustable bias voltage output by adding a third NMOS bias tube Mc in the adjustable bias mirror module 30 to provide charge storage;

[0041] 4. The present invention dynamically adapts the voltage output by the adjustable bias mirror module 30, namely the input stage bias voltage Vg, through the output stage bias adjustment circuit 40 Nin Further generate an adjustable output stage bias voltage, namely the output stage gate bias voltage Vg No .

[0042] Figure 4 The following is a schematic diagram of simulation analysis of adjustable gain and power consumption in an embodiment of the present invention. From the simulation, it can be seen that the example results show the relationship between power consumption and gain under adjustable bias, and the gain can be changed from 13.4dB to 19.8dB when the power consumption changes from 2mA to 13mA.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art may modify and alter the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the claims.

Claims

1. A radio frequency amplifier with adjustable bias and gain, comprising: A bandgap reference, used to generate a reference current Iref and a reference voltage Vref and output them to an adjustable bias current circuit; An adjustable bias current circuit, used for converting a reference current Iref and a reference voltage Vref into an adjustable bias current Ipc required by an adjustable bias mirror module under the control of an nk-bit digital control signal CT[k+1,n]; The adjustable bias mirror module is used to convert the adjustable bias current Ipc into the adjustable bias voltage Vg required by the output stage bias adjustment circuit and the RF input stage under the control of the k-bit digital control signal CT[1,k] Nin ; The output stage bias adjustment circuit is used to adjust the adjustable bias voltage Vg output by the adjustable bias mirror module. Nin Converted into the output stage bias voltage Vpcb required by the output stage and transmitted to the output stage to provide the output stage gate bias voltage Vg required by the output stage No ; RF input stage, for the adjustable bias voltage Vg Nin The initial amplification of the RF input signal IN is completed under the action of A radio frequency output stage, used for further amplifying the radio frequency input signal IN amplified by the radio frequency input stage to obtain a radio frequency output signal OUT under the control of the output stage bias voltage Vpcb; A low voltage dropout voltage stabilizing circuit, used to generate a stable voltage to supply the adjustable bias current circuit, the adjustable bias mirror module, the output stage bias adjustment circuit, the radio frequency input stage and the radio frequency output stage; Among them, the input power supply Vdd is connected to the power input end of the bandgap reference and the low voltage difference voltage regulator circuit, the output end of the bandgap reference is connected to the input end of the adjustable bias current circuit, and the power output end of the low voltage difference voltage regulator circuit is connected to the power input end of the adjustable bias current circuit, the output stage bias adjustment circuit, the RF input stage and the RF output stage; the control end of the adjustable bias current circuit inputs an nk-bit digital control signal, the output end of the adjustable bias current circuit is connected to the input end of the adjustable bias mirror module, the control end of the adjustable bias mirror module inputs a k-bit digital control signal, the output end of the adjustable bias mirror module is connected to the output stage bias adjustment circuit and the bias voltage input end of the RF input stage, and the ground end of the adjustable bias mirror module is grounded; the output end of the output stage bias adjustment circuit is connected to the bias voltage input end of the RF output stage, the input end of the RF input stage inputs the RF input signal, the output end of the RF input stage is connected to the input end of the RF output stage, and the output end of the RF output stage outputs the RF output signal.

2. The RF amplifier with adjustable bias and gain as claimed in claim 1, characterized in that: The adjustable bias current circuit changes the current sampling load resistance R of the voltage feedback cs Adjustment makes the output current adjustable.

3. The RF amplifier with adjustable bias and gain as claimed in claim 2, characterized in that: The adjustable bias current circuit includes an error amplifier, a first NMOS bias tube N ind , the first adjustable resistor R cs and a first PMOS bias tube MPc, the output reference current Iref of the bandgap reference is connected to the current reference input terminal of the error amplifier, the output reference voltage Vref of the bandgap reference is connected to the inverting input terminal of the error amplifier, the output terminal of the error amplifier is connected to the gate of the first PMOS bias tube MPc, the drain of the first PMOS bias tube MPc is connected to the first NMOS bias tube N ind The gate, the first adjustable resistor R cs and the non-inverting input terminal of the error amplifier, the source and substrate of the first PMOS bias tube MPc are connected to the regulated power supply output by the low voltage difference voltage regulator circuit, and the first adjustable resistor R cs The other end is connected to the first NMOS bias tube N ind The drain of the first NMOS bias tube N ind The source and substrate are connected to the adjustable bias mirror module, and the first adjustable resistor R cs The nk control terminals are respectively connected to the nk-bit digital control signals CT[k+1,n], the positive power terminal of the error amplifier is connected to the regulated power supply, and the negative power terminal of the error amplifier is grounded.

4. The RF amplifier with adjustable bias and gain as claimed in claim 3, characterized in that: The adjustable bias mirror module introduces a second adjustable resistor R in the self-bias path of the mirror tube. T The voltage divider feedback fine-tunes the mirror branch current and generates the adjustable bias voltage, namely the input stage bias voltage VgNin, which is output to the output stage bias adjustment circuit and the RF input stage.

5. The RF amplifier with adjustable bias and gain as claimed in claim 4, characterized in that: The adjustable bias mirror module provides charge storage by adding a third NMOS bias tube Mc, thereby improving the transient stability of the adjustable bias voltage output.

6. The RF amplifier with adjustable bias and gain as claimed in claim 5, characterized in that: The adjustable bias mirror module includes a second NMOS bias tube N inb , the second adjustable resistor R T , bias resistor Rb and third NMOS bias transistor Mc, k-bit digital control signal CT[1,k] is connected to the second adjustable resistor R T k control terminal, the second adjustable resistor R T The other end is connected to the second NMOS bias tube N inb The drain terminal of the second adjustable resistor R T The third end of the bias resistor Rb is connected to one end of the bias resistor Rb, and the other end of the bias resistor Rb is connected to the second NMOS bias transistor N inb The gate of the third NMOS bias tube Mc is connected to the output stage bias adjustment circuit and the RF input stage to form the input stage bias voltage Vg Nin Node, the second NMOS bias tube N inb The source of is grounded, and the drain, source and substrate of the third NMOS bias tube Mc are grounded to serve as a MOS capacitor.

7. The RF amplifier with adjustable bias and gain as claimed in claim 6, characterized in that: The output stage bias adjustment circuit includes a fourth NMOS bias transistor N inm , the third variable resistor R p and the second PMOS bias tube MPv, the fourth NMOS bias tube N inm The drain of the third variable resistor R p One end of the third variable resistor R p The other end is connected to the RF output stage and then connected to the gate and drain of the second PMOS bias tube MPv to form an output stage bias voltage Vpcb node, the source and substrate of the second PMOS bias tube MPv are connected to a regulated power supply, and the fourth NMOS bias tube N inm The source is grounded.

8. The RF amplifier with adjustable bias and gain as claimed in claim 7, characterized in that: The radio frequency input stage adopts an inductive negative feedback common source structure, and the radio frequency output stage adopts a common gate structure.

9. The RF amplifier with adjustable bias and gain as claimed in claim 8, characterized in that: The RF input stage includes a first gate isolation resistor Rg1, an input matching inductor L g , input matching capacitor C g , Input NMOS amplifier tube N in and emitter degeneration inductor L s One end of the first gate isolation resistor Rg1 is connected to the input stage bias voltage Vg Nin The other end is connected to the input NMOS amplifier tube N in The gate and input matching capacitor C g One end of the input matching capacitor C g The other end is connected through the input matching inductor L g Connected to the RF input signal, the input NMOS amplifier tube N in The source of the emitter is negatively fed back to the inductor L s Ground, the input NMOS amplifier tube N in The drain of the RF output stage is connected.

10. The RF amplifier with adjustable bias and gain as claimed in claim 9, characterized in that: The RF output stage includes an output load inductor L d , output coupling capacitor C o , output NMOS amplifier tube N o , gate decoupling capacitor C b A second gate isolation resistor Rg2, one end of which is connected to the output stage bias voltage Vpcb node, and the other end is connected to the output NMOS amplifier tube N o The gate and gate decoupling capacitor C b One end is connected to form the output stage gate bias voltage Vg No Node, output NMOS amplifier tube N o The drain connected output load inductor L d One end and the output coupling capacitor C o One end of the output coupling capacitor C o The other end is the RF output signal, the gate decoupling capacitor C b The other end and the output load inductor L d The other end is connected to a regulated power supply.

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