Hardware-accelerated K-mer graph generation

Abstract

The present invention provides a method, system and apparatus for hardware-accelerating K-mer graph generation using a programmable logic device. In one aspect, the method includes the following actions: obtaining a first set of nucleic acid sequences; using the obtained first set of nucleic acid sequences and multiple non-pipeline hardware logic units of a programmable logic device to generate a K-mer graph; and after performing one or more operations by each hardware logic unit, periodically updating the graph description data of the K-mer graph using a control machine.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 006,668, filed on April 7, 2020, the entire contents of which are incorporated herein by reference. Background Art

[0003] K-mer graphs can be used to represent multiple sequencing reads. Summary of the invention

[0004] According to an innovative aspect of the present disclosure, a method for hardware-accelerating K-mer graph generation using a programmable logic device is disclosed. In one aspect, the method may include the following actions: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences includes (i) multiple reads corresponding to active regions of a reference sequence and (ii) a portion of the reference sequence; using the obtained first set of nucleic acid sequences and using multiple non-pipelined hardware logic units of a programmable logic device to generate a K-mer graph, wherein each hardware logic unit includes a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each edge of the K-mer graph represents a link between a pair of K-mers. Each weight of an edge represents the number of occurrences of a K-mer sequence represented by a pair of K-mers; and during the generation of the K-mer graph: after the one or more operations are performed by each hardware logic unit used to generate at least a portion of the K-mer graph, a control machine is used to periodically update the graph description data of the K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, wherein the control machine uses the non-pipelined hardware logic unit to create a workflow of operations by triggering each corresponding hardware logic unit to perform the one or more operations during the generation of the K-mer graph.

[0005] Other versions include corresponding systems and apparatus that have been configured to perform the actions of the aforementioned method defined by the hardware logic circuitry of the hardware accelerated graph generation unit.

[0006] These and other versions may optionally include one or more of the following features.For example, in some implementations, the output of each of the plurality of hardware logic units is stored via a hash table cache.

[0007] In some implementations, the control engine is implemented using hardware logic units of a programmable logic device.

[0008] In some implementations, the control machine is implemented using one or more CPUs or GPUs that execute software instructions to perform the functions of the control machine.

[0009] In some implementations, the operations may also include providing the generated K-mer graph to a variant calling unit, wherein the variant calling unit processes the K-mer graph to determine candidate variants between one or more reads in the plurality of reads and a reference sequence.

[0010] In some implementations, the software instructions may be executed by one or more CPUs or GPUs to implement one or more functions of the variant calling unit.

[0011] In some implementations, a programmable logic device is used to accelerate one or more functions of a variant calling unit.

[0012] In some embodiments, the graph description data also includes (iii) data representing a last hardware logic unit among multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

[0013] According to another innovative aspect of the present disclosure, a system for hardware-accelerated K-mer graph generation using a programmable logic device is disclosed. In one aspect, the system may include a hardware-accelerated graph generation unit, which includes a hardware digital logic circuit that has been arranged to perform an operation. In some specific implementations, the operation may include: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences includes (i) multiple reads corresponding to active regions of a reference sequence and (ii) a portion of the reference sequence; using the obtained first set of nucleic acid sequences and using multiple non-pipelined hardware logic units of a programmable logic device to generate a K-mer graph, wherein each hardware logic unit includes a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each edge of the K-mer graph represents a link between a pair of K-mers. Each weight of an edge represents the number of occurrences of a K-mer sequence represented by a pair of K-mers; and during the generation of the K-mer graph: after the one or more operations are performed by each hardware logic unit used to generate at least a portion of the K-mer graph, a control machine is used to periodically update the graph description data of the K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, wherein the control machine uses the non-pipelined hardware logic unit to create a workflow of operations by triggering each corresponding hardware logic unit to perform the one or more operations during the generation of the K-mer graph.

[0014] Other versions include corresponding methods and apparatus for performing the aforementioned operations.

[0015] These and other versions may optionally include one or more of the following features.For example, in some implementations, the output of each of the plurality of hardware logic units is stored via a hash table cache.

[0016] In some implementations, the operations may also include providing the generated K-mer graph to a variant calling unit, wherein the variant calling unit is configured to process the K-mer graph to determine candidate variants between one or more of the plurality of reads and a reference sequence.

[0017] In some implementations, the system may further include one or more computers and one or more memory devices storing instructions, which, when executed by the one or more computers, cause the one or more computers to perform a second operation of the variant calling unit. In some implementations, the second operation of the variant calling unit may include obtaining the generated K-mer graph by the variant calling unit, and identifying one or more candidate variants based on the variant calling unit processing the generated K-mer graph, wherein the candidate variant is a difference between the base call of one or more reads in the read pile and a reference genome nucleotide at a specific position of the reference genome.

[0018] In some specific implementations, the operation may also include obtaining a K-mer graph generated by a variant calling unit, and identifying one or more candidate variants based on the K-mer graph generated by the variant calling unit, wherein the candidate variant is a difference between a base call of one or more reads in the read stack and a reference genome nucleotide at a specific position of the reference genome.

[0019] In some embodiments, the graph description data also includes (iii) data representing a last hardware logic unit among multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

[0020] According to another innovative aspect of the present disclosure, a hardware accelerated graph generation unit is disclosed. In one aspect, the hardware accelerated graph generation unit may include a hardware digital logic circuit that has been arranged to perform an operation. In some specific implementations, the operation may include: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences includes (i) multiple reads corresponding to active regions of a reference sequence and (ii) a portion of the reference sequence; using the obtained first set of nucleic acid sequences and using multiple non-pipelined hardware logic units of a programmable logic device to generate a K-mer graph, wherein each hardware logic unit includes a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each edge of the K-mer graph Each weight of an edge represents the number of occurrences of a K-mer sequence represented by a pair of K-mers; and during the generation of the K-mer graph: after the one or more operations are performed by each hardware logic unit used to generate at least a portion of the K-mer graph, a control machine is used to periodically update the graph description data of the K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, wherein the control machine uses the non-pipelined hardware logic unit to create a workflow of operations by triggering each corresponding hardware logic unit to perform the one or more operations during the generation of the K-mer graph.

[0021] Other implementations may include methods and systems configured to perform operations of hardware circuitry of a hardware accelerated graph generation unit.

[0022] These and other versions may optionally include one or more of the following features.For example, in some implementations, the output of each of the plurality of hardware logic units is stored via a hash table cache.

[0023] In some implementations, the operations may also include providing the generated K-mer graph to a variant calling unit, wherein the variant calling unit is configured to process the K-mer graph to determine candidate variants between one or more of the plurality of reads and a reference sequence.

[0024] In some specific implementations, the operation may also include obtaining the generated K-mer graph by the variant calling unit, and identifying one or more candidate variants based on the variant calling unit processing the generated K-mer graph, wherein the candidate variant is a difference between the base call of one or more reads in the read stack and the reference genome nucleotide at a specific position of the reference genome.

[0025] In some embodiments, the graph description data also includes (iii) data representing a last hardware logic unit among multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

[0026] According to another innovative aspect of the present disclosure, a method for hardware-accelerated K-mer graph generation in a programmable logic device is disclosed. In one aspect, the method may include the following actions: obtaining a first group of nucleic acid sequences, wherein the first group of nucleic acid sequences includes (i) a plurality of read segments corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; for each specific nucleic acid sequence of the first group of nucleic acid sequences: generating data for storage in a hash table cache by a first hardware logic unit, the data representing a graph node of each K-mer of the specific nucleic acid sequence; detecting by a control machine that the first hardware logic unit has completed the generation of a graph node for each K-mer of the specific nucleic acid sequence; configuring a second hardware logic unit by the control machine to perform graph edge generation on the generated graph nodes; and for one or more pairs of generated graph nodes: generating data for storage in a graph hash table by a second hardware logic unit, the data representing a graph edge between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph node of each K-mer stored in the hash table cache and the data representing the graph edge stored in the hash table cache represent a K-mer graph of the first group of nucleic acid sequences.

[0027] Other versions include corresponding systems and apparatus that have been configured to perform the actions of the aforementioned method defined by the hardware logic circuitry of the hardware accelerated graph generation unit.

[0028] These and other versions may optionally include one or more of the following features. For example, in some implementations, the method may further include periodically storing, by a control machine and in a memory unit accessible by the control machine, graph description data for an instance of a K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information.

[0029] In some specific implementations, the first hardware logic unit can also be configured to: determine whether one or more specific K-mers among the specific K-mers of a specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, and based on determining that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, store data marking the one or more specific K-mers as non-unique K-mers.

[0030] In some implementations, the second hardware logic is further configured to assign an edge weight to each edge of the K-mer graph.

[0031] In some specific implementations, the method may also include instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: obtain data representing the K-mer graph from the hash table cache, and provide the obtained data representing the K-mer graph to the variant detection unit.

[0032] In some specific implementations, the method may also include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to: selectively delete data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

[0033] In some specific implementations, the control engine is implemented using a third hardware logic unit of the programmable logic device.

[0034] In some implementations, the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

[0035] In some implementations, the control machine is implemented using one or more CPUs or GPUs that execute software instructions to perform the functions of the control machine.

[0036] In some embodiments, the graph description data also includes (iii) data representing a last hardware logic unit among multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

[0037] In some implementations, the method may further include evaluating the K-mer graph to check for the presence of a graph cycle. In such implementations, if a graph cycle is detected during the evaluation: the process may include terminating the generation of the K-mer graph. Alternatively, if a graph cycle is not detected during the evaluation: the method may include obtaining data describing the structure of the K-mer graph from a hash table cache, and providing the obtained data describing the structure of the K-mer graph to the variant calling module.

[0038] According to another innovative aspect of the present disclosure, a system for hardware-accelerating K-mer graph generation using a programmable logic device is disclosed. The system may include a hardware-accelerated graph generation unit, which includes a hardware digital logic circuit that has been arranged to perform an operation. In one aspect, the operation may include: obtaining a first group of nucleic acid sequences, wherein the first group of nucleic acid sequences includes (i) multiple read segments corresponding to active regions of a reference sequence and (ii) a portion of the reference sequence; for each specific nucleic acid sequence of the first group of nucleic acid sequences: generating data for storage in a hash table cache by a first hardware logic unit, the data representing a graph node of each K-mer of the specific nucleic acid sequence; detecting by a control machine that the first hardware logic unit has completed the generation of graph nodes for each K-mer of the specific nucleic acid sequence; configuring a second hardware logic unit by the control machine to perform graph edge generation on the generated graph nodes; and for one or more pairs of generated graph nodes: generating data for storage in a graph hash table by a second hardware logic unit, the data representing a graph edge between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph node of each K-mer stored in the hash table cache and the data representing the graph edge stored in the hash table cache represent a K-mer graph of the first group of nucleic acid sequences.

[0039] Other versions include corresponding methods and apparatus for performing the aforementioned operations.

[0040] These and other versions may optionally include one or more of the following features. For example, in some implementations, operations may also include periodically storing, by the control engine and in a memory unit accessible by the control engine, graph description data for an instance of a K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information.

[0041] In some specific implementations, the first hardware logic unit is also configured to: determine whether one or more specific K-mers among the specific K-mers of a specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, and based on determining that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, store data marking the one or more specific K-mers as non-unique K-mers.

[0042] In some implementations, the second hardware logic is further configured to assign an edge weight to each edge of the K-mer graph.

[0043] In some specific implementations, the operation may also include instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: obtain data representing the K-mer graph from the hash table cache, and provide the obtained data representing the K-mer graph to the variant detection unit.

[0044] In some implementations, the operations may also include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to selectively delete data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

[0045] In some implementations, the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

[0046] In some embodiments, the graph description data also includes (iii) data representing a last hardware logic unit among multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

[0047] In some implementations, the method may further include evaluating the K-mer graph to check for the presence of a graph cycle. In such implementations, if a graph cycle is detected during the evaluation: the process may include terminating the generation of the K-mer graph. Alternatively, if a graph cycle is not detected during the evaluation: the method may include obtaining data describing the structure of the K-mer graph from a hash table cache, and providing the obtained data describing the structure of the K-mer graph to the variant calling module.

[0048] According to another innovative aspect of the present disclosure, a hardware accelerated graph generation unit is disclosed. The hardware accelerated graph generation unit may include a hardware digital logic circuit that has been arranged to perform an operation. In one aspect, the operation may include: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences includes (i) a plurality of read segments corresponding to an active region of a reference sequence and (ii) a portion of a reference sequence; for each specific nucleic acid sequence of the first set of nucleic acid sequences: generating data for storage in a hash table cache by a first hardware logic unit, the data representing a graph node of each K-mer of the specific nucleic acid sequence; detecting by a control machine that the first hardware logic unit has completed the generation of a graph node for each K-mer of the specific nucleic acid sequence; configuring a second hardware logic unit by the control machine to perform graph edge generation on the generated graph nodes; and for one or more pairs of generated graph nodes: generating data for storage in a graph hash table by a second hardware logic unit, the data representing a graph edge between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph node of each K-mer stored in the hash table cache and the data representing the graph edge stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences.

[0049] Other implementations may include methods and systems configured to perform operations of hardware circuitry of a hardware accelerated graph generation unit.

[0050] These and other versions may optionally include one or more of the following features. For example, in some implementations, operations may also include periodically storing, by the control engine and in a memory unit accessible by the control engine, graph description data for an instance of a K-mer graph, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information.

[0051] In some specific implementations, the first hardware logic unit may be configured to: determine whether one or more specific K-mers among the specific K-mers of a specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, and based on determining that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, store data marking the one or more specific K-mers as non-unique K-mers.

[0052] In some implementations, the second hardware logic is further configured to assign an edge weight to each edge of the K-mer graph.

[0053] In some specific implementations, the operation may also include instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: obtain data representing the K-mer graph from the hash table cache, and provide the obtained data representing the K-mer graph to the variant detection unit.

[0054] In some implementations, the operations may also include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to selectively delete data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache.

[0055] In some implementations, the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

[0056] In some embodiments, the graph description data also includes (iii) data representing a last hardware logic unit among multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

[0057] In some embodiments, the operation may also include evaluating the K-mer graph to check for the presence of a graph cycle, and if a graph cycle is detected during the evaluation: terminating the generation of the K-mer graph, or if no graph cycle is detected during the evaluation: obtaining data describing the structure of the K-mer graph from a hash table cache, and providing the obtained data describing the structure of the K-mer graph to the variant detection module.

[0058] These and other aspects of the disclosure are discussed in more detail below in the detailed description with reference to the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is an example of a system for hardware-accelerated K-mer graph generation.

[0060] Figure 2 is a flow chart of an example of a process for hardware accelerated K-mer graph generation.

[0061] Figure 3 is a flow chart of another example of a process for hardware accelerated K-mer graph generation.

[0062] Figure 4 is an example of a K-mer graph.

[0063] Figure 5 is a block diagram of an example of system components that may be used to hardware accelerate K-mer graph generation. DETAILED DESCRIPTION

[0064] The present disclosure is directed to hardware accelerated K-mer graph generation. Using hardware circuits to generate K-mer graphs significantly reduces the amount of time required to generate K-mer graphs, and offloads the computationally intensive K-mer graph generation process from a software processor to the hardware logic of an integrated circuit (such as a field programmable gate array or ASIC). This frees up software resources of the software processor for use in performing other genomic data processing tasks.

[0065] Hardware accelerated K-mer graph generation can be implemented using a control machine configured to manage a workflow of operations performed by multiple non-pipeline hardware logic units. Specifically, the control machine can use multiple non-pipeline hardware logic units to abstractly implement high-level pipeline functions. The control machine can implement this function by storing and updating graph description data, which includes (i) a K-mer graph identifier that identifies an instance of a K-mer graph and (ii) K-mer graph state information. The K-mer graph state information may include, for example, data indicating the last hardware logic unit that operates on the original graph data of a specific instance of the K-mer graph, data indicating whether the last hardware logic unit terminates the operation, data indicating the length of the K-mer, data indicating a K-mer node list, data indicating a pointer list that can be used to identify a K-mer node in a cache, the length of the K-mer node list, data indicating a list of non-unique K-mers, or any subset or combination thereof. The control machine manages K-mer graph generation by calling a specific hardware logic unit that will perform operations on the original graph data and providing a set of updated graph description data to the called hardware logic unit.

[0066] This storage and updating of graph description data enables the control engine to manage the parallel processing of non-pipelined hardware logic units in a manner that enables each non-pipelined hardware logic unit to operate on data corresponding to a different K-mer graph. Therefore, in addition to the increased speed benefits achieved by using hardware logic rather than executing software instructions to generate K-mer graphs, the present disclosure increases throughput by using different hardware logic units managed by the control engine to simultaneously generate fragments of different K-mer graphs, thereby achieving further accelerated operation.

[0067] Figure 1is an example of a system 100 for hardware accelerated K-mer graph generation. In some implementations, the system 100 may include a nucleic acid sequencer 110, a reference sequence database 120, a hardware accelerated graph generation unit 130, a plurality of hardware logic units 131, 132, 133, 134, 135, 136, 137, 138, a control machine 140, a graph hash table cache 150, a DRAM 160, and a variant detection unit 180. In some implementations, the hardware accelerated graph generation unit 130 may be implemented using a programmable logic circuit such as a field programmable gate array (FPGA). In other implementations, the hardware accelerated graph generation unit 130 may be implemented using an application specific integrated circuit (ASIC). In either case, the functions described with respect to the hardware accelerated graph generation unit 130 and each component implemented thereon are implemented using a hardware logic circuit that is arranged to implement the functions described herein without executing software instructions to implement the functions.

[0068] The term "unit" is used in this specification to describe a software module, a hardware module, or a combination of the two for performing a specified function. Whether a specific "unit" described herein is hardware, software, or a combination of the two can be determined based on the context in which it is used. For example, the "input unit" 131, "graph node unit" 132, "graph edge unit" 133, etc. residing in a hardware accelerated graph generation unit 130 implemented using an FPGA or ASIC are hardware units whose functions are implemented by hard-wired digital logic gates or hard-wired digital logic blocks that have been arranged to implement the functions described herein with respect to the specific "unit". For example, an unused Figure 1 The “variant calling unit” 180 implemented by the hardware accelerated map generation unit 130 in the embodiment is a software module, and its functions are implemented by one or more computers executing software instructions defining the functions of the “variant calling unit” 180. As another example, a computer or a processing unit may be a hardware device that implements functions by processing software instructions, and thus the functions of a computer or a processing unit are a combination of hardware and software.

[0069] Although Figure 1 Examples of one or more components in are provided herein as hardware implementations such as a “control machine” 140, but since the “control machine” is Figure 1 140 is shown as being implemented in a hardware accelerated graph generation unit 130, and thus the present disclosure is not limited to such examples. Instead, other specific implementations may be employed in which the "control machine" 140 is implemented in software as a software module or a combination of hardware and software, and a computer or processing unit executes software instructions to implement the functions of the "control machine" 140 described herein. Likewise, there may be specific implementations of the present disclosure in which relative to Figure 1Certain components described as software, such as the "variant calling unit" 180, are implemented as hardware implementations.

[0070] The nucleic acid sequencer 110 is a device configured to perform preliminary analysis. The preliminary analysis may include receiving a biological sample 105 such as a blood sample, a tissue sample, saliva, or nucleic acid by the nucleic acid sequencer 110, and generating output data such as one or more reads 112 by the nucleic acid sequencer 110, each read representing the nucleotide sequence of the nucleic acid sequence of the received biological sample. In some embodiments, sequencing performed by the nucleic acid sequencer 110 may be performed in multiple read cycles, wherein a first read cycle generates one or more first reads including a string of base calls representing the nucleotide sequence from a first end of a nucleic acid sequence fragment, and a second read cycle generates one or more corresponding second reads including a string of base calls representing the nucleotide sequence from the other end of one of the nucleic acid sequence fragments. In some embodiments, reads may be generated using clonal amplification. In Figure 1 In the example of , one or more reads 112 may include an accumulation of reads for a particular reference genome position, where the reference genome position consists of a plurality of contiguous reference genome positions.

[0071] Therefore, each read is data representing a portion of a nucleic acid genome of an organism such as an animal, an insect, a plant, etc. Assuming that a short nucleic acid sequence fragment of about 600 bases is detected, the first read may represent 150 ordered nucleotides at the first end of the nucleic acid sequence fragment, and the second read may represent 150 ordered nucleotides at the other end of the nucleic acid sequence fragment. However, these numbers are merely examples, and any nucleic acid sequencer 110 may be configured to generate reads that can be operated using any sequencing method by a hardware-accelerated graph generation unit as described herein. The length of such reads may be different from the length mentioned herein. For example, in some specific implementations, the present disclosure may be used to generate a hardware-accelerated K-mer graph for reads, and the reads are generated by nucleic acid sequence fragments having up to 1000 or more nucleotides, wherein each read has, for example, 50 base calls, 75 base calls, 150 base calls, 200 base calls, 300 base calls, 500 base calls, or more base calls from the end of each fragment. Each base call may correspond to one nucleotide. The present disclosure can also be used to generate hardware accelerated K-mer graphs for long reads. Therefore, the hardware accelerated graph generation unit 130 can be used to generate K-mer graphs for any reads generated in any manner by any type of nucleic acid sequencer.

[0072] In some implementations, the biological sample 105 may include a DNA sample, and the nucleic acid sequencer 110 may include a DNA sequencer. In such implementations, the order of ordered nucleotides in the reads generated by the nucleic acid sequencer may include one or more of guanine (G), cytosine (C), adenine (A), and thymine (T) in any combination. In some implementations, the nucleic acid sequencer 110 may be used to sequence RNA samples. In some implementations, this can be performed using an RNA-seq protocol. By way of example, an RNA sample may be pretreated using a reverse transcriptase to form complementary DNA (cDNA) using a reverse transcriptase. In other implementations, the nucleic acid sequencer 110 may include an RNA sequencer, and the biological sample may include an RNA sample. Therefore, although Figure 1 The example of describes a nucleic acid sequencer that generates a read consisting of G, C, A, and T based on a DNA sample by a DNA sequencer, but the present disclosure is not limited thereto. In contrast, other specific implementations may process a read consisting of C, G, A, and U generated by an RNA sequencer based on an RNA sample. In some specific implementations, a DNA read or RNA read generated by a nucleic acid sequencer may include a base call N, where N indicates an unknown base call generated by the nucleic acid sequencer.

[0073] In some implementations, the nucleic acid sequencer 110 may include a next generation sequencer (NGS) configured to generate sequence reads such as reads 112 for a given sample using massively parallel sequencing technology in a manner that achieves ultra-high throughput, scalability, and speed. NGS enables rapid sequencing of entire genomes, the ability to scale up to target regions for deep sequencing, discovery of novel RNA variants and splice sites using RNA sequencing (RNA-Seq), or quantification of mRNA for gene expression analysis, analysis of epigenetic factors such as genome-wide DNA methylation and DNA-protein interactions, sequencing of cancer samples to study rare somatic variants and tumor subclones, and study of microbial diversity in humans or the environment.

[0074] The nucleic acid sequencer 110 may obtain a reference genome 122 from a reference genome database 122. In some implementations, only a portion of the reference genome 122 is obtained. A portion of the reference genome 122 obtained may correspond to a reference position of the reference genome 122, to which the accumulation of reads 112 is mapped and aligned. The reference genome database 122 may include a data storage for organizing the storage of multiple different reference genomes. In some implementations, a specific reference genome 122 selected from the reference genome database may be based on the type of DNA sample 105. In some implementations, the type of the selected reference genome 122 selected from the reference genome database 120 may be selected based on input from a user of the nucleic acid sequencer 110. In such implementations, a user may, for example, select a reference genome 120 identifier that can be used by the nucleic acid sequencer 110 to select a specific reference genome 122 from the reference genome database 120. The reference genome 122 may include, for example, a nucleic acid sequence assembled as a representative example of a set of genes for a specific species.

[0075] The combination of the pile of reads 112 generated by the nucleic acid sequencer 110 and the obtained reference genome 122 may be provided as an input to the hardware accelerated graph generation unit 130. These inputs may be processed by one or more of the hardware logic units 131 to 138 of the hardware accelerated graph generation unit 130 to generate an instance of a K-mer graph. For example, each of the hardware logic units 131 to 138 may be configured to perform its corresponding operation on each read of the pile of reads 112 included as an input to the hardware accelerated graph generation unit 130.

[0076] Figure 1 The system 100 is described herein as including a nucleic acid sequencer. In some embodiments, such as reference Figure 1 As described, the system may include a sequencer 110 and a hardware-accelerated graph generation unit 130, and the other components of the system 100 may be integrated within the nucleic acid sequencer 110. However, the present disclosure is not limited to integration within the nucleic acid sequencer 110. Rather, in some implementations, the hardware-accelerated graph generation unit 130 may be implemented in a programmable logic device or ASIC that is integrated or housed within a computer remote from the nucleic acid sequencer 110 and communicatively coupled to the nucleic acid sequencer 110, such as by using one or more wired or wireless networks. Similarly, the database 120, the variant detection unit 180, or both may be implemented externally to the nucleic acid sequencer 110. Likewise, the system 100 is not required to include the nucleic acid sequencer 110 at all. Rather, in some implementations, the hardware-accelerated graph generation unit 130 and Figure 1Other components of the system 100 may be implemented in a computer system that does not include the nucleic acid sequencer 110. In such a specific implementation, the hardware accelerated graph generation unit may obtain the accumulation of the read segments 112, the reference sequence 122, or both, etc. from one or more storage locations of one or more memory devices via a network. Therefore, the system 100 illustrates an example of the present disclosure, but does not limit the present disclosure to any one specific configuration of the system components.

[0077] One or more hardware logic units of the hardware accelerated graph generation unit 130 may include an input unit 131, a graph node unit 132, a graph edge unit 133, a back-propagation unit 134, a loop unit 135, a pruning unit 136, a graph output unit 137, and an erasing unit 138. In some implementations, generating a K-mer graph by the hardware accelerated graph generation unit 130 may include the control engine 140 activating and configuring each of the hardware logic units 131 to 138 to perform its corresponding hardware logic operation on a set of data stored in the cache 150 or the DRAM 160. In other implementations, the control engine 140 may activate and configure only a subset of the hardware logic units 131 to 138 to perform its corresponding hardware logic operation on a set of original graph data stored in the cache 150 or the DRAM 160.

[0078] By way of example, in some implementations, the hardware accelerated graph generation unit 130 may be used to generate a special form of the Debreing graph. This special form of the Debreing graph may be optimized so that non-unique K-mers are represented in the graph using multiple corresponding nodes, each node having a single edge, rather than being represented by a single node with multiple edges. This may be achieved in part by using the graph unit 132 to identify non-unique K-mers and mark the non-unique K-mers for further processing. Non-unique K-mers may be defined as K-mer sequences that appear at least twice in any single read or at least twice in a reference sequence. Unique K-mers will not appear more than once in the same read, but may still appear in multiple reads.

[0079] However, in other implementations, a De Blain graph may be generated without distinguishing between unique or non-unique K-mers. Therefore, in some implementations, it is not necessary to implement a graph node unit 132 that can identify non-unique K-mers. In another example, the back propagation unit 134 does not need to be used to generate all K-mer graphs. Instead, the back propagation unit 134 may be limited to implementations in which it can improve performance. By way of example, the back propagation unit 134 may be used to improve the quality of edge weights when the K-mer graph generated is subsequently converted to a sequence graph in anticipation.

[0080] Relative to Figure 1The example of K-mer graph generation described in the example of shows each hardware logic unit 131 to 138 that can be activated and configured by the control machine 140. In this description, each hardware logic unit 131 to 138 is generally described as being activated by the control machine 140, configured by the control machine 140, using, for example, graph description data stored by the control machine 140, obtaining original graph data, performing one or more specific processing operations on the obtained original graph data or other data, and then updating the original graph data, graph description data, or both, and the present disclosure is not limited to this. However, the present disclosure is not limited to such specific implementations. On the contrary, in some specific implementations, each hardware logic unit 131 to 138 may be configured to perform multiple instances of its corresponding function. For example, the graph node unit 132 may be configured to accept up to 3 sets of different original graph data and perform its operations on these original graph data simultaneously, the loop hardware logic unit 135 may be configured to accept up to 3 sets of different original graph data and perform its operations on these original graph data simultaneously, and the PRU may be configured to accept up to 2 sets of different original graph data and perform its operations on these original graph data simultaneously. The number of different groups of raw graph data, each corresponding to a different K-mer graph, that can be received and processed by a particular hardware logic unit 131 to 138 is limited only by the available hardware resources of the system 100. For example, assuming sufficient levels of DRAM and FPGA logic units are available, the number of different groups of raw graph data that can be received and simultaneously processed by a hardware logic unit 131 to 138 can be greater than 3. Likewise, if such resources are not readily available or if a particular hardware logic unit is not expected to be heavily used, one or more hardware logic units 131 to 138 can be configured to receive and simultaneously process a lower number of groups of raw graph data.

[0081] In other specific implementations, it is not required that each hardware logic unit 131 to 138 has only one instance, and each hardware logic unit can simultaneously process different groups of original graph data corresponding to different K-mer graphs. On the contrary, in some specific implementations, multiple instances of each hardware accelerated graph generation unit 130 can be configured to include multiple instances of one or more hardware logic units in the hardware logic units 131 to 138. In such instances, the control engine 140 can be configured to monitor the status and availability of each hardware logic unit 131 to 138, and then activate and configure each hardware logic unit in a manner that load balances processing operations across each corresponding hardware logic unit. For example, in some specific implementations, the hardware accelerated graph generation unit 130 may be configured to have: 3 instances of a graph node unit 132, each instance being capable of receiving up to 3 different sets of original graph data and performing its operations on these original graph data simultaneously; 3 instances of a graph edge unit 133, each instance being capable of receiving up to 3 different sets of original graph data and performing its operations on these original graph data simultaneously; 2 back propagation units 134, each back propagation unit being capable of receiving up to 2 different sets of original graph data and performing its operations on these original graph data simultaneously; and 3 loop units 135, each loop unit being capable of receiving up to 2 different sets of original graph data and performing its operations on these original graph data simultaneously. The activation / deactivation of each hardware logic unit, the configuration of each hardware logic unit, the input of each hardware logic unit, the output of each hardware logic unit, and the update of the graph description data by each hardware logic unit are managed and directed by the control engine 140.

[0082] Input unit

[0083] The input unit 131 may receive input data including a stack of generated reads 112 and a selected reference genome 122, which may be referred to herein as raw graph data. The selected reference genome 122 may include a portion of a reference genome. The raw graph data may include, for example, data processed by one or more hardware logic units 131 to 138 during an instance of generating a K-mer graph. Although the raw graph data includes, for example, the generated reads 112 and the selected reference genome 122, the raw graph data may also include, for example, K-mer nodes generated by the graph node unit 132, edges generated by the graph edge unit 133, and the like. The input unit 131 may format the generated reads 112 and the obtained reference genome 122 for storage in the DRAM 160. Formatting the generated reads may include, for example, encoding the reads for storage in the DRAM 160. In some specific implementations, encoding the reads may include encoding each base call corresponding to the nucleotides of the reads as a 4-bit value. For example, A may be encoded as 0000, C may be encoded as 0001, G may be encoded as 0010, T may be encoded as 0011, and N may be encoded as 0100, where N is an unknown base call. In some implementations, the encoded data may also include data representing a MAPQ score, a read number, a sequence length, a SAM tag, a base call or nucleotide of the read, one or more quality indicators of the read other than the MAPQ score, or any combination thereof. The encoded read data may range from a 16-bit value to a 64-bit value or more describing the read. The input unit 131 may write the generated reads to the DRAM 160.

[0084] The control engine 140 may detect receipt of raw input data, activate input unit 131, and initialize graph description data corresponding to an instance of a K-mer graph to be generated based on the raw input data. Activating input unit 131 may include the control engine 140 sending one or more control messages to input unit 131, the one or more control messages instructing input unit 131 to perform operations defined by the hardware logic circuit of input unit 131 on the raw data provided as input to input unit 131. In some specific implementations, activating a hardware logic unit such as input unit 131 may also include the control engine providing the hardware logic unit with graph description data that can be used to configure the hardware logic unit to perform its operations. Configuring the hardware logic unit may include, for example, providing a pointer to a cache storage location storing a K-mer, a K-mer node, providing information describing the length of the K-mer, or similar information that the hardware logic unit needs to operate.

[0085] Initialization graph description data may include, for example, a K-mer graph identifier for raw input data generated by the control engine 140, a generated graph state information data structure, or a combination thereof. The K-mer graph identifier includes a data string of one or more characters, one or more numbers, or a combination thereof, which can be used to identify an instance of a K-mer graph during the entire K-mer graph generation process after the K-mer graph is generated for a particular set of raw graph data, wherein the K-mer graph generation process is from the time when the input unit 131 receives the raw graph data to at least the time when the erase unit 138 is used to remove data associated with the K-mer graph identifier from the cache 150, DRAM 160, or both. In some specific implementations, the K-mer graph identifier may include a number, such as a 6-digit number with a value between 0-63. In some specific implementations, the K-mer graph identifier may be used to refer to the K-mer graph even after the erase unit is used to remove the aforementioned data from the cache 150, DRAM 160, or both. The graph state information data structure is a data structure having one or more fields that store data describing the current state of an instance of a K-mer graph to be generated for a particular set of raw input data. The status information may include, for example, data indicating the last hardware logic unit that operated on the raw graph data of a particular instance of a K-mer graph, data indicating whether the last hardware logic unit terminated the operation, data indicating the length of the K-mer, data indicating a list of K-mer nodes, data indicating a list of pointers that can be used to identify K-mer nodes in a cache, the length of the list of K-mer nodes, data indicating a list of non-unique K-mers, data indicating the location of the raw input data in a cache or DRAM, data indicating the base address of the nodes of the K-mer graph instance in DRAM, or any subset or combination thereof.

[0086] The input unit 131 may format the input reads 112 and the reference genome 122 and write the input reads 112 and the reference genome to the DRAM 160. The control engine 140 may detect when the input unit 131 has completed formatting the input reads 112 and the reference genome 122 and writing them to the DRAM 160. After the control engine 140 detects that the formatting of the input reads 112 and the reference genome 122 and writing them to the DRAM is complete, the control engine 140 may update the graph state information to indicate that the input unit 131 has completed its operation on the first raw graph data of the first instance of the K-mer graph.

[0087] Once the first raw graph data has been input, formatted, and stored in DRAM 160, the control engine 140 may determine the next hardware logic unit to be activated and configured. For example, the control engine 140 may activate and configure the graph node unit 132 to generate a K-mer node based on a portion of the reference genome 122 and the read segment pile formatted and stored in DRAM 160.

[0088] Graph Node Unit

[0089] The control engine 140 can activate and configure the graph node unit 132 to continue generating the first instance of the K-mer graph by processing the formatted read segments 112 and the reference genome 122 stored in the DRAM. This may include, for example, sending a control signal to the graph node unit 132, providing graph description data to the graph node unit 132, or a combination thereof. The graph description data can be used to configure the graph node unit 132 for operation. For example, providing graph description data to the graph node unit 132 and from the control engine 140 can configure the graph node unit 132 to identify K-mers of a specific size defined by the graph description data. Other fields of the graph description data described herein can be used to configure hardware logic units such as the graph node unit 132 in a similar manner.

[0090] In addition, the control engine 140 can detect in a substantially parallel manner that the input unit 131 receives the second raw graph data as input. Then, the control engine 140 can activate the input unit 131, instruct the unit 131 to format the read segment and the reference genome of the second raw graph data, and generate the second graph description data for the second instance of the K-mer graph to be generated based on the second raw graph data. Therefore, the control engine 140 can achieve a high level of throughput by simultaneously managing the performance of different hardware logic units 131 and 132, which perform the generation process of the K-mer graph on different groups of raw graph data at different processing stages. The control engine 140 is configured to manage this parallel function across each of the hardware logic units 131, 132, 133, 134, 135, 136, 137, and 138, so that at any particular point in time, there may be up to eight hardware logic units operating on eight different groups of raw graph data, where the hardware accelerated graph generation unit 130 is dedicated to generating eight different K-mer graphs simultaneously. The control engine 140 manages the entire process by activating and configuring each corresponding hardware logic unit using the graph description data to abstractly implement high-level pipeline functions from the non-pipeline hardware logic units 131, 132, 133, 134, 135, 136, 137, 138, which makes it possible to have no direct and physical input / output connection between each corresponding hardware logic unit. Although an example of performing eight K-mer graphs simultaneously is shown, the present disclosure can be configured to implement more K-mer graphs simultaneously, such as by implementing multiple hardware accelerated graph generation units 130 at a time, implementing multiple instances of multiple hardware logic units on one or more hardware accelerated graph generation units 130, or a combination thereof.

[0091] The graph node unit 132 may analyze each of the read segments 112 stacked up to identify each K-mer of the read segment. This may include, for example, sliding a K-mer access window along each position of each read segment to identify each specific K-mer of the corresponding read segment. For each identified K-mer of each read segment, the graph node unit 132 may store data representing a node of the K-mer graph in the cache 150. Similarly, the graph node unit 132 may also generate and store a list of node pointers in a data structure of node pointers in DRAM, wherein each node pointer points to a K-mer node cache location. The graph node unit 132 may also generate and store information indicating the location and length of a list of node pointers for each K-mer graph in the graph description data maintained by the control machine. These pointers may be used by the control machine 140 as graph state information to configure another hardware logic unit during a subsequent portion of the K-mer graph generation process. Cache 150 may employ one or more cache coherence policies, such as an LRU cache coherence policy configured to evict the oldest objects from cache 150 , where the oldest objects are determined based on when the objects were written to cache 150 .

[0092] Example references to data generated by graph node unit 132 and stored in cache 150, DRAM 160, or both Figure 4 shown. Figure 4 A reference genome 410, a portion of reads 420 are shown and a Debreyin graph 400 is provided. The Debreyin graph 400, described in more detail below, includes a node for each K-mer in the portion of the genome 410 and reads 420 and an edge between each pair of K-mer nodes connecting a pair of nodes having k-1 overlapping nucleotides.

[0093] refer to Figure 4 For example, the graph node unit 132 may generate data of nodes 431, 432, 433, 434, 435, 436, 437, 438 representing the first path 430 of the DeBreen graph 400 based on receiving a portion of the reference genome 410 and the read segment 420 and may generate nodes 441, 442, 443, 444. First, the graph node unit 132 may compare the overlapping portions of the reference genomes 410a and 410b and the overlapping portions of the read segments 420a and 420b to identify the overlapped portions of the reference genomes 410a and 410b. Figure 4The overlapping area shown. The graph node unit 132 can identify each K-mer of the portion of the genome 410 and the read segment 420. This can be achieved by: using an access window of length k (equal to 4 in this example); capturing the K-mer identified by the access window at the first position of the portion of the reference genome 410; generating data representing a node of the graph including the captured K-mer; storing the data representing the node in the cache 150; advancing the access window by one nucleotide; and then iteratively repeating the process. In this example, the graph node unit 132 can identify the K-mers ATCG, TCGC, CGCC, GCCT, CCTA, CTAG, TAGA, and AGAA of the portion of the reference genome 410, and generate corresponding nodes 431, 432, 433, 434, 435, 436, 437, 438, one of which corresponds to the corresponding K-mer. Each node is created to have a length of k (4 in this example) and has an overlapping number of k-1 K-mers with the next adjacent node. The graph node unit 132 may store the generated nodes in the cache 150, the DRAM 160, or both. In some implementations, the cache may include a hash table cache. In such implementations, the nodes may be stored as keys to a hash table. The graph node unit 132 may store data describing a pointer to a K-mer node location in the graph description data maintained by the controller 140.

[0094] The graph node unit 132 may perform the same operation on the read segment 420. Relative to the read segment 420, the graph node unit 132 may identify the K-mers ATCG, TCGC, CGCG, GCGT, CGTA, GTAG, TAGA, and AGAA. This can be similarly implemented by using an access window of length k (equal to 4 in this example); capturing the K-mer identified by the access window at the first position of the portion of the read segment 420; and then advancing the access window and repeating the process. The graph node unit 132 may start by identifying each K-mer of the portion of the genome 410. In some specific implementations, the graph node unit 132 may generate a corresponding node for each K-mer. In other specific implementations, the graph node unit 132 may only generate 431, 432, 433, 434, 435, 436, 437, 438 corresponding to the identified K-mer, and the identified K-mer is different from the K-mer node of the portion of the reference genome 410. In each case, each node is created to have a length of k (4 in this example) and to have an overlap number of k-1 K-mers with the next adjacent node. This can continue until a node for each K-mer of that portion of the reference genome 410 is created and stored in cache 150 or DRAM 160.

[0095] In some specific implementations, the graph node unit 132 may also be configured to identify non-unique K-mers. In such specific implementations, the graph node unit 132 may determine whether the identified K-mer is a unique K-mer or a non-unique K-mer for each specific read of the first stack of reads. If the graph node unit 132 determines that a specific K-mer is a unique K-mer, the graph node unit 132 may advance the access window by a single nucleotide to evaluate the next K-mer. Alternatively, if the graph node unit 132 determines that a specific K-mer is a non-unique K-mer, the graph node unit 132 may store data indicating that the specific K-mer is a non-unique K-mer. For example, the graph node unit 132 may store a data tag in the graph description data maintained by the controller for a specific instance of the K-mer graph, and the data tag indicates that the K-mer is a non-unique K-mer. However, such data may be stored by any other component of the hardware accelerated graph generation unit 130, stored in any other memory unit of the hardware accelerated graph generation unit 130, or in a combination thereof. Subsequent hardware logic units may then perform operations to resolve non-unique K-mers in order to reduce or eliminate cycles in instances of the K-mer graph.

[0096] At this point in the process, the graph node unit 132 stores data representing nodes of the K-mer graph for each K-mer in the cache 150, DRAM 160, or both. That is, the hardware accelerated graph generation unit 130 has not yet generated graph edges 431a, 432a, 433a, 434a, 435a, 436a, 437a, 432b, 441a, 442a, 443a, 444a, graph edge weights, etc. These features of this instance of the K-mer graph may be generated by one or more other hardware logic units of the hardware accelerated graph generation unit 130.

[0097] The control engine 140 may monitor the operation of the graph node unit 132. Once the graph node unit 132 generates data representing a K-mer node for each K-mer of each read segment of the first original graph data for the first instance of the K-mer graph, the control engine may update the graph description data to indicate that the hardware accelerated graph generation unit 130 has completed the operation of the graph node unit 132 on the first original graph data. In addition, the control engine 140 may also store the graph description data, which includes, for example, a tag identifying each non-unique K-mer, a storage location of the K-mer graph node, and data indicating that the graph node unit 132 has completed its operation.

[0098] Once the K-mer graph nodes have been generated and stored in cache 150, control engine 140 may determine the next hardware logic unit to activate and configure. For example, control engine 140 may activate and configure graph edge unit 133 to generate, weight, or both graph edges between node pairs.

[0099] Graph edge unit

[0100] The graph edge unit 133 may generate graph edges between pairs of K-mer nodes generated by the graph node unit 132. Once it is determined that the graph node unit 132 for the first K-mer graph instance is complete and the graph edge unit 133 is available, the control engine 140 may activate the graph edge unit 133. In some specific implementations, the control engine 140 may provide or otherwise be able to access the location of the graph edge unit 133, which stores the K-mer graph nodes generated by the graph node unit 132 for a specific instance of the K-mer graph. For example, the control engine 140 may access K-mer graph description data generated and stored by the graph node unit 132 during the generation of K-mer nodes for an instance of the K-mer graph. The accessed K-mer graph description data may indicate or otherwise describe a K-mer list.

[0101] Once the graph edge unit 133 has obtained the location of the K-mer graph nodes for the first instance of the K-mer graph, the graph edge unit can begin generating one or more graph edges between the data representing the K-mer nodes. In some embodiments, the graph edge unit 133 may access the data representing the graph nodes for each K-mer of a particular read segment from the hash table cache. The graph edge unit 133 may generate data for graph edges between graph nodes representing K-mers for storage in the hash table cache. For example, the data representing the graph edges may be stored in the hash table cache as part of the graph node record of the source node of the edge. In some embodiments, the graph edge unit 133 may assign an edge weight to each edge of the K-mer graph. For example, for each occurrence of a graph edge connecting corresponding K-mer pairs, the graph edge unit 133 may add a +1 or other weight.

[0102] By way of example, the graph edge unit 133 may use the graph description data obtained from the control engine 140 to identify a node that is an adjacent node. Nodes may be determined to be adjacent nodes based on a variety of factors, including determining that the nodes share k-1 overlapping nucleotides and that the nodes are observed in two consecutive positions of a sliding K-mer access window. For example, the graph edge unit 133 may slide the K-mer access window along each position of each read segment of the original graph data. In some specific implementations, the graph edge unit 133 may create an edge or increase the edge weight when it is determined that two consecutive K-mers are observed in the read segment to overlap with all bases except one base. The graph node 133 creates an edge or increases the edge weight in this case because this situation means an edge between the graph nodes corresponding to the two consecutive K-mers.

[0103] In some implementations, data representing graph nodes may be stored as hash keys of a hash table. In such implementations, graph edge unit 133 may generate an edge from a first node (or hash key) to a second node (or hash key) by accessing the hash location to which the first node (or hash key) is mapped and generating a pointer to the second node (or hash key) for storage in the hash location. Subsequent edges may be generated in the same manner, creating paths 430 or 440 through the graph that may be traversed using one or more graph traversal algorithms.

[0104] refer to Figure 4 For example, the graph edge unit 133 may generate data representing one or more edges between node pairs of nodes 431, 432, 433, 434, 435, 436, 437, 438 of the first path 430, node pairs of nodes 441, 442, 443, 444 of the second path 440, or one or more pairs of node pairs in the first path 430 and the second path 440. Examples of these edges are shown in FIG. Figure 4 Shown in the figure are edges 431a, 432a, 433a, 434a, 435a, 436a, 437a, 432b, 441a, 442a, 443a, 444a.

[0105] In this example, the sequence of nucleotides 420 is referred to as a read. However, in some implementations, removal of low-quality bases may occur so that the sequence of nucleotides 420 is part of a read or an overlap. In such implementations, a graph edge connecting a pair of nodes will only create a path of one or more links within a particular overlap, rather than a path from a K-mer node of a first overlap to a K-mer node of a second overlap. An overlap may include a nucleotide sequence that appears after the removal of low-quality bases.

[0106] Back Propagation Unit

[0107] The hardware accelerated graph generation unit 130 may include a back propagation unit 134. However, in some implementations, the control engine 140 may only activate and configure the back propagation unit 134. For example, when the control engine 140 determines that the K-mer graph generated by the original graph data of the current group will be converted into a sequence graph later, the control engine 140 may activate the back propagation unit 134. When activated, the back propagation module 134 may receive graph description data from the control engine 140. In such implementations, the adjustment of the graph edge weights may make the weights more reliable when inherited by the sequence graph.

[0108] The graph edge unit 133 can construct the edges between the K-mer nodes of the overlapping group by: identifying the corresponding K-mer nodes in the cache 150; generating the edges connecting the K-mer nodes; and then increasing the weight of +1 for each edge that occurs. In some specific implementations, after the K-mer nodes of the overlapping group have been added to the K-mer graph and weighted using the graph edge unit 134, the back propagation unit 134 can be used to back propagate the +1 edge weight increment k-1 stage through the linear chain of graph edges to the "left" of the overlapping group starting node in the K-mer graph. In this context, the "left" of the overlapping group starting node in the K-mer graph is the direction of the K-mer graph, which is opposite to the directed edge of the K-mer graph. To illustrate this concept, the "left" of node 434 in the De Blain graph 400 will be nodes 433, 432 and 431.

[0109] For example, in some implementations, the back-propagation module 134 may access data representing a K-mer graph in a hash table cache, the K-mer graph including its K-mer nodes, corresponding graph edges, etc., and then adjust the edge weights of the k-1 nodes that appeared before the new configuration began. The back-propagation unit 135 may locate appropriate K-mer nodes and edges to adjust based on graph description data received from the control engine 160, the graph description data including a pointer to a cache location storing this information. The graph description data may be updated by any changes that occur during back-propagation.

[0110] In some implementations, it may be advantageous to perform the aforementioned back propagation, since the N-base contigs may only increase a series of (NK) edge weights. However, if this K-mer graph is subsequently converted to a sequence graph with (N-1) internal edges corresponding to this contig, the first (K-1) edge weights will not inherit the correct incremental edge weights. The aforementioned back propagation solves most of this problem. Therefore, back propagation can be used to solve this problem, so as to increase the reliability of the inherited edge weights when the K-mer graph is converted to a sequence graph.

[0111] Cycle Unit

[0112] The hardware accelerated graph generation unit 130 may include a loop unit 135. In some specific implementations, the loop unit 135 may be activated and configured by the control engine 140 to detect loops in an instance of a K-mer graph. For example, the loop unit 135 may evaluate the K-mer nodes and K-mer edges of the original graph data of an instance of a K-mer graph that has been generated by one or more of the input unit 131, the graph node unit 132, the graph edge unit 133, and the back propagation unit 134. The loop unit 135 is configured to receive graph description data from the control engine 140. The loop unit 135 may iteratively mark the head node for deletion. The head node may include a node that does not contain any inner edges. Among them, the inner edge is an edge pointing from the first node to the first node itself. After each head node is marked for deletion, the loop unit 135 may determine whether any node pointed to by the outer edge has become a head node as a result of deleting the node. If such a node is determined, it is marked for deletion. The outer edge is a graph edge pointing from the first node to another node. The loop unit 135 may continue to perform this process until no head nodes remain.

[0113] In the case where it is determined that there are no head nodes remaining, the loop unit 135 can determine whether the graph is empty, which means that all nodes of the graph are marked for deletion. If the headless graph is empty, there is no loop. Alternatively, if the headless graph is not empty, the graph must contain a loop. Loops are resistant to such deletions because no node in the loop can become a head node by deleting a node outside the loop.

[0114] When making one of these determinations, the loop unit 135 may provide an indication to the control engine 140 as to whether a loop is detected. Then, based on the provided indication from the loop unit 135, the control engine 140 may determine the hardware logic unit that should be activated and configured next. For example, if a loop is detected and the generation of an instance of the K-mer graph should be aborted, the control engine 140 may activate and configure the erase unit 138. In such cases, the erase unit may delete the original graph data corresponding to the instance of the aborted K-mer graph from the cache 150 and the DRAM 160. Alternatively, if the instance of the K-mer graph will continue to be generated, the control engine 140 may activate and configure another hardware logic unit to perform subsequent operations on the original graph data to generate an instance of the K-mer graph. For example, if the generation of the K-mer graph will continue, the control engine 140 may activate and configure the pruning unit 136 or the graph output unit 137.

[0115] Although the loop unit 135 may be used by the hardware accelerated graph generation unit 130 to detect loops in an instance of a K-mer graph being generated, the loop unit 135 may be selectively activated and configured similarly to the backpropagation unit 134. This is because it is foreseeable that some types of K-mer graphs may contain loops. However, for certain types of K-mer graphs, it may be beneficial to not have graphs with loops. Therefore, the hardware accelerated graph generation unit 130 may be configured, for example, for the control engine 140 to receive input indicating whether the loop unit 135 should be executed for a particular instance of the graph.

[0116] Trimming unit

[0117] The hardware accelerated graph generation unit 130 may include a pruning unit 135. Like the backpropagation unit 134 and the loop unit 135, the pruning unit 136 may be selectively activated and configured by the control engine 160. If activated and configured, the pruning unit 135 may evaluate the weight of each graph edge in the original graph data for the instance of the K-mer graph that has been generated by the hardware accelerated graph generation unit 130 at this time. In some specific implementations, if the pruning unit 136 determines that the weight value of the graph edge fails to meet a predetermined threshold, the pruning unit 136 may delete the graph edge and any K-mer nodes that appear after the identified graph edge. Alternatively, if the pruning unit 136 determines that the weight value of the graph edge meets a predetermined threshold, the pruning unit 136 will keep the graph edge intact.

[0118] In other implementations, pruning unit 136 may identify a linear chain, where the linear chain is a maximum path through the graph, where all internal nodes between the start node and the end node have exactly one internal edge and one external edge. In such implementations, pruning unit 136 may determine whether each internal edge of the linear chain fails to meet a pruning threshold. If such a case occurs, pruning unit 136 may delete the entire linear chain, including all internal edges and all internal nodes, except for the start node and / or end node of the chain, which pruning unit 136 may retain if they have any non-interior edges.

[0119] Graph Output Unit

[0120] The hardware accelerated graph generation unit 130 may include a graph output unit 137. A final version 170 of an instance of a K-mer graph may be generated by the hardware accelerated graph generation unit 130 using the graph output unit 137, because the instance of the K-mer graph is described by graph description data and cache data. For example, the graph output unit 137 may obtain data representing the K-mer graph from the hash table cache 150 using graph description data including, for example, a pointer to a location in a hash table cache storing K-mer graph data. The graph output unit 137 may then provide the data describing the final version of the K-mer graph 170 obtained from the hash table cache 150 to the variant calling unit 180. The variant calling unit 180 may perform a variant calling analysis on the final version of the K-mer graph 170 to generate a set of variants 190. A set of variants 190 may include one or more candidate variants. A variant is a change in the genomic data of an organism. A candidate variant is a determination made by the variant calling unit based on the variant calling unit derived from processing the K-mer graph 170. In some implementations, a candidate variant can have a threshold error level in the variant determination.

[0121] The variant detection unit 180 can identify candidate variants by processing K-mer graph 180. In some specific implementations, for example, when the base detection or nucleotide of one or more reads in the read segment stack is different from the nucleotide of the reference genome at a specific position of the reference genome, the variant detection unit 180 can identify candidate variants. The data describing the group of variants 190 can be generated or determined in a variety of ways. For example, in some specific implementations, the variant detection operation can be performed as described in more detail in, for example, U.S. Publication 2016 / 0180019, U.S. Publication 2016 / 0306922, and U.S. Publication 2019-0259468, and the entire contents of each of the above patents are incorporated herein by reference in their entirety. The data describing the group of variants 190 can be provided for output in a variety of different ways. For example, the data describing the group of variants 190 can be displayed on a display of a nucleic acid sequencer 110, displayed on a display of different computers, audibly output via one or more speakers of a computing device, output via a printer, or any combination thereof.

[0122] Erase Unit

[0123] The erasing unit 138 may be used to perform memory reclamation tasks when an instance of a K-mer graph is completed and output by the hardware accelerated graph generation unit 130. For example, the erasing unit may delete all original graph data associated with a specific instance of a K-mer graph completed and output by the hardware accelerated graph generation unit 130. Alternatively or in addition, the erasing unit 138 may delete all data associated with a specific instance of the graph unit 130 stored by the control machine, delete all data associated with a specific instance of the graph unit 130 stored in the DRAM 160, and the like. Thus, the erasing unit 138 may selectively delete data representing graph nodes and data representing graph edges of the K-mer graph from the hash table cache. This deletion is selective because only a portion of the contents of the cache, the control machine, or the DRAM need to be removed. In addition, when the graph is stored as a hash table, the hash table may typically be sparsely populated, and the erasing unit 138 selectively erasing only occupied hash table entries is faster than clearing the entire hash table, thereby improving performance.

[0124] However, in some implementations, it is not necessary to erase the non-hash table data associated with the graph item by item. In such implementations, the erase unit 138 may set the list length to zero in the graph description data, or may simply release the allocated memory space for reuse without erasing the content.

[0125] Figure 2is a flowchart of an example of a process 200 for hardware-accelerated K-mer graph generation. In general, process 200 may include: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences includes (i) a plurality of reads corresponding to active regions of a reference sequence and (ii) a portion of the reference sequence (210); generating a K-mer graph using the obtained first set of nucleic acid sequences and using a plurality of non-pipelined hardware logic units of a programmable logic device, wherein each hardware logic unit includes a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph represents the number of occurrences of a K-mer sequence represented by a pair of K-mers (220); in generating During the generation of a K-mer graph: after performing one or more operations by each hardware logic unit used to generate at least a portion of the K-mer graph, periodically update graph description data of the K-mer graph using a control engine, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, wherein the control engine uses the non-pipelined hardware logic unit to create a workflow of operations (230) by triggering each corresponding hardware logic unit to perform one or more operations during the generation of the K-mer graph; and provide the K-mer graph to a variant detection module, wherein the variant detection unit processes the K-mer graph to determine one or more candidate variants between one or more of the multiple reads and a reference sequence.

[0126] Figure 3 is a flow chart of another example of a process 300 for hardware accelerated K-mer graph generation. Generally speaking, process 300 may include: obtaining a first group of nucleic acid sequences, wherein the first group of nucleic acid sequences includes (i) multiple read segments corresponding to active regions of a reference sequence and (ii) a portion of the reference sequence (310); for each specific nucleic acid sequence of the first group of nucleic acid sequences: generating data for storage in a hash table cache by a first hardware logic unit, the data representing a graph node for each K-mer of the specific nucleic acid sequence (320); detecting by a control machine that the first hardware logic unit has completed the generation of graph nodes for each K-mer of the specific nucleic acid sequence (330); configuring a second hardware logic unit by the control machine to perform graph edge generation for the generated graph nodes (340); and for one or more pairs of generated graph nodes: generating data for storage in a graph hash table by a second hardware logic unit, the data representing a graph edge between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph node for each K-mer stored in the hash table cache and the data representing the graph edge stored in the hash table cache represent a K-mer graph of the first group of nucleic acid sequences (350).

[0127] Figure 4 is an example of a K-mer graph 400. In this example, the K-mer graph 400 is generated based on a reference genome 410 and at least a portion of reads 420. In this example, the K-mer graph 400 is a De Bleu graph.

[0128] The K-mer graph 400 is generated using multiple nodes and one or more edges between pairs of nodes. Each node represents a K-mer of length k, where k=4 in this example. Each edge indicates that there is an overlap of k-1 nucleotides of the K-mers connected by the edge. In the K-mer graph 400, the path 430 includes multiple nodes and edges for each K-mer representing that portion of the reference sequence 410. Then, the path 440 includes multiple nodes and edges representing portions of the read segment 420 that are different from that portion of the reference genome 410.

[0129] Figure 5 is a block diagram of an example of components of a system 500 that may be used for hardware accelerated K-mer graph generation.

[0130] Computing device 500 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Computing device 550 is intended to represent various forms of mobile devices, such as personal digital assistants, mobile phones, smart phones, and other similar computing devices. In addition, computing device 500 or 550 may include a universal serial bus (USB) flash drive. The USB flash drive can store operating systems and other applications. The USB flash drive may include input / output components, such as a wireless transmitter or USB connector that can be inserted into the USB port of another computing device. The components shown here, their connections and relationships, and their functions are intended only as examples and are not intended to limit the specific implementation of the present invention described and / or claimed in this document.

[0131] The computing device 500 includes a processor 502, a memory 504, a storage device 506, a high-speed interface 508 connected to the memory 504 and a high-speed expansion port 510, and a low-speed interface 512 connected to a low-speed bus 514 and the storage device 506. Each of the components 502, 504, 506, 508, 510, and 512 is interconnected using various buses and can be installed on a common motherboard or installed in other ways as appropriate. The processor 502 can process instructions for execution within the computing device 500, including instructions stored in the memory 504 or on the storage device 506, to display graphical information of a GUI on an external input / output device (such as a display 516 coupled to the high-speed interface 508). In other specific implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple types of memories as appropriate. In addition, multiple computing devices 500 can be connected, each device providing some parts of the necessary operations, for example, as a server library, a group of blade servers, or a multi-processor system.

[0132] The memory 504 stores information within the computing device 500. In one implementation, the memory 504 is one or more volatile memory units. In another implementation, the memory 504 is one or more non-volatile memory units. The memory 504 may also be another form of computer-readable medium, such as a magnetic disk or optical disk.

[0133] Storage device 506 can provide mass storage for computing device 500. In one specific implementation, storage device 506 can be or include a computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device or a tape device, a flash memory or other similar solid-state memory device, or an array of devices, including devices in a storage area network or other configuration. A computer program product can be tangibly embodied in an information carrier. A computer program product can also include instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer-readable medium or a machine-readable medium, such as memory 504, storage device 506, or a memory on processor 502.

[0134] The high-speed controller 508 manages bandwidth-intensive operations of the computing device 500, while the low-speed controller 512 manages bandwidth-less intensive operations. This functional allocation is only an example. In a specific implementation, the high-speed controller 508 is coupled to the memory 504, the display 516, and is coupled to the high-speed expansion port 510, which can accept various expansion cards (not shown) through a graphics processor or an accelerator. In this specific implementation, the low-speed controller 512 is coupled to the storage device 506 and the low-speed expansion port 514. The low-speed expansion port (which may include various communication ports, such as USB, Bluetooth, Ethernet, wireless Ethernet) may be coupled to one or more input / output devices, such as keyboards, pointing devices, microphone / speaker pairs, scanners or networking devices such as switches or routers, for example, through a network adapter. The computing device 500 can be implemented in a variety of different forms, as shown in the figure. For example, the computing device can be implemented as a standard server 520, or it can be implemented multiple times in a group of such servers. It can also be implemented as a part of a rack server system 524. In addition, the computing device can be implemented in a personal computer such as a laptop computer 522. Alternatively, components from computing device 500 may be combined with other components in a mobile device (not shown), such as device 550. Each of such devices may contain one or more of computing devices 500, 550, and the entire system may be comprised of multiple computing devices 500, 550 in communication with each other.

[0135] The computing device 500 can be implemented in a variety of different forms, as shown. For example, the computing device can be implemented as a standard server 520, or multiple times in a group of such servers. It can also be implemented as part of a rack server system 524. In addition, the computing device can be implemented in a personal computer such as a laptop computer 522. Alternatively, components from the computing device 500 can be combined with other components in a mobile device (not shown) such as device 550. Each of such devices can contain one or more of the computing devices 500, 550, and the entire system can be composed of multiple computing devices 500, 550 that communicate with each other.

[0136] Computing device 550 includes processor 552, memory 564, and input / output devices such as display 554, communication interface 566, and transceiver 568, among other components. Device 550 may also be provided with a storage device, such as a microdrive or other device, to provide additional storage. Each of components 550, 552, 564, 554, 566, and 568 are interconnected using various buses, and several of these components may be mounted on a common motherboard or otherwise as appropriate.

[0137] The processor 552 can execute instructions within the computing device 550, including instructions stored in the memory 564. The processor can be implemented as a chipset including a plurality of independent analog processors and digital processor chips. In addition, the processor can be implemented using any of a variety of architectures. For example, the processor 510 can be a CISC (complex instruction set computer) processor, a RISC (reduced instruction set computer) processor, or a MISC (minimum instruction set computer) processor. The processor can provide, for example, coordination of other components of the device 550, such as control of a user interface, applications run by the device 550, and wireless communications performed by the device 550.

[0138] The processor 552 can communicate with the user through a control interface 558 and a display interface 556 coupled to the display 554. The display 554 can be, for example, a TFT (thin film transistor liquid crystal display) display or an OLED (organic light emitting diode) display or other appropriate display technology. The display interface 556 may include appropriate circuits for driving the display 554 to present graphics and other information to the user. The control interface 558 can receive commands from the user and convert these commands to submit to the processor 552. In addition, an external interface 562 in communication with the processor 552 can be provided to enable close range area communication of the device 550 with other devices. The external interface 562 can provide wired communication in some specific implementations, or wireless communication in other specific implementations, and multiple interfaces can also be used.

[0139] The memory 564 stores information within the computing device 550. The memory 564 may be implemented as one or more of one or more computer-readable media, one or more volatile memory units, or one or more non-volatile memory units. An expansion memory 574 may also be provided and connected to the device 550 via an expansion interface 572, which may include, for example, a SIMM (single in-line memory module) card interface. Such an expansion memory 574 may provide additional storage space for the device 550, or may also store applications or other information for the device 550. Specifically, the expansion memory 574 may include instructions for executing or supplementing the above-mentioned processes, and may also include security information. Therefore, for example, the expansion memory 574 may be provided as a security module for the device 550, and may be programmed to have instructions that allow the device 550 to be used safely. In addition, a security application may be provided via a SIMM card together with additional information, such as placing identification information on the SIMM card in an unbreakable manner.

[0140] The memory may include, for example, flash memory and / or NVRAM memory, as described below. In one embodiment, a computer program product is tangibly embodied in an information carrier. The computer program product includes instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer readable medium or machine readable medium, such as memory 564, expansion memory 574, or memory on processor 552 that can be received by, for example, transceiver 568 or external interface 562.

[0141] Device 550 may communicate wirelessly via communication interface 566, which may include digital signal processing circuitry where necessary. Communication interface 566 may provide for communication in various modes or protocols, such as GSM voice calls, SMS, EMS or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA2000, or GPRS, etc. Such communications may occur, for example, via radio frequency transceiver 568. In addition, short range communications may occur, such as using Bluetooth, Wi-Fi, or other such transceivers (not shown). In addition, GPS (Global Positioning System) receiver module 570 may provide additional navigation-related and location-related wireless data to device 550, which may be used as appropriate by applications running on device 550.

[0142] Device 550 may also communicate audibly using audio codec 560, which may receive verbal information from a user and convert it into usable digital information. Audio codec 560 may also generate audible sounds for the user, such as through a speaker (e.g., in a handset of device 550). Such sounds may include sounds from voice phone calls, may include recorded sounds, such as voice messages, music files, etc., and may also include sounds generated by applications operating on device 550.

[0143] The computing device 550 can be implemented in many different forms, as shown. For example, the computing device can be implemented as a mobile phone 580. The computing device can also be implemented as part of a smart phone 582, a personal digital assistant, or other similar mobile devices.

[0144] Various implementations of the systems and methods described herein can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations of such implementations. These various implementations can include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose processor, coupled to receive data and instructions from a storage system, at least one input device, and at least one output device and to send data and instructions to the storage system, at least one input device, and at least one output device.

[0145] These computer programs (also referred to as programs, software, software applications, or code) include machine instructions for a programmable processor and may be implemented in high-level procedural and / or object-oriented programming languages ​​and / or in assembly language / machine language. As used herein, the terms "machine-readable medium," "computer-readable medium," refer to any computer program product, apparatus, and / or device, such as a disk, optical disk, memory, programmable logic device (PLD), for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0146] To provide interaction with a user, the systems and techniques described herein may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) that the user can use to provide input to the computer. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input.

[0147] The systems and techniques described herein may be implemented in a computing system that includes a back-end component (e.g., as a data server) or includes a middleware component (e.g., an application server) or includes a front-end component (e.g., a client computer with a graphical user interface or a web browser) through which a user may interact with a specific implementation of the systems and techniques described herein, or with any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), and the Internet.

[0148] The computing system may include clients and servers. Clients and servers are generally remote from each other and generally interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0149] Other Implementations

[0150] A number of embodiments have been described. However, it should be appreciated that various modifications may be made without departing from the spirit and scope of the invention. Furthermore, the logic flows shown in the accompanying drawings do not require the particular order or ordered order shown to achieve the desired results. Additionally, other steps may be provided in the flow, or steps may be eliminated, and other components may be added to or removed from the system. Therefore, other embodiments are also within the scope of the following claims.

Claims

1. A method for hardware-accelerating K-mer graph generation using a programmable logic device, the method comprising: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences comprises (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; generating a K-mer graph using the obtained first set of nucleic acid sequences and using a plurality of non-pipelined hardware logic units of a programmable logic device, wherein there is no direct and physical input / output connection between each corresponding hardware logic unit in the plurality of non-pipelined hardware logic units, each hardware logic unit includes a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph represents a number of occurrences of a K-mer sequence represented by a pair of K-mers; and During the generation of the K-mer graph: After each of the one or more operations is performed by each hardware logic unit used to generate at least a portion of the K-mer graph, a graph description data of the K-mer graph is updated using a control machine, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, wherein the control machine uses the non-pipelined hardware logic units to create a workflow of operations by triggering each corresponding hardware logic unit to perform the one or more operations during the generation of the K-mer graph; wherein the control machine triggers each corresponding hardware logic unit to perform one or more operations by providing the hardware logic unit with graph description data that can be used to configure the hardware logic unit to perform its operation. 2 . The method of claim 1 , wherein the output of each of the plurality of hardware logic units is stored via a hash table cache. 3 . The method according to claim 1 , wherein the control engine is implemented using a hardware logic unit of the programmable logic device. 4 . The method of claim 1 , wherein the control machine is implemented by using one or more CPUs or GPUs executing software instructions to realize the functions of the control machine.

5. The method according to claim 1, further comprising: The generated K-mer graph is provided to a variant calling unit, wherein the variant calling unit processes the K-mer graph to determine candidate variants between one or more reads in the plurality of reads and the reference sequence.

6. The method of claim 5, wherein software instructions are executed by one or more CPUs or GPUs to implement one or more functions of the variant calling unit.

7. The method of claim 5, wherein the programmable logic device is used to accelerate one or more functions of the variant calling unit.

8. A method according to claim 1, wherein the graph description data also includes (iii) data representing a last hardware logic unit among the multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

9. A system for hardware-accelerating K-mer graph generation using a programmable logic device, the system comprising: A hardware accelerated graph generation unit, the hardware accelerated graph generation unit comprising hardware digital logic circuits arranged to perform operations comprising: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences comprises (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; generating a K-mer graph using the obtained first set of nucleic acid sequences and using a plurality of non-pipelined hardware logic units of a programmable logic device, wherein there is no direct and physical input / output connection between each corresponding hardware logic unit in the plurality of non-pipelined hardware logic units, each hardware logic unit includes a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph represents a number of occurrences of a K-mer sequence represented by a pair of K-mers; and During the generation of the K-mer graph: After each of the one or more operations is performed by each hardware logic unit used to generate at least a portion of the K-mer graph, a graph description data of the K-mer graph is updated using a control machine, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, wherein the control machine uses the non-pipelined hardware logic units to create a workflow of operations by triggering each corresponding hardware logic unit to perform the one or more operations during the generation of the K-mer graph; wherein the control machine triggers each corresponding hardware logic unit to perform one or more operations by providing the hardware logic unit with graph description data that can be used to configure the hardware logic unit to perform its operation.

10. The system of claim 9, wherein the output of each of the plurality of hardware logic units is stored via a hash table cache.

11. The system of claim 9, wherein the operations further comprise: The generated K-mer graph is provided to a variant calling unit, wherein the variant calling unit is configured to process the K-mer graph to determine candidate variants between one or more reads of the plurality of reads and the reference sequence.

12. The system according to claim 9, further comprising: one or more computers; and one or more memory devices storing instructions that, when executed by the one or more computers, cause the one or more computers to perform a second operation of the variant calling unit, the second operation comprising Obtaining the generated K-mer graph by the variant calling unit; and One or more candidate variants are identified based on the K-mer graph generated by processing the variant calling unit, wherein the candidate variant is a difference between the base calls of one or more reads in the read pile and a reference genome nucleotide at a specific position of the reference genome.

13. The system of claim 9, wherein the operations further comprise: Obtaining the generated K-mer graph by variant calling unit; and One or more candidate variants are identified based on the K-mer graph generated by processing the variant calling unit, wherein the candidate variant is a difference between the base calls of one or more reads in the read pile and a reference genome nucleotide at a specific position of the reference genome.

14. A system according to claim 9, wherein the graph description data also includes (iii) data representing a last hardware logic unit among the multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

15. A method for hardware-accelerated K-mer graph generation in a programmable logic device, the method comprising: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences comprises (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; For each specific nucleic acid sequence of the first group of nucleic acid sequences: generating, by a first hardware logic unit, data for storage in a hash table cache, the data representing a graph node of each K-mer of the specific nucleic acid sequence; Detecting, by the control machine, that the first hardware logic unit has completed the generation of a graph node for each K-mer of the specific nucleic acid sequence; updating, by a control engine, graph description data of the K-mer graph based on data generated by the first hardware logic unit, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information; configuring, by the control machine based on the updated graph description data, a second hardware logic unit that is not in a pipeline configuration with the first hardware logic unit to perform generation of graph edges for the generated graph nodes; For one or more pairs of generated graph nodes: generating, by the second hardware logic unit, data for storage in the graph hash table, the data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences; Detecting, by the control machine, that the second hardware logic unit has completed the generation of graph edges for the generated graph nodes; and The graph description data of the K-mer graph is updated by a control machine based on the data generated by the second hardware logic unit.

16. The method according to claim 15, further comprising: Graph description data for an instance of the K-mer graph is stored by the control engine and in a memory unit accessible by the control engine.

17. The method according to claim 15, The first hardware logic unit is further configured as: determining whether one or more of the specific K-mers of the specific nucleic acid sequence matches another K-mer of the specific nucleic acid sequence; and Based on determining that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, data marking the one or more specific K-mers as non-unique K-mers is stored.

18. The method of claim 15, wherein the second hardware logic is further configured to: Assign an edge weight to each edge of the K-mer graph.

19. The method according to claim 15, further comprising: Instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: Obtaining data representing the K-mer graph from the hash table cache; and The obtained data representing the K-mer graph is provided to a variant calling unit.

20. The method according to claim 15, further comprising: Instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: Data representing graph nodes and data representing graph edges of the K-mer graph are selectively deleted from the hash table cache.

21. The method of claim 15, wherein the control engine is implemented using a third hardware logic unit of the programmable logic device.

22. The method of claim 15, wherein the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

23. The method of claim 15, wherein the control machine is implemented using one or more CPUs or GPUs that execute software instructions to implement the functions of the control machine.

24. The method of claim 15, wherein the graph description data further comprises (iii) data representing a last hardware logic unit of the plurality of hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

25. The method according to claim 15, further comprising: evaluating the K-mer graph to check for the presence of graph cycles; If a graph cycle is detected during said evaluation: terminating the generation of the K-mer graph; or If no graph cycles are detected during said evaluation: Obtaining data describing the structure of the K-mer graph from the hash table cache; and The obtained data describing the structure of the K-mer graph is provided to a variant calling module.

26. A system for hardware-accelerating K-mer graph generation using a programmable logic device, the system comprising: A hardware accelerated graph generation unit, the hardware accelerated graph generation unit comprising hardware digital logic circuits arranged to perform operations comprising: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences comprises (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; For each specific nucleic acid sequence of the first group of nucleic acid sequences: generating, by a first hardware logic unit, data for storage in a hash table cache, the data representing a graph node of each K-mer of the specific nucleic acid sequence; Detecting, by the control machine, that the first hardware logic unit has completed the generation of a graph node for each K-mer of the specific nucleic acid sequence; updating, by a control engine, graph description data of the K-mer graph based on data generated by the first hardware logic unit, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information; configuring, by the control machine based on the updated graph description data, a second hardware logic unit that is not in a pipeline configuration with the first hardware logic unit to perform generation of graph edges for the generated graph nodes; For one or more pairs of generated graph nodes: generating, by the second hardware logic unit, data for storage in the graph hash table, the data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences; Detecting, by the control machine, that the second hardware logic unit has completed the generation of graph edges for the generated graph nodes; and The graph description data of the K-mer graph is updated by a control machine based on the data generated by the second hardware logic unit.

27. The system of claim 26, the operations further comprising: Graph description data for an instance of the K-mer graph is stored by the control engine and in a memory unit accessible by the control engine.

28. The system according to claim 26, The first hardware logic unit is further configured as: determining whether one or more of the specific K-mers of the specific nucleic acid sequence matches another K-mer of the specific nucleic acid sequence; and Based on determining that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, data marking the one or more specific K-mers as non-unique K-mers is stored.

29. The system of claim 26, wherein the second hardware logic is further configured to: Assign an edge weight to each edge of the K-mer graph.

30. The system of claim 26, the operations further comprising: Instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: Obtaining data representing the K-mer graph from the hash table cache; and The obtained data representing the K-mer graph is provided to a variant calling unit.

31. The system of claim 26, the operations further comprising: Instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: Data representing graph nodes and data representing graph edges of the K-mer graph are selectively deleted from the hash table cache.

32. The system of claim 26, wherein the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

33. A system according to claim 26, wherein the graph description data also includes (iii) data representing a last hardware logic unit of the multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

34. The system of claim 26, the operations further comprising: evaluating the K-mer graph to check for the presence of graph cycles; If a graph cycle is detected during said evaluation: terminating the generation of the K-mer graph; or If no graph cycles are detected during said evaluation: Obtaining data describing the structure of the K-mer graph from the hash table cache; and The obtained data describing the structure of the K-mer graph is provided to a variant calling module.

35. A hardware accelerated graph generation unit, the hardware accelerated graph generation unit comprising hardware digital logic circuits arranged to perform operations comprising: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences comprises (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; generating a K-mer graph using the obtained first set of nucleic acid sequences and using a plurality of non-pipelined hardware logic units of a programmable logic device, wherein there is no direct and physical input / output connection between each corresponding hardware logic unit in the plurality of non-pipelined hardware logic units, each hardware logic unit includes a different hardware logic circuit configured to perform one or more operations, wherein each node of the K-mer graph represents a K-mer, each edge of the K-mer graph represents a link between a pair of K-mers, and each weight of each edge of the K-mer graph represents a number of occurrences of a K-mer sequence represented by a pair of K-mers; and During the generation of the K-mer graph: After each of the one or more operations is performed by each hardware logic unit used to generate at least a portion of the K-mer graph, a graph description data of the K-mer graph is updated using a control machine, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information, wherein the control machine uses the non-pipelined hardware logic units to create a workflow of operations by triggering each corresponding hardware logic unit to perform the one or more operations during the generation of the K-mer graph; wherein the control machine triggers each corresponding hardware logic unit to perform one or more operations by providing the hardware logic unit with graph description data that can be used to configure the hardware logic unit to perform its operation.

36. The hardware accelerated graph generation unit of claim 35, wherein the output of each of the plurality of hardware logic units is stored via a hash table cache.

37. The hardware accelerated graph generation unit of claim 35, wherein the operations further comprise: The generated K-mer graph is provided to a variant calling unit, wherein the variant calling unit is configured to process the K-mer graph to determine candidate variants between one or more reads of the plurality of reads and the reference sequence.

38. The hardware accelerated graph generation unit of claim 35, wherein the operations further comprise: Obtaining the generated K-mer graph by variant calling unit; and One or more candidate variants are identified based on the K-mer graph generated by processing the variant calling unit, wherein the candidate variant is a difference between the base calls of one or more reads in the read pile and a reference genome nucleotide at a specific position of the reference genome.

39. A hardware accelerated graph generation unit according to claim 35, wherein the graph description data also includes (iii) data representing a last hardware logic unit among the multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

40. A hardware accelerated graph generation unit, the hardware accelerated graph generation unit comprising hardware digital logic circuits arranged to perform operations comprising: obtaining a first set of nucleic acid sequences, wherein the first set of nucleic acid sequences comprises (i) a plurality of reads corresponding to an active region of a reference sequence and (ii) a portion of the reference sequence; For each specific nucleic acid sequence of the first group of nucleic acid sequences: generating, by a first hardware logic unit, data for storage in a hash table cache, the data representing a graph node of each K-mer of the specific nucleic acid sequence; Detecting, by the control machine, that the first hardware logic unit has completed the generation of a graph node for each K-mer of the specific nucleic acid sequence; updating, by a control engine, graph description data of the K-mer graph based on data generated by the first hardware logic unit, wherein the graph description data represents (i) a K-mer graph identifier and (ii) K-mer graph state information; configuring, by the control machine based on the updated graph description data, a second hardware logic unit that is not in a pipeline configuration with the first hardware logic unit to perform generation of graph edges for the generated graph nodes; For one or more pairs of generated graph nodes: generating, by the second hardware logic unit, data for storage in the graph hash table, the data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein the data representing the graph nodes for each K-mer stored in the hash table cache and the data representing the graph edges stored in the hash table cache represent a K-mer graph of the first set of nucleic acid sequences; Detecting, by the control machine, that the second hardware logic unit has completed the generation of graph edges for the generated graph nodes; and The graph description data of the K-mer graph is updated by a control machine based on the data generated by the second hardware logic unit.

41. The hardware accelerated graph generation unit according to claim 40, wherein the operation further comprises: Graph description data for an instance of the K-mer graph is stored by the control engine and in a memory unit accessible by the control engine.

42. The hardware accelerated graph generation unit according to claim 40, The first hardware logic unit is further configured as: determining whether one or more of the specific K-mers of the specific nucleic acid sequence matches another K-mer of the specific nucleic acid sequence; and Based on determining that the one or more specific K-mers of the specific nucleic acid sequence match another K-mer of the specific nucleic acid sequence, data marking the one or more specific K-mers as non-unique K-mers is stored.

43. The hardware accelerated graph generation unit according to claim 40, wherein the second hardware logic is further configured to: Assign an edge weight to each edge of the K-mer graph.

44. The hardware accelerated graph generation unit according to claim 40, wherein the operation further comprises: Instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: Obtaining data representing the K-mer graph from the hash table cache; and The obtained data representing the K-mer graph is provided to a variant calling unit.

45. The hardware accelerated graph generation unit according to claim 40, wherein the operation further comprises: Instructing a third hardware logic unit of the programmable logic device to execute hardware logic, wherein the hardware logic is configured to: Data representing graph nodes and data representing graph edges of the K-mer graph are selectively deleted from the hash table cache.

46. ​​The hardware accelerated graph generation unit of claim 40, wherein the hash table cache is implemented using a third hardware logic unit of the programmable logic device.

47. A hardware accelerated graph generation unit according to claim 40, wherein the graph description data also includes (iii) data representing a last hardware logic unit among the multiple hardware logic units that execute hardware logic on the K-mer graph or stacked nucleic acid sequence associated with the K-mer graph identifier.

48. The hardware accelerated graph generation unit of claim 40, wherein the operations further comprise: evaluating the K-mer graph to check for the presence of graph cycles; If a graph cycle is detected during said evaluation: terminating the generation of the K-mer graph; or If no graph cycles are detected during said evaluation: Obtaining data describing the structure of the K-mer graph from the hash table cache; and The obtained data describing the structure of the K-mer graph is provided to a variant calling module.

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