Polycrystalline silicon guard ring for enhancing breakdown voltage in power semiconductor devices

Abstract

This paper presents a coupled polysilicon guard ring for enhancing the breakdown voltage in a power semiconductor device. The polysilicon guard ring is disposed above the drift region of the power device and electrically coupled to the power device region (e.g., device diffusion) in order to spread the electric field associated with the operating voltage. Additionally, PN junctions (i.e., P-type and N-type junctions) are formed within the polysilicon guard ring to operate in reverse bias such that there is a low leakage current between the power device regions (e.g., device diffusion). The low leakage current can advantageously enhance the electric field spreading without detrimentally affecting the existing (i.e., conventional) power device performance; and the enhanced electric field spreading can in turn reduce the breakdown voltage drift.

Description

Field of the Disclosure

[0001] The present invention relates to a guard ring for increasing the breakdown voltage in a power field effect transistor, and more particularly to a polysilicon guard ring. Background Information

[0002] A power field effect transistor (FET) can be gated to block high voltage in the off-state and provide high current in the on-state. A power FET can be characterized by its breakdown (i.e., blocking) voltage and its on-resistance; and the figure of merit typically used to characterize a power FET is the specific on-resistance. The specific on-resistance refers to the on-resistance multiplied by the device area, and provides a measure of how much semiconductor area may be required to achieve a desired on-resistance value. Ideally, a power device is designed to have a low specific on-resistance and a high breakdown voltage.

[0003] One type of power FET is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS), which is designed for lateral current flow from drain to source. This lateral current flow can be gated by controlling the channel region at or near the surface interface between the oxide and the semiconductor; and a drift region can be used to support (i.e., block) high voltage in the off-state. The blocking voltage (i.e., breakdown voltage) can generally be increased by increasing the drift region length and by tailoring the doping concentration profile. For example, the doping concentration can be adjusted according to reduced surface field (RESURF) techniques.

[0004] Another type of power FET is a junction field effect transistor (JFET). Current flow can also be lateral from drain to source; however, unlike in an LDMOS, the current can be gated by a reverse-biased diffusion junction of opposite material types (e.g., p-type and n-type). Brief Description of the Drawings

[0005] Non-limiting and non-exhaustive embodiments of a coupled polysilicon guard ring for enhancing the breakdown voltage in a power semiconductor device are described with reference to the following drawings, where like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0006] Figure 1AShows a top view of a simple device structure including a guard ring according to one embodiment.

[0007] Figure 1B Shows a top view of a simple device structure including a guard ring according to another embodiment.

[0008] Figure 1C Shows a top view of a simple device structure depicting a cross-sectional slice line according to one embodiment.

[0009] Figure 1D Shows a cross-section along the Figure 1C slice line according to the first embodiment.

[0010] Figure 1E Shows a cross-section along the Figure 1C slice line according to the second embodiment.

[0011] Figure 1F Shows a schematic diagram of a simple device structure according to Figure 1A the embodiment.

[0012] Figure 1G Shows a schematic diagram of a simple device structure according to Figure 1B the embodiment.

[0013] Figure 2A Shows a top view of a guard ring segment according to the first embodiment.

[0014] Figure 2B Shows a side perspective view of a guard ring segment according to Figure 2A the embodiment.

[0015] Figure 2C Shows a top view of a guard ring segment according to the second embodiment.

[0016] Figure 2D Shows a side perspective view of a guard ring segment according to Figure 2C the embodiment.

[0017] Figure 2E Shows a top view of a guard ring segment according to the third embodiment.

[0018] Figure 2F Shows a side perspective view of a guard ring segment according to Figure 2E the embodiment.

[0019] Figure 2G Shows a top view of a guard ring segment according to the fourth embodiment.

[0020] Figure 2H Shows a side perspective view of a guard ring segment according to Figure 2G the embodiment.

[0021] Figure 3A Simplified top - down schematic view illustrating a simple device structure according to one embodiment.

[0022] Figure 3B Simplified top - down schematic view illustrating a simple device structure according to another embodiment.

[0023] Figure 3C Simplified top - down schematic view illustrating a simple device structure according to another embodiment.

[0024] Figure 4A Illustrates a device cross - section according to one embodiment.

[0025] Figure 4B Illustrates a device cross - section according to another embodiment.

[0026] Figure 4C Illustrates a schematic diagram corresponding to one embodiment of the device.

[0027] Figure 4D Illustrates a schematic diagram corresponding to another embodiment of the device.

[0028] Figure 5A Illustrates a device cross - section according to one embodiment.

[0029] Figure 5B Illustrates a device cross - section according to another embodiment.

[0030] Figure 5C Illustrates a schematic diagram corresponding to one embodiment of the device.

[0031] Figure 5D Illustrates a schematic diagram corresponding to another embodiment of the device.

[0032] Figure 6A Illustrates a simplified layout for routing a guard - ring path between device regions according to one embodiment.

[0033] Figure 6B Illustrates an enlarged simplified layout of a diode array according to one embodiment.

[0034] Figure 6C Illustrates an enlarged simplified layout of a diode array according to another embodiment.

[0035] Figure 6D Illustrates an enlarged simplified layout of a connection region according to one embodiment.

[0036] Figure 7 Illustrates a method for placing a guard - ring with diodes according to one embodiment.

[0037] Figure 8 Illustrates a method for placing a guard ring with a diffusion diode according to one embodiment.

[0038] In all of the several views of the drawings, corresponding reference characters indicate corresponding parts. Those skilled in the art will understand that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements and layers in the drawings may be exaggerated relative to other elements to help improve the understanding of the various embodiments of the teachings herein. In addition, commonly understood elements, layers, and / or process steps that are useful or necessary in a commercially viable embodiment are generally not depicted so as not to unduly obscure the view of these various embodiments of the coupled polysilicon guard ring for enhancing the breakdown voltage in a power semiconductor device. Detailed Description

[0039] In the following description, numerous specific details are set forth to provide a thorough understanding of the coupled polysilicon guard ring for enhancing the breakdown voltage in a power semiconductor device. However, it will be apparent to one of ordinary skill in the art that practicing the teachings herein does not require the use of these specific details. In other instances, well-known materials or methods have not been described in detail to avoid obscuring the present disclosure.

[0040] Reference throughout this specification to "one embodiment", "an embodiment", "one example" or "an example" means that a particular feature, structure, method, process, and / or characteristic described in connection with the embodiment or example is included in at least one embodiment of the coupled polysilicon guard ring for enhancing the breakdown voltage in a power semiconductor device. Thus, the phrases "in one embodiment", "in an embodiment", "one example" or "an example" appearing throughout this specification do not necessarily all refer to the same embodiment or example. In addition, the particular features, structures, methods, processes, and / or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Further, it should be understood that the accompanying drawings are for the purpose of explanation to those of ordinary skill in the art and are not necessarily drawn to scale.

[0041] In the context of the present application, when a transistor is in an "off state" or "off", the transistor blocks current and / or conducts substantially no current. Conversely, when a transistor is in an "on state" or "on", the transistor is capable of conducting current significantly. For example, the transistor may include an N-channel metal oxide semiconductor (NMOS) field effect transistor (FET), where a high voltage is supported between a first terminal, the drain, and a second terminal, the source.

[0042] In addition, throughout this specification, several technical terms are used. Unless specifically defined herein or the context of their use will otherwise clearly imply, these terms will assume their ordinary meaning in the field from which they are derived. For example, one of ordinary skill in the art can recognize and distinguish sheet resistance (i.e., sheet rho) from resistivity. Further, it should be noted that throughout this document, element names and symbols may be used interchangeably (e.g., Si for silicon); however, both have the same meaning.

[0043] Research in the field of modern power devices is dedicated to increasing the breakdown voltage, reducing the specific on-resistance, and reducing the cost of manufacturing. In this endeavor, device researchers look for various ways to fabricate and improve the characteristics of power FETs formed in a standard (i.e., low-cost) complementary metal oxide semiconductor (CMOS) process.

[0044] As discussed above, current can flow laterally in a power FET, including LDMOS and / or JFET, through the drift region. Both the specific on-resistance and the breakdown voltage can depend at least in part on the nature of the drift region; for example, both the breakdown voltage and the specific on-resistance can increase as a function of the drift region length.

[0045] Also as discussed above, ideally, a power device is designed to have a low specific on-resistance and a high breakdown voltage. Thus, simply increasing the drift region length may not achieve the ideal; and charge sharing techniques (such as RESURF) can be used to further reduce the peak electric field.

[0046] However, even with the RESURF technique, the design of high voltage JFETs and / or high voltage LDMOS still encounters challenges. For example, in a standard CMOS process using the RESURF technique, a breakdown voltage of seven hundred volts or higher may require a minimum drift region length of at least sixty microns.

[0047] Unfortunately, the surface above the drift region may be exposed to mobile and / or fixed charges; and devices having a long drift region length (e.g., greater than sixty microns) may be vulnerable to reliability issues. For example, in some applications, the mold compound used during the packaging process may introduce mobile and / or fixed surface charges. Alternatively, and additionally, in a shallow trench isolation (STI) CMOS process, the interlayer dielectric (ILD) layer may also introduce mobile and / or fixed surface charges.

[0048] Mobile and / or fixed charges may cause the breakdown voltage to drift (i.e., change) below the desired rated value after a long-term high-temperature reverse bias (HTRB) reliability test or after a temperature humidity bias test (THBT). Such a change in the breakdown voltage is undesirable. Therefore, there is a need for a power device structure that mitigates the detrimental effects of mobile and / or fixed charges at the surface of the drift region. Additionally, there is a need for a power device structure that mitigates breakdown voltage drift in existing power device structures without introducing additional process complexity and without affecting the performance of existing power devices.

[0049] A coupled polysilicon guard ring for enhancing the breakdown voltage in a power semiconductor device is proposed herein. The polysilicon guard ring is disposed above the drift region of the power device and electrically coupled to the power device region (e.g., a diffusion region) to spread the electric field associated with the operating voltage. Additionally, a PN junction (i.e., a P-type junction and an N-type junction) is formed within the polysilicon guard ring to operate in reverse bias such that there is a low leakage current between the power device regions (e.g., diffusion regions). The low leakage current can advantageously enhance the electric field spread without detrimentally affecting the performance of existing (i.e., conventional) power devices; and the enhanced electric field spread can in turn reduce the breakdown voltage drift.

[0050] Figure 1A A top view of a simple device structure 100 including guard rings 110, 112 according to an embodiment is illustrated. The simple device structure 100 includes device regions 101, 102, and interconnect segments 107a - 107c. As will be further illustrated with respect to Figure 1D and Figure 1E The device regions 101, 102 may be diffusion regions and / or implanted regions. Additionally, the guard rings 110, 112 may be thin film guard rings. For example, the guard rings 110, 112 may be polysilicon guard rings.

[0051] As illustrated, the interconnect segment 107a can be electrically connected to the device region 101 through the ohmic contact 108a and to the guard ring 110 through the ohmic contact 109a. In this way, the device region 101 can be electrically coupled to the guard ring 110 through the interconnect segment 107a. Similarly, the interconnect segment 107b can be electrically connected to the guard ring 110 through the ohmic contact 108b and to the guard ring 112 through the ohmic contact 109b, such that the guard ring 110 and the guard ring 112 are electrically coupled through the interconnect segment 107b. In addition, the interconnect segment 107c can be electrically connected to the guard ring 112 through the ohmic contact 108c and to the device region 102 through the ohmic contact 109c; and in this way, the device region 102 can be electrically coupled to the guard ring 112 through the interconnect segment 107c.

[0052] Also as illustrated, the guard ring 110 includes N regions 105a - 105d and P regions 106a - 106d; and the guard ring 112 includes N regions 105e - 105j and P regions 106e - 106j. In some embodiments, the N regions 105a - 105j and the P regions 106a - 106j can be implanted. For example, during a CMOS process, the N regions 105a - 105j and the P regions 106a - 106j can be formed simultaneously with the masking and implantation steps related to the formation of CMOS transistors.

[0053] In addition, the N regions 105a - 105j and the P regions 106a - 106j can be placed to form barriers (e.g., PN junctions) within the guard rings 110, 112. For example, as will be further illustrated below with respect to Figure 1F As further illustrated, the N regions 105a - 105j can be arranged to act as cathodes electrically, while the P regions 106a - 106j can be placed to act as anodes electrically. In this way, the N regions 105a - 105j and the P regions 106a - 106j can advantageously block (i.e., limit) the current flow within the guard rings 110, 112 while improving the field spreading profile of the guard rings 110, 112.

[0054] Although the simple device structure 100 shows two guard rings 110, 112, ten N regions 105a - 105j, and ten P regions 106a - 106j, device structures with more or fewer guard rings and more or fewer N regions and / or P regions are possible. Additionally, although the simple device structure 100 shows the device regions 101, 102 and the guard rings 110, 112 as being electrically coupled using three interconnect segments 107a - 107c - each having ohmic contacts 108a - 108c, 109a - 109c - other interconnect layers and / or coupling methods are possible. For example, the interconnect segments 107a, 107c could be formed on a first metal layer; and the interconnect segments could be formed using the same material as the guard rings 110, 112 (e.g., polysilicon) to eliminate the need for the ohmic contacts 108b, 109b.

[0055] Figure 1B Illustrates a top view of a simple device structure 113 including guard rings 110, 112 according to another embodiment. The simple device structure 113 is similar to the device structure 100, except that the guard rings 110, 112 include additional N regions 115a - 115e and P regions 116a - 116e. Additionally, as will be described with respect to Figure 1G As shown, the N regions 115a - 115e can act electrically as cathodes, and the P regions 116a - 116e can act electrically as anodes to form a PN junction (e.g., a diode) that is in the opposite direction to the PN junction formed by the P regions 106a - 106j and the N regions 105a - 105j.

[0056] Figure 1C Illustrates a top view depicting a cross - section slice line 142 in the simple device structure 100 according to one embodiment; and Figure 1D Illustrates a cross - section 143 along the Figure 1C slice line according to the first embodiment. As shown in Figure 1C The slice line 142 cuts through the simple device structure 100 through the N region 105j, the N region 105c, the P region 106b, and through the intrinsic portion of the guard ring 112. Thus, the cross - section 143 shows cross - section slices of the N region 105j, the N region 105c, the P region 106b, and the intrinsic (I) portion of the guard ring 112, respectively.

[0057] Additionally, referring to Figure 1C and Figure 1DSecond, cross-section 143 shows a P layer 152, an N drift region 150, and an oxide layer 160 that can be formed during fabrication steps in a CMOS process (e.g., a silicon CMOS process). For example, the P layer 152 can be formed as a buried layer, and the N drift region 150 can be formed as an epitaxial layer. Cross-section 143 also shows device region 101 as having an n-type (N+) diffusion profile and device region 102 as having a p-type (P) diffusion profile.

[0058] According to a first embodiment, the CMOS process can use shallow trench isolation (STI) trenches 161, 162 formed under guard rings 110, 112. Both STI trenches 161, 162 can have a similar pattern (e.g., a ring-shaped pattern) consistent with the pattern of guard rings 110, 112, and can include (i.e., be filed with) an oxide and / or an insulating material (e.g., silicon dioxide SiO2). Depending on the critical dimension (CD) defined by the process, the STI trenches can be located within the N drift region 150. In addition, the spacing between guard ring 110 and guard ring 112 can be determined at least in part by the active layer oxide density (OD) (e.g., OD layer) requirements that allow subsequent ILD layers and metallization layers to be properly formed by chemical mechanical polishing (CMP). For example, as illustrated in Figure 1D STI trench 161 and STI trench 162 can be separated by a dimension OD1 (e.g., OD layer dimension). In this way, STI trenches 161 and 162 can be located within the N drift region 150 according to the OD layer critical dimension and / or OD layer density requirements; this can in turn advantageously mitigate "dishing" and / or erosion during subsequent CMP process steps.

[0059] Cross-section 143 can correspond to a cross-section of a simplified power device structure. For example, the N drift region 150 can be a high-voltage drift region for supporting the voltage applied between device region 101 and device region 102. As illustrated, guard rings 110, 112 and underlying STI trenches 161, 162 are located along the surface between device region 101 and device region 102. In this way, guard rings 110, 112 can advantageously spread the electric field caused by the voltage applied between device regions 101, 102; and the field spreading can mitigate and / or reduce any harmful effects of mobile and / or fixed surface charges. In addition, placing guard rings 110, 112 on top of STI trenches 161, 162 can advantageously allow (i.e., maintain) a higher breakdown voltage, partly due to the thickness of the insulating material and insulating material (e.g., SiO2) within STI trenches 161, 162.

[0060] Figure 1E illustrates a cross-section 144 along a slicing line 142 according to a second embodiment Figure 1C The cross-section 144 is similar to the cross-section 143, except that instead of showing an embodiment with STI trenches 161, 162, the cross-section 143 shows a second embodiment with a field oxide 146. For example, the field oxide 146 can be a thick field oxide formed during a CMOS process of a local oxidation of silicon (LOCOS) process recipe. Instead of being placed above the STI trenches 161, 162, the guard rings 110, 112 can be disposed above the field oxide 146 to mitigate and / or reduce any harmful effects of mobile and / or fixed surface charges.

[0061] Figure 1F illustrates a schematic diagram 150 of a simple device structure 100 according to an embodiment of Figure 1A The schematic diagram 150 is generated from a top view of the simple device structure 100 and shows the electrical connections of the device regions 101, the device region 102, the guard rings 110 and the guard rings 112 to the interconnect segments 107a - 107c; and the schematic diagram 150 also provides a diode representation, where the diodes D1 - D10 are formed by the N regions 105a - 105j and the P regions 106a - 106j.

[0062] By comparison with Figure 1A the cathode of the diode D1 (i.e., the N region 105a) is coupled to the device region 101 by means of the interconnect segment 107a and the ohmic contacts 108a, 109a. As illustrated, the diodes D1 - D4 are connected in series, and the anode of the diode D4 (i.e., the P region 106d) is coupled to the cathode of the diode D5 (i.e., the N region 105e) by means of the interconnect segment 107b and the ohmic contacts 108b, 109b. In addition, the diodes D5 - D10 are connected in series, and the anode of the diode D10 (i.e., the P region 106j) is coupled to the device region 102 by means of the interconnect segment 107c and the ohmic contacts 108c, 109c.

[0063] In addition, as illustrated by Figure 1A and Figure 1F diodes can be formed (e.g., implanted) in both the curved portions (e.g., curved segments) and the linear portions (e.g., straight segments) of the guard rings 110, 112. For example, the diodes D7, D8 are shown in the curved (i.e., bent) segment of the guard ring 112; and the diodes D1, D2 are shown in the linear (i.e., straight) segment of the guard ring 110.

[0064] During device operation, a voltage may be applied between device region 101 and device region 102. Diodes D1 - D10 may be placed in guard rings 110, 112 to distribute the applied voltage along guard rings 110, 112 without disturbing normal device operation. For example, as will be further described with respect to Figure 4C and Figure 5C the diodes D1 - D10 may be reverse - biased (i.e., operated at a reverse bias voltage) to distribute the applied voltage between device region 101 and device region 102.

[0065] Figure 1G FIG. 170 illustrates a schematic diagram of a simple device structure 113 according to an embodiment of Figure 1B FIG. 170 is generated from a top - view of the simple device structure 113 and shows the electrical connection of device region 101, device region 102, guard rings 110 and 112 to interconnect segments 107a - 107c. Schematic diagram 150 is similar to schematic diagram 170, except that schematic diagram 170 includes additional diodes D11 - D15 formed by N - regions 115a - 115e and P - regions 116a - 116e. For example, diode D11 is in series between diodes D1 and D2 such that diodes D1 and D11 are positioned in a back - to - back arrangement; in the back - to - back arrangement, the anode of D11 (i.e., P - region 116a) is adjacent (i.e., coupled) to the anode of D1 (i.e., P - region 106a). Placing the diodes in a back - to - back arrangement may allow one or more of diodes D1 - D15 to operate at a reverse bias for both positive and negative excursions of the applied voltage. For example, when the applied voltage between device region 101 and device region 102 is positive, then diodes D1 - D10 may be reverse - biased while diodes D11 - D15 are forward - biased (i.e., operated at a forward bias voltage); and when the applied voltage is negative, then diodes D11 - D15 may be reverse - biased while diodes D1 - D10 are forward - biased.

[0066] Figure 2A FIG. 200 illustrates a top - view of a guard - ring segment 210 according to a first embodiment; and Figure 2B FIG. illustrates a schematic diagram according to Figure 2ASide perspective view 220 of guard ring segment 210 of an embodiment. Top view 200 shows guard ring segment 210 as having a dimension WGR (e.g., 0.5 microns) and shows the formation of diodes D20, D22 within guard ring segment 210. As illustrated, diode D20 can be formed of an intrinsic region of width WI sandwiched between a P region 206b and an N region 205b, and thus, diode D20 can be referred to as a PIN (p-type, intrinsic, n-type) diode. Diode D22 is also shown as having a PIN structure having a P region 206a and an N region 205a.

[0067] As discussed above, N regions 205a, 205b and P regions 206a, 206b can be implant regions and / or diffusion regions. Although the guard ring (i.e., guard ring segment 210) can be undoped (i.e., intrinsic) polysilicon, in other embodiments, the guard ring (i.e., guard ring segment 210) can also be lightly doped relative to the doping concentrations of N regions 205a, 205b and P regions 206a, 206b.

[0068] Top view 200 also illustrates the width WP of P region 206b on the left side and the width WN of N region 205b on the right side of an intrinsic (or lightly doped) polysilicon material of width WI. In one embodiment, widths WP, WN and WI can be determined by critical dimensions and / or design rules; for example, width WP and width WN can have values between zero point one eight (0.18) microns and five microns, and width WI can have values between zero microns and five microns.

[0069] Figure 2C Top view 230 illustrating guard ring segment 210 according to a second embodiment; and Figure 2D Illustrating according to Figure 2C Side perspective view 240 of guard ring segment 210 of an embodiment. In the second embodiment, N regions 205a, 205b and P regions 206a, 206b are juxtaposed to form a PN junction diode rather than a PIN diode as drawn in Figure 2A and Figure 2B as shown.

[0070] Figure 2E Top view 250 illustrating guard ring segment 252 according to a third embodiment; and Figure 2F Illustrating according to Figure 2EA side perspective view 260 of the guard ring segment 252 of an embodiment. In the third embodiment, diodes D25 and D26 are formed in the guard ring segment 252 using N-region 215b and N-region 215a, respectively. As illustrated, the guard ring segment 252 may be doped p-type (P) polysilicon before implanting and / or diffusing N-regions 215a, 215b. Additionally, the top view 250 illustrates the width WN of the N-region 215b, which may also be determined by critical dimensions and / or design rules.

[0071] Figure 2G A top view 270 of the guard ring segment 272 according to a fourth embodiment is illustrated; and Figure 2H is illustrated according to Figure 2G A side perspective view 280 of the guard ring segment 272 of an embodiment. In the fourth embodiment, diodes D27 and D28 are formed in the guard ring segment 272 using P-region 225b and P-region 225a, respectively. As illustrated, the guard ring segment 272 may be doped n-type (N) polysilicon before implanting and / or diffusing P-regions 225a, 225b. Additionally, the top view 270 illustrates the width WP of the P-region 225b, which may also be determined by critical dimensions and / or design rules.

[0072] Figure 3A A simplified top view schematic of a simple device structure 300 according to an embodiment is illustrated. The simplified top view schematic depicts guard rings 310 - 313, interconnect segments 340 - 345, device regions 301, 302, and a diode array 330. The simplified top view schematic shows the guard rings 310 - 313 as lines with curved arcs and the interconnect segments 340 - 345 as connected lines for ease of presentation; and although the simple device structure shows an embodiment with four guard rings 310 - 313, there may be more or fewer than four guard rings 310 - 313 as needed to cover the surface area between device region 301 and device region 302.

[0073] Also as illustrated, the interconnect segments 340 - 345 serially couple the guard rings 310 - 313 between device region 301 and device region 302. For example, diode D33 of the diode array 330 is placed within guard ring 312 and has a cathode electrically coupled to guard ring 311 through interconnect segment 342.

[0074] During operation, the applied voltage between device region 301 and device region 302 may be distributed along the serially connected guard rings 310 - 313 such that mobile and / or stationary surface charges do not cause a breakdown voltage drift. The diode array 330 may be used as described above with respect to Figures 1A to 2Hplaced in the N and P regions as described in the embodiments; and the diodes can be in series by virtue of the series-connected protection rings 310-313.

[0075] Figure 3B Illustrates a simplified top view schematic of a simple device structure 360 according to another embodiment. The simple device structure 360 is similar to the device structure 300, except that the simple device structure 360 uses a diode array 331 having diodes oriented in a direction opposite to that of the diodes shown in Figure 3A For example, the diode D34 is oriented such that its anode is electrically coupled to the protection ring 311 through the interconnect segment 342. Placing the diode array 331 with the diodes oriented in the opposite direction can advantageously allow the device to operate with an applied voltage that is opposite in sign to the applied voltage used by the device structure 300.

[0076] Figure 3C Illustrates a simplified top view schematic of a simple device structure 370 according to another embodiment. The simple device structure 370 is similar to the device structure 300 and the device structure 360, except that the simple device structure 370 uses a diode array 332 having diodes oriented in two directions. For example, the diodes D35, D36, and D37 are placed such that the direction of the diode D36 is opposite to the directions of the diodes D35 and D37; and as illustrated, D35 and D36 are positioned as back-to-back diodes (i.e., the anodes of D35 and D36 are electrically coupled).

[0077] Figure 4A Illustrates a device cross-section 400 according to an embodiment. The embodiment of the device cross-section 400 can be similar to the cross-section 143, except that the device cross-section 400 shows more details related to a gate-controlled power device (e.g., LDMOS). The device cross-section 400 includes a P layer 432, an N drift region 430, a device region 401, a device region 402, a polysilicon gate 406, STI trenches 421-423, protection rings 410-412, an ohmic contact 405, and an ohmic contact 407.

[0078] As illustrated, the device region 402 can be a p-type (P) region. Also as illustrated, the device region 402 includes a P+ region 403 and an N+ region 404. Regarding forming a power device (e.g., LDMOS), the device region 402 with the P+ region 403 can form a body; and electrical contact with the body can be facilitated through an ohmic contact 405. A polysilicon gate 406 with an underlying oxide 460 (i.e., gate oxide) can functionally form a gate; and when a gate voltage is applied to the polysilicon gate 406, a channel (i.e., an N-channel) can be controlled in the device region 402 adjacent to the N+ region 404 (i.e., the source). As shown, the ohmic contact 405 can electrically couple the N+ region 404 and the P+ region 403 together to form a source / body (S / B) connection.

[0079] Also as illustrated, the device region 401 can be a heavily doped n-type (N+) region. Regarding forming a power device (e.g., LDMOS), the N-drift region 430 with the device region 401 can form a drain (DR); and electrical contact with the drain can be facilitated through an ohmic contact 407. When a gate voltage is applied to the gate 406 to achieve a channel, current can flow laterally between the drain and the source through the N-drift region 430. Alternatively, when a gate voltage is applied to the gate 406 to form a barrier, for an electric field less than the critical field, a voltage can be maintained across the N-drift region 430.

[0080] According to the teachings herein, when the guard rings 410 - 412 include PN junctions, the guard rings 410 - 412 covering the STI trenches 421 - 423 can advantageously enhance the voltage maintained across the N-drift region 430 and increase the maximum breakdown voltage. The maximum breakdown voltage can be increased by spreading the electric field between the device region 401 and the device region 402; and according to the teachings herein, a PN junction can be formed for reverse bias operation. Forming a PN junction in the guard rings 410 - 412 such that one or more of them operate in reverse bias can advantageously enhance device breakdown without affecting device performance. For example, as will be further illustrated below in Figure 4C it can be further illustrated that, with a diode operating in reverse bias, the guard rings 410 - 412 can advantageously distribute the voltage without significantly affecting the reverse leakage current.

[0081] As discussed above, in some embodiments, the number and / or density of the guard rings 410 - 412 and the underlying STI trenches 421 - 423 can be selected based on process-defined critical dimensions and spacing rules (e.g., OD layer requirements and / or critical dimensions); and although Figure 4AIllustrated is a device cross-section 400 according to one embodiment — showing an N-drift region 430 having three STI trenches 421-423 under three guard rings 410-412, but other configurations are possible. For example, based on the size of the N-drift region 430, there may be more or fewer than three STI trenches 421-423 under the three guard rings 410-412. The size of the N-drift region 430 can be selected based on the desired breakdown voltage.

[0082] In addition, as would be understood by one of ordinary skill in the art, power devices can be formed using the opposite polarity type. For example, an LDMOS can be formed as a P-channel device having a P-drift region instead of the N-drift region 430.

[0083] Figure 4B Illustrated is a device cross-section 450 according to another embodiment. The embodiment of the device cross-section 450 is similar to the embodiment of the device cross-section 400, except that the process uses a field oxide 446 instead of the STI trenches 421-423. For example, the field oxide 446 can be formed in a CMOS process using a LOCOS process recipe. The field oxide 446 can have a higher dielectric breakdown strength relative to the gate oxide 434; and the guard rings 440-442 can be placed in the same manner as the guard rings 410-412 to spread the electric field at and / or near the surface of the N-drift region 430. In addition, according to the teachings herein, when the guard rings 440-442 include PN junctions, the guard rings 440-442 covering the field oxide 446 can advantageously enhance the voltage maintained across the N-drift region 430 and increase the maximum breakdown voltage.

[0084] In addition, as discussed above, in some embodiments, the number and / or density of the guard rings 440-442 can be selected based on the critical dimensions and spacing rules defined by the process associated with the LOCOS process recipe. In addition, like the embodiment of the device cross-section 400, the embodiment of the device cross-section 450 should not be considered limiting. For example, there can be more and / or fewer than three guard rings 440-442; and power devices of the opposite polarity (e.g., P-type LDMOS) can also be possible.

[0085] Figure 4C Illustrated is a schematic diagram 470 corresponding to an embodiment of a device. For example, this embodiment can be a power device (e.g., an LDMOS) as depicted by Figure 4A the cross-section 400 and / or Figure 4B the cross-section 450. The embodiment of the schematic diagram 470 includes an LDMOS 471 having a gate G, a drain DR, and a connected source / bulk S / B. Referring to Figure 4A and / or Figure 4B, the gate G can correspond to polysilicon gate 406 and / or polysilicon gate 446; the drain DR can correspond to and include a region (e.g., device region 401) electrically coupled through ohmic contact 407, and the source / bulk S / B can correspond to and include a connection region (e.g., N+ region 404 and P+ region 403) electrically coupled through ohmic contact 405.

[0086] As illustrated, the embodiment can include a diode array 472 that is electrically connected in parallel with the drain DR and the connected source / bulk S / B of the LDMOS 471. The diode array 472 includes a plurality of diodes D41 - D50 connected in series, and the diodes D41 - D50 can correspond to PN junctions placed (e.g., diffused) within guard rings 410 - 412 and / or guard rings 440 - 442. As shown, the cathode of diode D41 (e.g., the N region of the guard ring) is electrically connected to the drain DR of the LDMOS 471; and the anode of diode D50 (e.g., the P region of the guard ring) is electrically connected to the source / bulk S / B of the LDMOS 471.

[0087] Also as illustrated, the connected source / bulk S / B of the LDMOS 471 is electrically coupled (i.e., referenced) to ground GND; and in this way, the drain - to - source voltage VDS and the gate - to - source voltage VGS can also be referenced to ground GND. As illustrated, the drain - to - source voltage VDS and the gate - to - source voltage VGS are respectively coupled to the drain DR and the gate G of the LDMOS 471. When the gate - to - source voltage VGS is less than the threshold voltage of the LDMOS 471 (e.g., two volts), the drain - to - source current IDS can ideally be limited to a very low value (e.g., approximately and / or less than one microampere). Alternatively, when the gate - to - source voltage VGS is greater than the threshold voltage of the LDMOS 471, then the drain - to - source current IDS can ideally be large (e.g., approximately several amperes).

[0088] In accordance with the teachings herein, the diode array 472 can be formed within guard rings (e.g., guard rings 410 - 412 and / or guard rings 440 - 442) and electrically coupled to the LDMOS 471 such that the guard rings mitigate breakdown voltage drift without disturbing device operation and / or characteristics. For example, diodes D41 - D50 are electrically connected in series such that when VDS is greater than zero, diodes D41 - D50 operate in reverse bias. The number of diodes D41 - D50 can be selected such that the reverse leakage current IL is low relative to the off-state value of the drain-to-source current IDS. The off-state value of IDS can correspond to a condition where the gate-to-source voltage VGS is less than the threshold voltage (e.g., two volts). For example, the number of diodes D41 - D50 can be selected such that when the gate-to-source voltage is less than the threshold voltage for a specified value of the drain-to-source voltage VDS (e.g., seven hundred volts), the reverse leakage current IL is substantially zero and / or significantly less than the drain-to-source current IDS.

[0089] Figure 4D Schematic 480 illustrates another embodiment corresponding to the device. The device can also be a power device as depicted by Figure 4A cross-section 400 and / or Figure 4B cross-section 450, except that diode array 473 replaces diode array 472. Different from diode array 472, diode array 473 includes diodes D41 - D46 coupled in series and diodes D51 - D55 oriented in the opposite direction. For example, diode D41 and diode D51 are electrically coupled in a back-to-back arrangement. Also as illustrated, the cathode of diode D41 is electrically coupled to the drain DR of LDMOS 471 and the cathode of diode D55 is electrically coupled to the source / bulk S / B of LDMOS 471. Thus, when the drain-to-source voltage VDS is greater than zero, then diodes D41 - D46 can operate in reverse bias to limit the leakage current IL. Additionally, when the drain-to-source voltage VDS is less than zero, then diodes D51 - D55 can also advantageously limit the leakage current IL by operating in reverse bias.

[0090] Figure 5A Device cross-section 500 illustrates an embodiment in accordance with one embodiment. This embodiment of device cross-section 500 can also be similar to cross-section 143, except that device cross-section 500 shows more details related to the power device, where the gate can be formed by a junction (e.g., JFET). Device cross-section 500 includes a P layer 532, an N drift region 530, device region 501, device region 502, well region 503, STI trenches 521 - 523, guard rings 510 - 512, ohmic contacts 505, ohmic contacts 507, ohmic contacts 509, and surface oxide 560.

[0091] As illustrated, the device region 502 and the well region 503 can be p-type (P) regions. The device region 502 can include a P+ region 504 for electrical coupling to the ohmic contact 505; and the well region 503 can include a P+ region 508 for electrical coupling to the ohmic contact 509. In addition, the N drift region includes an N+ region 506 between the device region 502 and the well region 503; and as shown, the device region 501 can also be a heavily doped n-type (N+) region.

[0092] Regarding the formation of a power device (e.g., a JFET), the device region 502, the P+ region 504, and the ohmic contact 505 can electrically function as part of the JFET gate (G); and the well region 503, the P+ region 508, and the ohmic contact 509 can electrically function as part of the JFET gate (G). In addition, the N+ region 506 can be electrically coupled to the ohmic contact 507 to electrically function as the source (S); and the N drift region with the device region 501 and its ohmic contact 514 can electrically function as the drain (DR). According to semiconductor device physics, the electron current from the source (e.g., the N+ region 506) can be controlled by the gate voltage electrically coupled at the ohmic contacts 505, 509. The well region 503 and the device region 502 can create depletion regions and / or pinched regions in response to the gate voltage to control (i.e., to gate) the electron current flowing laterally within the N drift region 530. When a gate voltage is applied to the gate to form a potential barrier, for an electric field less than the critical field, a voltage can be maintained across the N drift region 530.

[0093] According to the teachings herein, when the guard rings 510 - 512 include PN junctions, the guard rings 510 - 512 covering the STI trenches 521 - 523 can advantageously enhance the voltage maintained across the N drift region 530 and increase the maximum breakdown voltage. The maximum breakdown voltage can be increased by spreading the electric field between the device region 501 and the device region 502; and according to the teachings herein, a PN junction can be formed for reverse bias operation. Forming a PN junction in the guard rings 510 - 512 such that one or more of them operate in reverse bias can advantageously enhance device breakdown without affecting device performance. For example, as will be further illustrated below in Figure 5C with a diode operating in reverse bias, the guard rings 510 - 512 can advantageously distribute the voltage without significantly affecting the reverse leakage current.

[0094] As discussed above, in some embodiments, the guard rings 510-512 and the number and / or density of the underlying STI trenches 521-523 may be selected based on process-defined critical dimensions and spacing rules (e.g., OD layer requirements); and although Figure 5A FIG. 500 illustrates a device cross-section 500 according to one embodiment—showing an N-drift region 530 having three STI trenches 521-523 under three guard rings 510-512, but other configurations are possible. For example, based on the size of the N-drift region 530, there may be more or fewer than three STI trenches 521-523 under the three guard rings 510-512. Based on the desired breakdown voltage, one or more dimensions in the N-drift region 530 may be selected.

[0095] In addition, as would be understood by one of ordinary skill in the art, power devices may be formed using the opposite polarity type. For example, a JFET may be formed in a P-drift region instead of the N-drift region 530.

[0096] Figure 5B FIG. 550 illustrates a device cross-section 550 according to another embodiment. The embodiment of the device cross-section 550 is similar to the embodiment of the device cross-section 500, except that the process uses a field oxide 546 instead of the STI trenches 521-523. For example, the field oxide 546 may be formed in a CMOS process using a LOCOS process recipe. The field oxide 546 may have a higher dielectric breakdown strength relative to the surface oxide 560 of the cross-section 500; and the guard rings 570-572 may be placed in the same manner as the guard rings 510-512 to spread the electric field at and / or near the surface of the N-drift region 530. In addition, according to the teachings herein, when the guard rings 570-572 include PN junctions, the guard rings 570-572 overlying the field oxide 546 may advantageously enhance the voltage maintained across the N-drift region 530 and increase the maximum breakdown voltage.

[0097] In addition, as discussed above, in some embodiments, the number and / or density of the guard rings 570-572 may be selected based on process-defined critical dimensions and spacing rules associated with the LOCOS process recipe. In addition, like the embodiment of the device cross-section 500, the embodiment of the device cross-section 550 should not be considered limiting. For example, there may be more and / or fewer than three guard rings 570-572; and power devices of the opposite polarity may also be possible.

[0098] Figure 5C FIG. 580 illustrates a schematic diagram 580 corresponding to an embodiment of a device. For example, this embodiment may be as shown by Figure 5A the cross-section 500 and / or Figure 5BThe power device (e.g., JFET) depicted by the cross-section 550. An embodiment of the schematic diagram 580 includes a JFET 581 having a gate G, a drain DR, and a source S. Refer to Figure 5A and / or Figure 5B , the gate G may correspond to and include regions (e.g., the device region 502 and the well region 503) coupled by ohmic contacts 505, 509; the drain DR may correspond to and include a region (e.g., the device region 501) electrically coupled by the ohmic contact 514, and the source S may correspond to and include a region (e.g., the N+ region 506) electrically coupled by the ohmic contact 507.

[0099] As illustrated, this embodiment may include a diode array 582, which is electrically connected in parallel with the drain DR and the gate G of the JFET 581. The diode array 582 includes a plurality of diodes D61 - D71 connected in series, and the diodes D61 - D71 may correspond to PN junctions placed (e.g., diffused) within the guard rings 510 - 512 and / or the guard rings 570 - 572. As shown, the cathode of the diode D61 (e.g., the N region of the guard ring) is electrically connected to the drain DR of the JFET 581; and the anode of the diode D71 (e.g., the P region of the guard ring) is electrically connected to the gate G of the JFET 581.

[0100] Also as illustrated, the gate of the JFET 581 is electrically coupled to (i.e., referenced to) ground GND; and in this way, the drain-to-source voltage VDS and the source-to-gate voltage VSG can also be referenced to ground GND. As illustrated, the drain-to-source voltage VDS and the source-to-gate voltage VSG are respectively coupled to the drain DR and the source S of the JFET 581. When the source-to-gate voltage VSG exceeds the pinch-off voltage (e.g., four volts) of the JFET 581, the drain-to-source current IDS can ideally be limited to a very low value (e.g., approximately and / or less than one microampere). Alternatively, when the source-to-gate voltage VSG is greater than the pinch-off voltage of the JFET 581, then the drain-to-source current IDS can ideally be large (e.g., approximately several amperes).

[0101] In accordance with the teachings herein, a diode array 582 can be formed within guard rings (e.g., guard rings 510 - 512 and / or guard rings 570 - 572) and electrically coupled to a JFET 581 such that the guard rings mitigate breakdown voltage drift without disturbing device operation and / or characteristics. For example, diodes D61 - D71 are electrically connected in series such that when VDS is greater than zero, diodes D61 - D71 operate in reverse bias. The number of diodes D61 - D71 can be selected such that the reverse leakage current IL is low relative to the off-state value of the drain-to-source current IDS. The off-state value of IDS can correspond to a condition where the source-to-gate voltage VSG is greater than the pinch-off voltage (e.g., four volts). For example, the number of diodes D61 - D71 can be selected such that when the source-to-gate voltage exceeds the pinch-off voltage for a specified value of the drain-to-source voltage VDS (e.g., seven hundred volts), the reverse leakage current IL is substantially zero (e.g., one-tenth and / or one-hundredth microampere) and / or significantly less than the drain-to-source current IDS (e.g., one microampere).

[0102] Figure 5D Schematic 590 illustrates another embodiment corresponding to the device. The device can also be a power device as depicted by Figure 5A cross-section 500 and / or Figure 5B cross-section 550, except that diode array 592 replaces diode array 582. Different from diode array 582, diode array 592 includes diodes D61 - D66 coupled in series and diodes D72 - D76 oriented in the opposite direction. For example, diode D61 and diode D72 are electrically coupled in a back-to-back arrangement. Also as illustrated, the cathode of diode D61 is electrically coupled to the drain DR of JFET 581 and the cathode of diode D76 is electrically coupled to the gate G of JFET 581. Thus, when the drain-to-source voltage VDS is greater than zero, then diodes D61 - D66 can operate in reverse bias to limit the leakage current IL. In addition, when the drain-to-source voltage VDS is less than zero, then diodes D72 - D76 can also operate in reverse bias.

[0103] Figure 6A Simplified layout 600 illustrates a route for a guard ring path 610 through device regions 601, 602 in accordance with an embodiment. Device regions 601, 602 can correspond to any of the foregoing device regions; for example, device region 601 can correspond to device region 401 and / or device region 501, and device region 602 can correspond to device region 402 and / or device region 502. By way of example, referring to Figure 4A and / or Figure 4B, the device region 601 may correspond to a drain (DR) having drain fingers 603a - 603c (i.e., extensions); and the device region 602 may correspond to a source / bulk (S / B) region having source / bulk S / B fingers 604a - 604b. Additionally, for clarity, the guard ring path 610 is illustrated by a single path line having a curved segment, and to show where the diode array 612 and the connection region 613 may be located in the simplified layout 600.

[0104] According to the teachings herein, the diode array 612 may be located in any part of the guard ring path 610, and for ease of illustration, the diode array 612 is shown as being formed along a straight - line portion of the guard ring path 610. Additionally, according to the teachings herein, the connection region 613 may be located in any part of the guard ring path 610; for example, as illustrated, the connection region 613 may be formed in a curved portion of the guard ring path 610.

[0105] Figure 6B An enlarged view 620 of the simplified layout of the diode array 612 according to an embodiment is illustrated. The enlarged view 620 of the simplified layout may correspond to an enlarged view of the guard ring path 610 between the drain finger 603b and the source finger 604b shown in the simplified layout 600. However, in the enlarged view 620 of the simplified layout, the guard ring path 610 of the simplified layout 600 is replaced by guard rings 621 - 623, which are schematically represented by directed lines and curved segments in the counter - clockwise direction. The guard rings 621 - 623 may be formed of polysilicon, which is deposited and patterned at the surface of the drift region defined between the device region 601 and the device region 602. For example, the guard rings 621 - 623 are shown by the drift region length marker 611 as following the counter - clockwise direction above the drift region of size WD (i.e., the drift region length).

[0106] According to the teachings herein, diodes may be formed within the guard rings 621 - 623 using standard process techniques (e.g., implantation regions and diffusion regions as described in the figures Figures 2A - 2H ). For example, the guard ring 621 includes a plurality of diodes, the plurality of diodes including diodes D81 - D82. Additionally, the guard ring 622 includes a plurality of diodes, the plurality of diodes including diodes D83 - D84; and the guard ring 623 includes a plurality of diodes, the plurality of diodes including diodes D85 - D86.

[0107] Although the simplified layout enlarged view 620 shows one embodiment with three guard rings 621-623, the number of guard rings can be more or less depending on the value of dimension WD (i.e., the drift region length). According to the teachings herein, the number of guard rings can be selected to meet the process critical dimension and / or OD layer requirements. For example, when implemented in a sub-micron (e.g., 0.35 micron) CMOS process, dimension WD can be sixty microns to meet the breakdown voltage (e.g., seven hundred and twenty-five volts); and the number of guard rings 621-623 can be between fifty and seventy.

[0108] Figure 6C A simplified layout enlarged view 620 of a diode array 612 according to another embodiment is illustrated. Figure 6C The embodiment of Figure 6B is similar to the embodiment of

[0109] Figure 6D A simplified layout enlarged view 650 of a connection region 613 according to an embodiment is illustrated. The simplified layout enlarged view 650 can correspond to an enlarged view of a guard ring path 610 around a curved portion of a drain finger 603b. However, in the simplified layout enlarged view 650, the guard ring path 610 of the simplified layout 600 is again replaced by guard rings 621-623, which are schematically represented by directed lines and curved segments in a clockwise direction.

[0110] According to the teachings herein, the connection region 613 can provide an electrical connection such that diodes (e.g., diodes D81-D86) are connected in series (see, for example, the series-connected diode arrays 472, 473, 582, and / or 592). For example, the connection region 613 schematically illustrates interconnect segments 641-645 as being serially coupled to the guard rings 621-623. For example, referring to the diode array 612, the interconnect segment 641 can electrically couple the device region 602 to the guard ring 621 such that the anode of diode D81 is electrically coupled to the device region 602 (e.g., source / bulk S / B). Similarly, the interconnect segment 644 can electrically couple the guard ring 622 to the guard ring 623 such that the cathode of diode D84 is connected in series (i.e., electrically coupled) with the anode of diode D85; and the interconnect segment 645 can electrically couple the guard ring 623 to the device region 601 such that the cathode of diode D86 is electrically coupled to the device region 601 (e.g., drain DR). Also as illustrated, the cathode of diode D82 can follow to the interconnect segment 642, which can be electrically coupled to a subsequent guard ring; and as illustrated, there can be more or fewer than four interconnect segments for serially connecting multiple guard rings 621-623.

[0111] Figure 7 Illustrates a method 700 for placing a guard ring with diodes according to one embodiment. Step 702 may correspond to determining a drift diffusion size WD (e.g., the size WD of the simplified layout enlargement 620) for meeting a maximum device voltage (i.e., breakdown voltage). Step 704 may correspond to determining the number of guard rings (e.g., the number of guard rings 621 - 623) to meet the OD density requirement. For example, in a sub-micron (e.g., 0.35 micron) process, the size WD may be sixty to seventy microns to meet the breakdown voltage requirement of approximately seven hundred and fifty volts; and to meet the OD density requirement, the number of guard rings (e.g., polysilicon guard rings) may be between fifty and seventy. The next step 706 may correspond to determining the number of diodes based on the maximum voltage. According to the teachings herein, the number of diodes (e.g., the number of diodes D41 - D50 connected in series, diodes D51 - D51, diodes D81 - D86) may be selected such that the leakage current of the diodes (e.g., leakage current IL) is significantly less than the drain-to-source current IDS in the off state (see, for example, any one of the Figure 4C , Figure 4D , Figure 5C , Figure 5D figures).

[0112] Figure 8 Illustrates a method 800 for placing a guard ring with diffused diodes according to one embodiment. Step 802 may correspond to placing a guard ring (e.g., guard ring 112) between a first device region (e.g., device region 101) and a second device region (e.g., device region 102). Step 804 may correspond to providing a first doping having a first polarity type (e.g., N region 105f). Step 806 may correspond to providing a second doping having a second polarity type (e.g., P region 106f) to form a diode (e.g., a PN junction formed by P region 106f and N region 105f). Step 808 may correspond to connecting the guard ring (e.g., guard ring 112) such that at least one diode operates in reverse bias. As described above, the at least one diode may have a leakage current IL less than the drain-to-source current IDS in the off state.

[0113] As presented herein, one aspect of the present teachings is a semiconductor device (e.g., a power device, LDMOS, and / or JFET as described herein). The semiconductor device includes a first device region (e.g., device regions 101, 301, 401, 501, and / or 601) and a second device region (e.g., device regions 102, 302, 402, 502, and / or 602). The semiconductor device further includes a drift region (e.g., N-drift regions 150, 430, and / or 530) between the first device region and the second device region and at least one guard ring (e.g., guard rings 110, 112, 410 - 412, 440 - 442, 510 - 512, 570 - 572, and / or 621 - 623). The at least one guard ring includes at least one diode (e.g., diodes D1 - D15, D20, D22, D25 - D27, and / or D28). The at least one diode is electrically coupled between the first device region and the second device region. The semiconductor device may receive a voltage (e.g., drain-to-source voltage VDS) between the first device region and the second device region. The at least one diode is configured to provide a leakage current (i.e., operate with a leakage current) in response to the voltage; and the at least one guard ring is configured to support an electric field within the drift region in response to the voltage. According to the teachings herein, a low leakage current can advantageously enhance the electric field spread without detrimentally affecting existing (i.e., conventional) semiconductor device performance; and the enhanced electric field spread can in turn reduce the breakdown voltage drift.

[0114] In another aspect, a power semiconductor device includes a first device region, a second device region, and a plurality of guard rings. The first device region (e.g., device region 101) and the second device region (e.g., device region 102) are separated by a drift region (e.g., N-drift region 150). The plurality of guard rings (e.g., guard rings 110, 112) are disposed above the drift region and are serially electrically coupled between the first device region and the second device region. For example, the Figure 1C drawings illustrate the serial coupling of guard rings 110, 112 using interconnect segments 107a - 107c. At least one of the guard rings (e.g., guard ring 110) includes a plurality of diodes (e.g., the Figure 1F diodes D1 - D4 of the drawings). The plurality of guard rings are configured to spread an electric field within the drift region. The electric field may be spread at or near the surface of the drift region to mitigate the detrimental effects of mobile and / or fixed charges at the surface of the drift region.

[0115] As in the Figure 1F drawings and Figure 1GAs shown, the plurality of guard rings may surround (i.e., encircle) the first device region; and the second device region may surround (i.e., encircle) the plurality of guard rings.

[0116] As in the Figure 4C , Figure 4D , Figure 5C , and Figure 5D shown, the plurality of diodes may form a series diode array (e.g., diode arrays 472, 473, 582, 592). The plurality of diodes may include at least one PIN diode (e.g., diode D20 in Figure 2A of the drawings). The series diode array may be configured to provide a leakage current (e.g., leakage current IL).

[0117] The above description of the illustrated embodiments of the present disclosure, including what is described in the abstract, is not intended to be exhaustive or limiting of the exact form disclosed. While specific embodiments and fabrication steps for a coupled polysilicon guard ring for enhancing the breakdown voltage in a power semiconductor device are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it should be understood that the specific example process recipes and device cross-sections are provided for purposes of explanation, and other recipes with more or fewer steps may also be employed in other embodiments and examples in accordance with the teachings herein.

[0118] Embodiment

[0119] Although the teachings herein are defined in the appended claims, it should be understood that the present disclosure may also be defined in accordance with the following embodiments:

[0120] 1. A semiconductor device, comprising:

[0121] A first device region;

[0122] A second device region;

[0123] A drift region located between the first device region and the second device region; and

[0124] At least one guard ring including at least one diode electrically coupled between the first device region and the second device region;

[0125] wherein the semiconductor device is configured to receive a voltage between the first device region and the second device region,

[0126] wherein the at least one diode is configured to provide a leakage current in response to the voltage, and

[0127] wherein the at least one guard ring is configured to support an electric field within the drift region in response to the voltage.

[0128] 2. The semiconductor device according to embodiment 1, wherein the semiconductor device includes a laterally diffused metal oxide field effect transistor (LDMOS).

[0129] 3. The semiconductor device according to any one of the preceding embodiments, wherein the semiconductor device includes a junction field effect transistor (JFET).

[0130] 4. The semiconductor device according to any one of the preceding embodiments, wherein the at least one guard ring includes polysilicon.

[0131] 5. The semiconductor device according to any one of the preceding embodiments, wherein the at least one diode includes a plurality of diodes electrically coupled in series.

[0132] 6. The semiconductor device according to any one of the preceding embodiments, wherein the at least one diode is a p-type, intrinsic, n-type (PIN) diode.

[0133] 7. The semiconductor device according to any one of the preceding embodiments, wherein the at least one guard ring is disposed on a field oxide.

[0134] 8. The semiconductor device according to any one of the preceding embodiments, wherein the at least one diode includes:

[0135] a first diode configured to operate in reverse bias in response to the voltage; and

[0136] a second diode.

[0137] 9. The semiconductor device according to any one of the preceding embodiments, wherein the second diode is configured to operate in reverse bias in response to the voltage.

[0138] 10. The semiconductor device according to any one of the preceding embodiments, wherein the second diode is configured to operate in forward bias in response to the voltage.

[0139] 11. The semiconductor device according to any one of the preceding embodiments, wherein the first device region is a drain region having a first polarity type.

[0140] 12. The semiconductor device according to any one of the preceding embodiments, wherein the first polarity type is n-type.

[0141] 13. The semiconductor device according to any one of the foregoing embodiments, wherein the second device region is a body region having a second polarity type opposite to the first polarity type.

[0142] 14. The semiconductor device according to any one of the foregoing embodiments, wherein the second polarity type is a p-type.

[0143] 15. The semiconductor device according to any one of the foregoing embodiments, wherein the at least one protection ring includes a first protection ring.

[0144] 16. The semiconductor device according to any one of the foregoing embodiments,

[0145] wherein the drift region includes a first shallow trench isolation (STI) trench; and

[0146] wherein the first protection ring is disposed on an oxide of the first STI trench.

[0147] 17. The semiconductor device according to any one of the foregoing embodiments,

[0148] wherein the at least one protection ring includes a second protection ring;

[0149] wherein the drift region includes a second STI trench; and

[0150] wherein the second protection ring is disposed on an oxide of the second STI trench.

[0151] 18. The semiconductor device according to any one of the foregoing embodiments, wherein the second STI trench is separated from the first STI trench by a critical dimension of an oxide density (OD) layer.

[0152] 19. A power semiconductor device, comprising:

[0153] a first device region and a second device region separated by a drift region; and

[0154] a plurality of protection rings disposed above the drift region and serially electrically coupled between the first device region and the second device region;

[0155] wherein at least one of the plurality of protection rings includes a plurality of diodes, and

[0156] wherein the plurality of protection rings are configured to disperse an electric field within the drift region.

[0157] 20. The power semiconductor device according to embodiment 19, wherein the plurality of protection rings surround the first device region and the second device region surrounds the plurality of protection rings.

[0158] 21. The power semiconductor device according to any one of the foregoing embodiments, wherein the voltage is greater than three hundred volts.

[0159] 22. The power semiconductor device according to any one of the foregoing embodiments, wherein the first device region is n-type, the second device region is p-type, and the drift region is n-type.

[0160] 23. The power semiconductor device according to any one of the foregoing embodiments, wherein the power semiconductor device is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS).

[0161] 24. The power semiconductor device according to any one of the foregoing embodiments, wherein the power semiconductor device is a junction field effect transistor (JFET).

[0162] 25. The power semiconductor device according to any one of the foregoing embodiments, wherein the plurality of diodes form a series diode array between the first device region and the second device region.

[0163] 26. The power semiconductor device according to any one of the foregoing embodiments, wherein the plurality of diodes includes at least one p-type, intrinsic, n-type (PIN) diode.

[0164] 27. The power semiconductor device according to any one of the foregoing embodiments, wherein the series diode array is configured to provide the leakage current.

[0165] 28. The power semiconductor device according to any one of the foregoing embodiments, wherein the series diode array is configured to be reverse biased by the voltage.

[0166] 29. The power semiconductor device according to any one of the foregoing embodiments, wherein the series diode array includes:

[0167] A first diode configured to be reverse biased by the voltage.

[0168] 30. The power semiconductor device according to any one of the foregoing embodiments, wherein the series diode array includes:

[0169] A second diode configured to be forward biased by the voltage.

[0170] 31. The power semiconductor device according to any one of the foregoing embodiments, wherein the plurality of protection rings include:

[0171] At least one straight segment; and

[0172] At least one curved segment.

[0173] 32. The power semiconductor device according to any one of the foregoing embodiments, wherein the plurality of diodes include at least one diode diffused within the at least one straight segment.

[0174] 33. The power semiconductor device according to any one of the foregoing embodiments, wherein the plurality of diodes include at least one diode diffused within the at least one curved segment.

Claims

1. A semiconductor device, comprising: A first device region; A second device region; A drift region located between the first device region and the second device region; A first guard ring and a second guard ring, each guard ring including a guard ring pattern and including at least one diode electrically coupled between the first device region and the second device region; And A first shallow trench isolation trench and a second shallow trench isolation trench, each shallow trench isolation trench including a trench pattern consistent with the guard ring pattern of the corresponding first guard ring and second guard ring, wherein the first guard ring is disposed on the oxide of the first shallow trench isolation trench, the second guard ring is disposed on the oxide of the second shallow trench isolation trench, and the first shallow trench isolation trench and the second shallow trench isolation trench are separated; Wherein the semiconductor device is configured to receive a voltage between the first device region and the second device region, Wherein the at least one diode is configured to provide a leakage current in response to the voltage, and Wherein the first guard ring and the second guard ring are configured to support an electric field in the drift region in response to the voltage.

2. The semiconductor device according to claim 1, wherein the semiconductor device includes a laterally diffused metal oxide semiconductor field effect transistor (LDMOS).

3. The semiconductor device according to claim 1, wherein the semiconductor device includes a junction field effect transistor (JFET).

4. The semiconductor device according to claim 1, wherein the first guard ring and the second guard ring include polysilicon.

5. The semiconductor device according to claim 1, wherein the at least one diode includes a plurality of diodes electrically coupled in series.

6. The semiconductor device according to claim 1, wherein the at least one diode is a p-type, intrinsic, n-type (PIN) diode.

7. The semiconductor device according to claim 1, wherein the first guard ring and the second guard ring are disposed on a gate oxide.

8. The semiconductor device according to claim 1, wherein: The first device region and the second device region include a drain and a source of a transistor; The voltage forward biases the source with respect to the drain; And The at least one diode includes: a first diode configured to operate in reverse bias in response to the voltage; And a second diode.

9. The semiconductor device according to claim 8, wherein the second diode is configured to operate in reverse bias in response to the voltage.

10. The semiconductor device according to claim 8, wherein the second diode is configured to operate in forward bias in response to the voltage.

11. The semiconductor device according to claim 1, wherein the first device region is a drain region having a first polarity type.

12. The semiconductor device according to claim 11, wherein the first polarity type is n-type.

13. The semiconductor device according to claim 11, wherein the second device region is a body region having a second polarity type opposite to the first polarity type.

14. The semiconductor device according to claim 13, wherein the second polarity type is a p-type.

15. A power semiconductor device, comprising: a first device region and a second device region separated by a drift region; and a plurality of guard rings disposed above the drift region and electrically coupled in series to form a guard ring pattern between the first device region and the second device region; and a shallow trench isolation pattern conforming to the guard ring pattern, wherein the shallow trench isolation pattern includes a plurality of separated shallow trench isolation trenches, each shallow trench isolation trench being located below a corresponding guard ring; wherein at least one of the plurality of guard rings includes a plurality of diodes, and wherein the plurality of guard rings are configured to spread the electric field within the drift region.

16. The power semiconductor device according to claim 15, wherein the plurality of guard rings surround the first device region and the second device region surrounds the plurality of guard rings.

17. The power semiconductor device according to claim 15, wherein the first device region is an n-type, the second device region is a p-type, and the drift region is an n-type.

18. The power semiconductor device according to claim 15, wherein the power semiconductor device is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS).

19. The power semiconductor device according to claim 15, wherein the power semiconductor device is a junction field effect transistor (JFET).

20. The power semiconductor device according to claim 15, wherein the plurality of diodes form a series diode array between the first device region and the second device region.

21. The power semiconductor device according to claim 20, wherein the plurality of diodes include at least one p-type, intrinsic, n-type (PIN) diode.

22. The power semiconductor device according to claim 20, wherein the series diode array is configured to provide a leakage current.

23. The power semiconductor device according to claim 20, wherein the series diode array is configured to be reverse biased by a voltage.

24. The power semiconductor device according to claim 20, wherein: the first device region and the second device region include a drain and a source of a transistor; and the series diode array includes: a first diode configured to be reverse biased by a voltage, and the source is forward biased with respect to the drain.

25. The power semiconductor device according to claim 24, wherein the series diode array includes: a second diode configured to be forward biased by the voltage, and the source is forward biased with respect to the drain.

26. The power semiconductor device according to claim 20, wherein the plurality of guard rings include: at least one straight segment; and at least one curved segment.

27. The power semiconductor device according to claim 26, wherein the plurality of diodes includes at least one diode diffused within the at least one straight segment.

28. The power semiconductor device according to claim 26, wherein the plurality of diodes includes at least one diode diffused within the at least one curved segment.

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