Method for manufacturing semiconductor optical device and semiconductor optical device

Abstract

A method for manufacturing a semiconductor optical device is provided, which can improve the optical device characteristics of a semiconductor optical device having a semiconductor layer containing at least In, As and Sb. The method for manufacturing a semiconductor optical device of the present invention comprises the following steps: a first step of forming an etching stop layer on an InAs growth substrate; a second step of forming a semiconductor stack; a third step of forming a power distribution unit; a fourth step of bonding to a support substrate via a metal bonding layer; and a fifth step of removing the InAs growth substrate.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor optical device and the semiconductor optical device. Background Art

[0002] In the past, semiconductor light-emitting elements that emit or receive light in the mid-infrared region, such as semiconductor light-emitting elements that emit light in the mid-infrared region with a wavelength of 1700 nm or more and semiconductor light-receiving elements that detect light in the mid-infrared region, are known. For example, semiconductor light-emitting elements that emit light in the mid-infrared region are widely used in sensors, gas analysis, and the like.

[0003] When the wavelength of light received and emitted by such a semiconductor optical device is set to the mid-infrared region of 1.7μm to 12μm, generally speaking, compound substrates such as GaAs, InP, InAs, GaSb, and InSb are used as growth substrates in order from the material with the smallest lattice constant, and a combination of mixed crystals of these compounds is epitaxially grown on the growth substrate to form the substrate. Among these compound substrates, the lattice constants of the light-emitting layer in the mid-infrared region of 1.7μm to 12μm are similar to those of the InAs, GaSb, and InSb compound substrates. Therefore, it can be considered that the use of InAs, GaSb, and InSb is preferred as a growth substrate for semiconductor optical devices in the mid-infrared region.

[0004] For example, in Patent Document 1, an InAsSbP layer is formed on an InAs substrate, and then an InAsSbP active layer is formed. In Patent Document 1, a conductive InAs substrate is used directly for a light emitting element for a wavelength of 2.6 to 4.7 μm.

[0005] In addition, Patent Document 2 states that a GaSb layer and an InGaAsSb-based multi-quantum well layer are formed on an InP substrate to form a light-receiving element. It also states that the GaSb layer has light absorption due to the influence of free carriers and that the InP substrate is transparent to light with a wavelength of 3 μm to 12 μm.

[0006] Furthermore, Patent Document 3 discloses a series connection type optical device having an operating wavelength of 1 μm or more formed on a semi-insulating GaAs substrate for growth.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application No. 2015-534270

[0010] Patent Document 2: Japanese Patent Application Publication No. 2012-256826

[0011] Patent Document 3: Japanese Patent Application Publication No. 2010-238999 Summary of the invention

[0012] Problem that the invention aims to solve

[0013] In recent years, it has been sought to further improve the characteristics of semiconductor optical devices such as the efficiency of light-emitting elements and the sensitivity of light-receiving elements. Here, any of the technologies described in Patent Documents 1 to 3 is to use the growth substrate directly as a supporting substrate for semiconductor optical devices. However, in this case, it is difficult to apply a method of improving the characteristics of semiconductor optical devices by arranging a distribution unit containing an insulating material and a conductive material between the supporting substrate and the semiconductor layer. Therefore, the inventors of the present invention have tried to apply a method (hereinafter referred to as "bonding method") in which a distribution unit is arranged on a semiconductor stack formed by epitaxial growth on a growth substrate, and the semiconductor stack and the distribution unit are bonded to a supporting substrate different from the growth substrate, and then the growth substrate is removed. In order to produce a semiconductor optical device with a mid-infrared region as an operating wavelength, an InAsSbP-based III-V compound semiconductor containing at least In, As and Sb is usually epitaxially grown on a growth substrate. When using an InAsSbP-based III-V compound semiconductor containing at least Sb, it is an option to use an InP substrate or a GaAs substrate as a growth substrate as in Patent Documents 2 and 3. However, in view of the lattice constant difference between the semiconductor layer formed on the growth substrate, there is a concern that the crystallinity of the semiconductor layer will deteriorate for these growth substrates. Therefore, the inventors of the present invention thought of using an InAs substrate as a growth substrate. However, the inventors of the present invention confirmed through experiments that when an InAs substrate is used as a growth substrate and a bonding method is applied to form a power distribution unit on a semiconductor stack, the InAs substrate needs to be removed. As a result, it is difficult to remove the InAs substrate without etching the semiconductor stack grown on the InAs substrate and without undergoing an overly complicated process as a manufacturing process. The inventors of the present invention thought of the following new topic: In order to use a bonding method to set a power distribution unit, in order to achieve the improvement of the characteristics of a semiconductor optical device having a semiconductor layer containing at least In, As and Sb, it is necessary to establish a removal technology for the InAs substrate. If the InAs substrate can be appropriately removed in the bonding method, the power distribution unit can be configured, and therefore, the improvement of the characteristics of a semiconductor optical device having an InAsSbP-based III-V compound semiconductor can be fully anticipated.

[0014] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor optical device, which can improve the optical device characteristics of a semiconductor optical device having a semiconductor layer containing at least In, As and Sb. Furthermore, an object of the present invention is to provide a semiconductor optical device manufactured by the manufacturing method.

[0015] Solutions for solving problems

[0016] The inventors have conducted in-depth research on solutions to the above-mentioned problems and have discovered an etching stopper layer that can remove the InAs growth substrate without etching the semiconductor stack disposed on the InAs growth substrate when using a bonding method and without undergoing an excessively complicated manufacturing process, thereby completing the present invention. That is, the main structure of the present invention is as follows.

[0017] (1) A method for manufacturing a semiconductor optical device, characterized by comprising the following steps:

[0018] In a first step, an etching stopper layer is formed on an InAs growth substrate, wherein the etching stopper layer is formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb;

[0019] In a second step, a semiconductor stack is formed on the etching stop layer, wherein the semiconductor stack is stacked with a plurality of layers formed of an InAsSbP-based III-V compound semiconductor containing at least In and As;

[0020] A third step is to form a power distribution portion on the semiconductor stack, wherein the power distribution portion includes a transparent insulating layer having a through hole and an ohmic electrode portion provided in the through hole;

[0021] A fourth step is to bond the semiconductor stack and the power distribution unit to a support substrate at least via a metal bonding layer; and

[0022] The fifth step is to remove the aforementioned InAs growth substrate.

[0023] The InAsSbP-based Group III-V compound semiconductor of at least one of the layers in the semiconductor stack contains at least In, As, and Sb.

[0024] (2) The method for manufacturing a semiconductor optical device according to (1) above, wherein the GaAsSb-based III-V compound semiconductor constituting the etching stopper layer contains at least Ga, As, and Sb.

[0025] (3) The method for manufacturing a semiconductor optical device according to (1) above, wherein the etching stop layer comprises a superlattice stacked body,

[0026] The superlattice stacked body includes a layer containing Ga, As, and Sb.

[0027] (4) The method for manufacturing a semiconductor optical device according to any one of (1) to (3), wherein the semiconductor stacked body includes an n-type cladding layer, an active layer, and a p-type cladding layer in this order.

[0028] (5) The method for manufacturing a semiconductor optical device according to (4) above, wherein the semiconductor stack has a double heterostructure, and the InAsSbP-based III-V compound semiconductor constituting the active layer contains at least In, As, and Sb.

[0029] (6) A method for manufacturing a semiconductor optical device according to (4) above, wherein the semiconductor stack has a quantum well structure having a barrier layer and a well layer, and the InAsSbP-based III-V compound semiconductor constituting the barrier layer contains at least In, As and Sb.

[0030] (7) The method for manufacturing a semiconductor optical device according to any one of (1) to (6), wherein an operating wavelength of the semiconductor optical device is 3.4 μm or more.

[0031] (8) A semiconductor optical device, characterized in that it comprises:

[0032] support base plate;

[0033] A metal bonding layer disposed on the surface of the supporting substrate;

[0034] a power distribution portion on the metal bonding layer, comprising a transparent insulating layer having a through hole and an ohmic electrode portion provided in the through hole; and

[0035] The semiconductor stack on the power distribution portion is formed by stacking a plurality of layers of InAsSbP-based III-V compound semiconductors containing at least In and As.

[0036] (9) The semiconductor optical device according to (8), wherein the semiconductor stack includes an n-type cladding layer, an active layer, and a p-type cladding layer in this order.

[0037] (10) The semiconductor optical device according to (9) above, wherein the semiconductor stack has a double heterostructure, and the InAsSbP-based III-V compound semiconductor constituting the active layer contains at least In, As, and Sb.

[0038] (11) A semiconductor optical device according to (9) above, wherein the semiconductor stack has a quantum well structure having a barrier layer and a well layer, and the InAsSbP-based III-V compound semiconductor constituting the barrier layer contains at least In, As and Sb.

[0039] (12) The semiconductor optical device according to any one of (8) to (11) above, wherein an operating wavelength of the semiconductor optical device is 3.4 μm or more.

[0040] Effects of the Invention

[0041] According to the present invention, a method for manufacturing a semiconductor optical device can be provided, which can improve the optical device characteristics of a semiconductor optical device having a semiconductor layer containing at least In, As and Sb. Furthermore, the present invention can provide a semiconductor optical device manufactured by the manufacturing method. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0043] Figure 2 Then Figure 1 A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0044] Figure 3 Then Figure 2 A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0045] Figure 4A Then Figure 3 A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0046] Figure 4B Then Figure 4A A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0047] Figure 4C Then Figure 4B A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0048] Figure 4D Then Figure 4C A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0049] Figure 5 Then Figure 4D A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0050] Figure 6 Then Figure 5 A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0051] Fig. 7A Then Figure 6 A schematic cross-sectional view illustrating an embodiment of a method for manufacturing a semiconductor optical device according to the present invention.

[0052] Figure 7B Then Fig. 7A A schematic cross-sectional view illustrating an example of a semiconductor optical device obtained by one embodiment of the method for manufacturing a semiconductor optical device according to the present invention.

[0053] Figure 8 It is a schematic enlarged cross-sectional view for explaining a suitable embodiment of a power distribution unit in the method for manufacturing a semiconductor optical device according to the present invention.

[0054] Fig. 9 It is a schematic cross-sectional view illustrating another embodiment of the semiconductor optical device according to the present invention.

[0055] Fig. 10A It is a schematic plan view showing the shape and arrangement of the ohmic electrode portion after the power distribution portion in Example 1 is manufactured.

[0056] Fig. 10B 1 is a schematic plan view showing the shape and arrangement of the upper electrode in Example 1. DETAILED DESCRIPTION

[0057] Before describing the embodiments of the present invention, the following aspects will be described in advance.

[0058] <Composition>

[0059] First, in this specification, when the composition ratio of the III-V compound is not clearly stated and it is abbreviated as "AlInGaAsSbP", it refers to an arbitrary compound in which the chemical composition ratio of the III group element (the sum of Al, In, and Ga) and the V group element (As, Sb, and P) is 1:1, and the ratio of Al, In, and Ga as the III group elements and the ratio of As, Sb, and P as the V group elements are each uncertain. At this time, it includes the case where the III group element does not contain any one or two elements of Al, In, and Ga, and it includes the case where the V group element does not contain any one or two elements of As, Sb, and P. Among them, when it is clearly stated that "at least one or two of the specific III group elements and the V group elements are included", the III group element and the V group element as the recording object are respectively included in an amount of more than 0% and less than 100%. For example, AlInGaAsSbP "at least In and Sb" contains In and Sb in an amount of more than 0% and less than 100%. At this time, Al and Ga other than In and Sb and As and P may be included or not included. In addition, the AlInGaAsSbP “system” III-V group compound semiconductor may contain any dopant. It should be noted that the component composition ratio of each III-V group element of AlInGaAsSbP can be measured by photoluminescence measurement, X-ray diffraction measurement, and the like.

[0060] On the other hand, when the specific group-III element or group-V element is removed from the description of "AlInGaAsSbP" and described, it is regarded that the group-III element or group-V element as the object is not contained in the composition. For example, when it is denoted as "InAsSbP", its composition is represented by the general formula InAs x Sb y P z ) indicating that Al and Ga are not contained. It should be noted that in this case, regarding the composition ratio of each element, the following relationship holds, and the total of the composition ratios of the group-V elements is 1. In addition, the total of the composition ratios of the group-III elements is also 1.

[0061] z = 1 - x - y, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1.

[0062] <p-Type, n-Type, i-Type, and Doping Concentration>

[0063] In this specification, a layer that functions as a p-type electrically is called a p-type semiconductor layer (sometimes simply referred to as a "p-type layer"), and a layer that functions as an n-type electrically is called an n-type semiconductor layer (sometimes simply referred to as an "n-type layer"). On the other hand, when specific impurities such as Si, Zn, S, Sn, and Mg are not actively added and it does not function as a p-type or n-type electrically, it is called "i-type" or "undoped". In an undoped group-III-V compound semiconductor layer, impurities that are inevitable in the manufacturing process may be mixed in. Specifically, when the doping concentration is low (for example, less than 7.6×10 15 atoms / cm 3 ), it is regarded as "undoped" in this specification. The values of the impurity concentrations of Si, Sn, S, Te, Mg, Zn, etc. are based on SIMS analysis. It should be noted that near the boundary of each semiconductor layer, the value of the doping concentration changes significantly. Therefore, the value of the doping concentration at the center in the film thickness direction of each layer is used as the value of the doping concentration.

[0064] <Film Thickness and Composition of Each Layer>

[0065] In addition, the overall thickness of each formed layer can be calculated by cross-sectional observation based on a scanning electron microscope or a transmission electron microscope. Furthermore, the thickness of each layer can be calculated separately by cross-sectional observation of the growth layer based on a transmission electron microscope. In addition, when the thickness of each layer is small as in a superlattice structure, TEM-EDS can be used to measure the thickness. It should be noted that in a cross-sectional view, when a specified layer has an inclined surface, the thickness of this layer uses the maximum height from the flat surface of the layer directly below this layer.

[0066] <Correspondence of Drawings in Embodiment>

[0067] Before describing the semiconductor optical device based on the present invention, first for Figure 1 to Figure 7B The relationship between Figure 1 to Figure 7B 1 is a series of schematic cross-sectional views illustrating the various steps in one embodiment of a method for manufacturing a semiconductor optical device 100 according to the present invention. Figures 1 to 5 and Figure 6 to Figure 7B In addition, Figure 8 is a process for forming the power distribution unit 160 (corresponding to Figure 4C ) is an enlarged view of a suitable method of the power distribution unit 160 in the embodiment of the present invention. It should be noted that, in principle, the same reference numerals are given to the same or corresponding components, and repeated descriptions are omitted. In addition, the semiconductor optical device based on the present invention is roughly divided into two embodiments: a light-emitting type and a light-receiving type. The light-emitting type semiconductor optical device further includes a semiconductor light-emitting element with a single element structure and a semiconductor light array having semiconductor light-emitting elements connected in series on a substrate, Figure 7B The semiconductor optical device 100 is one embodiment of a semiconductor light emitting element. Fig. 9 The semiconductor optical device 200 is one embodiment of a semiconductor optical array. It should be noted that, in each drawing, for the sake of convenience of explanation, the aspect ratios of the substrate and each layer are exaggerated compared to the actual ratios.

[0068] Next, a method for manufacturing a semiconductor optical device according to the present invention will be described. The method for manufacturing a semiconductor optical device according to the present invention includes at least a first step, a second step, a third step, a fourth step, and a fifth step which will be described later.

[0069] In the above-mentioned first step, an etching stopper layer is formed on the InAs growth substrate, and the etching stopper layer is formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb. In the above-mentioned second step, a semiconductor stack is formed on the aforementioned etching stopper layer, and the semiconductor stack is stacked with multiple layers formed of an InAsSbP-based III-V compound semiconductor containing at least In and As. In the above-mentioned third step, a distribution unit is formed on the aforementioned semiconductor stack, and the distribution unit has a transparent insulating layer with a through hole and an ohmic electrode unit arranged in the aforementioned through hole. In the above-mentioned fourth step, the aforementioned semiconductor stack and the aforementioned distribution unit are bonded to a supporting substrate at least by means of a metal bonding layer. In the above-mentioned fifth step, the aforementioned InAs growth substrate is removed. Here, the InAsSbP-based III-V compound semiconductor of at least one of the aforementioned layers in the aforementioned semiconductor stack contains at least In, and As and Sb.

[0070] In the present invention, as described above, a layer formed of an InAsSbP-based III-V compound semiconductor containing at least In, As and Sb is epitaxially grown on an InAs growth substrate (second step), and then a power distribution unit is formed (third step). Furthermore, in the present invention, after bonding with a support substrate different from the InAs growth substrate (fourth step), the InAs growth substrate is removed (fifth step). Therefore, an etching stopper layer formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb is formed on the growth substrate (first step).

[0071] Hereinafter, first, the manufacturing method according to the present invention will be specifically described by describing an embodiment of a method for manufacturing a semiconductor optical device 100 as a semiconductor light emitting element.

[0072] (First Embodiment: Semiconductor Light Emitting Element)

[0073] The method for manufacturing the semiconductor optical device 100 according to the first embodiment of the present invention comprises at least the following steps: Figure 1 ) is formed on the first step ( Figure 2 ); a second step of forming a semiconductor stack 140 on the etching stop layer 130 ( Figure 3 ); forming a third step of distributing the power supply unit 160 on the semiconductor stack 140 ( Figure 4C ); a fourth step of bonding the support substrate 180 ( Figure 5 ); and a removal step of removing the growth substrate 110 ( Figure 6 ). Figure 1 to Figure 7B In this way, the present production method may further optionally include an initial buffer layer forming step (see Figure 2 ), metal reflective layer forming step (refer to Figure 4D ), metal bonding layer forming step (refer to Figure 5 ), initial buffer layer removal process (refer to Fig. 7A ), etching stop layer removal process (refer to Fig. 7A ) and electrode formation process (refer to Figure 7B ). Hereinafter, each step including the above-mentioned optional step will be described in sequence.

[0074] <First step>

[0075] Reference Figure 1 , Figure 2. First, in the first process, an etch stop layer 130 formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb is formed on the InAs growth substrate 110. And the etch stop layer 130 is formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb. It should be noted that before the first process, this manufacturing method may further have an initial buffer layer formation process of forming an initial buffer layer 120 on the surface of the InAs growth substrate 110. At this time, the etch stop layer 130 is formed on the initial buffer layer 120.

[0076] <<InAs growth substrate>>

[0077] The InAs growth substrate 110 can be any of a commonly available n-type InAs substrate, an undoped InAs substrate, and a p-type InAs substrate.

[0078] <<Etch stop layer>>

[0079] The etch stop layer 130 is a semiconductor layer that has a sufficiently low etching rate with respect to the etching solution (such as concentrated hydrochloric acid with a concentration of 8 M (mol / L) or more, which will be described in detail in the fifth process) when etching the InAs growth substrate 110 and is insoluble until the InAs growth substrate is completely removed. Furthermore, the etch stop layer 130 has a lattice constant that enables growth on the InAs growth substrate 110.

[0080] -Composition range of the etch stop layer-

[0081] If the As composition ratio is denoted as x ESL , then the composition range of the GaAsSb-based III-V compound semiconductor of the etch stop layer 130 is represented by GaAs xE Sb 1-xE . And the As composition x E is preferably 0 ≤ x E ≤ 0.4. If the As composition x E exceeds 0.4, it may be etched even by the above etching solution. If the As composition ratio x E is within this range, the etch stop layer 130 has insolubility in the above etching solution and can grow epitaxially on the InAs growth substrate 110. In addition, the GaAsSb-based III-V compound semiconductor preferably contains at least Ga, as well as As and Sb. That is, the As composition ratio x E is more preferably 0 < x E , and further preferably 0.02 ≤ x E ≤ 0.13. If the As composition ratio x E is within this range, the lattice constant difference from the InAs growth substrate can be reduced.

[0082] -Layer structure of etching stop layer-

[0083] It should be noted that the etching stopper layer 130 may have a single-layer structure or a multi-layer structure. Furthermore, it is also preferable that the etching stopper layer 130 has a superlattice stacked body, and the superlattice stacked body has a layer containing Ga, As, and Sb. Figure 2 In the embodiment, the etching stop layer 130 has a superlattice stack formed by repeatedly stacking the first layer 130a and the second layer 130b in sequence. For example, even if it is difficult to grow a composition that matches the lattice of the growth substrate in a single layer, the strain can be compensated by forming a superlattice structure with a composition having a larger lattice constant and a composition having a smaller lattice constant than the growth substrate with a thickness below the critical film thickness. By making the lattice constant of the overall average composition of the etching stop layer of the superlattice structure close to the lattice constant of the growth substrate, an etching stop layer with good crystallinity and sufficient film thickness can be obtained. In addition, the composition of the first layer 130a is shown as GaAs xE1 Sb 1-xE1 When , it can be set to 0.08≤x E1 ≤0.80, preferably 0.10≤x E1 ≤0.40. In addition, the composition of the second layer 130b is shown as GaAs xE2 Sb 1-xE2 When , it can be set to 0≤x E2 ≤0.08, preferably 0≤x E2 ≤0.05. At this time, when the film thickness of the first layer 130a is represented by t1 and the film thickness of the second layer 130b is represented by t2, the average composition x E3 You can use (x E1 ×t1+x E2 × t2) / (t1+t2). The average composition x E3 Can be set to 0≤x E3 ≤0.4, more preferably 0.02≤x E3 ≤0.13.

[0084] -Thickness of etching stop layer-

[0085] The thickness of the entire etching stopper layer 130 is not limited, and can be, for example, 10 nm to 200 nm. When the etching stopper layer 130 includes a superlattice stack, the thickness of each layer can be 0.05 nm to 10.0 nm, and the number of groups can be 10 to 200.

[0086] - Initial Buffer Layer -

[0087] As described above, the initial buffer layer 120 can be formed on the surface of the InAs growth substrate 110. This is because when the etching stop layer 130 is directly formed on the InAs growth substrate 110, the influence of the oxide film and contamination on the substrate surface of the InAs growth substrate 110 can be prevented. By growing the initial buffer layer formed of InAs, it is expected that the interface between the etching stop layer 130 and the initial buffer layer 120 will be cleaned. As a result, it is also expected that the crystallinity of the semiconductor layer to be epitaxially grown can be improved and the surface after the growth substrate is removed can be stabilized.

[0088] -Growth method-

[0089] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, etc. For example, trimethyl indium (TMIn) as an In source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as a Ga source, arsine (AsH3) and tert-butyl arsine (TBAs) as an As source, trimethyl antimony (TMSb), triethyl antimony (TESb), tri(dimethylamino) antimony (TDMASb) as an Sb source, phosphine (PH3) and tert-butyl phosphine (TBP) as a P source are used in a predetermined mixing ratio, and these raw material gases are vapor-phase grown while using a carrier gas, thereby forming an InGaAsSbP layer with a desired thickness according to the growth time. It should be noted that other InGaAsP and GaAsSb to be epitaxially grown can also be formed by the same method. When each layer is doped to a p-type or n-type, a desired dopant source gas may be used. The same applies to the second step.

[0090] <Second step>

[0091] Reference Figure 3 In the second step, a semiconductor stack 140 is formed on the etching stop layer 130, wherein the semiconductor stack 140 is stacked with a plurality of layers formed of InAsSbP-based III-V compound semiconductors containing at least In and As. The semiconductor stack 140 in this embodiment sequentially includes an n-type cladding layer 141, an active layer 145, and a p-type cladding layer 147. It should be noted that as long as the active layer is formed between the p-type cladding layer and the n-type cladding layer, it can be formed by either the p-type cladding layer or the n-type cladding layer. Figure 3 , describing a method of sequentially forming an active layer 145 and a p-type cladding layer 147 on an n-type cladding layer 141 .

[0092] <<Semiconductor stack>>

[0093] The semiconductor stack 140 can be made into a double heterogeneous (DH) structure in which the active layer 145 is sandwiched by an n-type cladding layer 141 and a p-type cladding layer 147. At this time, the InAsSbP-based III-V compound semiconductor constituting the active layer 145 preferably contains In, As and Sb. In addition, in order to improve the light output by suppressing crystal defects, the active layer 145 is also preferably provided with a multi-quantum well (MQW) structure. The active layer 145 having the multi-quantum well structure can be formed by alternating and repeating a structure of a well layer 145w and a barrier layer 145b. In addition, the well layer 145w can be made of InAsSb containing at least In, As and Sb. In addition, the barrier layer 145b can be made of InAsSbP having a larger band gap than the well layer 145w. Using such a semiconductor stack 140, the light emission wavelength of the semiconductor optical device 100 can be set to a wavelength in the desired mid-infrared region.

[0094] -Working wavelength (light emission wavelength)-

[0095] For example, by changing the composition of the active layer 145, the peak wavelength of light emission of the semiconductor optical device 100 can be set to 1700 to 12000 nm (1.7 to 12 μm). The operating wavelength (light emission wavelength) of the semiconductor optical device 100 can be set to be above 3.1 μm, and preferably above 3.4 μm. In the aforementioned patent document 1, when the InAs substrate used as a growth substrate is directly used as a supporting substrate, InAs partially absorbs mid-infrared light with a wavelength less than 3.4 μm, and even if the wavelength is above 3.4 μm, the light absorption is not zero. In the present embodiment, since the InAs growth substrate 110 is removed, there is no need to worry about the light emission from such an active layer being absorbed by the InAs substrate, and the optical device characteristics of the semiconductor optical device are particularly advantageous.

[0096] - Composition of the active layer -

[0097] In addition, the component composition of the well layer 145w is shown as InAs xw Sb 1-xw When , it can be set to 0.7≤xw≤1.0, preferably 0.8≤xw≤1.0. In addition, the component composition of the barrier layer 145b is shown as InAs xb P 1-xb When , it can be set to 0.5≤xb≤1, preferably 0.8≤xb≤1. It should be noted that, in the case of a quantum well structure, it is also preferred to adjust the composition difference between the well layer 145w and the barrier layer 145b based on the composition change of the InAsP series III-V group compound to apply strain to the well layer.

[0098] -Composition of the cladding-

[0099] The n-type cladding layer 141 and the p-type cladding layer 147 are preferably layers formed of an InAsP-based III-V compound semiconductor containing at least In and As. This is because, by making the n-type cladding layer 141 and the p-type cladding layer 147 free of Ga, it is possible to reliably prevent etching of each cladding layer when removing the etching stopper layer 130. In addition, as the n-type cladding layer 141, it is particularly preferred to use n-type InAs, and as the p-type cladding layer 147, it is particularly preferred to use p-type InAs.

[0100] -Film thickness of semiconductor stack-

[0101] The film thickness of the semiconductor stack 140 as a whole is not limited, and can be set to 2μm to 8μm, for example. In addition, the film thickness of the n-type cladding layer 141 is also not limited, and can be set to 0.5μm to 5μm, for example. Furthermore, the film thickness of the active layer 145 is also not limited, and can be set to 3nm to 1000nm, for example. In addition, the film thickness of the p-type cladding layer 147 is also not limited, and can be set to 0.1μm to 3μm, for example. When the active layer 145 has a quantum well structure, the film thickness of the well layer 145w can be set to 3nm to 20nm, the thickness of the barrier layer 145b can be set to 5 to 50nm, and the number of groups of the two can be set to 1 to 50.5 groups. It should be noted that it is also preferred to form the barrier layer 145b first, and then alternately stack the well layer 145w and the barrier layer 145b (film thickness: 8nm) in N groups (N is an integer), forming a total of N.5 groups. At this time, both ends of the quantum well structure become barrier layers 145b.

[0102] -Other semiconductor layers in the semiconductor stack-

[0103] In addition, although not shown in the figure, the semiconductor stack 140 is preferably further provided with a contact layer having a higher doping concentration than each cladding layer on the side of the n-type cladding layer 141 and the p-type cladding layer 147 opposite to the active layer 145 (i.e., the side where the electrode described later is formed). In addition, the semiconductor stack 140 may include an i-type spacer layer between the n-type cladding layer 141 and the active layer 145 and between the active layer 145 and the p-type cladding layer 147. In addition, a p-type electron blocking layer may be provided between the active layer 145 and the p-cladding layer 147.

[0104] <Third step>

[0105] In the third step, a power distribution unit 160 is formed on the p-type cladding layer 147 (on the contact layer when a contact layer is further provided), and the power distribution unit 160 includes a transparent insulating layer 161 having a through hole 161A and an ohmic electrode unit 165 provided in the through hole 161A. The specific method of forming the power distribution unit 160 is arbitrary. The order of the steps can be selected in various ways. Figure 4A , Figure 4B and Figure 4C , describing a specific method for forming the power distribution unit 160.

[0106] First, a transparent insulating layer 161 is formed on the semiconductor stack 140 ( Figure 4A As a film forming method, a known method such as a plasma CVD method and a sputtering method can be applied. Then, a resist pattern is formed on the transparent insulating layer 161 using a photomask. Next, using the resist pattern, a portion of the transparent insulating layer 161 is removed by etching to form the through hole 161A ( Figure 4B ). By providing a through hole 161A, a local area of ​​the outermost surface of the semiconductor stack 140 is exposed. Thereafter, as long as the ohmic electrode portion 165 is formed and then peeled off using the anti-etching pattern, the distribution portion 160 can be formed. The transparent insulating layer 161 and the ohmic electrode portion 165 are arranged in parallel in the distribution portion 160. It should be noted that here, the same pattern can be used for the anti-etching pattern when etching the transparent insulating layer 161 and the anti-etching pattern when peeling off the ohmic electrode portion 165, or a new pattern can be used. It should be noted that in the accompanying drawings, for the sake of simplicity, the through hole 161A is illustrated in a manner in which the ohmic electrode portion fills the through hole, but it is not limited to this. Although not illustrated, when etching is performed using a combination of anti-etching patterns and the anti-etching pattern, the etching of the portion covered by the anti-etching pattern will expand, thereby also creating a gap between the transparent insulating layer 161 and the ohmic electrode portion.

[0107] The ohmic electrode portion 165 can be formed by being dispersed in an island shape in a predetermined pattern. As the ohmic electrode portion 165, for example, Au, AuZn, AuBe, AuTi, etc. can be used, and their stacked structures are preferably used. For example, Ti / Au can be made into the ohmic electrode portion 165. The film thickness (or total film thickness) of the ohmic electrode portion 165 is not limited, and can be set to 300 to 1300 nm, and more preferably 350 nm to 800 nm.

[0108] It should be noted that the relationship between the film thickness H1 of the transparent insulating layer 161 and the film thickness H2 of the ohmic electrode portion 165 can be set to H1≥H2, and preferably to H1>H2. Under this condition, the film thickness of the transparent insulating layer 161 can be set to, for example, 360nm to 1600nm, and more preferably to 410nm to 1100nm. In addition, it is also preferred to set the difference H1-H2 between the film thickness H1 of the transparent insulating layer 161 and the film thickness H2 of the ohmic electrode portion 165 to be greater than 10nm and less than 100nm. In addition, when a contact layer is further provided as described above. The contact layer can be formed in a manner that only remains in the through hole 161A. In this case, the total thickness of the contact layer and the ohmic electrode portion can also be taken as the film thickness H2.

[0109] The transparent insulating layer 161 can be made of SiO 2 , SiN, ITO, Al 2 O 3 , AlN, or the like, and the transparent insulating layer 161 is preferably made of SiO 2 because SiO 2 can be easily etched using BHF or the like.

[0110] -Metal reflective layer forming step-

[0111] like Figure 4D As shown in the figure, it is also preferred to form a metal reflective layer 171 on the distribution unit 160. The metal reflective layer 171 preferably has 50% by mass or more of Au in the composition of the metal reflective layer 171. Au is more preferably 80% by mass or more. The metal reflective layer 171 may include a plurality of metal layers, and the metal constituting the metal reflective layer 171 may include Al, Pt, Ti, Ag, etc. in addition to Au. For example, the metal reflective layer 171 may be a single layer consisting only of Au, or the metal reflective layer 171 may include more than two Au metal layers. In order to ensure the bonding in the subsequent fifth step, it is preferred that the outermost layer of the metal reflective layer 171 (the surface on the opposite side of the semiconductor stack 140) is an Au metal layer.

[0112] For example, each metal layer may be formed in the order of Al, Au, Pt, and Au on the power distribution unit 160 (including the gap when the gap is provided) to form the metal reflective layer 171. The thickness of one layer of the Au metal layer in the metal reflective layer 171 may be set to, for example, 400 nm to 2000 nm, and the thickness of the metal layer formed of a metal other than Au may be set to, for example, 5 nm to 200 nm. The metal reflective layer 171 may be formed by film formation using conventional methods such as evaporation.

[0113] <Fourth step>

[0114] Reference Figure 5 In the fourth step, the semiconductor stack 140 and the power distribution unit 160 are bonded to the support substrate 180 via at least the metal bonding layer 179 . When the metal reflective layer 171 is provided, the metal reflective layer 171 and the metal bonding layer 179 may be bonded to each other.

[0115] -Metal bonding layer forming step-

[0116] Before the fourth step, the metal bonding layer 179 may be formed in advance on the surface of the support substrate 180 by sputtering, evaporation, etc. For example, the metal bonding layer 179 and the metal reflective layer 171 may be arranged opposite to each other and bonded together, and then heated and compressed at a temperature of about 250° C. to 500° C., so that the two can be bonded.

[0117] <<Metallic Bonding Layer>>

[0118] The metal bonding layer 179 can be formed by using metals such as Ti, Pt, Au, and metals that form a eutectic alloy with gold (Sn, etc.), and it is preferred that they be stacked to form the metal bonding layer 179. For example, the metal bonding layer 179 can be formed by stacking Ti with a thickness of 400nm to 800nm, Pt with a thickness of 5nm to 20nm, and Au with a thickness of 700 to 1200nm in order from the surface of the support substrate 180. It should be noted that when the metal reflective layer 171 and the metal bonding layer 179 are bonded, in order to ensure reliable bonding, it is preferred that the outermost layer of the metal bonding layer 179 is set to an Au metal layer, and the outermost layer of the metal reflective layer 171 is also set to Au, and the Au layers are bonded to each other by Au-Au diffusion.

[0119] <<Support substrate>>

[0120] The supporting substrate 180 can be any substrate as long as it is a substrate of a different type from the growth substrate 110. In addition to semiconductor substrates such as Si, Ge, and metal substrates such as Mo, Cu-W, ceramic substrates such as AlN can also be used as a support substrate for the base. Since the above-mentioned bonding method is used, the supporting substrate 180 can be lattice mismatched with each semiconductor layer formed in this embodiment. In addition, the supporting substrate 180 can be insulating depending on the purpose, but is preferably a conductive substrate. From the perspective of processability and price, it is preferred to use a Si substrate for the supporting substrate 180. By using a Si substrate, the thickness of the conductive supporting substrate 180 can be greatly reduced compared to the past, and it is also suitable for combined installation with various semiconductor devices. In addition, Si substrates are also advantageous in terms of heat dissipation compared to InAs substrates.

[0121] <Fifth Step>

[0122] Reference Figure 6. In the fifth step, the InAs growth substrate 110 is removed. It should be noted that the "removal" mentioned here is not limited to the "complete removal" of the InAs growth substrate 110. As long as the etching stop layer 130 is exposed after the "removal" of this step, a portion of the InAs growth substrate 110 can be allowed to remain to the extent that the InAs growth substrate 110 can be easily removed together with the etching stop layer 130. As a method for removing the InAs growth substrate 110 using the etching stop layer 130, the InAs growth substrate 110 can be etched only using concentrated hydrochloric acid, or an etching solution other than concentrated hydrochloric acid can be used in the stage before the etching stop layer 130 is exposed. For example, InAs can also be etched using a sulfuric acid-hydrogen peroxide mixture and a hydrochloric acid-hydrogen peroxide mixture. However, etching solutions containing these mixed solutions will also etch the etching stop layer 130. Therefore, it is difficult to stop etching at a specified position using only the above-mentioned mixed solution. Therefore, in the process of removing the InAs growth substrate 110, it is preferred to etch only with concentrated hydrochloric acid in the final stage of exposing the etching stop layer 130. In addition, a portion of the InAs can also be removed by methods other than wet etching, such as dry etching, grinding and other mechanical processing. The InAs growth substrate 110 can be finally removed by wet etching using concentrated hydrochloric acid of 8M or more (for example, 12M concentrated hydrochloric acid), and the etching can be terminated by at least using the etching stop layer 130. It should be noted that the etching stop layer 130 is a GaAsSb-based III-V compound semiconductor and therefore will not be removed by concentrated hydrochloric acid. For example, an ammonia-hydrogen peroxide mixture can be used to remove the etching stop layer 130 by wet etching.

[0123] <<Etching Conditions>>

[0124] As described above, the InAs growth substrate 110 can be wet-etched using concentrated hydrochloric acid of 8M or more (e.g., 12M concentrated hydrochloric acid). However, the etching rate is slow, and if productivity is taken into consideration, the following etching conditions are preferably adopted. For example, from the perspective of productivity, it is preferred to increase the etching rate by maintaining the liquid temperature of the etching solution containing 12M concentrated hydrochloric acid at above 35°C, and to remove the InAs growth substrate 110 in a short time. In addition, it is also preferred to remove the InAs growth substrate 110 halfway by using an etching solution that has a fast etching rate and no anisotropy and can etch flatly (e.g., a sulfuric acid-hydrogen peroxide mixture), and then, in the final stage of exposing the etching stop layer 130, completely remove the InAs substrate using concentrated hydrochloric acid with etching selectivity.

[0125] - Initial buffer layer removal process and etching stop layer removal process -

[0126] It should be noted that when the initial buffer layer 120 is provided, the initial buffer layer 120 can be removed using etching conditions that match the semiconductor composition thereof. When the initial buffer layer 120 is InAs, it is removed together with the InAs growth substrate 110. Next, the etching stop layer 130 ( Fig. 7A )

[0127] -Electrode formation process-

[0128] Furthermore, the following steps may be further included: Figure 7B As shown in FIG. 1 , on the semiconductor stack 140 (in Figure 7B In the process of forming the upper electrode 191 on the n-type cladding layer 141 and forming the back electrode 195 on the back of the support substrate 180, the upper electrode 191 may include a wiring portion and a pad portion. The upper electrode 191 and the back electrode 195 may be formed by a known method, such as a sputtering method, an electron beam evaporation method, or a resistance heating method.

[0129] In the present embodiment, the semiconductor optical device 100 can be manufactured by going through the above steps.

[0130] The semiconductor optical device is provided with a power distribution unit 160, so that current can be diffused through the upper electrode 191 and the ohmic electrode unit 165. Therefore, the light emission at the position not blocked by the upper electrode 191 increases, which can locally contribute to the increase of the light emission efficiency. In this way, the optical device characteristics can be improved by the present invention. It should be noted that in the prior art that uses the InAs growth substrate directly as a support substrate, this structure cannot be adopted.

[0131] Furthermore, the surface on the opposite side to the support substrate 180 can be used as the main light extraction port. On the other hand, in the conventional semiconductor light emitting element using the InAs substrate as both the growth substrate and the support substrate, there is no reflective layer, and the extraction efficiency of the light emitted from the semiconductor stack to the growth substrate side is low. Therefore, in the case of the semiconductor optical device 100 based on this embodiment, it is also advantageous in that the directivity of the emitted light can be narrowed compared to the conventional semiconductor light emitting element.

[0132] It should be noted that, although not shown in the figure, the manufacturing method based on this embodiment may further include the following step: a grinding step of grinding the support substrate 180 to a thickness within a range of 80 μm or more and less than 200 μm before forming the back electrode 195. In addition, if the thickness of the support substrate 180 is 80 μm or more, the semiconductor optical device 100 can be miniaturized and can be fully handled.

[0133] The semiconductor optical device 100 obtained by the above-mentioned manufacturing method is as follows: Figure 7BAs shown in the figure, it comprises: a supporting substrate 180; a metal bonding layer 179 arranged on the surface of the supporting substrate 180; a distribution unit 160 on the metal bonding layer 179, which comprises a transparent insulating layer 161 with a through hole and an ohmic electrode unit 165 arranged in the through hole; and a semiconductor stack 140 on the distribution unit 160, which is formed by stacking multiple layers of InAsSbP-based III-V compound semiconductors containing at least In and As.

[0134] In the semiconductor optical device 100 , the semiconductor stacked body 140 preferably includes an n-type cladding layer 141 , an active layer 145 , and a p-type cladding layer 147 in this order. Figure 7B In the embodiment, a p-type cladding layer 147, an active layer 145, and an n-type cladding layer 141 are sequentially provided from the support substrate 180 side. In addition, it is also preferred that the semiconductor stack 140 has a double heterostructure, and the InAsSbP-based III-V compound semiconductor constituting the active layer 145 contains at least In, As, and Sb. In addition, it is also preferred that the semiconductor stack 140 has a quantum well structure having a barrier layer 145b and a well layer 145w, and the InAsSbP-based III-V compound semiconductor constituting the barrier layer 145b contains at least In, As, and Sb. Furthermore, the operating wavelength of the semiconductor optical device is preferably above 3.4 μm.

[0135] Furthermore, in the first embodiment of the semiconductor light emitting element, the semiconductor optical device 100 may include a metal reflective layer 171 , an upper electrode 191 , and a back electrode 195 as necessary.

[0136] (Second Embodiment: Array Type Element)

[0137] By using an etching stopper in the same manner as in the first embodiment, after removing the InAs growth substrate, a portion of the semiconductor stack is removed by etching, thereby forming a plurality of electrically isolated elements on the support substrate. Thereafter, the electrodes may be connected via a protective film based on a dielectric film to form a series-connected element.

[0138] Reference Fig. 9 The semiconductor optical device 200 of this array type element is described below. It should be noted that for the configuration corresponding to the first embodiment, the common last two digits are marked and repeated description is omitted. The semiconductor optical device 200 comprises: a supporting substrate 280; a metal bonding layer 279 provided on the surface of the supporting substrate 280; a power distribution unit 260 on the metal bonding layer 279, comprising a transparent insulating layer 261 having a through hole and an ohmic electrode unit 265 provided in the through hole; and a semiconductor stack 240 on the power distribution unit 260, in which a plurality of layers of InAsSbP-based III-V compound semiconductors containing at least In and As are stacked.

[0139] The metal bonding layer 279 is preferably bonded to the metal reflective layer 271. On the metal reflective layer 271, another insulating layer 262 for ensuring insulation is preferably provided in the power distribution unit 260. In addition, while ensuring insulation by using the protective film 297, the semiconductor stack 240 can be connected in series by energizing the upper electrode 291 and the ohmic electrode unit 265. In this embodiment, the supporting substrate 280 can be made insulating. When the growth substrate is directly used as the supporting substrate, the conductivity and (semi) insulation that can be obtained, as well as the lattice constant, are restricted depending on the type of the growth substrate. However, the semiconductor optical device 200 is obtained by using an InAs growth substrate and by a bonding method in which it is removed, and therefore, the present invention is also advantageous over the prior art in that there is no such restriction.

[0140] (Third Embodiment: Semiconductor Light Receiving Element)

[0141] In addition, a semiconductor light-receiving element can be obtained by using an etching stop layer in the same manner as in the first embodiment. The semiconductor stack can be used as a semiconductor light-receiving element by, for example, having an InAsSb light-absorbing layer and an InAs window layer. The operating wavelength (light-receiving wavelength) at this time can be, for example, 1700 to 12000 nm (1.7 to 12 μm), can be 3.1 μm or more, and is preferably 3.4 μm or more.

[0142] Example

[0143] (Example 1)

[0144] Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples at all. Figure 1 to Figure 7B The semiconductor light emitting device described in Invention Example 1 was manufactured in the following order.

[0145] First, a 100 nm non-doped InAs layer (initial buffer layer) was formed on the (100) plane of a non-doped InAs substrate (substrate thickness: 475 μm). Next, a stack of 113 pairs of non-doped GaSb layers (film thickness: 0.9 nm) and GaAs was formed. 0.34 Sb 0.66 Next, on the superlattice stack, a Te-doped n-type InAs cladding layer (thickness 1 μm), an active layer of a quantum well structure with a main emission wavelength of 3800 nm (total thickness 830 nm), and a Zn-doped p-type InAs cladding layer (thickness: 1 μm) are sequentially formed by MOCVD. It should be noted that when forming the active layer of the quantum well structure, the InAs 0.15 P 0.85After the barrier layer (thickness: 30nm), InAs 0.7 Sb 0.3 Well layer (thickness: 10nm) and InAs 0.15 P 0.85 The barrier layers (thickness: 30 nm) were stacked alternately in order, 20 layers each, and 20.5 sets including the first barrier layer were set.

[0146] Next, a transparent insulating layer (thickness: 550 nm) made of SiO2 was formed on the entire surface of the p-type InAs cladding layer by plasma CVD. Fig. 10A The pattern shown is partially removed by wet etching based on BHF to form a through hole, exposing the p-type InAs cladding. Then, a p-type ohmic electrode portion (Ti / Au, total thickness: 540nm) is vapor-deposited in the through hole, and the resist pattern is peeled off, thereby forming a transparent insulating layer and a p-type ohmic electrode portion in parallel to form a current diffusion layer (distribution portion). It should be noted that Fig. 10A The upper electrode to be formed later is shown by a dotted line.

[0147] Next, a metal reflective layer (Al / Au / Pt / Au) was formed on the entire surface of the current diffusion layer by vapor deposition. The thickness of each metal layer of the metal reflective layer was 10 nm, 650 nm, 100 nm, and 900 nm, respectively.

[0148] On the other hand, a metal bonding layer (Ti / Pt / Au) was formed on a conductive Si substrate (substrate thickness: 200 μm) serving as a support substrate. The thicknesses of the metal layers of the metal bonding layer were 650 nm, 20 nm, and 900 nm, respectively.

[0149] The metal reflective layer and the metal bonding layer were arranged opposite to each other and were heated and compressed at 300°C. In addition, the InAs substrate, the initial buffer layer, and the etching stop layer were immersed in a 12M concentrated hydrochloric acid (manufactured by Kanto Chemical Co., Ltd.) placed in a beaker for 10.5 hours in a warm bath maintained at 25°C, thereby removing the InAs substrate and the initial buffer layer and leaving the GaSb layer and the GaAs substrate. 0.34 Sb 0.66 Next, after washing with pure water and drying, the superlattice stack (etching stop layer) is removed by wet etching using an ammonia-hydrogen peroxide mixed solution, thereby exposing the n-type InAs cladding layer.

[0150] Next, on the n-type InAs cladding layer, resist pattern formation, n-type electrode evaporation, and resist pattern stripping were performed to obtain a Fig. 10BThe n-type electrode (Ti (film thickness: 150nm) / Au (film thickness: 1250nm)) is formed in the pattern shown. Fig. 10B In FIG. 1 , the pattern of the previously formed p-type ohmic electrode portion is shown by a dotted line.

[0151] Finally, the semiconductor layer between each element (width 30μm) is removed by mesa etching to form a cutting line. In addition, a back electrode (Ti (thickness: 10nm) / Pt (thickness: 50nm) / Au (thickness: 200nm)) is formed on the back side of the Si substrate and heat treated at 300°C for 1 minute to perform alloying. Thereafter, the chip is singulated by dicing to produce the semiconductor light-emitting element described in Example 1. It should be noted that the chip size is 500μm×500μm.

[0152] (Comparative Example 1)

[0153] The semiconductor light-emitting element described in Comparative Example 1 was prepared as follows. First, an i-type InAs cladding layer (film thickness: 100 nm) was formed as an initial buffer layer on the (100) surface of the i-type InAs substrate. Then, in the same manner as in Example 1, an active layer (830 nm in total) of a quantum well structure with a main emission wavelength of 3800 nm and a Zn-doped p-type InAs cladding layer (thickness: 1 μm) were sequentially formed by the MOCVD method. Furthermore, an upper electrode (Ti (thickness: 150 nm) / Au (thickness: 1250 nm)) was formed on the central portion of the p-type InAs layer, and a back electrode (Ti (thickness: 10 nm) / Au (thickness 200 nm)) was formed on the back side of the i-type non-doped InAs substrate, and alloying and singulation were performed using the same conditions as in Inventive Example 1.

[0154] <Evaluation: Luminous output evaluation>

[0155] A constant current voltage power supply was used to flow a current of 300 mA into the semiconductor light emitting elements obtained in Example 1 and Comparative Example 1. The forward voltage Vf and the light emitting output Po based on the integrating sphere at this time were measured at one point respectively. The results are shown in Table 1. It should be noted that WPE (=Po / (I f ·V f ); luminous efficiency).

[0156] [Table 1]

[0157]

[0158] In Example 1, which satisfies the conditions of the present invention, the p-type ohmic electrode portion and the reflective electrode dispersed in an island shape are bonded to another support substrate, and the InAs growth substrate is removed. Therefore, it can be confirmed that compared with the semiconductor light-emitting element directly using the InAs growth substrate, the forward voltage can be reduced and the light output can be increased. In addition, since a metal reflective layer is used in Example 1, it is also advantageous in that narrow directivity can be achieved compared with Comparative Example 1.

[0159] (Reference experimental example)

[0160] On the InAs substrate, an etching stop layer was formed using the same conditions as in Example 1. In this state, an etching test was performed according to the etching conditions shown in Table 2. It should be noted that in Condition 3, after the InAs substrate was partially etched using a mixture of sulfuric acid and hydrogen peroxide water (sulfuric acid peroxide), the InAs substrate was then etched using hydrochloric acid (concentrated hydrochloric acid). The concentrations of the etching solution used were: 12M hydrochloric acid (concentrated hydrochloric acid), 18M sulfuric acid, 10M hydrogen peroxide water (peroxide water), and 13M nitric acid. In addition, the ratios in the table represent the volume ratios when preparing the etching solution. The results are shown in Table 2.

[0161] The results of substrate removal were visually observed and evaluated based on the following criteria.

[0162] ◎: The etching stopper layer was exposed, and removal of the InAs substrate was confirmed.

[0163] ○: Although side etching was observed at the outer periphery of the substrate, the etching stopper layer was exposed, and removal of the InAs substrate was confirmed.

[0164] ×: Etching could not be stopped by the etching stopper layer, and etching of the semiconductor stack was confirmed.

[0165] It was confirmed that, by using concentrated hydrochloric acid in the final stage of exposing the etching stop layer, the InAs substrate can be removed by utilizing the etching selectivity based on the etching stop layer.

[0166] [Table 2]

[0167]

[0168] Industrial Applicability

[0169] According to the present invention, a method for manufacturing a semiconductor optical device can be provided, which can improve the optical device characteristics of a semiconductor optical device having a semiconductor layer containing at least In, As and Sb. Furthermore, the present invention can provide a semiconductor optical device manufactured by the manufacturing method.

[0170] Description of Reference Numerals

[0171] 100, 200 Semiconductor optical devices

[0172] 110 InAs growth substrate

[0173] 120 Initial buffer layer

[0174] 130 Etch stop layer

[0175] 130a First floor

[0176] 130b Second floor

[0177] 140 Semiconductor stack

[0178] 141 n-type cladding

[0179] 145 Active layer

[0180] 145w well layer

[0181] 145b Barrier layer

[0182] 147 p-type cladding

[0183] 160 Power Distribution Department

[0184] 161 Transparent insulation layer

[0185] 161A Through hole

[0186] 165 Ohm Metal Division

[0187] 171 Metal reflective layer

[0188] 175 Metal bonding layer

[0189] 180 Support base plate

[0190] 191 Upper electrode

[0191] 195 Back electrode

Claims

1. A method for manufacturing a semiconductor optical device, characterized in that: The process is as follows: In a first step, an etching stopper layer is formed on an InAs growth substrate, wherein the etching stopper layer is formed of a GaAsSb-based III-V compound semiconductor containing at least Ga and Sb; A second step is to form a semiconductor stack on the etching stopper layer, wherein the semiconductor stack is stacked with a plurality of layers formed of an InAsSbP-based III-V compound semiconductor containing at least In and As; A third step is to form a power distribution unit on the semiconductor stack, wherein the power distribution unit includes a transparent insulating layer having a through hole and an ohmic electrode unit provided in the through hole; A fourth step of bonding the semiconductor stack and the power distribution unit to a support substrate at least via a metal bonding layer; as well as The fifth step is to remove the InAs growth substrate. After the removal, the etching stop layer is exposed. The InAsSbP-based III-V compound semiconductor of at least one of the layers in the semiconductor stack contains at least In, As, and Sb.

2. The method for manufacturing a semiconductor optical device according to claim 1, wherein: The GaAsSb-based III-V compound semiconductor constituting the etching stopper layer contains at least Ga, As, and Sb.

3. The method for manufacturing a semiconductor optical device according to claim 1, wherein: The etching stop layer comprises a superlattice stack. The superlattice stack includes a layer containing Ga, As, and Sb.

4. The method for manufacturing a semiconductor optical device according to any one of claims 1 to 3, wherein: The semiconductor stacked body includes an n-type cladding layer, an active layer, and a p-type cladding layer in this order.

5. The method for manufacturing a semiconductor optical device according to claim 4, wherein: The semiconductor stack has a double heterostructure, and the InAsSbP-based III-V compound semiconductor constituting the active layer contains at least In, As, and Sb.

6. The method for manufacturing a semiconductor optical device according to claim 4, wherein: The semiconductor stack has a quantum well structure including a barrier layer and a well layer, and the InAsSbP-based III-V compound semiconductor constituting the barrier layer contains at least In, As, and Sb.

7. The method for manufacturing a semiconductor optical device according to any one of claims 1 to 3, wherein: The operating wavelength of the semiconductor optical device is above 3.4 μm.

8. A semiconductor optical device, characterized in that: The semiconductor optical device is obtained by the method for manufacturing the semiconductor optical device according to any one of claims 1 to 3. The semiconductor optical device comprises: support base plate; A metal bonding layer disposed on a surface of the support substrate; The power distribution part on the metal bonding layer includes a transparent insulating layer having a through hole and an ohmic electrode part provided in the through hole; and The semiconductor stack on the power distribution unit is formed by stacking a plurality of layers of InAsSbP-based III-V compound semiconductors containing at least In and As.

9. The semiconductor optical device according to claim 8, wherein: The semiconductor stacked body includes an n-type cladding layer, an active layer, and a p-type cladding layer in this order.

10. The semiconductor optical device according to claim 9, wherein: The semiconductor stack has a double heterostructure, and the InAsSbP-based III-V compound semiconductor constituting the active layer contains at least In, As, and Sb.

11. The semiconductor optical device according to claim 9, wherein: The semiconductor stack has a quantum well structure including a barrier layer and a well layer, and the InAsSbP-based III-V compound semiconductor constituting the barrier layer contains at least In, As, and Sb.

12. The semiconductor optical device according to any one of claims 8 to 11, wherein: The operating wavelength of the semiconductor optical device is above 3.4 μm.

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