NAND flash memory device and forming method

Abstract

The present invention provides a method for forming a NAND flash memory device, comprising: providing a substrate, the substrate having a plurality of gates, a drain region and a source region formed on the substrate on both sides of the gates, and sidewalls formed on both sidewalls of the gates; forming a dielectric layer, the dielectric layer covering the substrate, the plurality of gates and the sidewalls; performing a first etching process on the dielectric layer, forming contact holes aligned with the drain regions and contact trenches aligned with the source regions in the dielectric layer, the contact trenches penetrating the dielectric layer and extending to the substrate; forming a protective layer on the dielectric layer, the protective layer having an opening, the opening exposing the contact holes and a portion of the dielectric layer around the contact holes; the protective layer protecting the contact trenches in the source regions from being subjected to a second etching process, thereby preventing excessive loss of substrate in the contact trenches in the source regions, thereby solving the problem of wafer leakage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a NAND flash memory device and a forming method thereof. Background Art

[0002] The main feature of flash memory is that it can retain stored information for a long time without power, and has the advantages of high integration, fast access speed, easy erasure and rewriting. Therefore, it has been widely used in many fields such as microcomputers and automatic control.

[0003] Flash memory can be divided into two types based on their structure: NOR Flash and NAND Flash. NAND Flash devices offer advantages such as higher cell density, higher storage density, and faster write and erase speeds. They have gradually become a more commonly used structure in flash memory and are currently primarily used in flash memory cards for digital cameras and MP3 players.

[0004] In traditional NAND FLASH cells, the cell drain contact (CT) is a contact hole, while the cell source contact (CT) is a trench. Due to the high loading dose of the contact trench in the source region, there is a high substrate loss (source silicon loss) in the source region, which can easily lead to cell leakage. Summary of the Invention

[0005] The object of the present invention is to provide a NAND flash memory device and a method for forming the same, so as to solve the problem of wafer leakage.

[0006] To solve the above technical problems, the present invention provides a method for forming a NAND flash memory device, comprising:

[0007] A substrate is provided, wherein the substrate has a plurality of gates, a drain region and a source region are formed on the substrate on both sides of the gates, and sidewalls are formed on both sidewalls of the gates;

[0008] forming a dielectric layer, wherein the dielectric layer covers the substrate, the plurality of gates and the sidewall spacers;

[0009] Performing a first etching process on the dielectric layer to form a contact hole aligned with the drain region and a contact trench aligned with the source region in the dielectric layer, wherein the contact trench penetrates the dielectric layer and extends into the substrate;

[0010] forming a protective layer on the dielectric layer, wherein the protective layer has an opening, and the opening exposes the contact hole and a portion of the dielectric layer around the contact hole;

[0011] A second etching process is performed to form a trench for the lateral connection of the drain region connected to the contact hole, while the contact hole penetrates the dielectric layer and extends into the substrate.

[0012] Optionally, before performing the first etching process on the dielectric layer, a patterned first photoresist layer is formed on the dielectric layer.

[0013] Optionally, the protective layer is a patterned second photoresist layer.

[0014] Optionally, the patterned photoresist is a negative photoresist.

[0015] Optionally, the contact trench of the source region is self-aligned with the sidewall to form an inverted trapezoidal contact trench.

[0016] Optionally, the process gases of the first etching process are C4F8 and CF4.

[0017] Optionally, the dielectric layer is an oxide layer.

[0018] Optionally, after performing the second etching process, a conductive layer is formed, which fills the contact holes, contact trenches and trenches for lateral connections to form a first conductive layer aligned with the source region and a second conductive layer aligned with the drain region.

[0019] Based on the same inventive concept, the present invention further provides a NAND flash memory device formed by any of the above-mentioned methods for forming a NAND flash memory device, comprising:

[0020] A substrate having a plurality of gates, a drain region and a source region formed on the substrate on both sides of the gates, and sidewalls formed on both sidewalls of the gates;

[0021] a dielectric layer, the dielectric layer covering the substrate, the plurality of gates and the sidewall spacers;

[0022] The conductive layer includes a first conductive layer in the source region and a second conductive layer in the drain region, wherein the first conductive layer penetrates the dielectric layer aligned with the source region, and the side of the first conductive layer close to the substrate is self-aligned with the side wall and is in an inverted trapezoidal shape, and the second conductive layer penetrates the dielectric layer aligned with the drain region.

[0023] Optionally, the second conductive layer includes a plurality of conductive plugs and a plurality of transverse connecting lines, and each conductive plug is connected to a transverse connecting line.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] In the NAND flash memory device and formation method provided by the present invention, a first etching process is performed to form a contact hole aligned with the drain region and a contact trench aligned with the source region within the dielectric layer. The contact trench penetrates the dielectric layer and extends to the substrate. Prior to the second etching process, a protective layer is formed on the dielectric layer to protect the contact trench in the source region from the second etching process, thereby preventing excessive loss of substrate within the contact trench in the source region, thereby resolving the problem of wafer leakage. Furthermore, since the contact hole aligned with the drain region during the first etching process does not penetrate the dielectric layer, there is no need to fill the contact hole with an organic distribution layer, nor is there any need to remove the organic distribution layer filled in the contact hole after the second etching process. This saves steps, reduces production costs, and improves production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a flow chart of a method for forming a NAND flash memory device according to an embodiment of the present invention;

[0027] Figures 2 to 7 is a structural schematic diagram corresponding to a method for forming a NAND flash memory device according to an embodiment of the present invention;

[0028] Figure 8 is a top view of a drain contact hole of a NAND flash memory device according to an embodiment of the present invention;

[0029] Figure 9 is a top view of a source region contact trench of a NAND flash memory device according to an embodiment of the present invention;

[0030] In the figure,

[0031] 10-substrate; 11-gate; 12-sidewall; 13-dielectric layer; 14-patterned first photoresist layer, 14a-patterned second photoresist layer; 15-contact hole; 15a-conductive plug; 16-contact trench; 16a-first conductive layer; 17-trench for lateral connection; 17a-lateral connection. DETAILED DESCRIPTION

[0032] The following is a detailed description of the NAND flash memory device and its manufacturing method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0033] The inventors discovered that the contact holes in the drain region and the contact trenches in the source region of a NAND flash memory device require two etching processes. The first etching process forms the contact holes and trenches in the drain region, and the second etching process forms the lateral wiring in the source region and the lateral wiring in the drain region. Before the second etching process, the contact holes and trenches in the drain region are filled with an organic distribution layer to prevent the contact holes and trenches in the source region from extending further into the substrate. Because the contact trenches in the source region are long, the loading dose of the organic distribution layer in the contact trenches is high, resulting in a large amount of substrate loss in the contact trenches in the source region. When the depth of the contact trenches in the substrate exceeds 20nm, leakage in the NAND flash memory device may occur.

[0034] Based on this, the core idea of ​​the present invention is to use a protective layer to cover the contact trench of the source region during the second etching process to prevent the contact trench from extending further into the substrate during the second etching process, thereby solving the leakage problem of the NAND flash memory device.

[0035] Figure 1 FIG. 1 is a flow chart of a method for forming a NAND flash memory device according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a NAND flash memory device, including:

[0036] Step S10, providing a substrate, wherein the substrate has a plurality of gates, drain regions and source regions are formed on the substrate on both sides of the gates, and sidewall spacers are formed on both sidewalls of the gates;

[0037] Step S20, forming a dielectric layer, wherein the dielectric layer covers the substrate, the plurality of gates and the spacers;

[0038] Step S30, performing a first etching process on the dielectric layer to form a contact hole aligned with the drain region and a contact trench aligned with the source region in the dielectric layer, wherein the contact trench penetrates the dielectric layer and extends into the substrate;

[0039] Step S40, forming a protective layer on the dielectric layer, wherein the protective layer has an opening, and the opening exposes the contact hole and a portion of the dielectric layer around the contact hole;

[0040] Step S50 , performing a second etching process to form a trench for the lateral connection of the drain region connected to the contact hole, while the contact hole penetrates the dielectric layer and extends into the substrate.

[0041] Figures 2 to 7 1 is a schematic diagram of the structure of the NAND flash memory device according to the embodiment of the present invention. Figures 2 to 7 The specific embodiments of the present invention are described in detail.

[0042] First, if Figure 2 As shown, a substrate 10 is provided. The substrate 10 may be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or other III-V compound substrate. This embodiment does not limit the material and structure of the substrate 10. In addition, a device structure (not shown) may be formed in the substrate 10. The device structure may be a device structure formed in a semiconductor front-end process, such as a MOS transistor.

[0043] Then, if Figure 2 As shown, multiple gates 11 are formed on the substrate 10, and drain regions (D) and source regions (S) are formed on the substrate 10 on both sides of the gates 11. The drain and source regions are formed by ion implantation. Sidewall spacers 12 are formed on both side walls of the gates 11. In this embodiment, the gates 11 are, for example, polysilicon and are formed by chemical vapor deposition. The sidewall spacers 12 are, for example, silicon nitride and are formed by chemical vapor deposition. A dielectric layer 13 is formed, covering the substrate 10, the multiple gates 11, and the sidewall spacers 12. The dielectric layer 13 is, for example, an oxide layer and is formed by chemical vapor deposition.

[0044] Before step S30, that is, before performing the first etching process on the dielectric layer 13, a patterned first photoresist layer 14 is formed on the dielectric layer 13. The patterned first photoresist layer 14 exposes a portion of the dielectric layer 13 aligned with the source region and a portion of the dielectric layer 13 aligned with the drain region.

[0045] like Figure 3 As shown, a first etching process is performed on the dielectric layer 13 using a patterned first photoresist layer 14 as a mask, forming a contact hole 15 aligned with the drain region and a contact trench 16 aligned with the source region in the dielectric layer 13. The contact trench 16 penetrates the dielectric layer 13 and extends into the substrate 10. The process gases used in the first etching process are C4F8 and CF4, which react only with the oxide layer and not with silicon nitride. Therefore, the contact trench 16 in the source region is self-aligned with the sidewalls to form an inverted trapezoidal contact trench 16. The top width of the contact trench 16 in the source region is, for example, 140 nm to 160 nm, which is equivalent to the width of the contact trench in the prior art plus the width of the lateral connection line connected to the contact trench. After the first etching process, the contact trench 16 in the source region extends to a depth of, for example, 10 nm to 15 nm into the substrate. The contact hole 15 in the drain region does not penetrate the dielectric layer 13.

[0046] After the step of forming the contact trench 16 , if the patterned first photoresist layer 14 has not been completely consumed, a photoresist removal process is required. Usually, an ashing process or a stripping method is used to remove the residual patterned photoresist.

[0047] like Figure 4 As shown, a protective layer is formed on the dielectric layer 13. The protective layer has an opening that exposes the contact hole 15 and the portion of the dielectric layer 13 surrounding the contact hole 15. The protective layer is a patterned second photoresist layer 14a. The photoresist used in forming the patterned second photoresist layer 14a is a negative photoresist. The patterned second photoresist layer 14a covers the contact trench 16 in the source region, preventing excessive loss of substrate 10 within the contact trench 16 during the second etching process, which could cause leakage in the NAND flash memory device.

[0048] like Figure 5 As shown, a second etching process is performed using the patterned second photoresist layer 14a as a mask to form a trench 17 for the lateral connection of the drain region that is connected to the contact hole 15. At the same time, the contact hole 15 penetrates the dielectric layer 13 and extends into the substrate 10. The depth of the drain region contact hole 15 extending into the substrate 10 is, for example, 10 nm to 15 nm.

[0049] like Figure 6 As shown, after the step of forming the trench 17 for the horizontal connection, if the patterned second photoresist layer 14a has not been completely consumed, a photoresist removal process is required, usually using an ashing process or a stripping method to remove the remaining patterned photoresist.

[0050] like Figure 7 As shown, after step S40, i.e., after performing the second etching process, a conductive layer is formed. This conductive layer fills the contact holes 15, contact trenches 16, and trenches 17 for lateral connections, thereby forming a first conductive layer 16a aligned with the source region and a second conductive layer aligned with the drain region. The side of the first conductive layer 16a near the substrate 10 is self-aligned with the sidewalls and has an inverted trapezoidal shape. The second conductive layer penetrates the dielectric layer 13 aligned with the drain region. The second conductive layer includes a plurality of conductive plugs 15a and a plurality of lateral connections 17a, with each conductive plug 15a connected to a lateral connection 17a.

[0051] After the conductive layer is formed, the height of the conductive layer is higher than the dielectric layer 13 , and the conductive layer is polished by chemical mechanical polishing (CMP) to form a first conductive layer 16 a aligned with the source region and a second conductive layer aligned with the drain region.

[0052] Since the contact hole 15 of the drain region does not penetrate the dielectric layer after the first etching process, and the contact trench 16 of the source region is covered with a protective layer during the second etching process, in this embodiment, there is no need to fill the contact hole 15 of the drain region and the contact trench 16 of the source region with an organic distribution layer (ODL), nor is there any need to remove the organic distribution layer in the contact hole 15 of the drain region and the contact trench 16 of the source region after the second etching process, thereby saving steps, reducing production costs, and improving production efficiency.

[0053] like Figure 7 As shown, based on the same inventive concept, this embodiment further provides a NAND flash memory device, which is formed using the above-mentioned method for forming a NAND flash memory device, including:

[0054] A substrate 10 having a plurality of gates 11 thereon, a drain region and a source region formed on the substrate 10 on both sides of the gates 11, and sidewall spacers 12 formed on both sidewalls of the gates 11;

[0055] a dielectric layer 13, wherein the dielectric layer 13 covers the substrate 10, the plurality of gates 11 and the spacers 12;

[0056] The conductive layer includes a first conductive layer 16a in the source region and a second conductive layer in the drain region. The first conductive layer 16a penetrates the dielectric layer 13 aligned with the source region. The side of the first conductive layer 16a close to the substrate 10 is self-aligned with the sidewall 12 and has an inverted trapezoidal shape. The second conductive layer penetrates the dielectric layer 13 aligned with the drain region.

[0057] Figure 8 is a top view of a drain contact hole of a NAND flash memory device according to an embodiment of the present invention; Figure 9 This is a top view of a source region contact trench in a NAND flash memory device according to an embodiment of the present invention. The second conductive layer includes a plurality of conductive plugs 15a and a plurality of transverse wirings 17a, with each conductive plug 15a connected to a transverse wiring 17a. In this embodiment, the second conductive layer is, for example, two columns, and the first conductive layer is, for example, a long strip.

[0058] In summary, the NAND flash memory device and formation method provided in the embodiments of the present invention form a contact hole aligned with the drain region and a contact trench aligned with the source region in the dielectric layer by performing a first etching process. The contact trench penetrates the dielectric layer and extends to the substrate. Prior to the second etching process, a protective layer is formed on the dielectric layer. The protective layer protects the contact trench in the source region from undergoing the second etching process, preventing excessive loss of substrate in the contact trench in the source region, thereby resolving the problem of wafer leakage. Furthermore, the contact hole aligned with the drain region in the first etching process does not penetrate the dielectric layer. Therefore, there is no need to fill the contact hole with an organic distribution layer, nor is there any need to remove the organic distribution layer filled in the contact hole after the second etching process. This saves steps, reduces production costs, and improves production efficiency.

[0059] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for forming a NAND flash memory device, characterized in that: include: A substrate is provided, wherein the substrate has a plurality of gates, a drain region and a source region are formed on the substrate on both sides of the gates, and sidewalls are formed on both sidewalls of the gates; forming a dielectric layer, wherein the dielectric layer covers the substrate, the plurality of gates and the sidewall spacers; Performing a first etching process on the dielectric layer to form a contact hole aligned with the drain region and a contact trench aligned with the source region in the dielectric layer, wherein the contact trench penetrates the dielectric layer and extends into the substrate; forming a protective layer on the dielectric layer, wherein the protective layer has an opening, and the opening exposes the contact hole and a portion of the dielectric layer around the contact hole; A second etching process is performed to form a trench for the lateral connection of the drain region connected to the contact hole, while the contact hole penetrates the dielectric layer and extends into the substrate.

2. The method for forming a NAND flash memory device according to claim 1, wherein: Before performing the first etching process on the dielectric layer, a patterned first photoresist layer is formed on the dielectric layer.

3. The method for forming a NAND flash memory device according to claim 1, wherein: The protection layer is a patterned second photoresist layer.

4. The method for forming a NAND flash memory device according to claim 2, wherein: The patterned photoresist is a negative photoresist.

5. The method for forming a NAND flash memory device according to claim 1, wherein: The contact trench of the source region is self-aligned with the sidewall to form an inverted trapezoidal contact trench.

6. The method for forming a NAND flash memory device according to claim 1, wherein: The process gases for the first etching process are C4F8 and CF4.

7. The method for forming a NAND flash memory device according to claim 1, wherein: The dielectric layer is an oxide layer.

8. The method for forming a NAND flash memory device according to claim 1, wherein: After the second etching process is performed, a conductive layer is formed to fill the contact holes, contact trenches and trenches for lateral wiring to form a first conductive layer aligned with the source region and a second conductive layer aligned with the drain region.

9. A NAND flash memory device, characterized in that: The method for forming a NAND flash memory device according to any one of claims 1 to 7 comprises: A substrate having a plurality of gates, a drain region and a source region formed on the substrate on both sides of the gates, and sidewalls formed on both sidewalls of the gates; a dielectric layer, the dielectric layer covering the substrate, the plurality of gates and the sidewall spacers; The conductive layer includes a first conductive layer in the source region and a second conductive layer in the drain region, wherein the first conductive layer penetrates the dielectric layer aligned with the source region, and the side of the first conductive layer close to the substrate is self-aligned with the side wall and is in an inverted trapezoidal shape, and the second conductive layer penetrates the dielectric layer aligned with the drain region.

10. The NAND flash memory device according to claim 9, wherein: The second conductive layer includes a plurality of conductive plugs and a plurality of transverse connecting lines, and each conductive plug is connected to a transverse connecting line.

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