Method of forming air gap between word line structures and method of manufacturing NAND device

Abstract

The application provides a method for forming air gaps between word line structures and a manufacturing method of a NAND device, the method for forming air gaps between word line structures comprising: providing a substrate, the substrate having word line structures and peripheral units; forming a silicon nitride material layer to fill between the word line structures and cover the word line structures and the peripheral units; forming a first mask layer to cover the silicon nitride material layer of the flash memory area, and form a silicon nitride sidewall of the peripheral unit in the peripheral area; forming a second mask layer to cover the peripheral area, and remove the silicon nitride material layer of the flash memory area; and forming air gaps between the word line structures. In the application, the cavities in the silicon nitride material layer are not exposed in the process of forming the silicon nitride sidewall by the first mask layer, thereby avoiding the problem of residual silicon nitride material layer caused by the cavities being filled with other materials, which is beneficial to improve the yield of the device, and can also reduce the process requirements of filling the silicon nitride material layer between the word line structures, which is beneficial to improve the manufacturing efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method for forming an air gap between word line structures and a method for manufacturing a NAND device. BACKGROUND

[0002] NAND flash (NAND device) is an important flash memory device, which has a very high cell density and can achieve a high storage density, and its writing and erasing speed is extremely fast, so it is widely used in various types of memory cards and is gradually replacing mechanical hard disks in solid state disks.

[0003] Taking a 2D NAND device as an example, when the NAND device enters a 20 nm technology node, because the critical dimension is reduced, the distance between the word line structures (gate structures) of the NAND device is also reduced, which will cause serious inter-cell coupling interference problems in the floating gate type memory, thereby affecting the size of the cell threshold voltage, the programming and reading speed of the memory array. In order to solve this problem, an air gap (Airgap) isolation technology is introduced into the manufacture of the NAND device, and by introducing air with the lowest dielectric constant between the word line structures, the crosstalk phenomenon is maximally reduced.

[0004] In the related art, as shown in Fig. la , when the silicon nitride material layer 13' is formed to fill the word line structures 11', it is easy to form a void 14' between the word line structures 11'; as shown in Fig. lb , the silicon nitride material layer 13' is etched to form a silicon nitride sidewall 13a' in the peripheral area 10b', and then a mask layer 15' (such as a silicon oxide layer) is formed to cover the peripheral area 10b', since the void 14' is opened in this step, the material of the mask layer 15' fills the void 14' and forms a residual defect 15a' at the void 14'; as shown in Fig. lc and 1d , the silicon nitride material layer 13' between the word line structures 11' and the mask layer 15a' are removed, due to the blockage of the residual defect 15a', it is difficult to completely remove (residual) the silicon nitride material layer between the word line structures with the void 14', thereby affecting the formation of the air gap between the word line structures, and thereby affecting the electrical performance of the final NAND device. SUMMARY

[0005] The present application aims to provide a method for forming an air gap between word line structures and a method for manufacturing a NAND device, to prevent residual silicon nitride between the word line structures.

[0006] To solve the above technical problems, the present application provides a method for forming air gaps between word line structures, comprising: providing a substrate, the substrate having a flash memory area and a peripheral area, the flash memory area being provided with a plurality of word line structures arranged at intervals, and the peripheral area being provided with a peripheral unit; forming a silicon nitride material layer, the silicon nitride material layer being filled between the word line structures and covering the word line structures and the peripheral unit; forming a first mask layer, the first mask layer covering the silicon nitride material layer of the flash memory area, and forming a silicon nitride sidewall of the peripheral unit in the peripheral area by taking the first mask layer as a mask; forming a second mask layer, the second mask layer covering the peripheral area, and removing the silicon nitride material layer of the flash memory area by taking the second mask layer as a mask; and forming air gaps between the word line structures.

[0007] Optionally, the flash memory area further has a select gate, and the select gate is located on both sides of the word line structure.

[0008] Optionally, the first mask layer partially covers the silicon nitride material layer on the select gate.

[0009] Optionally, the method for forming the silicon nitride sidewall of the peripheral unit comprises: dry etching to remove the silicon nitride material layer on the top wall of the peripheral unit and the peripheral area by taking the first mask layer as a mask, and taking the remaining silicon nitride material layer on the sidewall of the peripheral unit as the silicon nitride sidewall.

[0010] Optionally, the first mask layer is a photoresist layer.

[0011] Optionally, the dry etching for forming the silicon nitride sidewall also removes part of the silicon nitride material layer on the first mask layer and the word line structure.

[0012] Optionally, the step of removing the silicon nitride material layer of the flash memory area comprises: dry etching to remove part of the silicon nitride material layer of the flash memory area by taking the second mask layer as a mask, so that the word line structure partially protrudes from the remaining silicon nitride material layer; and wet etching to remove the remaining silicon nitride material layer.

[0013] Optionally, the second mask layer is made of silicon oxide.

[0014] Optionally, the method for forming the air gaps comprises: forming an interlayer dielectric layer by using a CVD process, the interlayer dielectric layer partially filling between adjacent word line structures and being sealed to form the air gaps.

[0015] Based on another aspect of the present application, the present application further provides a manufacturing method of a NAND device, comprising the method for forming air gaps between word line structures as described above.

[0016] In summary, the method for forming air gaps between word line structures and the method for manufacturing NAND devices provided by the present application have the following beneficial effects: a first mask layer is formed to cover the silicon nitride material layer on the word line structures, and the silicon nitride sidewall of the peripheral region is formed by using the first mask layer, then a second mask layer is formed to cover the peripheral region, and the silicon nitride material layer on the word line structures and between the word line structures is removed by using the second mask layer. The first mask layer prevents the cavities in the silicon nitride material layer (between the word line structures) from being exposed during the formation of the silicon nitride sidewall, thereby avoiding the problem that the cavities are filled with other materials (such as silicon oxide), which causes the silicon nitride material layer between the word line structures to be partially left during the subsequent removal process. This is beneficial to improve the yield of the device, and can also reduce the process requirements for filling the silicon nitride material layer between the word line structures, which is beneficial to improve the manufacturing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0017] Those skilled in the art will understand that the provided drawings are for the purpose of better illustrating the present application and do not constitute any limitation on the scope of the present application. Among them:

[0018] Fig. la to Fig. Id is a schematic diagram of forming air gaps between word line structures in existing NAND devices;

[0019] Fig. 2 is a flowchart of the method for forming air gaps between word line structures provided by the present application;

[0020] Fig. 3a to Fig. 3g is a structural schematic diagram corresponding to the respective steps of the method for forming air gaps between word line structures provided by the present application.

[0021] Fig. la to Fig. Id Among them:

[0022] 10'-substrate; 10a'-flash memory region; 10b'-peripheral region; 11'-word line structure; 12'-peripheral unit; 13'-silicon nitride material layer; 13a'-silicon nitride sidewall;

[0023] 14'-cavity; 15'-residual defect.

[0024] Fig. 3a to Fig. 3g Among them:

[0025] 10-substrate; 10a-flash memory region; 10b-peripheral region; 11-word line structure; 12-peripheral unit; 12a-low-voltage peripheral unit; 12b-high-voltage peripheral unit; 13-select tube; 14-silicon nitride material layer; 14a-silicon nitride sidewall; 15-cavity;

[0026] 21-first mask layer; 31-second mask layer;

[0027] 32-Opening; 33-Gap; 34-Interlayer medium layer; 35-Air gap. Detailed Implementation

[0028] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0029] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0030] This invention provides a method for forming air gaps between word line structures and a method for manufacturing NAND devices to prevent residual silicon nitride between word line structures.

[0031] Fig. 2 This is a flowchart of a method for forming air gaps between word line structures provided in an embodiment of this application.

[0032] like Fig. 2 As shown, the method for forming air gaps between word lines provided in this embodiment includes:

[0033] S01: A substrate is provided, the substrate having a flash memory region and a peripheral region, the flash memory region having a plurality of word line structures arranged at intervals, and the peripheral region having peripheral cells;

[0034] S02: Forming a silicon nitride material layer, the silicon nitride material layer filling the spaces between the word line structures and covering the word line structures and peripheral units;

[0035] S03: Form a first mask layer, the first mask layer covering the silicon nitride material layer of the flash memory area, and using the first mask layer as a mask, form the silicon nitride sidewall of the peripheral unit in the peripheral area;

[0036] S04: forming a second mask layer covering the peripheral region, removing the silicon nitride material layer of the flash memory region with the second mask layer as a mask;

[0037] S05: forming air gaps between the word line structures.

[0038] Fig. 3a to Fig. 3g is the corresponding structure schematic diagram of the corresponding step of the method for forming air gaps between word line structures provided by the embodiment of the present application. Next, the method for forming air gaps between word line structures will be described in detail in combination with Fig. 3a to 3g the method for forming air gaps between word line structures.

[0039] First, referring to Fig. 3a , step S01 is performed to provide a substrate 10 having a flash memory region 10a and a peripheral region 10b, the flash memory region 10a is provided with a plurality of word line structures 11 arranged at intervals, and the peripheral region 10b is provided with a plurality of peripheral units 12 arranged at intervals.

[0040] The substrate 10 can be any suitable material or type of semiconductor substrate suitable for forming a NAND device known to those skilled in the art. The substrate 10 has a flash memory region 10a and a peripheral region 10b, and the peripheral region 10b surrounds the flash memory region 10a. A plurality of word line structures 11 are formed on the flash memory region 10a, and a plurality of select tubes 13 are arranged at intervals on the edges of the flash memory region 10a (i.e. on both sides of the word line structures 11); a plurality of peripheral units 12 are formed on the peripheral region 10b, and the peripheral units 12 can include MOS units (peripheral units) with different threshold voltages, such as low-voltage peripheral units 12a and high-voltage peripheral units 12b. It should be understood that the word line structures 11 in the flash memory region 10a can be uniformly arranged, and the interval distance between the peripheral units 12 is greater than the interval distance between the word line structures 11.

[0041] The word line structures 11, the select tubes 13 and the peripheral units 12 can be formed synchronously using the same (or similar) film layer structure, and have substantially the same height, which can be, for example, 1200 angstroms to 2000 angstroms, but the word line structures 11, the select tubes 13 and the peripheral units 12 have different widths, the width of the peripheral units 12 is greater than the width of the select tubes 13, and the width of the select tubes 13 is greater than the width of the word line structures 11. The film layer structure can include, for example, a floating gate dielectric layer, a polysilicon floating gate layer, an inter-gate dielectric layer and a polysilicon control gate layer in turn from bottom to top. In a specific implementation, because the threshold voltages of the peripheral units 12 in the peripheral region 10b are different, the thicknesses of the floating gate dielectric layers of the peripheral units 12 with different threshold voltages can also be different.

[0042] In addition, a silicon oxide sidewall can be formed on the sidewalls of the word line structures 11, the select tubes 13 and the peripheral units 12, for protecting the word line structures 11 during the subsequent formation of the air gap 35.

[0043] Next, referring to Fig. 3b , a step S02 is performed to form a silicon nitride material layer 14, which fills the gaps between the word line structures 11 of the flash memory region 10a and covers the word line structures 11 and the peripheral units 12.

[0044] Specifically, the silicon nitride material layer 14 can be formed by, for example, an ALD (atomic layer deposition) process, which fills the gaps between the word line structures 11 of the flash memory region 10a and covers the word line structures 11, while the silicon nitride material layer 14 also covers the outer walls (sidewalls and top walls) of the peripheral units 12 and the peripheral region 10b. The silicon nitride material layer 14 can be 200-500 angstroms higher than the word line structures 11. It should be understood that the gaps between the word line structures 11 are relatively small, so that the gaps between some of the word line structures 11 are sealed off in advance to form cavities 15, the top of which is usually at the top of the word line structures 11 (slightly higher than the word line structures 11); on the contrary, the gaps between the peripheral units 12 of the peripheral region 10b and the flash memory region 10a are relatively large, so that the silicon nitride material layer 14 does not completely fill the gaps between the peripheral units 12.

[0045] Next, referring to Fig. 3c , a step S03 is performed to form a first mask layer 21, which covers the silicon nitride material layer 14 of the flash memory region 10a, and to form silicon nitride sidewalls 14a of the peripheral units 12 in the peripheral region 10b by masking the first mask layer 21.

[0046] Specifically, the first mask layer 21 covers the word line structures 11 of the flash memory region 10a and partially covers the select tubes 13 at the edge of the flash memory region 10a, so that the silicon nitride sidewalls 14a of the peripheral units 12 are formed in the peripheral region 10b while the corresponding silicon nitride sidewalls 14a are formed on the side of the select tubes 13 facing the peripheral region 10b. The first mask layer 21 covering the select tubes 13 can at least cover the silicon nitride material layer 14 between the select tubes 13 and the adjacent word line structures 11, so as to facilitate the subsequent formation of a relatively uniform gap.

[0047] The method of forming the silicon nitride sidewalls 14a can include, for example, dry etching to remove the silicon nitride material layer 14 on the top walls of the select tubes 13, the top walls of the peripheral units 12 and the peripheral region 10b, and taking the remaining silicon nitride material layer 14 on the sidewalls of the peripheral units 12 and the sidewalls of the select tubes 13 as the silicon nitride sidewalls 14a.

[0048] Preferably, the first mask layer 21 is a photoresist layer, so as to take advantage of the characteristic that the photoresist layer is slowly consumed in dry etching, so that the first mask layer 21 (photoresist layer) is removed by dry etching at the same time when the silicon nitride sidewall 14a is formed on the sidewalls of the select gate 13 and the peripheral unit 12, and also etches to remove part of the silicon nitride material layer 14 on the word line structure 11, so as to reduce the etching amount (removal amount) of the subsequent silicon nitride material layer 14, so as to improve the overall manufacturing efficiency. It should be understood that the thickness of the photoresist layer as the first mask layer 21 needs to be reasonably set to achieve the above-mentioned expected effect, and the thickness can be, for example, 5000 angstroms to 9000 angstroms.

[0049] It should be noted that when the silicon nitride material layer 14 on the word line structure 11 is etched by dry etching, the thickness of the silicon nitride material layer 14 removed cannot be too deep, so as to prevent the cavity 15 of the silicon nitride material layer 14 from being exposed, so that the cavity 15 is filled with the second mask layer 31 subsequently. Among them, the thickness of the silicon nitride material layer 14 removed can be determined according to whether the cavity 15 between the word line structures 11 is exposed, and for example, when the height of the initial silicon nitride material layer 14 above the word line structure 11 is 400 angstroms, the thickness of the silicon nitride material layer 14 removed can be 100 angstroms to 300 angstroms.

[0050] Next, referring to Fig. 3d , step S04 is performed to form the second mask layer 31, and the second mask layer 31 covers the peripheral area 10b.

[0051] Specifically, the second mask layer 31 covers the peripheral area 10b and also partially covers the select gate 13, wherein the area of the second mask layer 31 covering the select gate 13 is the part of the select gate 13 exposed by the first mask layer 21. In a specific implementation, the mask plate of the first mask layer 21 can be formed by using a photoresist of an opposite type (positive or negative type) to improve the utilization rate of the mask plate. The material of the second mask layer 31 can be preferably silicon oxide, so as to be removed together with the silicon oxide sidewall on both sides of the word line structure 11.

[0052] Next, referring to Fig. 3e , the silicon nitride material layer 14 of part of the flash memory area 10a is removed by dry etching with the second mask layer 31 as a mask, so that part of the word line structure 11 protrudes from the remaining silicon nitride material layer 14.

[0053] Specifically, after the silicon nitride material layer 14 on the word line structure 11 is removed by dry etching, the etching is further continued for a certain depth (time) to form an opening 32 between the word line structures 11, so as to facilitate the subsequent wet etching to completely remove the silicon nitride material layer 14. Among them, the silicon nitride material layer 14 can be removed by dry etching using plasma containing fluorocarbon (CF4) and oxygen (O) or plasma containing nitrogen fluoride (NF3), and the plasma containing nitrogen fluoride (NF3) is preferred, so as to take advantage of its high selectivity to silicon nitride and silicon oxide.

[0054] It should be understood that the cavities 15 between the word line structures 11 are normally opened in the present embodiment, and the opening process and the electrical performance of the whole NAND device after the opening process have no effect, so that the process requirement of filling the silicon nitride material layer between the word line structures 11 (whether to form the cavities) can be reduced, and the manufacturing efficiency and yield can be improved.

[0055] Next, referring to Fig. 3f The remaining silicon nitride material layer 14 is removed by wet etching with the second mask layer 31 as a mask to form the gap between the word line structures 11. The etching solution of the wet etching includes phosphoric acid with a volume percentage of, for example, 80% to 88%, and the etching temperature of the etching solution can be, for example, 160°C to 200°C.

[0056] Next, referring to Fig. 3g Step S05 is performed to form the air gap 35 between the word line structures 11.

[0057] Specifically, the silicon oxide side walls (not shown in the figure) on both sides of the word line structures 11 are removed first, and then the second mask layer 31 covering the peripheral region 10b and the select transistor 13 is removed. If the material of the second mask layer 31 is also silicon oxide, the silicon oxide side walls on both sides of the word line structures 11 and the second mask layer 31 can be removed together to form the gap 33. Then, the interlayer dielectric layer 34 is formed by a CVD process with poor step coverage (filling property) and fast lateral growth, which quickly cuts off and seals the gap 33 between the word line structures 11 to form the air gap 35 and covers the peripheral region 10b correspondingly. Preferably, the CVD process for forming the interlayer dielectric layer 34 is, for example, PECVD, so as to increase the size of the formed air gap 35.

[0058] Of course, other suitable methods can also be used to form the air gap in the gap 33 of the word line structures 11, and the present application is not limited in this respect.

[0059] The present application also provides a manufacturing method of a NAND device with air gaps between the word line structures, and the air gaps are formed by the method for forming air gaps between word line structures as described above.

[0060] The method for forming air gaps between word line structures and the method for manufacturing NAND devices have the following beneficial effects: a first mask layer is formed to cover the silicon nitride material layer on the word line structures, and the silicon nitride sidewall of the peripheral region is formed by using the first mask layer; a second mask layer is formed to cover the peripheral region, and the silicon nitride material layer on the word line structures and between the word line structures is removed by using the second mask layer; the cavity in the silicon nitride material layer (between the word line structures) is not exposed during the formation of the silicon nitride sidewall by the first mask layer, thereby avoiding the problem that the cavity is filled with other materials (such as silicon oxide), and the silicon nitride material layer between the word line structures is partially left in the subsequent removal process, which is beneficial to improve the yield of the device, and the process requirement for filling the silicon nitride material layer between the word line structures is reduced, which is beneficial to improve the manufacturing efficiency.

[0061] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method of forming an air gap between word line structures, comprising: The application relates to a method for forming an air gap between word lines. A substrate is provided, which has a flash memory area and a peripheral area, the flash memory area is provided with a plurality of word line structures arranged at intervals, and the peripheral area is provided with a peripheral unit; A silicon nitride material layer is formed, which fills the space between the word line structures and covers the word line structures and the peripheral unit; A first mask layer is formed, which covers the silicon nitride material layer of the flash memory area, and a silicon nitride side wall of the peripheral unit is formed in the peripheral area by taking the first mask layer as a mask, the forming method of the silicon nitride side wall of the peripheral unit comprises the following steps: taking the first mask layer as a mask, dry etching is performed to remove the silicon nitride material layer on the peripheral area and the top wall of the peripheral unit, and the silicon nitride material layer remaining on the side wall of the peripheral unit is taken as the silicon nitride side wall, the first mask layer is a photoresist layer, and the first mask layer and part of the silicon nitride material layer on the word line structure are removed by dry etching when the silicon nitride side wall is formed; A second mask layer is formed, which covers the peripheral area, and the silicon nitride material layer of the flash memory area is removed by taking the second mask layer as a mask; An air gap is formed between the word line structures.

2. The method of forming word line structure to structure air gaps according to claim 1, wherein, The flash memory area is further provided with a selection tube, which is located on both sides of the word line structure.

3. The method of claim 2, wherein: The first mask layer partially covers the silicon nitride material layer on the selection tube.

4. The method of forming word line structure to structure air gaps of claim 1, wherein, The step of removing the silicon nitride material layer of the flash memory area comprises the following steps: The second mask layer is taken as a mask, and part of the silicon nitride material layer of the flash memory area is removed by dry etching, so that the word line structure partially protrudes from the remaining silicon nitride material layer; The remaining silicon nitride material layer is removed by wet etching.

5. The method of claim 4, wherein: The material of the second mask layer is silicon oxide.

6. The method of forming word line structure to structure air gaps of claim 1, wherein, The method for forming the air gap comprises the following steps: an interlayer dielectric layer is formed by a CVD process, the interlayer dielectric layer partially fills the space between adjacent word line structures and is sealed to form the air gap.

7. A method of manufacturing a NAND device, characterized by, The application further discloses a method for forming an air gap between word lines.

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