Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device. The method comprises the following steps: providing a stop layer and a stack layer on the stop layer, wherein the stop layer has a convex structure on the side away from the stack layer; and forming a gate slit structure penetrating through the stack layer and extending into the stop layer, and the bottom of the gate slit structure is projected on the stop layer and located in the convex structure. The application can reduce the risk of leakage between the common source layer and the gate layer, and improve the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] In semiconductor devices, differences in film stress can easily lead to gaps between the gate gap structure and the substrate. When removing the substrate, these gaps may etch the interlayer insulating layer in the stacked layer, causing the common source layer to be electrically connected to the gate layer in the stacked layer through the gaps during subsequent deposition, posing a risk of leakage. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor device and a semiconductor device that can reduce the risk of leakage between the common source layer and the gate layer and improve the performance of the semiconductor device.

[0004] This invention provides a method for fabricating a semiconductor device, comprising:

[0005] A stop layer is provided, and a stack layer is located on the stop layer, the stop layer having a protruding structure on the side opposite to the stack layer;

[0006] A gate slot structure is formed that penetrates the stack layer and extends into the stop layer, and the orthogonal projection of the bottom of the gate slot structure on the stop layer is located within the protrusion structure.

[0007] More preferably, the gate slot structure also extends into the protrusion structure.

[0008] More preferably, the step of providing the stop layer includes:

[0009] Forming grooves in the substrate;

[0010] The stop layer is formed on the substrate, and the stop layer fills the groove to form the protrusion structure in the groove.

[0011] More preferably, the substrate includes a substrate, a first insulating layer, a sacrificial layer, and a second insulating layer;

[0012] The step of forming a groove in the substrate includes:

[0013] The substrate is provided, a first insulating layer is located on the substrate, and a sacrificial layer is located on the first insulating layer;

[0014] The groove is formed in the sacrificial layer;

[0015] A second insulating layer is formed on the sacrificial layer, and the second insulating layer covers the inner surface of the groove; the stop layer is located on the second insulating layer and fills the groove.

[0016] More preferably, after the step of forming the gate gap structure that penetrates the stack layer and extends into the stop layer, the method further includes:

[0017] Remove the substrate;

[0018] A common source layer is formed on the side of the stop layer opposite to the stack layer, and the common source layer covers the protrusion structure.

[0019] More preferably, the gate gap structure includes a semiconductor layer that extends through the stack layer and into the stop layer, and an isolation layer disposed around the semiconductor layer.

[0020] Accordingly, the present invention also provides a semiconductor device, comprising:

[0021] A stop layer, wherein one side of the stop layer has a protruding structure;

[0022] The stack layer located on the side of the stop layer opposite to the protrusion structure; and,

[0023] A gate slot structure extends through the stack layer and into the stop layer, wherein the bottom of the gate slot structure is projected onto the stop layer within the protrusion structure.

[0024] More preferably, the gate slot structure also extends into the protrusion structure.

[0025] More preferably, the semiconductor device further includes a common source layer;

[0026] The common source layer is located on the side of the stop layer opposite to the stack layer and covers the protrusion structure.

[0027] More preferably, the gate gap structure includes a semiconductor layer that extends through the stack layer and into the stop layer, and an isolation layer disposed around the semiconductor layer.

[0028] The beneficial effects of the present invention are as follows: a stop layer and a stack layer located on the stop layer are provided. The stop layer has a protrusion structure on the side opposite to the stack layer, forming a gate gap structure that penetrates the stack layer and extends into the stop layer. The bottom of the gate gap structure is projected onto the stop layer within the protrusion structure. This completely separates the substrate from the gate gap structure and the stack layer through the stop layer, so that the stack layer is not affected when the substrate is removed subsequently. This reduces the risk of leakage between the subsequently formed common source layer and the gate layer in the stack layer, thereby improving the performance of the semiconductor device. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0031] Figures 2a to 2i A schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0032] Figure 3 This is a partial structural schematic diagram of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0033] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0034] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0037] See Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention.

[0038] like Figure 1 As shown in the embodiment of the present invention, a method for fabricating a semiconductor device, including but not limited to a three-dimensional memory, is provided. The method includes steps 101 to 102, as detailed below:

[0039] Step 101: Provide a stop layer and a stack layer on the stop layer, the stop layer having a raised structure on the side opposite to the stack layer.

[0040] In this embodiment of the invention, the stop layer has a raised structure located at the bottom of the stop layer, and the raised structure protrudes in a direction away from the stop layer. A stack layer is located on top of the stop layer; that is, the raised structure and the stack layer are located on opposite sides of the stop layer.

[0041] Specifically, providing the stop layer in step 101 includes:

[0042] Forming grooves in the substrate;

[0043] The stop layer is formed on the substrate, and the stop layer fills the groove to form the protrusion structure in the groove.

[0044] The substrate may include a substrate, a first insulating layer, a sacrificial layer, and a second insulating layer, wherein the step of forming a groove in the substrate includes:

[0045] The substrate is provided, a first insulating layer is located on the substrate, and a sacrificial layer is located on the first insulating layer;

[0046] The groove is formed in the sacrificial layer;

[0047] A second insulating layer is formed on the sacrificial layer, and the second insulating layer covers the inner surface of the groove; the stop layer is located on the second insulating layer and fills the groove.

[0048] Specifically, step 101 corresponds to Figures 2a to 2e .like Figure 2a As shown, a substrate 11 is provided, and a first insulating layer 12 is formed on the substrate 11 using a thin-film deposition process. Then, a sacrificial layer 13 is formed on the first insulating layer 12 using a thin-film deposition process. The thin-film deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, etc. The substrate 11 can be a silicon substrate, or a substrate including other elemental semiconductors or compound semiconductors. The first insulating layer 12 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The sacrificial layer 13 can be a semiconductor layer such as polycrystalline silicon.

[0049] like Figure 2b As shown, an etching process is used to form a groove 10 in the sacrificial layer 13. The etching process can be anisotropic, such as plasma etching, or isotropic, such as wet etching. The groove 10 does not penetrate the sacrificial layer 13; that is, the depth of the groove 10 is less than the thickness of the sacrificial layer 13. The cross-section of the groove 10 can be circular, rectangular, etc., without specific limitations.

[0050] like Figure 2c As shown, a second insulating layer 14 is formed on the sacrificial layer 13 using a thin-film deposition process, and the second insulating layer 14 covers the inner surface of the groove 10. Since the groove 10 does not penetrate the sacrificial layer 13, the second insulating layer 14 and the first insulating layer 12 are separated by the sacrificial layer 13, so that the second insulating layer 14 will not be etched during the subsequent etching removal of the first insulating layer 12. Simultaneously, the second insulating layer 14 isolates the sacrificial layer 13 from the subsequently formed stop layer 2, so that the stop layer 2 will not be etched during the subsequent etching removal of the sacrificial layer 13. The second insulating layer 14 is relatively thin, and it is only located on the sidewalls and bottom of the groove 10; therefore, the groove 10 is not completely filled. The second insulating layer 14 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0051] After the second insulating layer 14 is formed, the substrate 11, the first insulating layer 12, the sacrificial layer 13 and the second insulating layer 14 constitute the substrate 1, and the substrate 1 has a groove 10.

[0052] like Figure 2d As shown, a stop layer 2 is formed on the second insulating layer 14 using a thin-film deposition process. The stop layer 2 fills the groove 10 to form a protrusion structure 21 within the groove 10, with the protrusion structure 21 protruding towards the substrate 1. The shape of the protrusion structure 21 matches the shape of the groove 10; that is, the cross-section of the protrusion structure 21 can be circular, rectangular, etc., without specific limitations. Then, the upper surface of the stop layer 2 is chemically mechanically polished to ensure a smooth upper surface. The material of the stop layer 2 can be a semiconductor material such as polycrystalline silicon.

[0053] like Figure 2e As shown, a stack layer 3 is formed on the stop layer 2 using a thin film deposition process, that is, the stack layer 3 is located on the side of the stop layer 2 away from the protrusion structure 21.

[0054] Stack layer 3 may include multiple vertically alternating interlayer sacrificial layers 31 and interlayer insulating layers 32, where vertical refers to the direction perpendicular to the upper surface of stop layer 2. The number of stacked interlayer sacrificial layers 31 and interlayer insulating layers 32 is not limited, for example, 48 layers, 64 layers, 128 layers, etc. Interlayer sacrificial layers 31 include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and interlayer insulating layers 32 include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0055] like Figure 2e As shown, a storage channel structure 6 is formed in the stack layer 3, extending longitudinally through the stack layer 3, the stop layer 2, and the second insulating layer 14 into the sacrificial layer 13. The storage channel structure 6 includes an isolation layer 61, a channel layer 62 surrounding the isolation layer 61, and a storage medium layer 63 surrounding the channel layer 62. The storage medium layer 63 includes a tunnel layer (not shown) surrounding the channel layer 62, a charge storage layer (not shown) surrounding the tunnel layer, and a charge blocking layer (not shown) surrounding the charge storage layer. The isolation layer 61 can be an oxide such as silicon oxide, the channel layer 62 can be polycrystalline silicon, the tunnel layer can be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride, the charge storage layer can be an insulating layer containing quantum dots or nanocrystals or compounds containing nitrogen and silicon, and the charge blocking layer can be an oxide such as silicon oxide.

[0056] Step 102: Form a gate slot structure that penetrates the stack layer and extends into the stop layer, wherein the bottom of the gate slot structure is projected onto the stop layer within the protrusion structure.

[0057] In this embodiment of the invention, the number of grid slot structures is the same as the number of protrusion structures, that is, the number of grid slot structures can be at least one, the number of protrusion structures can be at least one, and at least one grid slot structure is provided in a one-to-one correspondence with at least one protrusion structure.

[0058] Specifically, step 102 corresponds to Figures 2f to 2g .like Figure 2f As shown, a gate slot 40 is first formed, penetrating the stack layer 3 and extending into the stop layer 2. Since the stop layer 2 is relatively thin, a protruding structure 21 is provided on the side of the stop layer 2 opposite to the stack layer 3, with the gate slot 40 corresponding to the protruding structure 21. This prevents the gate slot 40 from extending too far into the stop layer 2, ensuring that the stop layer 2 can surround the bottom of the gate slot 40. The cross-sectional area of ​​the protruding structure 21 can be larger than the cross-sectional area of ​​the bottom of the gate slot 40, meaning the orthographic projection of the bottom of the gate slot 40 onto the stop layer 2 lies within the protruding structure 21, allowing the gate slot 40 to extend further into the protruding structure 21.

[0059] Then, the interlayer sacrificial layer 31 in the stacked layer 3 is replaced with the gate layer 33 through the gate gap 40. The gate layer 33 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide.

[0060] like Figure 2g As shown, a gate slot structure 4 is formed in the gate slot 40, such that the gate slot structure 4 penetrates the stack layer 3 and extends into the stop layer 2. The cross-sectional area of ​​the bottom of the protrusion structure 21 can be larger than the cross-sectional area of ​​the gate slot structure 4, that is, the orthogonal projection of the bottom of the gate slot structure 4 onto the stop layer 2 is located within the protrusion structure 21, allowing the gate slot structure 4 to extend further into the protrusion structure 21. Since the stop layer 2 is relatively thin, by setting the protrusion structure 21, and by setting the protrusion structure 21 correspondingly to the gate slot structure 4, it is ensured that the stop layer 2 can surround the bottom of the gate slot structure 4.

[0061] The gate gap structure 4 can be an insulating layer, that is, an insulating layer is filled in the gate gap 40 to form the gate gap structure 4. The insulating layer includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. Figure 2g As shown, the gate gap structure 4 may also include a semiconductor layer 41 that penetrates the stacked layer 3 and extends into the stop layer 2, and a spacer layer 42 disposed around the semiconductor layer 41. That is, the spacer layer 42 is first formed on the sidewalls and bottom of the gate gap 40, and then the semiconductor layer 41 is filled in the gate gap 40, so that the semiconductor layer 41 and the spacer layer 42 constitute the gate gap structure 4. The semiconductor layer 41 can be a semiconductor material such as polysilicon, and the spacer layer 42 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0062] Since the second semiconductor 41 and the spacer layer 42 are made of different materials, by adjusting the film thickness of the semiconductor layer 41 and the spacer layer 42 in the gate gap structure 4, the stress window of the gate gap structure 4 can be increased, and the process window (wafer bow window) for the gate gap structure 4 to control the deformation of the semiconductor device can be expanded.

[0063] In addition, a transition layer (not shown in the figure) may be formed on the periphery of the gate gap structure 4 (i.e., between the sidewall of the gate gap structure 4 and the stacked layer 3), and a barrier layer (not shown in the figure) may also be formed on the periphery of the transition layer (i.e., between the transition layer and the stacked layer 3). The barrier layer includes, but is not limited to, aluminum oxide, and the transition layer includes, but is not limited to, titanium nitride.

[0064] Further, after step S102, which involves forming a gate gap structure that penetrates the stack layer and extends into the stop layer, the method further includes:

[0065] Remove the substrate;

[0066] A common source layer is formed on the side of the stop layer opposite to the stack layer, and the common source layer covers the protrusion structure.

[0067] like Figure 2h As shown, an etching process is used to sequentially remove the substrate 11, the first insulating layer 12, the sacrificial layer 13, and the second insulating layer 14. Since the second insulating layer 14 is made of the same material as the storage medium layer 63 of the storage channel structure 6, when removing the second insulating layer 14, the storage medium layer 63 at the bottom of the storage channel structure 6 (i.e., the storage medium layer 63 on the side of the stop layer 2 away from the stack layer 3) is also removed to expose the channel layer 62 at the bottom of the storage channel structure 6.

[0068] Then, as Figure 2i As shown, a common source layer 5 is formed on the side of the stop layer 2 away from the stack layer 3 using a thin-film deposition process, and the common source layer 5 covers the protrusion structure 21. Additionally, the common source layer 5 covers the channel layer 62 at the bottom of the memory channel structure 6 to connect with the channel layer 62. The common source layer 5 can be a semiconductor material such as polysilicon.

[0069] It should be noted that the gate gap structure in the prior art penetrates the stack layer, the stop layer, and the second insulating layer, extending into the sacrificial layer. The gate gap structure includes a semiconductor layer and an isolation layer surrounding the semiconductor layer. The isolation layer is relatively thin, while the semiconductor layer is relatively thick, resulting in differences in local stress within the gate gap structure. This can lead to gaps between the bottom of the gate gap structure and the sacrificial layer, the second insulating layer, and the stop layer. Since the sacrificial layer and the stop layer are made of the same material, removing the sacrificial layer will etch the stop layer through the gaps, forming an opening within it. Similarly, since the second insulating layer is made of the same material as the interlayer insulating layer in the stack layer, removing the second insulating layer will etch the interlayer insulating layer through the gaps, forming an opening within it. Then, during the formation of the common source layer, the common source layer is deposited through the gaps into the openings in the stop layer and the interlayer insulating layer, easily forming an electrical connection with the gate layer in the stack layer, creating a leakage risk between the common source layer and the gate layer.

[0070] Based on this, the gate gap structure 4 in this application penetrates the stacked layer 3 and extends into the stop layer 2. Since the stop layer 2 has a protrusion structure 21 on the side facing away from the stacked layer 3, and the orthogonal projection of the bottom of the gate gap structure 4 onto the stop layer 2 is located within the protrusion structure 21, the stop layer 2 can completely surround the bottom of the gate gap structure 4, thereby completely separating the gate gap structure 4 from the substrate 1. Furthermore, the stop layer 2 is completely separated from the sacrificial layer 13 by the second insulating layer 14. When removing the sacrificial layer 13 from the substrate 1, the stop layer 2 is not etched; when removing the second insulating layer 14 from the substrate 1, the interlayer insulating layer 32 in the stacked layer 3 is not etched. Because the stop layer 2 and the interlayer insulating layer 32 in the stacked layer 3 are not etched, after the common source layer 5 is formed, the common source layer 5 will not be electrically connected to the gate layer 33 in the stacked layer 3, thereby reducing the leakage risk between the common source layer 5 and the gate layer 33.

[0071] As can be seen from the above, the semiconductor device fabrication method provided by the embodiments of the present invention can provide a stop layer and a stack layer located on the stop layer. The stop layer has a protrusion structure on the side away from the stack layer, forming a gate gap structure that penetrates the stack layer and extends into the stop layer. The bottom of the gate gap structure is projected onto the stop layer within the protrusion structure, so that the substrate is completely separated from the gate gap structure and the stack layer by the stop layer. This prevents the stack layer from being affected when the substrate is removed later, reduces the leakage risk between the subsequently formed common source layer and the gate layer in the stack layer, and improves the performance of the semiconductor device.

[0072] Accordingly, embodiments of the present invention also provide a semiconductor device that can be manufactured by the semiconductor device manufacturing method described in the above embodiments.

[0073] like Figure 3As shown, this embodiment provides a semiconductor device, which includes, but is not limited to, a three-dimensional memory. The semiconductor device includes a stop layer 2, a stack layer 3, and a gate gap structure 4.

[0074] The stop layer 2 has a protrusion structure 21 on one side, which protrudes towards the side opposite to the stop layer 2. The stop layer 2 can be a semiconductor material such as polysilicon.

[0075] The stacked layer 3 is located on the side of the stop layer 2 opposite to the protrusion structure 21. The stacked layer 3 may include multiple vertically alternating gate layers 33 and interlayer insulating layers 32, where vertical refers to the direction perpendicular to the upper surface of the stop layer 2. The number of stacked gate layers 33 and interlayer insulating layers 32 is not limited, for example, 48 layers, 64 layers, 128 layers, etc. The gate layer 33 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, and the interlayer insulating layer 32 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0076] The semiconductor device also includes a memory channel structure 6 that extends through the stack layer 3 and the stop layer 2. The memory channel structure 6 includes an isolation layer 61, a channel layer 62 surrounding the isolation layer 61, and a memory dielectric layer 63 surrounding the channel layer 62. The memory dielectric layer 63 includes a tunnel layer (not shown) surrounding the channel layer 62, a charge storage layer (not shown) surrounding the tunnel layer, and a charge blocking layer (not shown) surrounding the charge storage layer.

[0077] The gate slot structure 4 penetrates the stack layer 3 and extends into the stop layer 2, and the gate slot structure 4 corresponds to the protrusion structure 21. Since the stop layer 2 is relatively thin, by providing the protrusion structure 21 on the side of the stop layer 2 away from the stack layer 3, the extension depth of the gate slot structure 4 can be prevented from being too large and penetrating the stop layer 2, thereby ensuring that the stop layer 2 surrounds the bottom of the gate slot structure 4.

[0078] The cross-sectional area of ​​the protrusion structure 21 can be larger than the cross-sectional area of ​​the bottom of the gate slot structure 4, that is, the orthogonal projection of the bottom of the gate slot structure 4 on the stop layer 2 is located inside the protrusion structure 21, so that the gate slot structure 4 can also extend into the protrusion structure 21.

[0079] The number of protruding structures 21 and the number of grid slot structures 4 are the same, that is, there is at least one protruding structure 21 and at least one grid slot structure 4, and at least one protruding structure 21 and at least one grid slot structure 4 are arranged in a one-to-one correspondence.

[0080] The gate gap structure 4 can be an insulating layer, and the gate gap structure 4 can also include a semiconductor layer 41 that penetrates the stacked layer 3 and extends into the stop layer 2, and a spacer layer 42 disposed around the semiconductor layer 41. The semiconductor layer 41 can be a semiconductor material such as polysilicon, and the spacer layer 42 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0081] Since the semiconductor 41 and the spacer layer 42 are made of different materials, by adjusting the film thickness of the semiconductor layer 41 and the spacer layer 42 in the gate gap structure 4, the stress window of the gate gap structure 4 can be increased, and the process window for the gate gap structure 4 to control the deformation of the semiconductor device can be expanded.

[0082] The semiconductor device may also include a common source layer 5, which is located on the side of the stop layer 2 opposite to the stack layer 3, and covers the bump structure 21. The common source layer 5 is also connected to the channel layer 62 in the memory channel structure 6, that is, the channel layer 62 in the memory channel structure 6 can extend into the common source layer 5. The common source layer 5 can be a semiconductor material such as polysilicon.

[0083] The semiconductor device provided in this invention provides a stop layer and a stacked layer on the stop layer. The stop layer has a protrusion structure on the side opposite to the stacked layer, forming a gate gap structure that penetrates the stacked layer and extends into the stop layer. The bottom of the gate gap structure is projected onto the stop layer within the protrusion structure. This completely separates the substrate from the gate gap structure and the stacked layer through the stop layer, so that the stacked layer is not affected when the substrate is removed subsequently. This reduces the risk of leakage between the subsequently formed common source layer and the gate layer in the stacked layer, thereby improving the performance of the semiconductor device.

[0084] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Forming grooves in the substrate; A stop layer is formed on the substrate, a portion of the stop layer fills the groove to form a protruding structure in the groove, and another portion of the stop layer is located on the substrate outside the groove; A stack layer is formed on the stop layer, the stack layer being located on the side of the stop layer opposite to the protrusion structure; A storage channel structure is formed, the storage channel structure penetrating the stack layer and another portion of the stop layer and extending into the substrate, the storage channel structure including a channel layer; A gate slot structure is formed that penetrates the stack layer and extends into the stop layer, and the orthogonal projection of the bottom of the gate slot structure on the stop layer is located within the protrusion structure; Remove the entire substrate; wherein, during the removal of the substrate, the stop layer is located between the substrate and the stack layer and isolates the substrate from the stack layer and the gate gap structure; A common source layer is formed on the side of the stop layer opposite to the stack layer. The common source layer covers the stop layer and is also in contact with and connected to the channel layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The grid slot structure also extends into the protrusion structure.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes: A storage channel structure is formed, which penetrates the stack layer and the stop layer and extends into the substrate. The storage channel structure includes an isolation layer, a channel layer disposed around the periphery of the isolation layer, and a storage medium layer disposed around the periphery of the channel layer. During the removal of the substrate, the storage medium layer at the bottom of the storage channel structure is removed.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The substrate includes a substrate, a first insulating layer, a sacrificial layer, and a second insulating layer; The step of forming a groove in the substrate includes: The substrate is provided, a first insulating layer is located on the substrate, and a sacrificial layer is located on the first insulating layer; The groove is formed in the sacrificial layer; A second insulating layer is formed on the sacrificial layer, and the second insulating layer covers the inner surface of the groove; the stop layer is located on the second insulating layer and fills the groove; the second insulating layer is made of the same material as the storage medium layer.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The stop layer comprises polycrystalline silicon.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The gate gap structure includes a semiconductor layer that extends through the stack layer and into the stop layer, and an isolation layer disposed around the semiconductor layer.

7. A semiconductor device, characterized in that, include: A stop layer, wherein one side of the stop layer has a protruding structure; A stack layer located on the side of the stop layer away from the protrusion structure, wherein the surface of the stack layer near the stop layer is covered by the stop layer; A gate slot structure extends through the stack layer and into the stop layer, wherein the orthographic projection of the bottom of the gate slot structure onto the stop layer is located within the protrusion structure; A storage channel structure extends through the stack layer and the stop layer, and includes the channel layer; The common source layer is located on the side of the stop layer away from the stack layer, covers the stop layer, and is in contact with and connected to the channel layer.

8. The semiconductor device according to claim 7, characterized in that, The grid slot structure also extends into the protrusion structure.

9. The semiconductor device according to claim 7, characterized in that, The stop layer comprises polycrystalline silicon.

10. The semiconductor device according to claim 7, characterized in that, The gate gap structure includes a semiconductor layer that extends through the stack layer and into the stop layer, and an isolation layer disposed around the semiconductor layer.

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