Adaptive output isolation control circuit and method

Abstract

The present invention discloses an adaptive output isolation control circuit, which adaptively turns on the MOS tube Q1 according to the slow start of the output voltage, which not only solves the hot plug problem but also allows it to work in the on state to the greatest extent; only when the output current is too large and the voltage is too low, it will be judged as a module output short circuit or fault state, and the MOS tube Q1 will be disconnected to achieve fault isolation between it and the DC bus without any external control signal, isolation drive power supply, isolation optical coupler, etc.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to an adaptive output isolation control circuit and method. Background Art

[0002] The current output isolation technologies include:

[0003] 1) Output diode isolation protection (often suitable for products with low output current).

[0004] 2) Positive MOS tube isolation protection (external isolation drive power supply and isolation drive optocoupler are required).

[0005] 3) Output relay isolation protection (needs isolated drive power supply).

[0006] Disadvantages of existing technology:

[0007] 1) Output diode isolation protection is only suitable for products with low current output; in high current applications, the diode conduction loss is very high.

[0008] 2) Isolation protection of the positive MOS tube requires external isolation control power supply, optocoupler and other devices, which increases design cost and failure rate.

[0009] 3) Output relay isolation protection. When the output end is short-circuited, the contacts will be disengaged, which will produce a large arc phenomenon and have low reliability. Summary of the invention

[0010] The main purpose of the present invention is to provide an adaptive output isolation control circuit, which can solve the hot plug problem and quickly realize the fault isolation problem.

[0011] To achieve the above object, the technical solution adopted by the present invention is:

[0012] An adaptive output isolation control circuit, comprising:

[0013] An adaptive voltage-dividing network of the transistor Q2, wherein the adaptive voltage-dividing network is connected to the base of the transistor Q2;

[0014] A slow-on capacitor C4, one end of which is connected to the base of the transistor Q2;

[0015] MOS transistor Q1 and resistors R7, R8 and R9 for providing adaptive driving voltage for the MOS transistor Q1;

[0016] A diode D3, wherein the anode of the diode D3 is connected to the source of the MOS transistor Q1, and the cathode of the diode D3 is connected to the gate of the MOS transistor Q1. The diode D3 is a driving protection diode of the MOS transistor Q1.

[0017] Furthermore, the resistor R7, the resistor R8 and the collector of the transistor Q2 are connected in series in sequence, one end of the resistor R9 is connected to the emitter of the transistor Q2, the other end of the resistor R9 is connected to the source of the MOS transistor Q1, and the emitter of the transistor Q2 is connected to the gate of the MOS transistor Q1.

[0018] Furthermore, the adaptive voltage divider network includes a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15 and a resistor R16, the resistor R13, the resistor R14, the resistor R15, the resistor R16 and the base of the transistor Q2 are connected in series in sequence, and one end of the resistor R11 and one end of the resistor R12 are respectively connected to the base of the transistor Q2.

[0019] Furthermore, it also includes a module transformer T1, the first output end and the third output end of the module transformer T1 are respectively connected to the positive poles of the output rectifier diode D1 and the output rectifier diode D2, the negative poles of the output rectifier diode D1 and the output rectifier diode D2 are connected to the DGND ground, the negative pole of the output capacitor C1 and the first end of the current sampling resistor R1, the second end of the current sampling resistor R1 is connected to the negative pole of the output capacitor C1, the negative pole of the output capacitor C1, ip+ and the drain of the MOS tube Q1, the second output end of the module transformer T1 is connected to the positive pole of the output capacitor C1, the positive pole of the output capacitor C2, the positive pole of the output capacitor C3, the resistor R13, the resistor R8 and Vout+, and the source of the MOS tube Q1, the other end of the resistor R9 and the negative pole of the diode D3 are connected to Vout-.

[0020] Furthermore, it also includes an operational amplifier U1, the positive input terminal of the operational amplifier U1 is connected to one end of the resistor R2 and one end of the resistor R4, the other end of the resistor R2 is connected to IP+, the negative input terminal of the operational amplifier U1 is connected to one end of the resistor R3 and one end of the resistor R5, the other end of the resistor R3 is connected to the DGND ground, the negative power supply terminal of the operational amplifier U1 is connected to the other end of the resistor R4 and the DGND ground, the positive power supply terminal of the operational amplifier U1 is connected to the second end of the operational amplifier decoupling capacitor C5, the output terminal of the operational amplifier U1 is connected to the other end of the resistor R5, and the resistors R2, R3, R4 and R5 are operational amplifier resistors.

[0021] Furthermore, it also includes a transistor Q3, the base of the transistor Q3 is connected to the resistor R6 and one end of the resistor R10, the resistor R6 is an isolation resistor, and also forms a voltage-dividing resistor of the base of the transistor Q3 with the resistor R10, the other end of the resistor R6 is connected to the output end of the operational amplifier U1 and the other end of the resistor R5, the other end of the resistor R10 is connected to the first end of the operational amplifier decoupling capacitor C5, the DGND ground, the other end of the capacitor C4, the other end of the resistor R11 and the emitter of the transistor Q3, and the collector of the transistor Q3 is connected to the other end of the resistor R12.

[0022] Furthermore, the MOS tube Q1 is an NMOS tube.

[0023] According to another aspect of the present invention, an adaptive output isolation control method based on any of the adaptive output isolation control circuits described above is also proposed, comprising the following steps:

[0024] When the output voltage rises to V1 or is close to V1, the transistor obtains a voltage through the voltage divider network to charge the capacitor C4 until the transistor Q2 is turned on, and the driving voltage of the MOS tube Q1 obtains a turn-on voltage, and the MOS tube Q1 is turned on normally;

[0025] Within the normal rated output voltage and current range, the MOS tube Q1 is always in the on state;

[0026] When the module output is short-circuited, the output current is greater than the normal value and the output voltage decreases.

[0027] Furthermore, the method further comprises the following steps:

[0028] When a fault occurs, the current flowing through the resistor R1 increases, the voltage difference across the resistor R1 increases, the input differential signal of the operational amplifier U1 increases, the output voltage of the operational amplifier U1 increases, and the base voltage of the transistor Q3 increases, turning on the transistor Q3, turning off the transistor Q2, and turning off the MOS tube Q1.

[0029] Furthermore, the method further comprises the following steps:

[0030] When the fault is removed, the output voltage and current detection values ​​return to normal, the voltage output by the operational amplifier U1 decreases, and the voltage divider value of the resistor R6 and the resistor R10 is not enough to turn on the transistor Q3, so the transistor Q2 and the MOS tube Q1 are turned on.

[0031] Compared with the prior art, the present invention has the following beneficial effects: the invention is reasonably designed, and according to the slow start of the output voltage, the MOS tube Q1 is adaptively turned on, which not only solves the hot plug problem, but also allows it to work in the on state to the greatest extent; only when the output current is too large and the voltage is too low, it will be judged as a module output short circuit or fault state, and Q1 will be disconnected to achieve fault isolation from the DC bus without any external control signal, isolated drive power supply, isolated optical coupler, etc. While greatly increasing the efficiency of the module as a whole, it also reduces the isolated drive power supply and peripheral circuit of the MOS tube, reducing the module cost. It can be seen that this invention has comprehensive functions and is suitable for wide promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of the adaptive output isolation control circuit of the present invention. DETAILED DESCRIPTION

[0033] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0034] like Figure 1 An adaptive output isolation control circuit is shown, comprising:

[0035] An adaptive voltage-dividing network of the transistor Q2, wherein the adaptive voltage-dividing network is connected to the base of the transistor Q2;

[0036] A slow-on capacitor C4, one end of which is connected to the base of the transistor Q2;

[0037] MOS transistor Q1 and resistors R7, R8 and R9 for providing adaptive driving voltage for the MOS transistor Q1;

[0038] A diode D3, wherein the anode of the diode D3 is connected to the source of the MOS transistor Q1, and the cathode of the diode D3 is connected to the gate of the MOS transistor Q1. The diode D3 is a driving protection diode of the MOS transistor Q1.

[0039] The resistor R7, the resistor R8 and the collector of the transistor Q2 are connected in series in sequence, one end of the resistor R9 is connected to the emitter of the transistor Q2, the other end of the resistor R9 is connected to the source of the MOS transistor Q1, and the emitter of the transistor Q2 is connected to the gate of the MOS transistor Q1.

[0040] Wherein, the adaptive voltage divider network includes resistor R11, resistor R12, resistor R13, resistor R14, resistor R15 and resistor R16, the resistor R13, the resistor R14, the resistor R15, the resistor R16 and the base of the transistor Q2 are connected in series in sequence, and one end of the resistor R11 and one end of the resistor R12 are respectively connected to the base of the transistor Q2.

[0041] Among them, it also includes a module transformer T1, the first output end and the third output end of the module transformer T1 are respectively connected to the positive poles of the output rectifier diode D1 and the output rectifier diode D2, the negative poles of the output rectifier diode D1 and the output rectifier diode D2 are connected to the DGND ground, the negative pole of the output capacitor C1 and the first end of the current sampling resistor R1, the second end of the current sampling resistor R1 is connected to the negative pole of the output capacitor C1, the negative pole of the output capacitor C1, ip+ and the drain of the MOS tube Q1, the second output end of the module transformer T1 is connected to the positive pole of the output capacitor C1, the positive pole of the output capacitor C2, the positive pole of the output capacitor C3, the resistor R13, the resistor R8 and Vout+, the source of the MOS tube Q1, the other end of the resistor R9 and the negative pole of the diode D3 are connected to Vout-.

[0042] Among them, it also includes an operational amplifier U1, the positive input terminal of the operational amplifier U1 is connected to one end of the resistor R2 and one end of the resistor R4, the other end of the resistor R2 is connected to IP+, the negative input terminal of the operational amplifier U1 is connected to one end of the resistor R3 and one end of the resistor R5, the other end of the resistor R3 is connected to the DGND ground, the negative power supply terminal of the operational amplifier U1 is connected to the other end of the resistor R4 and the DGND ground, the positive power supply terminal of the operational amplifier U1 is connected to the second end of the operational amplifier decoupling capacitor C5, the output terminal of the operational amplifier U1 is connected to the other end of the resistor R5, and the resistors R2, R3, R4 and R5 are operational amplifier resistors.

[0043] Among them, it also includes a transistor Q3, the base of the transistor Q3 is connected to the resistor R6 and one end of the resistor R10, the resistor R6 is an isolation resistor, and also forms a voltage-dividing resistor of the base of the transistor Q3 with the resistor R10, the other end of the resistor R6 is connected to the output end of the operational amplifier U1 and the other end of the resistor R5, the other end of the resistor R10 is connected to the first end of the operational amplifier decoupling capacitor C5, the DGND ground, the other end of the capacitor C4, the other end of the resistor R11 and the emitter of the transistor Q3, and the collector of the transistor Q3 is connected to the other end of the resistor R12.

[0044] Among them, the MOS tube Q1 is an NMOS tube.

[0045] According to another aspect of the present invention, an adaptive output isolation control method based on any of the adaptive output isolation control circuits described above is also proposed, comprising the following steps:

[0046] When the output voltage rises to V1 or is close to V1, the transistor obtains a voltage through the voltage divider network to charge the capacitor C4 until the transistor Q2 is turned on, and the driving voltage of the MOS tube Q1 obtains a turn-on voltage, and the MOS tube Q1 is turned on normally;

[0047] Within the normal rated output voltage and current range, the MOS tube Q1 is always in the on state;

[0048] When the module output is short-circuited, the output current is greater than the normal value and the output voltage decreases.

[0049] The following steps are also included:

[0050] When a fault occurs, the current flowing through the resistor R1 increases, the voltage difference across the resistor R1 increases, the input differential signal of the operational amplifier U1 increases, the output voltage of the operational amplifier U1 increases, and the base voltage of the transistor Q3 increases, turning on the transistor Q3, turning off the transistor Q2, and turning off the MOS tube Q1.

[0051] The following steps are also included:

[0052] When the fault is removed, the output voltage and current detection values ​​return to normal, the voltage output by the operational amplifier U1 decreases, and the voltage divider value of the resistor R6 and the resistor R10 is not enough to turn on the transistor Q3, so the transistor Q2 and the MOS tube Q1 are turned on.

[0053] Main components:

[0054] R11-R16 is the adaptive voltage divider network of Q2, C4 is the slow-on capacitor of Q2; R7-R9 provides adaptive driving voltage for Q1, and D3 is the driving protection diode of Q1.

[0055] R1 is the current sampling resistor, R2-R5 are op amp resistors, U1 is the op amp, C5 is the op amp decoupling capacitor, R6 is both an isolation resistor and a voltage divider resistor for the base of Q3 together with R10. By properly adjusting the above parameters, the maximum output current value corresponding to when Q3 is turned on can be controlled; R12 is the current limiting resistor.

[0056] T1, D1, D2, C1, C2, C3 are module transformer, output rectifier diode and output capacitor.

[0057] Mode 1: When the module is connected to the DC bus, due to the body diode of Q1, the voltage on the DC bus cannot flow back to C1 and C2 through Vout+ and Vout-, causing the voltage at both ends to suddenly change and cause sparking;

[0058] The module starts up normally and slowly starts up. The output voltage gradually climbs to V1. When it is infinitely close to the DC bus voltage, the MOS tube is turned on, thus realizing the hot-swap function.

[0059] The MOS tube turn-on condition can be adjusted by appropriately adjusting R12-R16, R11 and C4 to match the build-up time of the output voltage V1, and adjusting R7-R9 to obtain a suitable driving voltage.

[0060] How it works when powered on:

[0061] When the output voltage rises to V1 or close to V1, Q2 obtains a voltage through the voltage divider network R11-R16 to charge C4 until Q2 turns on (the time of Q2 turning on can be adjusted according to the voltage divider network R11-R16 and the time constant of R11 and C4) Q1's Vg (driving voltage) obtains a turn-on voltage and Q1 turns on normally. (Assuming Vout is 53V, Vg is 10.6V) Adjusting R7-R9 can be applied to different output voltages to obtain a suitable Vg (driving voltage).

[0062] Mode 2: Within the normal rated output voltage and current range, Q1 tube is always in the on state.

[0063] Mode 3: When the module output is short-circuited, the output current is greater than the normal value and the output voltage decreases.

[0064] Working principle during fault isolation: the current flowing through R1 increases → the voltage difference across R1 increases → the input differential signal of the U1 amplifier increases → the voltage output of U1 increases → that is, the base voltage of Q3 increases → Q3 turns on → Q2 turns off → Q1 turns off.

[0065] When the fault is removed, the output voltage and current detection values ​​return to normal, the voltage output by the U1 amplifier decreases → the voltage divider value of R6 and R10 is not enough to turn on Q3 → Q2 turns on (R11-R16 obtains a voltage through Vout+ to turn on Q2) → Q1 turns on (R7-R9 obtains a voltage through Vout+ to turn on Q1).

[0066] The closed-loop control of switching power supply products will collect the voltage and current signals at the output end, so there is no need to add additional circuits to obtain the voltage and current signals.

[0067] In high-power module applications, adaptive negative-electrode MOS tubes are very suitable for output isolation; while greatly increasing the overall module efficiency, they also reduce the isolated drive power supply and peripheral circuits of the MOS tube, reducing module costs.

[0068] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. An adaptive output isolation control circuit, characterized in that: include: An adaptive voltage divider network, wherein the adaptive voltage divider network is connected to the base of the transistor Q2; A slow-on capacitor C4, one end of which is connected to the base of the transistor Q2; MOS transistor Q1 and resistors R7, R8 and R9 for providing adaptive driving voltage for the MOS transistor Q1; A diode D3, wherein the anode of the diode D3 is connected to the source of the MOS transistor Q1, the cathode of the diode D3 is connected to the gate of the MOS transistor Q1, and the diode D3 is a driving protection diode of the MOS transistor Q1; The resistor R7, the resistor R8 and the collector of the transistor Q2 are connected in series in sequence, one end of the resistor R9 is connected to the emitter of the transistor Q2, the other end of the resistor R9 is connected to the source of the MOS transistor Q1, and the emitter of the transistor Q2 is connected to the gate of the MOS transistor Q1; The adaptive voltage divider network includes a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15 and a resistor R16, wherein the resistor R13, the resistor R14, the resistor R15, the resistor R16 and the base of the transistor Q2 are sequentially connected in series, and one end of the resistor R11 and one end of the resistor R12 are respectively connected to the base of the transistor Q2; It also includes an operational amplifier U1, wherein the positive input terminal of the operational amplifier U1 is connected to one end of a resistor R2 and one end of a resistor R4, the other end of the resistor R2 is connected to IP+, the negative input terminal of the operational amplifier U1 is connected to one end of a resistor R3 and one end of a resistor R5, the other end of the resistor R3 is connected to a DGND ground, the negative power supply terminal of the operational amplifier U1 is connected to the other end of the resistor R4 and the DGND ground, the positive power supply terminal of the operational amplifier U1 is connected to the second end of an operational amplifier decoupling capacitor C5, the output terminal of the operational amplifier U1 is connected to the other end of the resistor R5, and the resistors R2, R3, R4 and R5 are operational amplifier resistors; It also includes a transistor Q3, the base of the transistor Q3 is connected to a resistor R6 and one end of a resistor R10, the resistor R6 is an isolation resistor, and also forms a voltage-dividing resistor of the base of the transistor Q3 with the resistor R10, the other end of the resistor R6 is connected to the output end of the operational amplifier U1 and the other end of the resistor R5, the other end of the resistor R10 is connected to the first end of the operational amplifier decoupling capacitor C5, the DGND ground, the other end of the capacitor C4, the other end of the resistor R11 and the emitter of the transistor Q3, and the collector of the transistor Q3 is connected to the other end of the resistor R12; MOS tube Q1 is an NMOS tube; It also includes a module transformer T1, the first output end and the third output end of the module transformer T1 are respectively connected to the positive electrodes of the output rectifier diode D1 and the output rectifier diode D2, the negative electrodes of the output rectifier diode D1 and the output rectifier diode D2 are connected to the DGND ground, the negative electrode of the output capacitor C1 and the first end of the current sampling resistor R1, the second end of the current sampling resistor R1 is connected to the negative electrode of the output capacitor C1, the negative electrode of the output capacitor C1, ip+ and the drain of the MOS tube Q1, the second output end of the module transformer T1 is connected to the positive electrode of the output capacitor C1, the positive electrode of the output capacitor C2, the positive electrode of the output capacitor C3, the resistor R13, the resistor R8 and Vout+, and the source of the MOS tube Q1, the other end of the resistor R9 and the negative electrode of the diode D3 are connected to Vout-.

2. An adaptive output isolation control method based on the adaptive output isolation control circuit according to claim 1, characterized in that: The following steps are involved: When the output voltage rises to V1 or is close to V1, the transistor obtains a voltage through the voltage divider network to charge the capacitor C4 until the transistor Q2 is turned on, and the driving voltage of the MOS tube Q1 obtains a turn-on voltage, and the MOS tube Q1 is turned on normally; Within the normal rated output voltage and current range, the MOS tube Q1 is always in the on state; When the module output is short-circuited, the output current is greater than the normal value and the output voltage decreases.

3. The adaptive output isolation control method according to claim 2, characterized in that: The following steps are also included: When a fault occurs, the current flowing through the resistor R1 increases, the voltage difference across the resistor R1 increases, the input differential signal of the operational amplifier U1 increases, the output voltage of the operational amplifier U1 increases, and the base voltage of the transistor Q3 increases, turning on the transistor Q3, turning off the transistor Q2, and turning off the MOS tube Q1.

4. The adaptive output isolation control method according to claim 3, characterized in that: The following steps are also included: When the fault is removed, the output voltage and current detection values ​​return to normal, the voltage output by the operational amplifier U1 decreases, and the voltage divider value of the resistor R6 and the resistor R10 is not enough to turn on the transistor Q3, so the transistor Q2 and the MOS tube Q1 are turned on.

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