Conversion circuit, method, device and encoder

Abstract

The present application discloses a transformation circuit, method, device and encoder, wherein the transformation circuit includes a processing unit corresponding to each operation transformation element in an operation transformation matrix; the operation transformation matrix is ​​obtained according to the initial transformation matrix transformation of a specific transformation algorithm; the processing unit is used to obtain the product between the corresponding operation transformation element and the input residual element by setting a summation path. The present application can reduce the area of ​​the residual transformation circuit and reduce the power consumption of the residual transformation circuit; by configuring each processing unit and / or adjusting the input and output, it can quickly switch between multiple transformation algorithms, with high switching efficiency and utilization; it can also transform multiple residual sequences of relatively small sizes at the same time, and / or realize the transformation of residual sequences of relatively large sizes through multiple transformations, with high flexibility; it can improve the performance of the corresponding encoder and reduce the development cost of the encoder.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a conversion circuit, method, device and encoder. Background Art

[0002] In the field of consumer electronics, video compression has always been an important research direction. Compared with the previous generation video compression standard (HEVC), the new generation video codec standard (VVC) has achieved a certain degree of coding performance improvement. Among them, by introducing the adaptive multiple transform (AMT) technology, higher energy concentration effect and better compression performance can be obtained on the transform coding module. However, since this technology introduces two additional transform types, DST-VII and DCT-VIII, and allows transforms of asymmetric sizes, the computational complexity of the corresponding video encoder is high. Summary of the invention

[0003] In view of this, the present application provides a transformation circuit, method, device and encoder to solve the problem of high computational complexity of existing video encoders.

[0004] On one hand, the present application provides a transformation circuit, comprising a processing unit corresponding to each operation transformation element in an operation transformation matrix; the operation transformation matrix is ​​obtained by transforming an initial transformation matrix of a specific transformation algorithm;

[0005] The processing unit is used to obtain the product between the corresponding operation transformation element and the input residual element by setting a summation path.

[0006] Optionally, the specific transformation algorithm includes a plurality of residual transformation algorithms; the operation transformation elements corresponding to each residual transformation algorithm are within a set value range;

[0007] The processing unit is further used to perform parameter configuration according to the operation transformation elements corresponding to each residual transformation algorithm to obtain the product between the operation transformation element and the corresponding residual element.

[0008] Optionally, the specific transformation algorithm includes at least one group of residual transformation algorithms; in the initial transformation matrices corresponding to each group of residual transformation algorithms, the corresponding row initial transformation elements of each initial transformation matrix have the following characteristics: the same absolute value, opposite order, the initial transformation elements corresponding to odd rows have the same signs, and the initial transformation elements corresponding to even rows have opposite signs.

[0009] Optionally, the transformation circuit is further used to switch from one residual transformation algorithm in each group of residual transformation algorithms to another residual transformation algorithm.

[0010] Optionally, the processing unit includes a plurality of shifters, each shifter corresponds to a channel selector and a multi-stage adder, and each stage of the multi-stage adder includes two input terminals;

[0011] The input end of each shifter is respectively connected to the corresponding residual element, and the output end is connected to the shift end of the corresponding channel selector; the zeroing end of each channel selector is respectively connected to the zeroing signal, the control end is respectively connected to the shift selection signal representing the selected shifting end or the zeroing selection signal representing the selected zeroing end, and the output end is respectively connected to an input end of a first-stage adder; the two input ends of the first-stage adder are respectively connected to the output ends of the first two channel selectors, the output end of the last-stage adder is used to output the product between the operation transformation element and the residual element, and the other input ends of the other stages of adders are connected to the output end of the previous stage adder.

[0012] Optionally, the processing unit further includes a sign selector; an input end of the sign selector is connected to an output end of the last-stage adder, and is used to determine the positive or negative sign of the product.

[0013] Optionally, the operational transformation matrix is ​​determined according to an equivalent matrix of the initial transformation matrix; the equivalent matrix is ​​a matrix obtained by reducing each initial transformation element of the initial transformation matrix by 2n times and rounding each reduced initial transformation element.

[0014] Optionally, the value of n is 3; the processing unit includes a first shifter, a second shifter, a third shifter, a first channel selector corresponding to the first shifter, a second channel selector corresponding to the second shifter, a third channel selector corresponding to the third shifter, a first-stage adder, and a second-stage adder;

[0015] One input end of the first-stage adder is connected to the output end of the first channel selector, the other input end is connected to the output end of the second channel selector, the output end is connected to one input end of the second-stage adder, the other input end of the second-stage adder is connected to the output end of the third channel selector, and the output end is used to output the product between the operational transformation element and the residual element.

[0016] Optionally, if the first matrix model of the initial transformation matrix is ​​larger than the array model of the processing units in the transformation circuit, the operational transformation matrix includes partial elements of the equivalent matrix.

[0017] Another aspect of the present application provides a transformation method, comprising:

[0018] Transforming an initial transformation matrix of a specific transformation algorithm to obtain an operational transformation matrix;

[0019] Any of the above transformation circuits is used to transform the residual sequence to be transformed according to the operation transformation matrix.

[0020] Optionally, transforming an initial transformation matrix of a specific transformation algorithm to obtain an operational transformation matrix comprises:

[0021] Each initial transformation element of the initial transformation matrix is ​​reduced by 2 n After times, the reduced initial transformation elements are rounded to get the equivalent matrix;

[0022] The operation transformation matrix is ​​determined according to the equivalent matrix.

[0023] Optionally, determining the operation transformation matrix according to the equivalent matrix includes: acquiring at least one operation transformation matrix matching the transformation circuit according to the equivalent matrix;

[0024] The method of transforming the residual sequence to be transformed according to the operational transformation matrix using any of the above-mentioned transformation circuits includes: dividing the residual sequence to be transformed into at least one sub-residual sequence according to the equivalent matrix and each operational transformation matrix, and respectively using the transformation circuit to transform the corresponding sub-residual sequence according to each operational transformation matrix to transform the residual sequence to be transformed.

[0025] Optionally, the transformation process of the sub-residual sequence includes:

[0026] According to each operational transformation element of the operational transformation matrix, a corresponding processing unit in the transformation circuit is configured so that each processing unit can obtain a product between a corresponding operational transformation element and a residual element;

[0027] The sub-residual sequence is input into the configured transformation circuit to transform the sub-residual sequence.

[0028] Optionally, the second matrix model of the operational transformation matrix is ​​smaller than or equal to the array model of the processing unit in the transformation circuit;

[0029] Before configuring the corresponding processing unit in the transformation circuit according to each operation transformation element of the operation transformation matrix, the transformation process of the sub-residual sequence further includes:

[0030] If the second matrix model is smaller than the array model, a current operation circuit corresponding to the second matrix model is selected in the transformation circuit to determine the correspondence between each operation transformation element in the operation transformation matrix and each processing unit in the current operation circuit.

[0031] Optionally, the processing units of the transformation circuit form a square array; the current operation circuit includes an upper left corner array and / or a lower right corner array of the square array.

[0032] Optionally, the configuration process of the processing unit includes:

[0033] The shift parameters of each shifter and the channel selection signal connected to the control end of each channel selector are determined according to the corresponding operation transformation elements; the channel selection signal includes a shift selection signal representing the selected shift end or a zero selection signal representing the selected zero end.

[0034] Optionally, the configuration process of the processing unit further includes:

[0035] The sign selector is configured to have a positive or negative sign according to the sign of the corresponding operation transformation element.

[0036] Optionally, the transformation method further includes:

[0037] Amplify the initial conversion result output by the conversion circuit by 2 n times.

[0038] Optionally, the transformation circuit is a DCT-VIII circuit that implements a DCT-VIII algorithm; and the process of using the DCT-VIII circuit to obtain a transformation result corresponding to a DST-VII algorithm includes:

[0039] Inputting each residual element in the residual sequence to be transformed into the DCT-VIII circuit in reverse order;

[0040] The output result of the DCT-VIII circuit is inverted at the even positions to obtain the transformation result corresponding to the DST-VII algorithm.

[0041] On the other hand, the present application provides a conversion device, comprising any of the above-mentioned conversion circuits.

[0042] On the other hand, the present application provides an encoder, comprising any one of the above-mentioned conversion circuits.

[0043] In the above-mentioned transformation circuit, method, device and encoder of the present application, each processing unit obtains the product between the corresponding operation transformation element and the input residual element by setting the summation path, thereby realizing the residual transformation corresponding to the specific transformation algorithm, which can reduce the area of ​​the residual transformation circuit and reduce the power consumption of the residual transformation circuit; by configuring each processing unit and / or adjusting the input and output, it can quickly switch between multiple residual transformation algorithms, with high switching efficiency and utilization rate; it can also transform multiple residual sequences of relatively small sizes at the same time, and / or realize the transformation of residual sequences of relatively large sizes through multiple transformations, with high flexibility; it can improve the performance of the corresponding encoder and reduce the development cost of the encoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a schematic diagram of the conversion circuit structure of an embodiment of the present application;

[0046] Figure 2a and Figure 2b is a schematic diagram of an initial transformation matrix according to an embodiment of the present application;

[0047] Figure 3a , Figure 3b and Figure 3c This is a schematic diagram of the processing unit structure of an embodiment of the present application

[0048] Figure 4 is a schematic diagram of a sub-matrix and a sub-residual sequence according to an embodiment of the present application;

[0049] Figure 5 It is a flowchart of a transformation method according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] As described in the background technology, the introduction of adaptive multiple transform technology can achieve higher energy concentration effect and better compression performance on the transform coding module, but because the technology introduces two additional transform types, DST-VII and DCT-VIII, and allows asymmetric size transforms, the computational complexity of the overall encoder increases dramatically. Therefore, low-cost, high-performance transform circuit hardware implementation is essential for the realization of real-time VVC encoders. The transform architecture of the relevant highly pipelined design uses a shift-and-add unit instead of the original multiplication operation, and supports a maximum transform size of 32x32. Although it saves area to a certain extent, different sizes in the transform architecture still use independent circuits, and there is no reuse mechanism between them, so there is still a lot of room for optimization in terms of area.

[0051] In response to the above problems, in the transformation circuit, method, device and encoder provided by the present application, each processing unit obtains the product between the corresponding operation transformation element and the input residual element by setting the summation path, thereby realizing the residual transformation corresponding to the specific transformation algorithm, which can reduce the area of ​​the residual transformation circuit and reduce the power consumption of the residual transformation circuit; by configuring each processing unit and / or adjusting the input and output, it can quickly switch between multiple residual transformation algorithms, with high switching efficiency and utilization rate; it can also transform multiple residual sequences of relatively small sizes at the same time, and / or realize the transformation of residual sequences of relatively large sizes through multiple transformations, with high flexibility; it can improve the performance of the encoder and reduce the development cost of the corresponding encoder.

[0052] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0053] The first aspect of the present application provides a conversion circuit, referring to Figure 1 As shown, the transformation circuit includes a processing unit corresponding to each operation transformation element in the operation transformation matrix; the operation transformation matrix is ​​obtained according to the initial transformation matrix transformation of a specific transformation algorithm; the processing unit is used to obtain the product between the corresponding operation transformation element and the input residual element by setting a summation path. Figure 1 1 shows a transformation circuit including 8×8 processing units, wherein the operation transformation element corresponding to each small box is Tij, and i and j are integers greater than or equal to 0 and less than or equal to 7. Figure 1 As shown, the residual sequence to be transformed X T =[X0,X1,X2,X3,X4,X5,X6,X7] T Each residual element of Figure 1 Each row processing unit of the transformation circuit shown can make each processing unit perform operations on each residual element respectively to transform the residual sequence to be transformed. Each of the above processing units can be configured with parameters according to each operation transformation element in the operation transformation matrix corresponding to a specific transformation algorithm. The configured processing unit can accurately transform the corresponding residual element, so that the transformation circuit can realize a complex residual transformation process with a simple circuit, and can also be reused by multiple residual transformation algorithms, which can reduce the area of ​​the residual transformation circuit, reduce the power consumption of the residual transformation circuit, and thus reduce the development cost of the corresponding encoder.

[0054] In one embodiment, the above-mentioned specific transformation algorithm includes multiple residual transformation algorithms; the operation transformation elements corresponding to each residual transformation algorithm are within the set value range, so that by configuring the processing unit parameters corresponding to the above-mentioned operation transformation elements, the processing unit can accurately calculate the operation transformation elements and the corresponding residual operation, thereby ensuring the corresponding transformation accuracy. The above-mentioned processing unit is also used to configure parameters according to the operation transformation elements corresponding to each residual transformation algorithm to obtain the product between the operation transformation element and the corresponding residual element. Specifically, the above-mentioned processing unit can configure parameters according to the operation transformation elements corresponding to a residual transformation algorithm in each transformation process to perform corresponding operations on the operation transformation element and the corresponding residual element, so that the transformation circuit can use a residual transformation algorithm to transform the residual sequence to be transformed at each transformation, so that each residual transformation algorithm can reuse the transformation circuit, which can improve the utilization rate of the transformation circuit, improve the transformation function, thereby improving the encoding ability of the corresponding encoder, and reducing the circuit area and development cost of the above-mentioned encoder. The set value range is determined according to the specific structure of each processing unit in the transformation circuit, and can be a relatively small numerical range such as 0 to 11, so that the circuit structure of the processing unit is relatively simple.

[0055] Specifically, the specific transformation algorithm includes at least one group of residual transformation algorithms; each group of residual transformation algorithms may include two residual transformation algorithms, such as the DST-VII algorithm and the DCT-VIII algorithm. In the initial transformation matrix corresponding to each group of residual transformation algorithms, the initial transformation elements of the corresponding rows (rows with the same serial number) of each initial transformation matrix have the following characteristics: the absolute value is the same, the order is opposite, the initial transformation elements corresponding to the odd rows have the same sign, and the initial transformation elements corresponding to the even rows have opposite signs. That is, the corresponding rows of each initial transformation matrix include the same row of elements, and the row elements are arranged in positive order in one initial transformation matrix and in reverse order in another initial transformation matrix; if the corresponding row is an odd row, the corresponding elements in each initial transformation matrix have the same sign and the same absolute value; if the corresponding row is an even row, the corresponding elements in each initial transformation matrix are opposite numbers, that is, the signs are opposite and the absolute values ​​are equal. Reference Figure 2aAs shown, A1 is the initial transformation matrix of a residual transformation algorithm in a group of residual transformation algorithms (referred to as A1 algorithm), and A2 is the initial transformation matrix of another residual transformation algorithm in the group of residual transformation algorithms (referred to as A2 algorithm). In A1 and A2, the initial transformation elements of the first row of A1 are a00, a01, a02 and a03, and the initial transformation elements of the first row of A2 are a03, a02, a01 and a00, which are in the opposite order of the initial transformation elements of the first row of A1, and the signs of the corresponding elements are the same and the absolute values ​​are equal; the initial transformation elements of the second row of A1 are a10, a11, a12 and a13, and the initial transformation elements of the second row of A2 are -a13, -a12, -a11 and -a10, which are in the opposite order of the initial transformation elements of the second row of A1, and the signs of the corresponding elements in each row are opposite and the absolute values ​​are equal. In the corresponding row, the first element corresponds to the last element, the second element corresponds to the second to last element, the third element corresponds to the third to last element, and so on.

[0056] Optionally, the above-mentioned transformation circuit is also used to switch from one residual transformation algorithm in each group of residual transformation algorithms to another residual transformation algorithm, so that without adding additional computing resources, only the input and output conditions need to be fine-tuned, and the above-mentioned transformation circuit can be used to implement the functions of each residual transformation algorithm in each group of residual transformation algorithms, which can improve the circuit reuse rate and work efficiency and reduce the circuit area. For example, if the transformation circuit is currently an A1 circuit that implements the A1 algorithm, the following two operations are performed on the input and output of the A1 circuit to obtain the transformation result corresponding to the A2 algorithm: (1) input each residual element in the residual sequence to be transformed into the A1 circuit in reverse order, and (2) invert the output result of the A1 circuit at the even position.

[0057] In an example, the DST-VII algorithm and the DCT-VIII algorithm are used as examples to illustrate the transformation principle of the above transformation circuit. The transformation coding process when encoding video data is to perform a two-dimensional transformation on the residual block. According to the separability of the two-dimensional transformation, the two-dimensional transformation can be decomposed into two one-dimensional transformations, namely, row transformation and column transformation. Both have order-preserving rows, that is, whether to perform row transformation first or column transformation first does not affect the final result. The corresponding one-dimensional transformation formulas include: Y = T N ·X T , where T N Represents the initial transformation matrix of the DST-VII algorithm or the DCT-VIII algorithm. The matrix model is N×N and is used to transform the residual sequence to be transformed including N residual elements. X T Here, we take N=4 as an example to illustrate the relationship between the DST-VII algorithm and the DCT-VIII algorithm. The initial transformation matrix DCT-VIII of the DCT-VIII algorithm is 4×4and the initial transformation matrix DST-VII of the DST-VII algorithm 4×4 You can refer to Figure 2b As shown, compared Figure 2b It can be seen from the two initial transformation matrices shown that: (1) the initial transformation elements of the corresponding rows have a corresponding relationship, and the elements of a row are arranged in positive order in one initial transformation matrix and in reverse order in the other initial transformation matrix; (2) the corresponding elements in odd rows have the same signs, and the corresponding elements in even rows are opposite numbers. According to the above two characteristics, combined with the one-dimensional transformation process, it can be seen that by using the transformation circuit provided by the present application, it is only necessary to configure and / or adjust the input and output, and then each residual transformation algorithm can be transformed into a residual transformation algorithm. For example, if the transformation circuit is currently a DCT-VIII circuit, the following two operations are performed on the input and output of the DCT-VIII circuit to obtain the transformation result corresponding to the DST-VII algorithm: (1) Input each residual element in the residual sequence to be transformed into the DCT-VIII circuit in reverse order, and (2) Invert the output result of the DCT-VIII circuit at the even position. In this way, without adding additional computing resources, the DCT-VIII circuit can be used to implement the functions of the DST-VII algorithm by only fine-tuning the input and output conditions, thereby improving the circuit reuse rate and reducing the circuit area.

[0058] The purpose of residual transformation in the video encoding process is to be able to concentrate the residual in the upper left corner, combined with quantization and entropy coding to achieve higher compression efficiency. The integer transform used in VVC (Versatile Video Coding, a new generation of video codec standard) is to approximate the standard transformation matrix by scaling it. Based on this idea, this example uses two matrix multiplications to approximate the transformation matrix in VVC. The corresponding matrix transformation process is shown in the following formula: Represents the initial transformation matrix T N The approximated transformation matrix, C N Indicates that each initial transformation element of the initial transformation matrix is ​​reduced by 2 n After multiplying, the equivalent matrix S is obtained by rounding off each initial transformation element after reduction (such as rounding off or rounding up). N Represented as a diagonal matrix, the values ​​in the diagonal direction are all 2 n , the value of n can be determined according to characteristics such as circuit resources, calculation accuracy and / or processing complexity, and can be 3 or the like. Taking the DCT-VIII algorithm as an example, the above matrix transformation process can be:

[0059]

[0060] From the above formula, we can see that When implementing the residual transformation corresponding to the DCT-VIII algorithm, first convert C N As the operation transformation matrix, the output position is enlarged by 2 n That’s it. n Scaling is just a rearrangement of lines in the hardware circuit, so it does not introduce additional area and can effectively reduce the circuit area required for the transformation circuit. The operation transformation matrix C corresponding to the above DCT-VIII algorithm is N It can be seen that the absolute value of each operation transformation element is between 0 and 11. Although the values ​​of each element of the initial transformation matrices of different sizes are different, after similar approximation, the elements in the corresponding operation transformation matrices are also between 0 and 11. This enables each processing unit in the above-mentioned transformation circuit to be configured accordingly to implement each residual transformation algorithm, and also provides the possibility for the reuse design of circuits of different sizes.

[0061] In one embodiment, reference Figure 3a As shown, the processing unit includes a plurality of shifters 110, each shifter 110 corresponds to a channel selector 120, and also includes a multi-stage adder 130, each stage of the multi-stage adder 130 includes two input terminals;

[0062] The input end of each shifter 110 is connected to the corresponding residual element, and the output end is connected to the shift end of the corresponding channel selector 120; the zeroing end of each channel selector 120 is connected to the zeroing signal (such as Figure 3a As shown in FIG0), the control end is respectively connected to a shift selection signal representing the selected shift end or a zero selection signal representing the selected zero end, and the output end is respectively connected to an input end of a first-level adder, such as Figure 3a In the embodiment, the control end of each channel selector 120 is respectively connected to the selection signal mux. When mux=1, the selection signal mux represents the shift selection signal, and the shift end is selected at this time. When mux=0, the selection signal mux represents the zero selection signal, and the zero end is selected at this time. The two input ends of the first-stage adder are respectively connected to the output ends of the first two channel selectors, and the output end of the last-stage adder is used to output the product between the operational transformation element and the residual element. The other input ends of the adders at other stages are connected to the output ends of the previous adder.

[0063] Optionally, refer to Figure 3bAs shown, the processing unit may further include a sign selector 141; the input end of the sign selector 141 is connected to the output end of the last-stage adder, for determining the positive and negative signs of the product. Here, the sign selector 141 is connected to the output end of the last-stage adder, so that when the signs of the operation transformation elements corresponding to the various residual transformation algorithms are opposite, the circuit for implementing one residual transformation algorithm can be quickly switched to the circuit for implementing another residual transformation algorithm, which can improve the switching efficiency of the transformation circuit between the various residual transformation algorithms.

[0064] Since the operation transformation elements corresponding to each residual transformation algorithm are within the set value range, the above-mentioned processing unit can realize the multiplication operation between the operation transformation elements and the residual elements through multiple shifters, corresponding channel selectors and adders at various levels. This embodiment uses shifting and addition to replace the original multiplication, which can make the area of ​​each processing unit smaller. In addition, by configuring the shift parameters of each shifter 110, the signal channels selected by each channel selector 120, and the symbol channels selected by the symbol selector 141, the corresponding transformation circuit can quickly switch between various residual transformation algorithms.

[0065] Specifically, the operational transformation matrix is ​​determined according to the equivalent matrix of the initial transformation matrix; the equivalent matrix is ​​obtained by reducing each initial transformation element of the initial transformation matrix by 2. n After multiple times, the matrix is ​​obtained by rounding the reduced initial transformation elements; the value of n can be determined according to circuit resources, calculation accuracy and / or processing complexity. Optionally, the corresponding transformation circuit can also further amplify the initial transformation result by 2 at the output position. n , in order to ensure the accuracy of the final transformation result.

[0066] Optionally, if the first matrix model of the initial transformation matrix (i.e., the number of rows or columns of the corresponding square matrix) is larger than the array model of the processing unit in the transformation circuit (i.e., the number of rows or columns of the processing unit), the equivalent matrix can be divided into multiple equivalent blocks, and the operational transformation matrix includes some elements corresponding to an equivalent block in the equivalent matrix, so that the above-mentioned transformation circuit can be used to transform the corresponding residual elements according to each equivalent block, thereby ensuring the integrity of the implemented algorithm.

[0067] In one example, the value of n is 3; see Figure 3cAs shown, the processing unit includes a first shifter 111, a second shifter 112, a third shifter 113, a first channel selector 121 corresponding to the first shifter 111, a second channel selector 122 corresponding to the second shifter 112, a third channel selector 123 corresponding to the third shifter 113, a first-stage adder 131 and a second-stage adder 132; one input end of the first-stage adder 131 is connected to the output end of the first channel selector 121, the other input end is connected to the output end of the second channel selector 122, the output end is connected to one input end of the second-stage adder 132, the other input end of the second-stage adder 132 is connected to the output end of the third channel selector 123, and the output end is used to output the product between the operational transformation element and the residual element.

[0068] The operation transformation elements corresponding to the operation transformation matrix are within the set value range, such as between 0 and 11. At this time, each processing unit can achieve output from 0x to 11x through three shifters and two adders. The reconfigurability of the processing unit is mainly reflected in the shift control and output sign control. Figure 3c The processing unit shown can use a 3-bit shift signal to configure the number of shifts of each shifter to the left, and three selection signals mux are used to select the outputs of the three shifters, so that the product of the residual element and the operational transformation element can be obtained through a fixed summation path; finally, the sign selector is used to select the positive and negative values ​​of the product. For example, when the processing unit is used to implement 10x (where 10 is the coefficient and x is the input), the shift parameters of the first shifter, the second shifter, and the third shifter can be configured to 3, 1, and 0 respectively, to obtain 8x, 2x, and 0. After the corresponding channel selector is selected, the sum result is (8x+2x+0=10x). When the sign selector selects the positive channel, the multiplication operation of 10x can be implemented.

[0069] Furthermore, when the conversion circuit includes 8×8=64 processing units, it can be as follows Figure 1 As shown, a structure of horizontal input and vertical output is adopted. That is, 8 input residual elements are input from the horizontal direction, pass through 8 processing units in sequence, and output 64 intermediate results; the intermediate results in the vertical direction are accumulated and shifted to obtain the initial transformation results of the corresponding residual elements, so there are 8 output results in total. The transformation circuit including 8×8=64 processing units can be directly used for the transformation of 8 points (i.e., the residual sequence to be transformed including 8 residual elements).

[0070] Optionally, for the transformation of a single 4-point (including a residual sequence to be transformed of 4 residual elements), this example can select some processing units in the transformation circuit for transformation, such as a 4x4 processing unit array in the upper left corner or the lower right corner. At this time, the processing unit arrays in the upper left corner or the lower right corner can be configured according to the corresponding operation transformation elements, and other processing units output a value of 0. In this way, a single 4-point transformation can be conveniently implemented, and multiple 4x4 processing unit arrays can be used simultaneously to implement multiple 4-point transformations, such as using the 4x4 areas in the upper left corner and the lower right corner to perform two 4-point transformations at the same time, further improving the transformation efficiency.

[0071] Optionally, for residual transformations with a size greater than 8 points, such as 16-point transformation (including a residual sequence to be transformed of 16 residual elements) and 32-point transformation (including a residual sequence to be transformed of 32 residual elements), when the first matrix model of the initial transformation matrix is ​​larger than the array model of the processing unit in the transformation circuit, the equivalent matrix can be divided into multiple equivalent blocks, and each equivalent matrix is ​​used as an operation transformation matrix, and then the above-mentioned transformation circuit is used to transform the corresponding residual elements according to each equivalent block, and the transformation circuit is used multiple times to transform each part of the residual elements to transform the entire residual sequence to be transformed. For example, refer to Figure 4 As shown, a transformation circuit including 8×8=64 processing units is used to perform 16-point transformation. The residual sequence to be transformed can be first divided into two sub-residual sequences, L0 and L1, each of which is an 8×1 input. The 16×16 equivalent matrix is ​​divided into four 8×8 blocks: A, B, C and D, which are the operation transformation matrices used in each transformation process. At this time, the implementation process of the above 16-point transformation can be divided into four steps: A×L0, B×L1, C×L0 and D×L1, where each step is completed within one transformation cycle, that is, the 16-point transformation can be realized by multiplexing the transformation circuit 4 times. Specifically, in the first transformation cycle, L0 is input into the transformation circuit. At this time, the transformation circuit is configured as A, and A×L0 is completed. The intermediate results can be stored in 8 accumulators. In the second transformation cycle, L1 enters the transformation circuit. At this time, the transformation circuit is configured as B, and B×L1 is completed. The intermediate result obtained is accumulated with the intermediate result of A×L0 stored in the accumulator, so the final transformation result of the first 8 coefficients is obtained. Similarly, by controlling the configuration of the processing unit of the input and transformation circuit, the accumulation results of C×L0 and D×L1 can be obtained, which is the final transformation result of the last 8 coefficients. Through the above-mentioned split matrix multiplication algorithm, the 16-point transformation can be completed within 4 cycles when the transformation circuit including 8×8 processing units is reused. Similarly, the use of this transformation circuit can complete 32-point transformation within 16 transformation cycles.

[0072] The above transformation circuit includes a processing unit corresponding to each operation transformation element in the operation transformation matrix. Each processing unit obtains the product between the corresponding operation transformation element and the input residual element by setting a summation path, so as to transform the residual sequence to be transformed by adopting a specific transformation algorithm. This can reduce the area of ​​the residual transformation circuit and reduce the power consumption of the residual transformation circuit; by configuring each processing unit and / or adjusting the input and output, it can quickly switch between multiple residual transformation algorithms, with high switching efficiency and utilization rate; it can also transform multiple residual sequences of relatively small sizes at the same time, and / or realize the transformation of residual sequences of relatively large sizes through multiple transformations, with high flexibility; it can improve the performance of the encoder and reduce the development cost of the corresponding encoder.

[0073] In a second aspect, the present application also provides a transformation method, referring to Figure 5 As shown, the transformation method includes:

[0074] S510, transforming the initial transformation matrix of the specific transformation algorithm to obtain an operation transformation matrix; this step can transform the initial transformation matrix in the form of shrinking, etc., to obtain an operation transformation matrix that can simplify the operation process. Optionally, if the initial transformation matrix is ​​shrunk to obtain the required operation transformation matrix, the preliminary operation result can be amplified at the output end of the transformation circuit to ensure the accuracy of the obtained transformation result.

[0075] S520: Use the transformation circuit described in any of the above embodiments to transform the residual sequence to be transformed according to the operation transformation matrix.

[0076] The above steps can input each residual element of the residual sequence to be transformed into each row processing unit of the transformation circuit, so that each processing unit can perform operations on each residual element to transform the residual sequence to be transformed. Specifically, each processing unit can be configured with parameters according to each operation transformation element in the operation transformation matrix corresponding to a specific transformation algorithm, so that the corresponding residual elements can be accurately transformed using the configured processing unit, so that the transformation circuit can realize a complex residual transformation process with a simple circuit. By configuring each processing unit, multiple residual transformation algorithms can reuse the above transformation circuit, which can improve the utilization rate of the transformation circuit.

[0077] In one embodiment, transforming the initial transformation matrix of a specific transformation algorithm to obtain the operation transformation matrix includes: reducing each initial transformation element of the initial transformation matrix by 2 n After multiplying, the reduced initial transformation elements are rounded to obtain an equivalent matrix; the operation transformation matrix is ​​determined according to the equivalent matrix. The value of n can be determined according to characteristics such as circuit resources, operation accuracy and / or processing complexity. The operation transformation matrix determined in this embodiment can effectively reduce the amount of calculation in the subsequent transformation process and simplify the corresponding circuit structure.

[0078] Optionally, the above transformation method may further include: amplifying the initial transformation result output by the transformation circuit by 2 n times to obtain the transformation result corresponding to the residual sequence to be transformed, ensuring the accuracy of the final transformation result.

[0079] Specifically, the determining of the operation transformation matrix according to the equivalent matrix includes: obtaining at least one operation transformation matrix matching the transformation circuit according to the equivalent matrix; the second matrix model of the operation transformation matrix is ​​less than or equal to the array model of the processing unit in the transformation circuit, indicating that the operation transformation matrix matches the transformation circuit. For example, if the matrix model of the equivalent matrix is ​​less than or equal to the array model of the processing unit in the transformation circuit, the equivalent matrix can be used as the operation transformation matrix; if the matrix model of the equivalent matrix is ​​greater than the array model of the processing unit in the transformation circuit, the equivalent matrix can be divided into multiple block sub-matrices, and each block sub-matrix can be used as an operation transformation matrix in turn. At this time, the residual sequence to be transformed can be divided into multiple sub-residual sequences, and the corresponding relationship between the sub-matrices and the sub-residual sequences is determined, so that the transformation circuit uses each operation transformation matrix to transform the corresponding residual elements to transform the residual sequence to be transformed.

[0080] The above-mentioned use of the transformation circuit to transform the residual sequence to be transformed according to the operation transformation matrix includes: dividing the residual sequence to be transformed into at least one sub-residual sequence according to the equivalent matrix and each operation transformation matrix, and using the transformation circuit to transform the corresponding sub-residual sequence according to each operation transformation matrix to transform the residual sequence to be transformed. For example, referring to Figure 4As shown, a transformation circuit including 8×8=64 processing units is used to perform 16-point transformation, and the 16×16 equivalent matrix is ​​divided into 4 8×8 blocks: A, B, C and D, which are used as the operation transformation matrix for each transformation; the residual sequence to be transformed is divided into two sub-residual sequences L0 and L1, each sub-residual sequence is an 8×1 input, and the sub-residual sequences corresponding to A, B, C and D are determined. At this time, the implementation process of the above 16-point transformation can be divided into 4 steps: A×L0, B×L1, C×L0 and D×L1, each of which is completed within a transformation cycle, that is, the 16-point transformation can be realized by multiplexing the transformation circuit 4 times. Specifically, in the first transformation cycle, L0 enters the transformation circuit, and the transformation circuit is configured as A at this time, completing A×L0, and the intermediate results can be stored in 8 accumulators. In the second transformation cycle, L1 enters the transformation circuit. At this time, the transformation circuit is configured as B, and B×L1 is completed. The intermediate result obtained is accumulated with the intermediate result of A×L0 stored in the accumulator, so the final transformation result of the first 8 coefficients is obtained. Similarly, by controlling the configuration of the processing unit of the input and transformation circuit, the accumulation results of C×L0 and D×L1 can be obtained, which is the final transformation result of the last 8 coefficients. Through the above-mentioned split matrix multiplication algorithm, the 16-point transformation can be completed within 4 cycles when the transformation circuit including 8×8 processing units is reused.

[0081] In one example, the transformation process of the sub-residual sequence includes: configuring the corresponding processing units in the transformation circuit according to each operational transformation element of the operational transformation matrix so that each processing unit can obtain the product between the corresponding operational transformation element and the residual element; inputting the sub-residual sequence into the configured transformation circuit to transform the sub-residual sequence.

[0082] Specifically, the second matrix model of the operation transformation matrix is ​​less than or equal to the array model of the processing unit in the transformation circuit; before configuring the corresponding processing unit in the transformation circuit according to each operation transformation element of the operation transformation matrix, the transformation process of the sub-residual sequence also includes: if the second matrix model is less than the array model, selecting the current operation circuit corresponding to the second matrix model in the transformation circuit, and determining the corresponding relationship between each operation transformation element in the operation transformation matrix and each processing unit in the current operation circuit. Optionally, other processing units output 0 values ​​or other invalid parameters.

[0083] Optionally, the processing units of the transformation circuit form a square array; the current operation circuit includes the upper left corner array and / or the lower right corner array of the square array to facilitate the input of residual elements and / or the acquisition and processing of corresponding outputs.

[0084] Optionally, if the second matrix model is smaller than the array model, multiple current operation circuits corresponding to the second matrix model can be selected in the transformation circuit, and the corresponding relationship between each operation transformation element and the processing unit in each operation transformation matrix can be determined to simultaneously configure each processing unit of each current operation circuit, and each current operation circuit can be used to simultaneously transform the corresponding residual sequence to be transformed to improve the transformation efficiency. For example, for a 4-point transformation, the 4x4 processing units in the upper left corner and the 4x4 processing units in the lower right corner can be selected from the transformation circuit including 8×8=64 processing units as two current operation circuits, and the two current operation circuits respectively implement a 4-point transformation to perform two transformations at the same time.

[0085] In one example, the configuration process of the processing unit includes: determining the shift parameters of each shifter and the channel selection signal connected to the control end of each channel selector according to the corresponding operational transformation element, so that the processing unit obtains the product of the corresponding operational transformation element and the residual element; the channel selection signal includes a shift selection signal representing the selected shift end or a zero selection signal representing the selected zero end.

[0086] Furthermore, the configuration process of the processing unit also includes: configuring the positive and negative signs of the sign selector according to the signs of the corresponding operation transformation elements, so as to more accurately characterize the characteristics of the corresponding operation transformation elements.

[0087] In one embodiment, the transformation circuit is a DCT-VIII circuit that implements the DCT-VIII algorithm; the process of using the DCT-VIII circuit to obtain the transformation result corresponding to the DST-VII algorithm includes: inputting each residual element in the residual sequence to be transformed into the DCT-VIII circuit in reverse order; and inverting the output result of the DCT-VIII circuit at an even position to obtain the transformation result corresponding to the DST-VII algorithm.

[0088] In this embodiment, without increasing additional computing resources, only input and output conditions need to be fine-tuned to implement the functions of the DST-VII algorithm using the DCT-VIII circuit, thereby improving the circuit reuse rate and reducing the circuit area.

[0089] The above-mentioned conversion method is implemented by using the conversion circuit provided by any of the above-mentioned embodiments, and has all the beneficial effects of the above-mentioned conversion circuit, which will not be described in detail here.

[0090] For the specific description of the transformation method provided in the present application, reference may be made to the corresponding description of the transformation circuit in the aforementioned embodiments. The above-mentioned transformation method has all the beneficial effects of the above-mentioned transformation circuit, which will not be repeated here.

[0091] In a third aspect, the present application further provides a conversion device, comprising at least one conversion circuit described in any of the above embodiments.

[0092] The above-mentioned transformation device may include at least one transformation circuit, which can realize residual transformation corresponding to multiple residual transformation algorithms and reduce the area and power consumption of the residual transformation circuit; when it includes multiple transformation circuits, it can also use each transformation circuit to perform residual transformation simultaneously, which can improve the transformation speed and thereby improve the encoding efficiency of the corresponding encoder.

[0093] In a fourth aspect, the present application further provides an encoder, comprising the conversion circuit described in any of the above embodiments.

[0094] The above-mentioned encoder adopts the transformation circuit provided by any of the above-mentioned embodiments to perform residual transformation. The circuit used for residual transformation has a small area and low power consumption. By configuring each processing unit and / or adjusting the input and output, it can quickly switch between multiple residual transformation algorithms, with high flexibility. The performance of the encoder is improved and the development cost is reduced.

[0095] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementation of this specification shown herein.

[0096] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0097] In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0098] In this application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

Claims

1. A conversion circuit, characterized in that: The transformation circuit includes a processing unit corresponding to each operation transformation element in the operation transformation matrix; the operation transformation matrix is ​​obtained by transforming the initial transformation matrix according to the specific transformation algorithm; The processing unit is used to obtain the product between the corresponding operation transformation element and the input residual element by setting a summation path; The processing unit comprises a plurality of shifters, a sign selector, a channel selector corresponding to each shifter and a multi-stage adder, each stage of the multi-stage adder comprises two input ends; the input end of each shifter is respectively connected to the corresponding residual element, and the output end is connected to the shift end of the corresponding channel selector; the zeroing end of each channel selector is respectively connected to the zeroing signal, the control end is respectively connected to the shift selection signal representing the selected shifting end or the zeroing selection signal representing the selected zeroing end, and the output end is respectively connected to an input end of a first-stage adder; the two input ends of the first-stage adder are respectively connected to the output ends of the first two channel selectors, the output end of the last-stage adder is used to output the product between the operation transformation element and the residual element, and the other input end of the other stages of the adder is connected to the output end of the previous stage adder; the input end of the sign selector is connected to the output end of the last-stage adder, and is used to determine the positive and negative signs of the product.

2. The conversion circuit according to claim 1, characterized in that: The specific transformation algorithm includes a plurality of residual transformation algorithms; the operation transformation elements corresponding to each residual transformation algorithm are within a set value range; The processing unit is further used to perform parameter configuration according to the operation transformation elements corresponding to each residual transformation algorithm to obtain the product between the operation transformation element and the corresponding residual element.

3. The conversion circuit according to claim 2, characterized in that: The specific transformation algorithm includes at least one group of residual transformation algorithms; in the initial transformation matrix corresponding to each group of residual transformation algorithms, the corresponding row initial transformation elements of each initial transformation matrix have the following characteristics: the absolute value is the same, the order is opposite, the initial transformation elements corresponding to the odd rows have the same signs, and the initial transformation elements corresponding to the even rows have opposite signs.

4. The conversion circuit according to claim 3, characterized in that: The transformation circuit is also used for switching from one residual transformation algorithm in each group of residual transformation algorithms to another residual transformation algorithm.

5. The conversion circuit according to claim 1, characterized in that: The operational transformation matrix is ​​determined according to the equivalent matrix of the initial transformation matrix; the equivalent matrix is ​​obtained by reducing each initial transformation element of the initial transformation matrix by 2. n After multiplying, the matrix is ​​obtained by rounding the reduced initial transformation elements.

6. The conversion circuit according to claim 5, characterized in that: The value of n is 3; the processing unit includes a first shifter, a second shifter, a third shifter, a first channel selector corresponding to the first shifter, a second channel selector corresponding to the second shifter, a third channel selector corresponding to the third shifter, a first-stage adder and a second-stage adder; One input end of the first-stage adder is connected to the output end of the first channel selector, the other input end is connected to the output end of the second channel selector, the output end is connected to one input end of the second-stage adder, the other input end of the second-stage adder is connected to the output end of the third channel selector, and the output end is used to output the product between the operational transformation element and the residual element.

7. The conversion circuit according to claim 5, characterized in that: If the first matrix model of the initial transformation matrix is ​​larger than the array model of the processing units in the transformation circuit, the operational transformation matrix includes partial elements of the equivalent matrix.

8. A transformation method, characterized in that: The transformation method comprises: Transforming an initial transformation matrix of a specific transformation algorithm to obtain an operational transformation matrix; The transformation circuit according to any one of claims 1 to 7 is used to transform the residual sequence to be transformed according to the operation transformation matrix.

9. The transformation method according to claim 8, characterized in that: The transforming of the initial transformation matrix of the specific transformation algorithm to obtain the operation transformation matrix comprises: Each initial transformation element of the initial transformation matrix is ​​reduced by 2 n After times, the reduced initial transformation elements are rounded to get the equivalent matrix; The operation transformation matrix is ​​determined according to the equivalent matrix.

10. The transformation method according to claim 9, characterized in that: Determining the operation transformation matrix according to the equivalent matrix includes: acquiring at least one operation transformation matrix matching the transformation circuit according to the equivalent matrix; The method of transforming the residual sequence to be transformed according to the operation transformation matrix using the transformation circuit described in any one of claims 1 to 7 includes: dividing the residual sequence to be transformed into at least one sub-residual sequence according to the equivalent matrix and each operation transformation matrix, and using the transformation circuit to transform the corresponding sub-residual sequence according to each operation transformation matrix to transform the residual sequence to be transformed.

11. The conversion method according to claim 10, characterized in that: The transformation process of the sub-residual sequence includes: According to each operational transformation element of the operational transformation matrix, a corresponding processing unit in the transformation circuit is configured so that each processing unit can obtain a product between a corresponding operational transformation element and a residual element; The sub-residual sequence is input into the configured transformation circuit to transform the sub-residual sequence.

12. The conversion method according to claim 11, characterized in that: The second matrix model of the operational transformation matrix is ​​smaller than or equal to the array model of the processing unit in the transformation circuit; Before configuring the corresponding processing unit in the transformation circuit according to each operation transformation element of the operation transformation matrix, the transformation process of the sub-residual sequence further includes: If the second matrix model is smaller than the array model, a current operation circuit corresponding to the second matrix model is selected in the transformation circuit to determine the correspondence between each operation transformation element in the operation transformation matrix and each processing unit in the current operation circuit.

13. The conversion method according to claim 12, characterized in that: The processing units of the transformation circuit form a square array; the current operation circuit includes an upper left corner array and / or a lower right corner array of the square array.

14. The conversion method according to claim 12, characterized in that: The configuration process of the processing unit includes: The shift parameters of each shifter and the channel selection signal connected to the control end of each channel selector are determined according to the corresponding operation transformation elements; the channel selection signal includes a shift selection signal representing the selected shift end or a zero selection signal representing the selected zero end.

15. The transformation method according to claim 14, characterized in that: The configuration process of the processing unit also includes: The sign selector is configured to have a positive or negative sign according to the sign of the corresponding operation transformation element.

16. The transformation method according to claim 9, characterized in that: The transformation method further comprises: Amplify the initial conversion result output by the conversion circuit by 2 n times.

17. The transformation method according to claim 8, characterized in that: The transformation circuit is a DCT-VIII circuit for implementing the DCT-VIII algorithm; and the process of using the DCT-VIII circuit to obtain the transformation result corresponding to the DST-VII algorithm includes: Inputting each residual element in the residual sequence to be transformed into the DCT-VIII circuit in reverse order; The output result of the DCT-VIII circuit is inverted at the even positions to obtain the transformation result corresponding to the DST-VII algorithm.

18. A conversion device, characterized in that: The invention comprises the conversion circuit as claimed in any one of claims 1 to 7.

19. An encoder, characterized in that The invention comprises the conversion circuit as claimed in any one of claims 1 to 7.

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