Semiconductor substrate processing method and semiconductor device

Abstract

The embodiment of the present application discloses a semiconductor substrate processing method and a semiconductor device, the processing method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a photoresist layer formed on the substrate; setting a plasma etching power, introducing a reaction gas and a sealing gas into a chamber where the semiconductor substrate is located to trim the photoresist layer; reducing the sealing gas flow rate to improve the uniformity parameter of the critical dimension of the edge of the semiconductor substrate. When performing etching and trimming of the photoresist layer, the embodiment of the present application reduces the sealing gas flow rate, adjusts the distribution of the reaction gas during the plasma etching process, and then adjusts the uniformity parameter of the critical dimension of the edge area of ​​the processed semiconductor substrate, thereby alleviating the technical problem of poor uniformity of the critical dimension.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and more specifically, to a semiconductor substrate processing method and a semiconductor device. Background Art

[0002] In the field of semiconductor production, as the size of semiconductor device manufacturing is reduced, the line width on the semiconductor substrate continues to shrink. In order to prevent the photoresist pattern on the semiconductor substrate from having a large aspect ratio, a thinner photoresist needs to be used, but a thinner photoresist will encounter corrosion resistance problems. Therefore, in the field of photolithography technology, photoresist in-situ trimming, atomic layer deposition and double exposure development are used to reduce the line width of the semiconductor substrate. Using this method, the uniformity of the key dimensions formed in the edge area of ​​the semiconductor substrate after the photoresist is trimmed in situ is poor, which in turn has a certain impact on the product rate. Summary of the invention

[0003] In view of this, an object of the embodiments of the present application is to provide a semiconductor substrate processing method and a semiconductor device to alleviate the existing technical problems.

[0004] According to some embodiments, the first aspect of the present application provides a semiconductor substrate processing method, including: providing a semiconductor substrate, the semiconductor substrate including a substrate, and a photoresist layer formed on the substrate; setting a plasma etching power, introducing a reaction gas and a sealing gas into a chamber where the semiconductor substrate is located to trim the photoresist layer; reducing the sealing gas flow rate to improve the uniformity parameters of key dimensions of the edge of the semiconductor substrate.

[0005] In one embodiment, the method further includes: adjusting the plasma etching power and / or the ratio of reaction gas components.

[0006] In one embodiment, the method further includes: adjusting the temperature of the semiconductor substrate according to the temperature change of the semiconductor substrate and a set temperature threshold.

[0007] In one embodiment, the reaction gas contains oxygen, which includes: reducing the sealing gas flow rate, the plasma etching power, and the proportion of oxygen in the reaction gas components, and increasing the proportion of other gases in the reaction gas components except oxygen.

[0008] Inert gas is introduced into the surface of the semiconductor substrate, and the surface defects of the semiconductor substrate are removed by vacuuming.

[0009] In one embodiment, the time for removing surface defects of the semiconductor substrate by evacuating the gas is adjusted according to the sealing gas flow rate.

[0010] In one embodiment, the time for removing surface defects of the semiconductor substrate by vacuuming is 5-10 seconds.

[0011] In one embodiment, the molecular weight of the sealing gas is smaller than that of the reactive gas, the sealing gas is introduced into the chamber from the bottom of the chamber where the semiconductor substrate is located, and the reactive gas is introduced into the chamber from the top of the chamber.

[0012] In one embodiment, after removing surface defects of the semiconductor substrate by vacuuming, the method includes: depositing a first thin film layer on the surface of the semiconductor substrate; etching the first thin film layer on the surface of the substrate and the surface of the photoresist layer in a horizontal direction, retaining the first thin film layer on the side of the photoresist layer; and removing the photoresist layer.

[0013] In one embodiment, the first thin film layer is silicon dioxide.

[0014] In one embodiment, a semiconductor substrate includes a substrate, M mask layers and a photoresist layer, wherein the M mask layers are formed between the substrate and the photoresist layer, and include a first mask layer to an Mth mask layer from top to bottom; after removing the photoresist layer, it also includes: etching the first mask layer using the first thin film layer as a mask; and removing the first thin film layer.

[0015] In one embodiment, after removing the first thin film layer, the method further includes: depositing a second thin film layer on the surface of the semiconductor substrate; horizontally etching the second thin film layer on the surface of the first mask layer, retaining the second thin film layer on the side of the first mask layer; and removing the first mask layer.

[0016] According to some embodiments, the second side of the present application provides a semiconductor device, including: a substrate, and a photoresist layer formed on the substrate; the photoresist layer is trimmed by plasma etching in a chamber by introducing a reactive gas and a sealing gas, and during the plasma etching trimming process, the sealing gas flow rate is reduced.

[0017] In one embodiment, it further includes: a first thin film layer, wherein the first thin film layer is formed on a side of the photoresist layer.

[0018] In one embodiment, it further includes: M mask layers, which are formed between the substrate and the photoresist layer, and include a first mask layer to an Mth mask layer in sequence from top to bottom.

[0019] The disclosed embodiments may / at least have the following advantages: when performing etching and trimming of the photoresist layer, by reducing the sealing gas flow rate, adjusting the distribution of the reaction gas during the plasma etching process, and then adjusting the key dimension uniformity parameters of the edge area of ​​the processed semiconductor substrate, the technical problem of poor key dimension uniformity is alleviated. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic flow chart of a semiconductor substrate processing method according to an embodiment of the present application;

[0021] FIG. 2( a) to FIG. 2( e) are schematic diagrams of a semiconductor substrate processing process according to an embodiment of the present application;

[0022] FIG. 3( a )-FIG 3( b ) exemplarily show schematic diagrams of distribution of critical dimensions of a semiconductor substrate after surface treatment at different sealing gas flow rates;

[0023] 4(a) to 4(c) are schematic diagrams of another semiconductor substrate processing process according to an embodiment of the present application;

[0024] Figure 5 It is a logic diagram of semiconductor substrate processing according to an embodiment of the present application;

[0025] Figure 6 This is a schematic diagram of a semiconductor device according to an embodiment of the present application;

[0026] Figure 7 is another schematic diagram of a semiconductor device according to an embodiment of the present application;

[0027] Figure 8 This is another schematic diagram of a semiconductor device according to an embodiment of the present application.

[0028] Reference numerals:

[0029] 10: substrate; 20: photoresist layer; 30: first thin film layer; 40: second mask layer; 50: first mask layer; 100: semiconductor substrate; 101: reaction gas; 102: sealing gas. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with specific implementations and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present application. In addition, in the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concepts of the present application.

[0031] The accompanying drawings show schematic diagrams of layer structures according to embodiments of the present application. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clarity. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0032] Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application. The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0033] Figure 1 It is a schematic flow chart of a semiconductor substrate processing method according to an embodiment of the present application.

[0034] like Figure 1 As shown, the semiconductor substrate processing method provided in the embodiment of the present application mainly includes two steps, and the two steps are described in detail below.

[0035] Step S1, setting plasma etching power to trim the photoresist layer. Specifically, providing a semiconductor substrate, the semiconductor substrate comprising a substrate 10 and a photoresist layer 20 formed on the substrate; setting plasma etching power, introducing reaction gas and sealing gas into a chamber where the semiconductor substrate is located to trim the photoresist layer 20.

[0036] Figures 2(a) to 2(e) are schematic diagrams of a semiconductor substrate processing process according to an embodiment of the present application. Figure 2(a) is a schematic diagram of a semiconductor substrate structure; Figure 2(b) is a schematic diagram of Figure 2(a) after the photoresist layer 20 is trimmed in situ; Figure 2(c) is a schematic diagram of Figure 2(b) after the first thin film layer 30 is deposited; Figure 2(d) is a schematic diagram of Figure 2(c) after the first thin film layer 30 is etched in the horizontal direction; and Figure 2(e) is a schematic diagram of Figure 2(d) after the photoresist layer is removed.

[0037] Referring to FIG. 2( a ), the semiconductor substrate includes a substrate 10 and a photoresist layer 20 formed on the substrate. The photoresist layer is also called a photoresist or a photoresist, and is a material for exposure and development. For example, the photoresist layer 20 may be formed by patterning after spin coating a photoresist on the substrate 10, and the substrate 10 may be a wafer.

[0038] 2( b ), after the reaction gas and the sealing gas are introduced into the chamber where the semiconductor substrate is located, the plasma etching power is set to etch the photoresist layer 20 , that is, in-situ trimming.

[0039] It should be noted that the photoresist layer 20 is trimmed in this embodiment by plasma dry etching. This etching method can obtain both anisotropic and isotropic etching profiles, and is often used to obtain lines thinner than photolithography lines. On the other hand, since the lines produced by photolithography are prone to appear jagged, this method is also used to trim photoresist lines.

[0040] Step S2, adjusting the photoresist layer trimming control parameters. Specifically, reducing the sealing gas flow rate to improve the uniformity parameter of the critical dimension of the edge of the semiconductor substrate.

[0041] It should be noted that the uniformity parameter of the critical dimension of the edge of the semiconductor substrate is obtained based on the statistical parameter of the critical dimension. Exemplarily, the uniformity parameter is defined by the ratio of the variance to the average value in mathematical statistics.

[0042] The formula for the average value E is: E = (x 1 +x 2 +x 3 +...+x N ) / N. Where x 1 ...x N is the critical dimension of N points on the edge of the semiconductor substrate, and N is the number of selected points.

[0043] The formula for variance σ is:

[0044] The formula of the uniformity parameter U is: U = σ / E. The variance σ of the data indicates the degree of dispersion of the data. Therefore, the higher the uniformity parameter U is, the lower the uniformity is, and the lower the uniformity parameter U is, the higher the uniformity is.

[0045] The uniformity parameter U can also be obtained by other mathematical methods, such as fitting the critical dimension of the semiconductor substrate edge into a curve. From a qualitative perspective, the flatter the curve, the more uniform the critical dimension of the semiconductor substrate edge. From a quantitative analysis perspective, the closer the first-order derivative of each point of the curve is to 0, the more uniform the critical dimension of the semiconductor substrate edge is. The uniformity parameter U can be defined as the first-order derivative of the critical dimension of the semiconductor substrate edge.

[0046] It should be noted that the flow rate of the sealing gas can change the distribution of the reaction gas on the surface of the semiconductor substrate, thereby indirectly affecting the degree of etching of the critical dimension of the edge of the substrate. Reducing the sealing gas flow rate can increase the amount of reaction gas at the edge of the semiconductor substrate, thereby enhancing the degree of trimming at the edge. Exemplarily, a mapping relationship between the sealing gas flow rate and the uniformity parameter of the critical dimension of the edge of the semiconductor substrate can be set, and the two can be indexed to each other. According to the value of reducing the sealing gas flow rate, the uniformity parameter of the critical dimension of the edge of the semiconductor substrate can be indexed.

[0047] In some embodiments, in order to improve the uniformity parameters of the critical dimensions of the edge of the semiconductor substrate, the plasma etching power and / or the proportion of the reactive gas components can also be adjusted. The greater the plasma etching power, the greater the etching rate, but the uniformity of the etching will decrease. If the plasma etching power is too small, the etching rate is low. The ratio of various ions in the reactive gas component ratio will affect the etching rate, thereby indirectly affecting the etching degree of the critical dimensions of the edge of the semiconductor substrate. Therefore, at least one parameter of the plasma etching power and the reactive gas component ratio can change the uniformity parameters of the critical dimensions of the edge of the semiconductor substrate after etching. It should be noted that reducing the sealing gas flow combined with the plasma etching power and the reactive gas component ratio can achieve the technical effect of combining and adjusting the uniformity parameters of the critical dimensions of the edge of the semiconductor substrate. Exemplarily, the mapping relationship between the three parameters of reducing the value of the sealing gas flow, the plasma etching power, and the reactive gas component ratio and the uniformity parameter can be set, and the two can be indexed to each other. According to the sealing gas flow value, plasma etching power, and reactive gas component ratio reduced in the process, the uniformity parameters of the critical dimensions of the edge of the semiconductor substrate after etching can be indexed.

[0048] In some embodiments, the temperature of the semiconductor substrate is adjusted according to the temperature change of the semiconductor substrate and the set temperature threshold. It should be noted that if the temperature change of the semiconductor substrate is large, it will affect the processing of the semiconductor substrate. Exemplarily, the set temperature threshold includes a high temperature threshold and a low temperature threshold. If the temperature of the semiconductor substrate is higher than the high temperature threshold, the heating of the semiconductor substrate is stopped; correspondingly, if the temperature of the semiconductor substrate is lower than the low temperature threshold, the heating of the semiconductor substrate is started.

[0049] In some embodiments, the reaction gas contains oxygen, the sealing gas flow, the plasma etching power, and the proportion of oxygen in the reaction gas components are reduced, and the proportion of other gases in the reaction gas components other than oxygen is increased. When the proportion of oxygen in the reaction gas components is too large, the plasma etching rate is large, which will reduce the uniformity of the key dimensions of the edge of the semiconductor substrate after etching. Therefore, it is necessary to reduce the proportion of oxygen in the reaction gas components. Accordingly, the proportion of other gases in the reaction gas components other than oxygen needs to be increased to maintain the reaction gas pressure in the chamber where the semiconductor substrate is located. Exemplarily, the other gases other than oxygen can be nitrogen. It should be noted that the etching gas in the reaction gas, in addition to oxygen, can also be SF 6 CF 4 , Cl 2 , CHF 3 , O 2 For example, if the etching gas is Cl 2 , or by reducing Cl 2ratio, thereby controlling the plasma etching rate.

[0050] Reducing the sealing gas flow rate can enhance the degree of in-situ trimming of the semiconductor substrate edge, reduce the plasma etching power, that is, reduce the plasma etching rate, and improve the uniformity of the key dimensions of the semiconductor substrate edge after etching.

[0051] Exemplarily, the flow rate of the sealing gas is reduced from 1.6 slpm to 0.2 slpm, the plasma etching power is reduced from 40 W to 30 W, the flow rate of oxygen in the reaction gas component is reduced from 2.4 slpm to 2.2 slpm, and the flow rate of other gases in the reaction gas component except oxygen is increased from 0.2 slpm to 0.8 slpm, that is, the proportion of oxygen in the reaction gas component is reduced, and the proportion of other gases except oxygen is increased.

[0052] Figures 3(a) and 3(b) are schematic diagrams showing the distribution of key dimensions of semiconductor substrates after surface treatment at different sealing gas flow rates. Figure 3(a) shows the key dimensions of various positions of the semiconductor substrate when the sealing gas flow rate is 1.6 slpm, and Figure 3(b) shows the key dimensions of various positions of the semiconductor substrate when the sealing gas flow rate is 0.2 slpm. The sampling points of the data in Figures 3(a) and 3(b) are shown in Tables 1 and 2.

[0053] Table 1 Key dimensions of various locations on the semiconductor substrate when the sealing gas is 1.6 slpm

[0054] Position (unit: mm) 30 50 70 90 110 130 Critical size (unit: nm) 89.26087 89.45652 89.21739 89.41304 89.41304 89.86957

[0055] Table 2 Key dimensions of various locations on the semiconductor substrate when the sealing gas is 0.2 slpm

[0056] Position (unit: mm) 30 50 70 90 110 130 Critical size (unit: nm) 89.80435 89.6087 89.52174 89.47826 89.54348 89.32609

[0057] As shown in Figure 3(a) and Table 1, when the sealing gas flow rate is 1.6slpm and the radius of the semiconductor substrate is between 120mm and 150mm, the critical dimension curve has a large curvature, that is, the distribution of the critical dimension is uneven, ranging from 89.41304nm to 89.86957. Under this condition, the critical dimension average value E is: 89.4384058nm; the variance σ is: 0.211297439nm; the uniformity parameter U is: 0.002362491.

[0058] As shown in Figure 3(b) and Table 2, when the sealing gas flow rate is 0.2slpm, when the radius of the semiconductor substrate is between 120mm and 150mm, the curve of the critical dimension is flat relative to Figure 3(a). The distribution of the critical dimension is relatively uniform, ranging from 89.32609nm to 89.54348. Under this condition, the average value E of the critical dimension of the semiconductor substrate is: 89.54710145nm; the variance σ is: 0.143882099nm; the uniformity parameter U is: 0.001606776.

[0059] Therefore, after the sealing gas flow rate is reduced from 1.6 slpm to 0.2 slpm, the uniformity parameter changes from 0.002362491 to 0.001606776. Since the lower the uniformity parameter U is, the higher the uniformity is, the corresponding uniformity parameter U increases by 31.98%.

[0060] In some embodiments, after trimming the photoresist layer 20, the process includes: introducing an inert gas to the surface of the semiconductor substrate, and removing surface defects of the semiconductor substrate by vacuuming. For example, introducing an inert gas argon (Ar) to purge and remove surface defects of the semiconductor substrate, and vacuuming and removing them by vacuuming with a vacuum pump.

[0061] In some embodiments, the time for removing defects on the surface of the semiconductor substrate by exhausting gas is adjusted according to the sealing gas flow rate. For example, when the sealing gas flow rate decreases, the defects on the surface of the semiconductor substrate increase, so it is necessary to increase the time for removing defects on the surface of the semiconductor substrate by exhausting gas.

[0062] In some embodiments, the time for vacuuming to remove surface defects of the semiconductor substrate is 5-10 seconds.

[0063] In some embodiments, the molecular weight of the sealing gas is less than the molecular weight of the reactive gas, the sealing gas is introduced into the chamber from the lower part of the chamber where the semiconductor substrate is located, and the reactive gas is introduced into the chamber from the upper part of the chamber. Exemplarily, helium is selected as the sealing gas, and oxygen and nitrogen are selected as the reactive gas, and the molecular weight of helium is lower than that of oxygen and nitrogen. Therefore, when the sealing gas is introduced into the chamber from the lower part of the chamber where the semiconductor substrate is located, the sealing gas moves toward the upper part of the chamber. The reactive gas is introduced into the chamber from the upper part of the chamber, and under the pressure of the sealing gas moving upward, the reactive gas is distributed on the surface of the semiconductor substrate.

[0064] In some embodiments, after removing surface defects of the semiconductor substrate by vacuuming, the following steps include: depositing a first thin film layer 30 on the surface of the semiconductor substrate; horizontally etching the first thin film layer 30 on the surface of the substrate 10 and the surface of the photoresist layer 20, retaining the first thin film layer 30 on the side of the photoresist layer; and removing the photoresist layer 20.

[0065] Referring to FIG. 2(c), illustratively, the first thin film layer 30 can be formed by an ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced Atomic Layer Deposition) process. For example, for the PEALD process, a compound of silicon and hydrogen is first introduced into a semiconductor substrate, and then plasma is introduced to react with the compound of silicon and hydrogen to deposit and form the first thin film layer 30. It should be noted that ALD or PEALD has higher control accuracy than conventional deposition processes such as metal organic chemical vapor deposition, molecular beam epitaxy and physical vapor deposition, and the thickness of the first thin film layer 30 deposited can be accurately controlled by controlling the number of reaction cycles.

[0066] In some embodiments, the first film layer 30 is silicon dioxide. Exemplarily, a precursor, a plasma containing oxygen ions, is introduced into the surface of the semiconductor substrate, and the precursor is a compound of silicon and hydrogen. The plasma containing oxygen ions reacts with the compound of silicon and hydrogen to generate silicon dioxide.

[0067] 2( d ), the first thin film layer 30 is etched in the horizontal direction to retain the first thin film layer on the side of the photoresist layer. Exemplarily, the first thin film layer 30 is anisotropically etched by plasma dry etching.

[0068] The photoresist layer 20 is removed by dry or wet etching. Referring to FIG2(e), after the photoresist layer 20 is removed, the number of lines on the surface of the substrate 10 changes from 3 in FIG2(a) to 6, achieving thinning of the lines and increasing the number of lines.

[0069] Figures 4(a) to 4(c) are schematic diagrams of another semiconductor substrate processing process according to an embodiment of the present application. Figure 4(a) is a schematic diagram of another semiconductor substrate structure; Figure 4(b) is a schematic diagram of Figure 4(a) after the photoresist layer 20 is trimmed in situ, the first thin film layer 30 is deposited, the first thin film layer 30 in the horizontal direction is etched, and the photoresist layer is removed; Figure 4(c) is a schematic diagram of Figure 4(b) after the first mask layer 50 is etched using the first thin film layer 30 as a mask.

[0070] In some embodiments, the semiconductor substrate includes a substrate 10, M mask layers and a photoresist layer 20, the M mask layers are formed between the substrate 10 and the photoresist layer 20, and include a first mask layer to an Mth mask layer from top to bottom; after removing the photoresist layer 20, it also includes: etching the first mask layer using the first thin film layer as a mask 30; and removing the first thin film layer 30.

[0071] Referring to FIG. 4(a), illustratively, the M mask layers are the second mask layer 40 and the first mask layer 50, and the first mask layer 50 is the topmost mask layer among the M mask layers. The photoresist layer 20 in FIG. 4(a) is trimmed in situ, and then the first thin film layer 30 is deposited, and then the first thin film layer 30 in the horizontal direction is etched, and then the photoresist layer is removed, and these processes are shown in FIG. 2(b) to FIG. 2(e). In FIG. 4(c), the first mask layer 50 is etched using the first thin film layer 30 as a mask, and the first mask layer 50 has the same pattern as the first thin film layer 30.

[0072] In one embodiment, on the basis of FIG. 4(c), a second thin film layer can be deposited. The second thin film layer can be the same material as the first thin film layer 30. The second thin film layer on the surface of the first mask layer 50 is etched horizontally, and the second thin film layer on the side of the first mask layer 50 is retained; the first mask layer 50 is removed. At this time, the number of lines of the second thin film layer will become 12, which is doubled compared to the 6 lines in FIG. 2(e). When etching in this way, each time a mask in the M mask layers is removed, the number of lines generated will double, and the width of the lines will gradually narrow. The mask in the M mask layers can be a hard mask, which is processed by a plasma etching process.

[0073] Figure 5 It is a logic diagram of semiconductor substrate processing according to an embodiment of the present application.

[0074] refer to Figure 5 , the semiconductor substrate 100 is placed in the chamber, the reaction gas 101 and the sealing gas 102 enter the chamber, and when the plasma etching power is set, the reaction gas 101 etches the photoresist layer 20 on the surface of the semiconductor substrate 100. When the flow rate of the sealing gas 102 is large, the pressure of the sealing gas 102 is also large, because in the static pressure system, the flow rate of the gas is proportional to the pressure. Figure 5 When the pressure of the sealing gas 102 is high, the sealing gas 102 will compress the distribution of the reaction gas 101 on the surface of the semiconductor substrate 100, so that the reaction gas 101 in the middle part of the surface of the semiconductor substrate 100 is more, while the reaction gas 101 in the edge part is less, thereby causing the uniformity of the key dimension of the edge of the semiconductor substrate 100 to be low. Therefore, the flow rate of the sealing gas 102 can be reduced, thereby reducing the compression of the reaction gas 101 by the sealing gas 102, so that the gas volume of the reaction gas 101 at the edge of the semiconductor substrate 100 increases, thereby alleviating the technical problem of the low uniformity of the key dimension of the edge of the semiconductor substrate 100 after the photoresist layer 20 is etched and trimmed.

[0075] It should be noted that when the component ratio in the reaction gas 101 changes, it is necessary to ensure that the pressure of the reaction gas 101 does not decrease. Otherwise, if the pressure of the reaction gas 101 decreases, even if the sealing gas 102 reduces the pressure, the compression of the reaction gas 101 by the sealing gas 102 will not be alleviated, nor will the technical problem of the small amount of reaction gas 101 at the edge of the semiconductor substrate 100 be alleviated. Exemplarily, the flow rate of the sealing gas is reduced from 1.6slpm to 0.2slpm, the flow rate of oxygen in the reaction gas 101 component is reduced from 2.4slpm to 2.2slpm, and the flow rate of nitrogen in the reaction gas component is increased from 0.2slpm to 0.8slpm. If only the flow rate of oxygen in the reaction gas 101 component is reduced, the pressure of the reaction gas 101 will be reduced. The relative molecular weight of nitrogen is 28, and the relative molecular weight of oxygen is 32, and the relative molecular weights are close. According to the ideal gas equation, when the flow rates of the two are the same, the pressures generated are also similar. When the flow rate of oxygen in the reaction gas 101 components is reduced by 0.2 slpm, the flow rate of nitrogen is increased by 0.6 slpm, so the pressure of the reaction gas 101 will not decrease but increase.

[0076] Figure 6 This is a schematic diagram of a semiconductor device according to an embodiment of the present application.

[0077] refer to Figure 6 , the semiconductor device includes: a substrate 10, and a photoresist layer 20 formed on the substrate 10; the photoresist layer 20 is trimmed by plasma etching in a chamber by introducing a reactive gas and a sealing gas, and during the plasma etching trimming process, the sealing gas flow rate is reduced. It should be noted that reducing the sealing gas flow rate increases the amount of reactive gas at the edge of the semiconductor device, thereby improving the uniformity of the key dimensions at the edge of the semiconductor device. Exemplarily, the substrate 10 can be a wafer.

[0078] Figure 7 This is another schematic diagram of a semiconductor device according to an embodiment of the present application.

[0079] refer to Figure 7 The semiconductor device may further include a first thin film layer 30, which is formed on the side of the photoresist layer 20. The first thin film layer 30 may be formed by an ALD or PEALD process, and illustratively, the first thin film layer 30 is silicon dioxide. The first thin film layer 30 may be first deposited on the surface of the substrate 10 and the photoresist layer 20, and then the first thin film layer 30 on the surface of the substrate 10 and the surface of the photoresist layer 20 may be etched in a horizontal direction by anisotropic dry etching, and the first thin film layer 30 on the side of the photoresist layer may be retained.

[0080] Figure 8 This is another schematic diagram of a semiconductor device according to an embodiment of the present application.

[0081] The semiconductor device may further include: M mask layers, the M mask layers are formed between the substrate and the photoresist layer, and include a first mask layer to an Mth mask layer in order from top to bottom. Figure 8 , the M mask layers are the second mask layer 40 and the first mask layer 50, and the first mask layer 50 is the uppermost mask layer among the M mask layers. Exemplarily, the M mask layers are all hard mask layers, which can be formed by a deposition process.

[0082] It should be understood that the above specific embodiments of the present application are only used to illustrate or explain the principles of the present application, and do not constitute a limitation to the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present application should be included in the protection scope of the present application. In addition, the claims attached to the present application are intended to cover all changes and modifications that fall within the scope and boundaries of the attached claims, or the equivalent forms of such scope and boundaries.

Claims

1. A semiconductor substrate processing method, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a photoresist layer formed on the substrate; Setting the plasma etching power, and introducing the reaction gas and the sealing gas into the chamber where the semiconductor substrate is located to trim the photoresist layer; Reducing the sealing gas flow rate to improve the uniformity parameter of the critical dimension of the edge of the semiconductor substrate; Adjusting the plasma etching power and / or the ratio of reaction gas components; The reaction gas contains oxygen, and the step of adjusting the plasma etching power and / or the ratio of reaction gas components includes: The sealing gas flow rate, plasma etching power, and the proportion of oxygen in the reaction gas components are reduced, and the proportion of other gases in the reaction gas components except oxygen is increased.

2. The processing method according to claim 1, characterized in that: Also includes: The temperature of the semiconductor substrate is adjusted according to the temperature change of the semiconductor substrate and the set temperature threshold.

3. The processing method according to claim 1, characterized in that: After trimming the photoresist layer, it includes: Inert gas is introduced into the surface of the semiconductor substrate, and the surface defects of the semiconductor substrate are removed by vacuuming.

4. The processing method according to claim 3, characterized in that: The time for the vacuuming to remove surface defects of the semiconductor substrate is adjusted according to the sealing gas flow rate.

5. The processing method according to claim 4, characterized in that: The time for vacuuming to remove surface defects of the semiconductor substrate is 5-10S.

6. The processing method according to claim 1, characterized in that: The molecular weight of the sealing gas is smaller than that of the reaction gas. The sealing gas is introduced into the chamber from the lower part of the chamber where the semiconductor substrate is located, and the reaction gas is introduced into the chamber from the upper part of the chamber.

7. The processing method according to claim 3, characterized in that: After the surface defects of the semiconductor substrate are removed by vacuuming, the method includes: Depositing a first thin film layer on the surface of the semiconductor substrate; Etching the first thin film layer on the surface of the substrate and the surface of the photoresist layer in a horizontal direction, and retaining the first thin film layer on the side of the photoresist layer; The photoresist layer is removed.

8. The processing method according to claim 7, characterized in that: The first thin film layer is silicon dioxide.

9. The processing method according to claim 7, characterized in that: The semiconductor substrate comprises a substrate, M mask layers and a photoresist layer, wherein the M mask layers are formed between the substrate and the photoresist layer and sequentially comprise a first mask layer to an Mth mask layer from top to bottom; After removing the photoresist layer, the method further comprises: Using the first thin film layer as a mask, etching the first mask layer; The first film layer is removed.

10. The processing method according to claim 9, characterized in that: After removing the first film layer, the method further comprises: Depositing a second thin film layer on the surface of the semiconductor substrate; Etching the second thin film layer on the surface of the first mask layer in a horizontal direction, and retaining the second thin film layer on the side of the first mask layer; The first mask layer is removed.

11. A semiconductor device, characterized in that: include: A substrate, and a photoresist layer formed on the substrate; The photoresist layer is trimmed by plasma etching in a chamber by introducing a reactive gas and a sealing gas, and during the plasma etching trimming process, the flow rate of the sealing gas is reduced, and the plasma etching power and / or the proportion of reactive gas components are adjusted; The reaction gas contains oxygen, and the step of adjusting the plasma etching power and / or the ratio of reaction gas components includes: The sealing gas flow rate, plasma etching power, and the proportion of oxygen in the reaction gas components are reduced, and the proportion of other gases in the reaction gas components except oxygen is increased.

12. The semiconductor device according to claim 11, characterized in that Also includes: A first thin film layer is formed on a side of the photoresist layer.

13. The semiconductor device according to claim 11, characterized in that It also includes: M mask layers, which are formed between the substrate and the photoresist layer and include a first mask layer to an Mth mask layer in sequence from top to bottom.

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