A unidirectional transient voltage suppression diode and a manufacturing process thereof

Abstract

The application discloses a unidirectional transient suppression diode and a process. The diode comprises a substrate of a first conductive type, a first injection region and a second injection region of a second conductive type; the first injection region is arranged on the front surface of the substrate, and the second injection region is arranged on the back surface of the substrate; a pn junction formed between the second injection region and the substrate has a smaller junction depth than a pn junction formed between the first injection region and the substrate. A barrier layer and an insulating layer are sequentially arranged on the front surface of the substrate from bottom to top; the first injection region is led out by a first metal to form a first electrode; the insulating layer is arranged between the barrier layer and a first metal layer; the second injection region on the back surface and the substrate are led out by a second metal to form a second electrode, so that the second injection region on the back surface and the substrate are short-circuited; the first conductive type is different from the second conductive type; and the application improves the ability of negative surge.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, in particular to a unidirectional transient voltage suppression diode and a preparation process thereof. BACKGROUND

[0002] Surge refers to the transient overvoltage on the electrical equipment exceeding the normal working voltage, and the transient energy of the surge is huge enough to damage the circuit. TVS (Transient Voltage Suppression Diode) is a commonly used surge protection device, which can effectively protect the circuit.

[0003] With the increasing complexity of application environment, the circuit has higher and higher requirements for surge protection capability. In order to improve the surge capability, the area of the protection device can be increased, but the cost will be increased. With the increasing integration, the area of the surge protection device is getting smaller and smaller. Therefore, it is particularly important to improve the surge capability without increasing the area.

[0004] At the same time, the reliability of TVS is extremely susceptible to charge. The instability of breakdown voltage can cause many problems in practical application. Therefore, it is also very important to improve the reliability of TVS and ensure the stability of its breakdown voltage to ensure that the device can work normally for a long time. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide an ultra-low capacitance ESD protection device and a preparation method thereof. The embodiments of the present application can improve the surge protection capability of unidirectional TVS and the reliability of TVS.

[0006] In a first aspect, the embodiments of the present application provide a unidirectional transient voltage suppression diode, characterized in that it comprises a substrate of a first conductive type, a first implantation region and a second implantation region of a second conductive type.

[0007] The first implantation region is arranged on the front surface of the substrate, and the second implantation region is arranged on the back surface of the substrate, wherein the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate.

[0008] A barrier layer and an insulating layer are sequentially arranged on the front surface of the substrate from bottom to top; the first implantation region draws out a first electrode through a first metal layer, the insulating layer is arranged between the barrier layer and the first metal layer, and the back surface second implantation region and the substrate draw out a second electrode through a second metal layer, so that the back surface second implantation region and the substrate of the substrate are short-circuited, and the first conductive type is different from the second conductive type.

[0009] Compared with the prior art, the embodiment of the first aspect provides the following advantages: by arranging the insulating layer between the barrier layer and the first metal layer, and by arranging the pn junction between the second implantation region and the substrate to have a smaller junction depth than the pn junction between the first implantation region and the substrate, the insulating layer is used to shield the electric charges, thereby ensuring that the breakdown voltage of the diode is not affected, and the junction depth of the second implantation region on the back surface of the substrate is relatively small, thereby improving the ability of the diode to withstand negative surges.

[0010] In the second aspect, the embodiment of the present application provides another unidirectional transient suppression diode, which is characterized by comprising a substrate of a first conduction type, a first implantation region and a second implantation region of a second conduction type, and a trench.

[0011] The first implantation region is arranged on the front surface of the substrate, and the second implantation region is arranged on the back surface of the substrate, wherein the pn junction between the second implantation region and the substrate has a smaller junction depth than the pn junction between the first implantation region and the substrate.

[0012] The trench covers the first implantation region, the insulating layer is grown on the groove wall of the trench, the depth of the trench is greater than the junction depth of the pn junction between the first implantation region and the substrate, the first implantation region is led out by the first metal to form the first electrode, the second implantation region on the back surface and the substrate are led out by the second metal to form the second electrode, the second implantation region on the back surface and the substrate are short-circuited, and the first conduction type is different from the second conduction type.

[0013] Compared with the prior art, the embodiment of the second aspect provides the following advantages: by arranging the trench around the first implantation region, growing the insulating layer on the groove wall of the trench, and arranging the pn junction between the second implantation region and the substrate to have a smaller junction depth than the pn junction between the first implantation region and the substrate, the trench is used to shield the electric charges, thereby ensuring that the breakdown voltage of the diode is not affected, and the junction depth of the second implantation region on the back surface of the substrate is relatively small, thereby improving the ability of the diode to withstand negative surges.

[0014] In the third aspect, the embodiment of the present application provides a preparation process of a unidirectional transient suppression diode, which is used to prepare the diode of the first aspect, and the preparation process comprises the following steps.

[0015] Forming a barrier layer on the substrate of the first conduction type.

[0016] Forming the first implantation region on the front surface of the substrate and forming the second implantation region on the back surface in sequence, the first implantation region and the second implantation region have the first conduction type, the pn junction between the second implantation region and the substrate has a smaller junction depth than the pn junction between the first implantation region and the substrate, and the first conduction type is different from the second conduction type.

[0017] Forming a second implantation region on the back surface of the substrate, the first implantation region and the second implantation region have a second conductivity type, a junction depth of a pn junction formed between the second implantation region and the substrate is smaller than a junction depth of a pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type are different;

[0018] Forming an insulating layer above the blocking layer on the front surface of the substrate;

[0019] Leading out a first electrode through a first metal at the first implantation region, the insulating layer is arranged between the blocking layer and the first metal layer, leading out a second electrode through a second metal at the second implantation region and the substrate, so that the second implantation region on the back surface of the substrate and the substrate are short-circuited.

[0020] Compared with the prior art, the beneficial effects of the embodiments of the third aspect are the same as those of the unidirectional transient suppression diode provided by the embodiments of the first aspect of the application.

[0021] In the fourth aspect, the embodiments of the application provide a preparation process of a unidirectional transient suppression diode, characterized in that the preparation process is used for preparing the diode of the second aspect, and the preparation process comprises,

[0022] Forming a first implantation region on the front surface of the substrate;

[0023] Forming a trench on the front surface of the substrate, forming an isolation layer in the trench, the trench covering the first implantation region, and the depth of the trench being greater than the junction depth of the pn junction formed between the first implantation region and the substrate;

[0024] Forming a second implantation region on the back surface of the substrate, the first implantation region and the second implantation region have a first conductivity type, a junction depth of a pn junction formed between the second implantation region and the substrate is smaller than a junction depth of a pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type are different;

[0025] Leading out a first electrode through a first metal at the first implantation region, leading out a second electrode through a second metal at the second implantation region and the substrate, so that the second implantation region on the back surface of the substrate and the substrate are short-circuited.

[0026] Compared with the prior art, the beneficial effects of the unidirectional transient suppression diode provided by the fourth aspect are the same as those of the technical solutions provided by the second aspect, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0027] Non-limiting and non-exhaustive embodiments of the application are described by way of example with reference to the following drawings, in which:

[0028] Figure 1 And Figure 6 are structural schematic diagrams of two unidirectional transient suppression diodes in the prior art;

[0029] Figures 2-5 Fig. 1 shows a schematic diagram of a diode structure according to an embodiment of the present application; Figure 1 Fig. 2 shows a schematic diagram of a diode structure according to an embodiment of the present application;

[0030] Figures 7-10 Fig. 3 shows a schematic diagram of a diode structure according to an embodiment of the present application; Figure 2 Fig. 4 shows a schematic diagram of a diode structure according to an embodiment of the present application;

[0031] Figure 11 Fig. 5 shows a flow chart of a manufacturing process of an embodiment of the present application; Figures 2 to 5 Fig. 6 shows a flow chart of a manufacturing process of an embodiment of the present application.

[0032] Figure 12 Fig. 7 shows a flow chart of a manufacturing process of an embodiment of the present application. Figures 7 to 10 DETAILED DESCRIPTION

[0033] In order to make the above and other features and advantages of the present application more comprehensible, the present application will be further described below with reference to the drawings. It should be understood that the specific embodiments given herein are intended for illustrative purposes only and are not intended to limit the present application.

[0034] In order to make the above and other features and advantages of the present application more comprehensible, the present application will be further described below with reference to the drawings. It should be understood that the specific embodiments given herein are intended for illustrative purposes only and are not intended to limit the present application.

[0035] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present specification and the above drawings are intended to distinguish similar objects and not to describe a particular order or sequence. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the present application described herein can be carried out in other sequences than those illustrated or described herein. Moreover, the terms "comprising", "having", and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or apparatus that comprises a list of steps or units not necessarily limited to those specifically listed, but can include other not expressly listed or inherent to such process, method, product, or apparatus.

[0036] As shown in Fig. 1, Fig. 2, Fig. 3, and Fig. 4, the prior art unidirectional transient suppression diode structure is shown in the following specific structure: Figure 1 Figure 1 As shown in Fig. 1, Fig. 2, Fig. 3, and Fig. 4, the prior art unidirectional transient suppression diode structure is shown in the following specific structure: Figure 1

[0037] ​​​The front surface and the back surface of the substrate 11 are made to have the same junction depth of the injection area 12 and 13 in sequence, and the injection area 13 of the back surface is connected with the substrate 11 through the metal 16, so that the injection area 13 of the back surface of the substrate 11 is short-circuited with the substrate 11, the injection area 12 of the front surface of the substrate 11 is connected with the metal 15, and the injection area 12 of the front surface of the substrate 11 is separated from the substrate 11 by the barrier layer 14 which is silicon dioxide, the injection area 12 of the front surface and the injection area 13 of the back surface of the substrate 11 have the same conductive type, the conductive type of the injection area 12 and the injection area 13 is different from the conductive type of the substrate 12, wherein the substrate 11 can be P type, the injection area 12 and the injection area 13 are both N type, and the junction depth of the pn junction between the injection area 12 of the front surface of the substrate 11 and the substrate 11 is the same as the junction depth of the pn junction between the injection area 13 of the back surface and the substrate 11. In the prior art, the charge on the barrier layer 14 easily affects the breakdown voltage of the device, and the negative surge is only protected by the forward pn junction formed by the substrate 11 and the injection area 12 of the front surface of the substrate 11, so the anti-surge ability is weak. In the prior art, there is only one barrier layer 14 between the injection area 12 of the front surface and the metal layer 15. In the process of producing the chip, the interface of the barrier layer 14 is easy to generate charge, and the charge will form an electric field, which changes the depletion region of the pn junction, thereby causing the breakdown voltage to drift. The negative surge refers to the surge of current from the back surface of the substrate 11 to the front surface. From the back surface of the substrate 11 to the front surface, there are two paths, path one is from the substrate 11 to the injection area 12 of the front surface; path two is from the injection area 13 of the back surface to the substrate 11 to the injection area 12 of the front surface. In the prior art, the pn junction formed between the injection area 13 of the back surface and the substrate 11 is a high-voltage reverse-biased junction, so path two is difficult to conduct, and the current can only be discharged through path one, so the conduction area is small, the heat is large, and the anti-surge ability is weak.

[0038] Therefore, in order to solve the problems of the prior art Figure 1 structure, the applicant solves the problems in the prior art through the following specific embodiments.

[0039] Embodiment 1

[0040] As Figure 2 shown, the embodiment of the application provides a unidirectional transient suppression diode, which comprises a substrate 21 of a first conductive type, a first injection area 22 and a second injection area 23 of a second conductive type.

[0041] The first injection region 22 is arranged on the front surface of the substrate 21, and the second injection region 23 is arranged on the back surface of the substrate 21, wherein the junction depth of the pn junction formed between the second injection region 23 and the substrate 21 is smaller than the junction depth of the pn junction formed between the first injection region 22 and the substrate 21, and the blocking layer 24 and the insulating layer 27 are arranged on the front surface of the substrate 21 in sequence from bottom to top; the first injection region 22 leads out the first electrode through the first metal layer 25, the insulating layer 27 is arranged between the blocking layer 24 and the first metal layer 25, the back surface second injection region 23 and the substrate 21 lead out the second electrode through the second metal layer 26 respectively, so that the back surface second injection region 23 of the substrate 21 and the substrate 21 are short-circuited, the first conductive type and the second conductive type are different, and in the embodiment of the application, the first injection region 22 and the second injection region 23 are both heavily doped.

[0042] In the embodiment of the application, the first conductive type is P type, the second conductive type is N type, an NPN structure is formed, in another embodiment, the first conductive type can be N type, the second conductive type is P type, a PNP structure is formed, and the blocking layer 24 is silicon dioxide, which plays a role of isolation and blocking; the insulating layer 27 is phosphorus-doped silicon dioxide, and the role of the insulating layer 27 is to prevent short circuit, the breakdown voltage of the diode device is affected by charge, there are many unsaturated dangling bonds in the phosphorus-doped silicon dioxide, and these dangling bonds can play a role of electric field shielding.

[0043] In the embodiment of the application, the width of the second injection region 23 is greater than the width of the first injection region 22, which is mainly considered to adjust the positive and negative surge capacity, the wider the back surface second injection region 23 is, the stronger the positive surge capacity is, and the weaker the negative surge is. The back surface second injection region 23 is wider than the front surface first injection region 22, which can effectively adjust the positive and negative surge capacity.

[0044] Embodiment 2

[0045] On the basis of the embodiment 1, as Figure 3As shown, the unidirectional transient suppression diode provided by the embodiment of the present application further comprises a third implantation region 31 of the second conductivity type, and the width of the second implantation region 23 is greater than that of the third implantation region 31. The reason why the back second implantation region 23 is wider than the front first implantation region 22 is that the back second implantation region 23 is an electron emission region, and the number of emitted electrons is related to the area. The greater the area, the more electrons are emitted, and the stronger the current carrying capacity. In the embodiment of the present application, the junction depth of the pn junction formed between the third implantation region 31 and the substrate 21 is greater than the junction depth of the pn junction formed between the first implantation region 22 and the substrate 21. The second implantation region 23 is heavily doped. In the embodiment of the present application, the first conductivity type is P type, and the second conductivity type is N type. If the substrate 21 is P type, the third implantation region 31 is N type. If the substrate 21 is N type, the third implantation region 31 is P type. In another embodiment, the first conductivity type can be N type, and the second conductivity type can be P type. In the embodiment of the present application, the third implantation region 31 shortens the base length of the front first implantation region 22-substrate 21-back second implantation region 23, thereby improving the current amplification factor and the maximum current carrying capacity.

[0046] In the embodiment of the present application, the width of the second implantation region 23 is greater than that of the first implantation region 22. This is mainly to consider the adjustment of positive and negative surge capacity. The wider the back second implantation region 23, the stronger the positive surge capacity and the weaker the negative surge.

[0047] Embodiment 3

[0048] Based on the embodiment 3, as shown, Figure 4 The unidirectional transient suppression diode provided by the embodiment of the present application further comprises a fourth implantation region 42 of the first conductivity type and / or a fifth implantation region 41 of the second conductivity type. The fifth implantation region 41 covers the first implantation region 22, and the fifth implantation region 41 is spaced apart from the first implantation region 22 by a predetermined distance. The surface depletion region boundary can be extended smoothly only by spacing apart by a predetermined distance. The fourth implantation region 42 covers the second implantation region 23, and the fourth implantation region 42 is in contact with the second implantation region 23. The fourth implantation region 42 is in contact with the back second implantation region 23 of the substrate to form a pn junction between the fourth implantation region 42 and the back second implantation region 23 of the substrate. Otherwise, a pn junction will be formed between the substrate 21 and the back second implantation region 23 of the substrate.

[0049] In the embodiment of the present application, the unidirectional transient suppression diode provided by the embodiment of the present application can only comprise the fourth implantation region 42 of the first conductivity type or the fifth implantation region 41 of the second conductivity type.

[0050] In this embodiment, if the substrate 21 is P type, the fourth implant region 42 is P type, the fifth implant region 41 is N type, the fourth implant region 42 is P type and the fifth implant region 41 is N type are heavily doped.

[0051] In this embodiment, the fifth implant region 41 can make the first implant region 22 on the front side of the substrate and the pn junction formed by the substrate 21 more gentle relative to the depletion region edge of embodiments 2 and 3, making it easier for breakdown to occur inside rather than on the surface, where there is charge, and if the breakdown occurs on the surface, the breakdown voltage will be affected.

[0052] The fourth implant region 42 is highly doped, and the P region and the N region of the pn junction formed between the fourth implant region 42 and the fifth implant region 41 are both highly doped, so it is very easy to occur Zener breakdown, and the breakdown voltage is very low. When a negative surge occurs, the path of the substrate back side fourth implant region 42-substrate 21-substrate front side first implant region 21 is more likely to conduct to make current flow.

[0053] Embodiment 4

[0054] Embodiment 4 is based on embodiment 3, as Figure 5 The third implant region is a plurality of evenly spaced segmented implant regions 31-1.

[0055] It should be noted that the third implant region 31 in embodiment 2 can also be a plurality of spaced segmented implant regions, and at the same time, the fifth implant region 41 can make the first implant region 22 on the front side of the substrate and the pn junction formed by the substrate 21 more gentle relative to the depletion region edge of embodiments 2 and 3.

[0056] In this embodiment, when a negative surge occurs, the path of the substrate back side second implant region 23-substrate 21-substrate front side first implant region 22 will more evenly open the current flow, the current will be more evenly distributed, and the conduction area will be larger, rather than concentrated on the left and right ends.

[0057] Embodiment 5

[0058] As Figure 6As shown, on substrate 61, implantation regions 62 and 63 with the same junction depth are successively formed on the front and back sides of substrate 61, respectively. The implantation region 63 on the back side is connected to substrate 61 through metal 66, so that the implantation region 63 on the back side of substrate 61 is short-circuited with substrate 61. The implantation region 62 on the front side of substrate 61 is connected to metal 65. The conductivity types of the implantation regions 62 on the front side and 63 on the back side of substrate 61 are the same, while the conductivity types of the implantation regions 62 and 63 are different from those of substrate 61. A trench 67 is formed on substrate 61, and the trench 67 covers the first implantation region 62. An isolation layer 64 is grown on the trench wall of trench 67. The isolation layer 64 is silicon dioxide. On the one hand, the isolation layer 64 isolates metal 65 from substrate 61, otherwise a short circuit will occur (i.e., the current direction is from the front metal 65-substrate 61-back metal 66). On the other hand, it can isolate the side of the pn junction formed by the first implantation region 62 on the front side of substrate and substrate 61 from the external environment, preventing the pn junction from being affected by the external environment. In this embodiment, the substrate 61 can be P-type, and both the injection region 62 and the injection region 63 are N-type. The junction depth of the pn junction between the front injection region 62 and the substrate 61 is the same as that between the back injection region 63 and the substrate 61. The negative surge is only protected by the positive pn junction formed by the substrate 61 and the injection region 62 on the front of the substrate 61. Its surge protection capability is weak. In order to solve the problems in the prior art, the technical solution of the embodiment of this application is proposed.

[0059] like Figure 7 As shown, in Embodiment 5, which differs from Embodiment 1, a trench 77 is provided in the substrate 71. The trench 77 covers the first injection region 72, and an isolation layer 74 is grown on the trench wall. The depth of the trench 77 is greater than the junction depth of the pn junction formed between the first injection region 72 and the substrate 71. The first injection region 72 is located on the front side of the substrate 71, and the second injection region 73 is located on the back side of the substrate 71. The junction depth of the pn junction formed between the second injection region 72 and the substrate 71 is less than the junction depth of the pn junction formed between the first injection region 72 and the substrate 71. The first injection region 72 leads out a first electrode through a first metal, and the second injection region on the back side and the substrate respectively lead out a second electrode through a second metal, so that the second injection region on the back side of the substrate and the substrate are short-circuited, and the first conductivity type and the second conductivity type are different.

[0060] In this embodiment, the width of the second injection area 73 is greater than the width of the first injection area 72. This is mainly to consider the allocation of positive and negative surge capabilities. The wider the second injection area 73 on the back, the stronger the positive surge capability and the weaker the negative surge capability. The second injection area 73 on the back is wider than the first injection area 72 on the front, which can effectively allocate positive and negative surge capabilities.

[0061] Example 6

[0062] Based on Example 7, such as Figure 8As shown, the diode provided by the embodiment of the present application further comprises a third implantation region 81 of the second conductivity type, the width of the second implantation region 73 is greater than that of the third implantation region 81, and the junction depth of the pn junction formed between the third implantation region 81 and the substrate 71 is greater than that of the pn junction formed between the first implantation region 72 and the substrate 71, the second implantation region 73 is heavily doped, in the embodiment of the present application, if the substrate 71 is of P type, the third implantation region 81 is of N type, and if the substrate 71 is of N type, the third implantation region 81 is of P type, in the embodiment of the present application, the first conductivity type is P type, and the second conductivity type is N type, in another embodiment, the first conductivity type can be N type, and the second conductivity type is P type. In the embodiment of the present application, the third implantation region 81 shortens the base region length of the front first implantation region 72-substrate 71-back second implantation region 73, and improves the current amplification factor, thereby improving the maximum current carrying capacity.

[0063] In the embodiment of the present application, the width of the second implantation region 73 is greater than that of the first implantation region 72. This is mainly to consider the adjustment of positive and negative surge capacity, the wider the back second implantation region 73, the stronger the positive surge capacity, and the weaker the negative surge. The back second implantation region 73 is wider than the front first implantation region 72, which can effectively adjust the positive and negative surge capacity.

[0064] Embodiment 7

[0065] On the basis of embodiment 8, as shown in Figure 9 The diode further comprises a fourth implantation region 91 of the second conductivity type; the fourth implantation region 91 covers the second implantation region 73, the fourth implantation region 91 is in contact with the second implantation region 73, and the fourth implantation region 91 is a pn junction that is prone to Zener breakdown, and this pn junction is the junction between the fourth implantation region 91 and the back second implantation region 73, so that it is easier to conduct current.

[0066] Embodiment 8

[0067] On the basis of embodiment 9, as shown in Figure 10 The third implantation region 81 is a plurality of uniformly spaced segmented implantation regions 81-1.

[0068] It should be noted that the third implantation region 81 in embodiment 6 can also be a plurality of spaced segmented implantation regions.

[0069] In the embodiment of the present application, when a negative surge occurs, the path of the back second implantation region 73 of the substrate-substrate 71-front first implantation region 72 of the substrate will more evenly open the current to flow, and the current is not concentrated at the left and right ends as shown in Figure 9 .

[0070] As shown in Figure 11As shown, the embodiment of the application also provides a preparation process of the unidirectional transient suppression diode, and the process is used for preparing the unidirectional transient suppression diode described in Embodiments 1 to 4.

[0071] The process specifically includes:

[0072] Step S11, forming a barrier layer on a substrate of a first conductivity type;

[0073] Step S12, sequentially forming a first implantation region on a front surface of the substrate and a second implantation region on a back surface of the substrate, the first implantation region and the second implantation region being of the first conductivity type, a pn junction formed between the second implantation region and the substrate having a junction depth smaller than a junction depth of a pn junction formed between the first implantation region and the substrate, the first conductivity type being different from a second conductivity type;

[0074] Step S13, forming an insulating layer above the barrier layer on the front surface of the substrate;

[0075] Step S14, leading out a first electrode through a first metal layer at the first implantation region, the insulating layer being arranged between the barrier layer and the first metal layer, leading out a second electrode through a second metal layer at the second implantation region and the substrate, so that the second implantation region on the back surface of the substrate and the substrate are short-circuited.

[0076] It should be noted that the first oxidation is performed on the substrate first to form the barrier layer; the first implantation region pattern is photoetched on the front surface, impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the first implantation region on the front surface of the substrate; then the second implantation region on the back surface of the substrate is photoetched, impurity implantation or pre-diffusion is performed, and then activation is performed through short-time high temperature to form the second implantation region on the back surface of the substrate, and then an insulating layer is grown on the front surface of the substrate; finally, contact holes of corresponding sizes are etched on the front surface and the back surface of the substrate, metal is deposited, and the metal is etched to form the final device, and the diode structure described in Embodiment 1 can be prepared according to Steps S11 to S14.

[0077] Before the second implantation region is formed in Step S12, the process further includes,

[0078] Step S16, forming a third implantation region of the second conductivity type on the back surface of the substrate, the third implantation region having a width smaller than a width of the second implantation region, and a pn junction formed between the third implantation region and the substrate having a junction depth greater than a junction depth of the pn junction formed between the first implantation region and the substrate.

[0079] It should be noted that for the first and second implantation regions of the front and back surfaces of the substrate, the photoetching and ion implantation can be performed simultaneously, that is, the front surface and the back surface of the substrate are simultaneously photoetched to form the first implantation region of the front surface and the third implantation region of the back surface, impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the first implantation region of the front surface and the third implantation region of the back surface. Then, photoetching of the second implantation region of the back surface is performed, impurity implantation or pre-diffusion is performed, and then activation is performed by high temperature for a short time to form the second implantation region of the back surface. According to steps S11 to S14 and step S15, the diode structure shown in Example 2 can be obtained.

[0080] This step can also be performed after the first implantation region of the front surface of the substrate is formed, then the third implantation region is formed, and then the second implantation region is formed. Figure 11 In the embodiment, only one process mode of the third implantation region is shown, that is, the first implantation region and the third implantation region are formed simultaneously.

[0081] If the third implantation region is a plurality of segmented implantation regions arranged at intervals when photoetching is performed, according to steps S11 to S14 and step S15, the diode structure shown in Example 4 can be obtained.

[0082] In step S12, the second implantation region is formed, and the process further includes,

[0083] A fourth implantation region of the first conductive type is formed on the back surface of the substrate, wherein the fourth implantation region covers the second implantation region, and the fourth implantation region is in contact with the second implantation region.

[0084] Figure 11 In the embodiment, only one process mode of the third implantation region is shown, that is, the second implantation region and the fourth implantation region are formed simultaneously.

[0085] It should be noted that when the second implantation region is photoetched, the fourth implantation region of the back surface of the substrate is also photoetched, and then impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the fourth implantation region of the back surface of the substrate. The fourth implantation region can also be formed before the second implantation region is formed in the embodiment.

[0086] Before step S12, the process further includes,

[0087] A fifth implantation region of the first conductive type is formed on the front surface of the substrate, wherein the fifth implantation region covers the first implantation region, and the fifth implantation region is spaced apart from the first implantation region by a preset distance. According to steps S11 to S14 and step S16, the diode structure described in Example 3 can be prepared.

[0088] It should be noted that, when the first implantation region is formed, the fifth implantation region on the front surface of the substrate is also photoetched, and then impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the fifth implantation region on the back surface of the substrate, so that the process steps can be saved and the cost can be reduced; the fifth implantation region can also be made before the second implantation region, and the fifth implantation region is made before the second implantation region on the back surface to prevent the high-temperature diffusion of the fifth implantation region from affecting the depth of the back surface implantation region, Figure 11 The third implantation region is only shown in the process mode, that is, the first implantation region and the fifth implantation region are simultaneously made.

[0089] As Figure 12 shown, the embodiment of the present application also provides a preparation process of a unidirectional transient suppression diode, the preparation process comprises,

[0090] In step S21, a first implantation region is formed on the front surface of the substrate in sequence;

[0091] In step S22, a trench is formed on the substrate, and an isolation layer is grown in the trench, the trench covers the first implantation region, and the depth of the trench is greater than the junction depth of the pn junction formed between the first implantation region and the substrate;

[0092] In step S23, a second implantation region is formed on the back surface of the substrate, the first implantation region and the second implantation region have a first conductivity type, the junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate, and the first conductivity type and the second conductivity type are different;

[0093] In step S24, a first electrode is led out from the first implantation region through a first metal, and a second electrode is led out from the second implantation region and the substrate through a second metal, so that the second implantation region on the back surface of the substrate and the substrate are short-circuited.

[0094] It should be noted that the pattern of the first implantation region is photoetched on the front surface, impurity implantation or pre-diffusion is performed on the first implantation region, and then high-temperature diffusion is performed to form the first implantation region on the front surface of the substrate, and then a trench is dry-etched or wet-etched; then the second implantation region on the back surface of the substrate is photoetched, impurity implantation or pre-diffusion is performed, and then activation is performed through short-time high-temperature to form the second implantation region on the back surface of the substrate, and finally a contact hole with a corresponding size is etched on the front surface and the back surface of the substrate, metal is deposited, and the metal is etched to form the final device, and the diode structure described in Embodiment 5 can be prepared according to steps S21 to S24.

[0095] Before the second implantation region is formed in step S23, the process further comprises,

[0096] Step S25, forming a third implantation region of the second conductivity type on the back surface of the substrate, the width of the third implantation region is smaller than the width of the second implantation region, and the depth of the pn junction formed between the third implantation region and the substrate is greater than the depth of the pn junction formed between the first implantation region and the substrate.

[0097] It should be noted that for the first implantation region and the second implantation region on the front surface and the back surface of the substrate, the photolithography and ion implantation can be performed simultaneously, that is, the first implantation region on the front surface and the third implantation region on the back surface of the substrate are simultaneously photolithographed, impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the first implantation region on the front surface of the substrate and the third implantation region on the back surface of the substrate. Then, the second implantation region on the back surface of the substrate is photolithographed, impurity implantation or pre-diffusion is performed, and then activation is performed by high temperature for a short time to form the second implantation region on the back surface. According to steps S21 to S24 and step S25, the diode structure shown in Example 6 can be prepared.

[0098] This step can also be performed after the first implantation region on the front surface of the substrate is completed, then the third implantation region is performed, and then the second implantation region is performed. Figure 12 In the embodiment, only one process mode of the third implantation region is shown, that is, the third implantation region is performed simultaneously with the first implantation region.

[0099] If the third implantation region is a plurality of segmented implantation regions uniformly spaced when photolithography is performed, the diode structure shown in Example 8 can be obtained according to steps S21 to S24 and step S25.

[0100] In step S23, the process further includes,

[0101] forming a fourth implantation region of the first conductivity type on the back surface of the substrate, wherein the fourth implantation region covers the second implantation region, and the fourth implantation region is in contact with the second implantation region.

[0102] Figure 12 In the embodiment, only one process mode of the third implantation region is shown, that is, the second implantation region and the fourth implantation region are performed simultaneously.

[0103] It should be noted that the fourth implantation region is also photolithographed on the back surface of the substrate at the same time when the second implantation region is photolithographed, and then impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the fourth implantation region on the back surface of the substrate. The fourth implantation region can also be formed before the second implantation region is formed in the embodiments of the present application.

[0104] It should be noted that the fourth implantation region can also be formed before the second implantation region is formed, the fourth implantation region on the back surface of the substrate is first photolithographed, then impurity implantation or pre-diffusion is performed, and then high-temperature diffusion is performed to form the fourth implantation region on the back surface of the substrate. According to steps S21 to S24 and step S26, the diode structure shown in Example 7 can be prepared.

[0105] The various technical features of the above embodiments can be combined in any combination, and the description as to each technical feature in the above embodiments is not exhaustive of all possible combinations thereof. It is to be understood that the scope of the present description is not limited to the above embodiments.

[0106] Although the present application has been described in connection with the embodiments thereof, it will be understood that the description as to the above embodiments is merely illustrative in nature and is in no way limiting, with the true scope of the present application being indicated by the appended claims, along with the full range of equivalents to which such claims are entitled. It is appreciated that variations to the foregoing embodiments can become apparent to those skilled in the art upon reading this description.

Claims

1. A unidirectional transient suppression diode, characterized in that, Includes a substrate of a first conductivity type, and a first implantation region and a second implantation region of a second conductivity type; The first implantation region is disposed on the front side of the substrate, and the second implantation region is disposed on the back side of the substrate. The junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate. A barrier layer and an insulating layer are sequentially disposed from bottom to top on the front surface of the substrate; a first electrode is led out from the first metal in the first implantation region; an insulating layer is disposed between the barrier layer and the first metal layer; a second electrode is led out from the back side second implantation region and the substrate respectively through a second metal, so that the back side second implantation region and the substrate are short-circuited; the first conductivity type and the second conductivity type are different. The diode also includes a third injection region of a second conductivity type; The width of the second injection region is greater than the width of the third injection region, and the junction depth of the pn junction formed between the third injection region and the substrate is greater than the junction depth of the pn junction formed between the first injection region and the substrate.

2. The unidirectional transient suppression diode as described in claim 1, characterized in that, The third injection zone is a segmented injection zone with multiple intervals.

3. A unidirectional transient suppression diode as described in any one of claims 1 to 2, characterized in that, The diode also includes a fourth injection region of a first conductivity type and / or a fifth injection region of a second conductivity type; The fourth injection region covers the second injection region, and the fourth injection region is in contact with the second injection region; The fifth injection area covers the first injection area, and the fifth injection area is separated from the first injection area by a preset distance.

4. A unidirectional transient suppression diode as described in claim 3, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

5. A unidirectional transient suppression diode as described in any one of claims 1 to 2 and 4, characterized in that, The barrier layer is made of silicon dioxide, and the insulating layer is made of phosphorus-doped silicon dioxide.

6. A unidirectional transient suppression diode, characterized in that, Includes a substrate of a first conductivity type, a first implantation region and a second implantation region of a second conductivity type, and a trench; The first implantation region is disposed on the front side of the substrate, and the second implantation region is disposed on the back side of the substrate. The junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate. The trench covers the first injection region, and an isolation layer is grown on the trench wall. The depth of the trench is greater than the junction depth of the pn junction formed between the first injection region and the substrate. The first injection region leads out the first electrode through the first metal, and the second injection region on the back side and the substrate lead out the second electrode through the second metal, so that the second injection region on the back side of the substrate and the substrate are short-circuited, and the first conductivity type and the second conductivity type are different. The diode also includes a third injection region of a second conductivity type; The width of the second injection region is greater than the width of the third injection region, and the junction depth of the pn junction formed between the third injection region and the substrate is greater than the junction depth of the pn junction formed between the first injection region and the substrate.

7. A unidirectional transient suppression diode as described in claim 6, characterized in that, The third injection zone is a segmented injection zone with multiple intervals.

8. A unidirectional transient suppression diode as described in claim 6 or 7, characterized in that, The diode also includes a fourth injection region of the first conductivity type; The fourth injection region covers the second injection region, and the fourth injection region is in contact with the second injection region.

9. A unidirectional transient suppression diode as described in claim 8, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

10. A fabrication process for a unidirectional transient suppression diode, characterized in that, The fabrication process is used to fabricate the diode as described in any one of claims 1 to 5, and the fabrication process includes, A barrier layer is formed on a substrate of the first conductivity type; A first implantation region is formed on the front side of the substrate and a second implantation region is formed on the back side. The first and second implantation regions have a first conductivity type. The junction depth of the pn junction formed between the second implantation region and the substrate is smaller than the junction depth of the pn junction formed between the first implantation region and the substrate. The first conductivity type and the second conductivity type are different. An insulating layer is formed above the front barrier layer of the substrate; A first electrode is led out through a first metal in the first implantation region, and an insulating layer is disposed between the barrier layer and the first metal layer. A second electrode is led out through a second metal in the second implantation region and the substrate, so that the second implantation region on the back side of the substrate and the substrate are short-circuited.

11. The fabrication process of a unidirectional transient suppression diode as described in claim 10, characterized in that, Before forming the second implantation region on the back side of the substrate, the fabrication process includes, A third injection region of a second conductivity type is formed on the back side of the substrate. The width of the second injection region is greater than the width of the third injection region, and the junction depth of the pn junction formed between the third injection region and the substrate is greater than the junction depth of the pn junction formed between the first injection region and the substrate.

12. The fabrication process of a unidirectional transient suppression diode as described in claim 10 or 11, characterized in that, Before forming the second implantation region on the back side of the substrate, the fabrication process further includes, A fourth implantation region of a first conductivity type is formed on the back side of the substrate, wherein the fourth implantation region covers the second implantation region and is in contact with the second implantation region.

13. The fabrication process of a unidirectional transient suppression diode as described in claim 11, characterized in that, Before forming the second implantation region on the back side of the substrate, the fabrication process further includes, A fifth implantation region of a first conductivity type is formed on the front side of the substrate, wherein the fifth implantation region covers the first implantation region and the fifth implantation region is spaced apart from the first implantation region by a predetermined distance.

14. A fabrication process for a unidirectional transient suppression diode, characterized in that, The fabrication process is used to fabricate the diode according to any one of claims 6 to 9, and the fabrication process includes, A first implantation region is formed on the front side of the substrate; A trench is formed on the substrate, and an isolation layer is grown in the trench. The trench covers the first injection region, and the depth of the trench is greater than the junction depth of the pn junction formed between the first injection region and the substrate. A second implantation region is formed on the back side of the substrate. The first and second implantation regions have a first conductivity type. The junction depth of the pn junction formed between the second implantation region and the substrate is smaller than that of the pn junction formed between the first implantation region and the substrate. The first conductivity type and the second conductivity type are different. A first electrode is led out through a first metal in the first implantation region, and a second electrode is led out through a second metal in the second implantation region and the substrate, so that the second implantation region on the back side of the substrate and the substrate are short-circuited.

15. The fabrication process of a unidirectional transient suppression diode as described in claim 14, characterized in that, Before forming the second implantation region on the back side of the substrate, the fabrication process further includes, A third injection region of a second conductivity type is formed on the back side of the substrate. The width of the second injection region is greater than the width of the third injection region, and the junction depth of the pn junction formed between the third injection region and the substrate is greater than the junction depth of the pn junction formed between the first injection region and the substrate.

16. The fabrication process of a unidirectional transient suppression diode as described in claim 15, characterized in that, Before forming the second implantation region on the back side of the substrate, the process further includes, A fourth implantation region of a first conductivity type is formed on the back side of the substrate, wherein the fourth implantation region covers the second implantation region and is in contact with the second implantation region.

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