Layout Design Method for Edge Cells in a Standard Cell Library

Abstract

The present invention discloses a layout design method for the edge cells of a standard cell library, which includes the following steps: Step 1, determine the basic parameters of the edge cells according to the basic parameters of the corresponding standard cell library and the minimum design rules in the design rule file provided by the foundry; Step 2, design the edge cells according to the basic parameters of the edge cells and the layout design rules. Specifically, there are six types of edge cells, namely the first edge cell, the second edge cell, the third edge cell, the fourth edge cell, the fifth edge cell, and the sixth edge cell; Step 3, when the digital backend designs the layout of the edge cells, reasonably insert the edge cells along the outer edge of the IP module, so as to achieve P-well isolation. The present invention optimizes the design and development process of the standard cell library, can realize the horizontal splicing of standard cells of different device types, and improves the backend design efficiency of digital circuits.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a layout design method for the edge cells of a standard cell library. Background Art

[0002] The FDSOI (Fully Depleted - Silicon - On - Insulator) process is a method of fabricating integrated circuits that uses a silicon, insulator, silicon substrate structure to significantly reduce the parasitic capacitance of devices and improve device performance. Under the FDSOI process, the performance of devices can be adjusted by changing the P / N well potential. To isolate the P - Well and achieve the potential adjustment of the P - Well to prevent it from failing due to conduction with the substrate, an N - Well guard - ring 102 needs to be added around the IP module 101, as Figure 1 shown. Since the size of the guard - ring is related to the size of the IP module, corresponding guard - rings need to be customized for different IP modules. Summary of the Invention

[0003] In view of the above - mentioned situation, in order to overcome the defects of the prior art, the present invention provides a layout design method for the edge cells of a standard cell library.

[0004] The present invention solves the above - mentioned technical problems through the following technical solutions: A layout design method for the edge cells of a standard cell library, characterized in that it includes the following steps:

[0005] Step 1: Determine the basic parameters of the edge cells according to the basic parameters of the corresponding standard cell library and the minimum design rules in the design rule file provided by the foundry.

[0006] Step 2: Design the edge cells according to the basic parameters of the edge cells and the layout design rules. There are six types of edge cells, namely the first edge cell, the second edge cell, the third edge cell, the fourth edge cell, the fifth edge cell, and the sixth edge cell.

[0007] Step 3: When the digital backend designs the layout of the edge cells, reasonably insert the edge cells along the outer edge of the IP module to achieve P - Well isolation.

[0008] Preferably, the basic parameters of the standard cell library include: the height of the first cell, the width of the first power bus, the width of the first ground bus, the horizontal wiring pitch of the first Poly, the first P / N region demarcation line, the first N - Well boundary line; the basic parameters of the edge cells include: the height of the second cell, the width of the second power bus, the width of the second ground bus, the horizontal wiring pitch of the second Poly, the second P / N region demarcation line, the second N - Well boundary line.

[0009] Preferably, the height of the second unit is the same as the relative height of all standard cells in the corresponding standard cell library.

[0010] Preferably, the width of the second power supply bus is the same as the width of the first power supply bus of all standard cells in the corresponding standard cell library, and the width of the second ground bus is the same as the width of the first ground bus of all cells in the corresponding standard cell library.

[0011] Preferably, the second Poly horizontal routing pitch is the center line distance between two adjacent Polys, which is determined by the design rules of the process platform.

[0012] Preferably, the second P / N region boundary line is the boundary position between the PMOS region and the NMOS region of the edge cell. The position of the second P / N region boundary line is the same as the relative position of all standard cells in the corresponding standard cell library, and the relative position is the position relative to the origin.

[0013] Preferably, the second N-well side line is the center line distance between two adjacent N-well side lines.

[0014] The positive and progressive effects of the present invention are as follows: The present invention optimizes the design and development process of the standard cell library, can realize the horizontal splicing of standard cells of different device types, and improves the back-end design efficiency of digital circuits. Description of the Drawings

[0015] Figure 1 It is a schematic structural diagram of adding an N-well protection ring to the periphery of the IP module in the prior art.

[0016] Figure 2A As for Figure 2F It is a schematic structural diagram of six edge cells of the present invention.

[0017] Figure 3 It is a schematic layout diagram of the edge cell in the present invention.

[0018] Figure 4 It is a schematic layout diagram of the first edge cell in the present invention.

[0019] Figure 5 It is a schematic layout diagram of the second edge cell in the present invention.

[0020] Figure 6 It is a schematic layout diagram of the third edge cell in the present invention.

[0021] Figure 7 It is a schematic layout diagram of the fourth edge cell in the present invention.

[0022] Figure 8 It is a schematic layout diagram of the fifth edge cell in the present invention.

[0023] Figure 9 It is a layout schematic diagram of the sixth edge unit in the present invention. Specific implementation manners

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0025] The layout design method of the edge unit of the standard cell library of the present invention includes the following steps:

[0026] Step 1, determine the basic parameters of the edge unit according to the basic parameters of the corresponding standard cell library and the minimum design rules in the design rule file provided by the foundry;

[0027] Step 2, design the edge unit according to the basic parameters of the edge unit and the layout design rules. There are specifically six edge units, such as Figure 2A to Figure 2F shown, which are the first edge unit 1, the second edge unit 2, the third edge unit 3, the fourth edge unit 4, the fifth edge unit 5, and the sixth edge unit 6 respectively;

[0028] Step 3, when the digital backend designs the layout of the edge unit, reasonably insert the edge unit along the outer edge of the IP module 101 to achieve P-well isolation, as Figure 3 shown.

[0029] Among them, the basic parameters of the standard cell library include: the height of the first unit, the width of the first power bus, the width of the first ground bus, the horizontal wiring pitch of the first Poly, the first P / N region demarcation line, and the first N-well side line; the basic parameters of the edge unit include: the height of the second unit, the width of the second power bus, the width of the second ground bus, the horizontal wiring pitch of the second Poly, the second P / N region demarcation line, and the second N-well side line, which are convenient for correspondence.

[0030] The height of the second unit is the same as the relative height of all standard cells in the corresponding standard cell library, and the relative height is the height relative to the origin.

[0031] The width of the second power bus is the same as the width of the first power bus of all standard cells in the corresponding standard cell library, and the width of the second ground bus is the same as the width of the first ground bus of all cells in the corresponding standard cell library, which is convenient for supporting use.

[0032] The horizontal wiring pitch of the second Poly is the center line distance between two adjacent Polys (polycrystalline silicon), which is determined by the design rule of the process platform.

[0033] The second P / N region boundary line is the boundary position between the PMOS region and the NMOS region of the edge cell. The position of the second P / N region boundary line is the same as the relative position of all standard cells in the corresponding standard cell library, and the relative position is the position relative to the origin.

[0034] The second N-well edge line is the midline distance between two adjacent N-well edge lines, which is determined by the design rule of the process platform.

[0035] As Figure 4 shown, it can be seen from Figure 4 that in the layout of the first edge cell in the embodiment of the present invention, DeepN-Well (deep N-well) covers the entire edge cell, the PMOS region is covered by the N-Well layer, and the NMOS region is covered by the P-Well layer. The design rule restrictions shown in the figure refer to ensuring that the cell layout can pass the design rule check after automatic stitching according to the minimum design rule and half of the minimum rule provided by the foundry (collectively referred to as the total rule D). This embodiment is applicable to the upper edge and the lower edge of the IP module, and the inner side can be vertically stitched with the NMOS of the P substrate.

[0036] As Figure 5 shown, it can be seen from Figure 5 that in the layout of the second edge cell in the embodiment of the present invention, DeepN-Well covers the entire edge cell, the NMOS region is covered by the N-Well layer, and the PMOS region is covered by the P-Well layer. The design rule restrictions shown in the figure refer to ensuring that the cell layout can pass the design rule check after automatic stitching according to the minimum design rule and half of the minimum rule provided by the foundry. This embodiment is applicable to the upper edge and the lower edge of the IP module, and the inner side can be vertically stitched with the PMOS of the P substrate.

[0037] As Figure 6 shown, it can be seen from Figure 6 that in the layout of the third edge cell in the embodiment of the present invention, DeepN-Well covers the entire edge cell, the left half of the PMOS region and the NMOS region is covered by the N-Well layer, and the right half of the NMOS region is P-Well. The design rule restrictions shown in the figure refer to ensuring that the cell layout can pass the design rule check after automatic stitching according to the minimum design rule and half of the minimum rule provided by the foundry. This embodiment is applicable to the left and right edges of the IP module, and the inner side can be horizontally stitched with the standard cells of the NMOS of the P substrate and the PMOS of the N substrate; it can also be used as a corner boundary cell.

[0038] As Figure 7 shown, it can be seen from Figure 7As can be seen, in the layout of the fourth edge unit in the embodiment of the present invention, DeepN-Well covers the entire edge unit. The left half of the NMOS region and the PMOS region is covered by the N-Well layer, and the right half of the PMOS region is P-Well. The design rule limitations shown in the figure refer to ensuring that the cell layout can pass the design rule check after automatic stitching according to the minimum design rules provided by the foundry and half of the minimum rules. This embodiment is applicable to the left and right edges of the IP module, and can be horizontally stitched with standard cells of N-substrate NMOS and P-substrate PMOS on the inner side; it can also be used as a corner edge unit.

[0039] As Figure 8 shown, from Figure 8 As can be seen, in the layout of the fifth edge unit in the embodiment of the present invention, DeepN-Well covers the entire edge unit. Both the PMOS region and the NMOS region are covered by the N-Well layer. The design rule limitations shown in the figure refer to ensuring that the cell layout can pass the design rule check after automatic stitching according to the minimum design rules provided by the foundry and half of the minimum rules. This embodiment is applicable to the upper and lower edges of the module and can be vertically stitched with NMOS of N-substrate or PMOS of N-substrate; this embodiment is also applicable to the left and right edges of the IP module and can be horizontally stitched with standard cells of N-substrate NMOS and N-substrate PMOS; it can also be used as a corner edge unit.

[0040] As Figure 9 shown, from Figure 9 As can be seen, in the layout of the sixth edge unit in the embodiment of the present invention, DeepN-Well covers the entire edge unit. The left half of the PMOS region and the left half of the NMOS region are covered by the N-Well layer, and the right half of the PMOS region and the right half of the NMOS region are P-Well. The design rule limitations shown in the figure refer to ensuring that the cell layout can pass the design rule check after automatic stitching according to the minimum design rules provided by the foundry and half of the minimum rules. This embodiment is applicable to the left and right edges of the IP module, and the inner side can be horizontally stitched with standard cells of P-substrate NMOS and P-substrate PMOS.

[0041] Through the edge unit layout design method provided by the above embodiments, the layout height of the edge unit is consistent with the height of the corresponding standard unit. After horizontal and vertical mirroring, the inner side of the edge unit can be normally adjacent to the corresponding standard unit, realizing P-well isolation inside the entire module, optimizing the design and development process of the standard cell library, and improving the backend design efficiency of digital circuits.

[0042] The above specific embodiments are the preferred embodiments of the present invention and cannot limit the present invention. Any other changes or other equivalent replacement methods made without departing from the technical solution of the present invention are included in the protection scope of the present invention.

Claims

1. A layout design method for the edge cells of a standard cell library, characterized in that, it includes the following steps: Step 1, determine the basic parameters of the edge cells according to the basic parameters of the corresponding standard cell library and the minimum design rules in the design rule file provided by the foundry; Step 2, design the edge cells according to the basic parameters of the edge cells and the layout design rules. There are six specific edge cells, namely the first edge cell, the second edge cell, the third edge cell, the fourth edge cell, the fifth edge cell, and the sixth edge cell; In the layout of the first edge cell, Deep N-Well covers the entire edge cell, the PMOS region is covered by the N-Well layer, and the NMOS region is covered by the P-Well layer; In the layout of the second edge cell, Deep N-Well covers the entire edge cell, the NMOS region is covered by the N-Well layer, and the PMOS region is covered by the P-Well layer; In the layout of the third edge cell, Deep N-Well covers the entire edge cell, the left half of the PMOS region and the NMOS region is covered by the N-Well layer, and the right half of the NMOS region is P-Well; In the layout of the fourth edge cell, Deep N-Well covers the entire edge cell, the left half of the NMOS region and the PMOS region is covered by the N-Well layer, and the right half of the PMOS region is P-Well; In the layout of the fifth edge cell, Deep N-Well covers the entire edge cell, and both the PMOS region and the NMOS region are covered by the N-Well layer; In the layout of the sixth edge cell, Deep N-Well covers the entire edge cell, the left half of the PMOS region and the left half of the NMOS region are covered by the N-Well layer, and the right half of the PMOS region and the right half of the NMOS region are P-Well; Step 3, when the digital backend designs the layout of the edge cells, reasonably insert the edge cells along the outer edge of the IP module to achieve P-well isolation.

2. The layout design method for the edge cells of a standard cell library according to claim 1, characterized in that, the basic parameters of the standard cell library include: the first cell height, the first power bus width, the first ground bus width, the first Poly horizontal wiring pitch, the first P / N region demarcation line, the first N-well boundary line; the basic parameters of the edge cells include: the second cell height, the second power bus width, the second ground bus width, the second Poly horizontal wiring pitch, the second P / N region demarcation line, the second N-well boundary line.

3. The layout design method for the edge cells of a standard cell library according to claim 2, characterized in that, the second cell height is the same as the relative height of all standard cells in the corresponding standard cell library.

4. The layout design method for the edge cells of a standard cell library according to claim 2, characterized in that, The width of the second power supply bus is the same as the width of the first power supply bus of all standard cells in the corresponding standard cell library, and the width of the second ground bus is the same as the width of the first ground bus of all cells in the corresponding standard cell library.

5. The layout design method for the edge cells of the standard cell library as described in claim 2, characterized in that, The second Poly horizontal routing pitch is the center line distance between two adjacent Polys, which is determined by the design rules of the process platform.

6. The layout design method for the edge cells of the standard cell library as described in claim 2, characterized in that, The second P / N region boundary line is the boundary position between the PMOS region and the NMOS region of the edge cell, and the position of the second P / N region boundary line is the same as the relative position of all standard cells in the corresponding standard cell library, and the relative position is the position relative to the origin.

7. The layout design method for the edge cells of the standard cell library as described in claim 2, characterized in that, The second N-well edge line is the center line distance between two adjacent N-well edge lines.

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