A method for eliminating silicon residue in gate oxide layer buried process

Abstract

The present invention provides a method for eliminating silicon residue in a gate oxide layer buried process, which at least comprises: providing a substrate, forming a plurality of STIs on the substrate, wherein the regions between the STIs are respectively defined as a medium-voltage device region and a high-voltage device region, and forming a hard mask covering the medium-voltage device region, the high-voltage device region and the STI region on the substrate; etching in the medium-voltage device region and the high-voltage device region respectively to form silicon trenches of different depths; forming an etched silicon dioxide layer with a first thickness at the bottom of the silicon trench; isotropically etching the silicon trench region by utilizing a high selectivity of Si to SiO2 to remove silicon on the sidewall of the silicon trench near the STI region; and etching by utilizing a high selectivity of SiO2 to Si to remove an etch stop layer at the bottom of the trench region, thereby eliminating silicon residue in the gate oxide layer buried process, thereby achieving the purpose of suppressing the current tunneling effect of the gate oxide layer and greatly improving the reliability of the oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a method for eliminating silicon residues in a gate oxide layer burying process. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, the requirements for chip component density and integration continue to increase. This is especially true for system-on-chip (SoC) designs, which require the simultaneous integration of multiple circuits, including logic gates, static random access memory (SRAM), and input / output (I / O), on a single chip. These circuits rely on a variety of MOS (metal-oxide-semiconductor) transistors with different operating voltages to function. Taking the 28nm process node as an example, low-voltage (LV), medium-voltage (MV), and high-voltage (HV) devices must be integrated on the same chip. As the operating voltage of MOS transistors continues to increase, the thickness of the gate oxide layer must be increased to prevent breakdown. For devices operating at voltages of ~1V, ~10V, and ~20V, the gate oxide (GOX) thicknesses are ~10.5A, ~200A, and ~1100A, respectively. Therefore, in conventional manufacturing processes, there will be significant height differences between different regions formed by MOS transistors with different operating voltages. This height difference will create insurmountable difficulties in processes such as polysilicon gate lithography and etching, as well as chemical mechanical polishing (CMP) of the high-k metal gate (HKMG) and the first interlayer dielectric (ILD). Therefore, it is necessary to perform silicon trench etching in the regions with different operating voltages to achieve the purpose of burying gate oxide layers of different thicknesses, thereby maintaining the same height of the top surface of the gate oxide layer of MOS transistors with different operating voltages.

[0003] During the actual chip manufacturing process, when the silicon substrate trench is etched in the MV and HV regions, silicon residue will be formed at the junction of the active area (AA) and the shallow trench isolation (STI) due to the obstruction of the STI. Silicon residue will cause current flowing effect and greatly reduce the reliability of the oxide layer. In severe cases, it will directly lead to device failure. In the existing process, attempts are made to directly remove lateral silicon residues through isotropic etching. This process can eliminate lateral silicon residues to a certain extent, but it will also cause the bottom of the silicon trench to become curved. The curvature of the bottom of the silicon trench will greatly reduce the reliability of the final gate oxide layer. In the existing process, simple process parameter adjustment cannot achieve the formation of ideal silicon trenches. Therefore, eliminating silicon residues by improving the manufacturing process is crucial to improving device reliability. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for eliminating silicon residues in the gate oxide layer buried process, so as to solve the problem in the prior art that simple process parameter adjustment cannot achieve ideal silicon trench formation.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a method for eliminating silicon residues in a gate oxide layer buried process, comprising at least:

[0006] Step 1: providing a substrate, forming a plurality of STIs on the substrate, wherein the regions between the STIs are defined as a medium voltage device region and a high voltage device region, respectively, and forming a hard mask on the substrate covering the medium voltage device region, the high voltage device region and the STI region;

[0007] Step 2: etching the medium voltage device area and the high voltage device area respectively to form silicon trenches of different depths;

[0008] Step 3: forming an etched silicon dioxide layer having a first thickness at the bottom of the silicon trench;

[0009] Step 4: isotropically etching the silicon trench region using a high selectivity of Si to SiO2 to remove silicon from the sidewalls of the silicon trench near the STI region;

[0010] Step 5: Remove the silicon dioxide layer at the bottom of the trench region by etching with a high selectivity ratio of SiO2 to Si.

[0011] Preferably, the hard mask in step 1 is silicon nitride.

[0012] Preferably, in step three, oxygen gas is used as an ion source to form the silicon dioxide layer at the bottom of the silicon trench using plasma gas.

[0013] Preferably, the etching silicon dioxide layer having the first thickness in step three is determined by the gas flow rate and bias voltage of the plasma gas.

[0014] Preferably, in step 4, the silicon trench region is isotropically etched using a mixed plasma gas containing at least Cl 2 , NF 3 and He.

[0015] Preferably, the high selectivity ratio of Si to SiO2 in step 4 is greater than 10:1.

[0016] Preferably, the high selectivity of SiO2 to Si in step five is greater than 5:1.

[0017] As described above, the method of eliminating silicon residues in the gate oxide layer buried process of the present invention has the following beneficial effects:

[0018] By adding plasma in-situ oxidation to form an etch stop layer and an isotropic etching step of the silicon substrate with a high selectivity to silicon dioxide in the gate oxide layer buried process, silicon residue in the gate oxide layer buried process is eliminated, thereby achieving the purpose of suppressing the current tunneling effect of the gate oxide layer and greatly improving the reliability of the oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic flow chart of the method for eliminating silicon residues in the gate oxide layer buried process according to the present invention.

[0020] Figure 2 Shown is a schematic diagram of the structure of the substrate provided by the present invention after preliminary processing.

[0021] Figure 3 It is a schematic diagram showing the silicon trench formed according to the present invention.

[0022] Figure 4 It is a schematic diagram showing the present invention after an etch stop layer is formed at the bottom of the silicon trench.

[0023] Figure 5 A schematic diagram showing etching of Si blocked by STI according to the present invention is shown.

[0024] Figure 6 It is a schematic diagram showing the present invention after removing SiO2 from the bottom of the silicon trench.

[0025] Among them, 1-substrate, 2-STI, 3-hard mask, 4-silicon trench, 5-silicon dioxide layer. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.

[0027] See also Figure 1 The present invention provides a method for eliminating silicon residue in a gate oxide layer buried process, which at least comprises:

[0028] Step 1, see Figure 2 A substrate 1 is provided, and multiple STI2s are formed on the substrate 1. The areas between the STI2s are defined as a medium-voltage device area and a high-voltage device area, respectively. A hard mask 3 covering the medium-voltage device area, the high-voltage device area and the STI2 area is formed on the substrate 1; further, the hard mask 3 can be made of silicon nitride material.

[0029] Step 2, please refer to Figure 3 , respectively etching in the medium voltage device area and the high voltage device area to form silicon trenches 4 of different depths. Specifically, the hard mask 3 in different areas can be covered with photoresist, and the hard mask 3 in the target area is exposed by photolithography, and then the target area is etched by etching. Due to the setting of the selectivity, the photoresist has a protective effect on the mask layer in the non-processed area, so that silicon trenches 4 of a certain depth can be etched in the target area. The etching depth of different areas can be accurately controlled by a series of parameters such as etching time according to the actual process requirements;

[0030] Step 3, please refer to Figure 4 , forming an etched silicon dioxide layer 5 having a first thickness at the bottom of the silicon trench 4. Specifically, by adjusting process parameters such as the gas flow rate and bias voltage of the oxygen plasma gas, the silicon dioxide layer 5 of a certain thickness is oxidized at the bottom of the silicon trench 4. In the actual plasma gas oxidation process using oxygen as an ion source, the silicon remaining laterally below the STI 2 will inevitably be partially oxidized. Therefore, it is necessary to control the oxidation depth at the bottom of the trench to ensure a sufficient process window for subsequent processes;

[0031] Step 4, please refer to Figure 5 , utilizing the high selectivity of Si to SiO2 to isotropically etch the silicon trench 4 region, removing the silicon near the STI2 region on the sidewall of the silicon trench 4;

[0032] In one possible embodiment, a mixed plasma gas of Cl2, NF3 and He in a certain ratio is used, and by adjusting the process parameters (gas flow rate, bias voltage, etc.), high selectivity etching of Si relative to SiO2 can be achieved, wherein the high selectivity of Si relative to SiO2 is preferably Si:SiO2>10:1, so the amount of SiO2 etched in the vertical direction will be very small, and the etching will terminate on the surface of the silicon dioxide layer 5 at the bottom of the silicon trench 4, thereby achieving horizontal etching of the Si blocked by STI2, and ultimately eliminating Si residues.

[0033] Step 5, please refer to Figure 6 The silicon dioxide layer 5 at the bottom of the trench area is removed by etching using a high selectivity ratio of SiO2 to Si. The high selectivity ratio of SiO2 to Si is preferably greater than 5:1, which can remove the silicon dioxide layer 5 at the bottom of the silicon trench 4 and ultimately form a buried trench under the gate oxide layer without any Si residue.

[0034] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0035] In summary, the present invention eliminates silicon residue during the gate oxide embedding process by adding plasma oxidation to form an etch stop layer and an isotropic etching step of the silicon substrate with high selectivity to silicon dioxide. This suppresses the gate oxide current tunneling effect and significantly improves oxide layer reliability. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for eliminating silicon residue in a gate oxide layer buried process, characterized in that: At least: Step 1: providing a substrate, forming a plurality of STIs on the substrate, wherein the regions between the STIs are defined as a medium voltage device region and a high voltage device region, respectively, and forming a hard mask on the substrate covering the medium voltage device region, the high voltage device region and the STI region; Step 2: etching the medium voltage device area and the high voltage device area respectively to form silicon trenches of different depths; Step 3: Using oxygen as an ion source, plasma gas is used to oxidize the bottom of the silicon trench to form a silicon dioxide layer with a first thickness; Step 4: performing isotropic dry etching on the silicon trench using a high selectivity of Si to SiO2, using a mixed plasma gas containing at least Cl2, NF3, and He to remove silicon residues on the sidewalls of the silicon trench near the STI region; Step 5: Remove the silicon dioxide layer at the bottom of the silicon trench by etching with a high selectivity ratio of SiO2 to Si.

2. The method for eliminating silicon residue in a gate oxide layer buried process according to claim 1, wherein: The hard mask in step 1 is silicon nitride.

3. The method for eliminating silicon residue in a gate oxide layer buried process according to claim 1, wherein: The high selectivity of Si to SiO2 in step 4 is greater than 10:

1.

4. The method for eliminating silicon residue in a gate oxide layer buried process according to claim 1, wherein: The high selectivity of SiO2 to Si in step five is greater than 5:1.

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