High speed comparator system

Abstract

A high speed comparator system includes a comparator body. The comparator body includes a voltage input circuit, a regulated current source, a regulated resistance component, and a differential output circuit. The voltage input circuit can receive a first input voltage and a second input voltage and can couple a first control node and a second control node. The regulated current source can output a first current to the first control node and a second current to the second control node. The regulated resistance component can be coupled between the first control node and the second control node. The differential output circuit can couple the first control node and the second control node and can generate a first output voltage and a second output voltage.

Description

Technical Field

[0001] The present invention relates to a high-speed comparator system. Background Art

[0002] High-speed comparators are widely used in circuit modules such as digital voltage regulators and analog-to-digital converters to monitor input voltage differences and output digital levels. As the clock speeds of mobile devices continue to increase, the demand for faster response times for monitoring signals continues to rise, making the application prospects of high-speed comparators very promising. Therefore, it is necessary to propose a new solution to address the various shortcomings of traditional high-speed comparators. Summary of the Invention

[0003] In a preferred embodiment, the present invention provides a high-speed comparator system comprising a comparator body, a voltage regulator, a common-mode improvement circuit, an analog-to-digital converter, and a matching correction circuit. The comparator body includes: a voltage input circuit receiving a first input voltage and a second input voltage and coupled to a first control node and a second control node; a regulated current source outputting a first current to the first control node and a second current to the second control node; a regulated resistor element coupled between the first control node and the second control node; and a differential output circuit coupled to the first control node and the second control node to generate a first output voltage and a second output voltage.

[0004] Compared with conventional designs, the high-speed comparator system proposed in the present invention has at least the following advantages: (1) fast response speed, high accuracy, and simple structure; (2) insensitivity to process variations, such as power supply voltage and temperature fluctuations; (3) ability to monitor both high-speed and low-speed signal changes; (4) adjustable speed and power consumption; (5) adaptability to various application conditions without the need for repeated calibration; and (6) outputting comparison results to different voltage domains without significantly increasing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a schematic diagram of a high-speed comparator system 100 according to an embodiment of the present invention.

[0006] Figure 2 FIG. 2 is a schematic diagram of a comparator body 210 according to an embodiment of the present invention.

[0007] Figure 3 FIG. 3 is a schematic diagram of a high-speed comparator system 300 according to an embodiment of the present invention.

[0008] Figure 4 FIG. 1 is a schematic diagram of a voltage regulator 320 according to an embodiment of the present invention.

[0009] Figure 5FIG. 3 is a schematic diagram of a common-mode improvement circuit 330 according to an embodiment of the present invention.

[0010] Figure 6 FIG. 1 is a schematic diagram of an analog-to-digital converter 340 according to an embodiment of the present invention.

[0011] Figure 7 FIG. 3 is a schematic diagram of a matching correction circuit 350 according to an embodiment of the present invention.

[0012] Figure 8 FIG. 8 is a schematic diagram of a comparator body 810 according to an embodiment of the present invention.

[0013] Figure 9 FIG. 8 is a schematic diagram of a voltage regulator 820 according to an embodiment of the present invention.

[0014] Figure 10 FIG. 8 is a schematic diagram of a common-mode improvement circuit 830 according to an embodiment of the present invention.

[0015] Figure 11 FIG. 8 is a schematic diagram of an analog-to-digital converter 840 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to make the objects, features and advantages of the present invention more clearly understood, specific embodiments of the present invention are given below with reference to the accompanying drawings for detailed description.

[0017] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather based on differences in the functions of the components. The words "including" and "comprising" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly connected to the second device via other devices or connection means.

[0018] Figure 1 FIG. 1 is a schematic diagram of a high-speed comparator system 100 according to an embodiment of the present invention. Figure 1As shown, the high-speed comparator system 100 includes at least a comparator body 110 , which includes a voltage input circuit 112 , a regulated current source 114 , a regulated resistive element 116 , and a differential output circuit 118 .

[0019] Generally speaking, the voltage input circuit 112 can receive a first input voltage VIN and a second input voltage VREF, and can be coupled to a first control node NC1 and a second control node NC2, where the second input voltage VREF is a reference voltage. The regulated current source 114 can output a first current I1 to the first control node NC1 and a second current I2 to the second control node NC2. For example, the second current I2 can be substantially equal to the first current I1. The regulated resistor component 116 can be coupled between the first control node NC1 and the second control node NC2. The differential output circuit 118 can be coupled to the first control node NC1 and the second control node NC2, and can generate a differential first output voltage VOUT1 and a differential second output voltage VOUT2.

[0020] The following will introduce various detailed structures and variations of the high-speed comparator system 100. It should be understood that these drawings and descriptions are for illustrative purposes only and are not intended to limit the present invention.

[0021] Figure 2 FIG. 2 is a schematic diagram of a comparator body 210 according to an embodiment of the present invention. Figure 2 In the embodiment of the present invention, the comparator body 210 includes a voltage input circuit 212 , a voltage-stabilizing current source 214 , a voltage-stabilizing resistor component 216 , and a differential output circuit 218 .

[0022] The voltage input circuit 212 includes a first N-type transistor MN1, a second N-type transistor MN2, and a third N-type transistor MN3. For example, each N-type transistor in this specification may be an N-type metal oxide semiconductor field effect transistor, but is not limited thereto. The first N-type transistor MN1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first N-type transistor MN1 is used to receive a first input voltage VIN. The first terminal of the first N-type transistor MN1 is coupled to a first node N1, and the second terminal of the first N-type transistor MN1 is coupled to a first control node NC1. The second N-type transistor MN2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second N-type transistor MN2 is used to receive a second input voltage VREF. The first terminal of the second N-type transistor MN2 is coupled to the first node N1, and the second terminal of the second N-type transistor MN2 is coupled to a second control node NC2. The third N-type transistor MN3 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third N-type transistor MN3 is coupled to the first bias node NB1, the first terminal of the third N-type transistor MN3 is coupled to the ground voltage VSS (e.g., 0V), and the second terminal of the third N-type transistor MN3 is coupled to the first node N1.

[0023] The regulated current source 214 includes a first P-type transistor MP1 and a second P-type transistor MP2. For example, each P-type transistor in this specification may be a P-type metal oxide semiconductor field effect transistor, but is not limited thereto. The first P-type transistor MP1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first P-type transistor MP1 is coupled to the second bias node NB2, the first terminal of the first P-type transistor MP1 is coupled to the first supply voltage VDD1, and the second terminal of the first P-type transistor MP1 is coupled to the first control node NC1 to output the first current I1. The second P-type transistor MP2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second P-type transistor MP2 is coupled to the second bias node NB2, the first terminal of the second P-type transistor MP2 is coupled to the first supply voltage VDD1, and the second terminal of the second P-type transistor MP2 is coupled to the second control node NC2 to output the second current I2.

[0024] The voltage-stabilizing resistor component 216 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is coupled to the first control node NC1, and the second end of the first resistor R1 is coupled to the second node N2. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the second control node NC2, and the second end of the second resistor R2 is coupled to the second node N2. The first resistor R1 and the second resistor R2 can also be combined into a single resistor coupled between the first control node NC1 and the second control node NC2.

[0025] The differential output circuit 218 includes a first capacitor C1, a second capacitor C2, a third P-type transistor MP3, a fourth P-type transistor MP4, a fifth P-type transistor MP5, a sixth P-type transistor MP6, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, and a seventh N-type transistor MN7.

[0026] The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the first control node NC1, and the second terminal of the first capacitor C1 is coupled to the third node N3. The third P-type transistor MP3 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third P-type transistor MP3 is coupled to the third node N3, the first terminal of the third P-type transistor MP3 is coupled to the first control node NC1, and the second terminal of the third P-type transistor MP3 is coupled to the third node N3. The fourth N-type transistor MN4 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth N-type transistor MN4 is coupled to the third node N3, the first terminal of the fourth N-type transistor MN4 is coupled to the ground voltage VSS, and the second terminal of the fourth N-type transistor MN4 is coupled to the third node N3. The fourth P-type transistor MP4 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth P-type transistor MP4 is coupled to the fourth node N4, the first terminal of the fourth P-type transistor MP4 is coupled to the first control node NC1, and the second terminal of the fourth P-type transistor MP4 is coupled to the first output node NOUT1 to output the first output voltage VOUT1. The fifth N-type transistor MN5 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifth N-type transistor MN5 is coupled to the fourth node N4, the first terminal of the fifth N-type transistor MN5 is coupled to the ground voltage VSS, and the second terminal of the fifth N-type transistor MN5 is coupled to the first output node NOUT1.

[0027] The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the second control node NC2, and the second terminal of the second capacitor C2 is coupled to the fourth node N4. The fifth P-type transistor MP5 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth P-type transistor MP5 is coupled to the fourth node N4, the first terminal of the fifth P-type transistor MP5 is coupled to the second control node NC2, and the second terminal of the fifth P-type transistor MP5 is coupled to the fourth node N4. The sixth N-type transistor MN6 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth N-type transistor MN6 is coupled to the fourth node N4, the first terminal of the sixth N-type transistor MN6 is coupled to the ground voltage VSS, and the second terminal of the sixth N-type transistor MN6 is coupled to the fourth node N4. The sixth P-type transistor MP6 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth P-type transistor MP6 is coupled to the third node N3, the first terminal of the sixth P-type transistor MP6 is coupled to the second control node NC2, and the second terminal of the sixth P-type transistor MP6 is coupled to the second output node NOUT2 to output the second output voltage VOUT2. The seventh N-type transistor MN7 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh N-type transistor MN7 is coupled to the third node N3, the first terminal of the seventh N-type transistor MN7 is coupled to the ground voltage VSS, and the second terminal of the seventh N-type transistor MN7 is coupled to the second output node NOUT2.

[0028] In some embodiments, the third P-type transistor MP3 and the fourth N-type transistor MN4 can provide a bias voltage near a flip threshold of an inverter formed by the sixth P-type transistor MP6 and the seventh N-type transistor MN7. Furthermore, the fifth P-type transistor MP5 and the sixth N-type transistor MN6 can provide another bias voltage near another flip threshold of another inverter formed by the fourth P-type transistor MP4 and the fifth N-type transistor MN5. With this design, the differential-mode portion of the input signal can be quickly responded to. The first capacitor C1 and the second capacitor C2 can accelerate high-frequency signal comparison. The first resistor R1 and the second resistor R2 can be used to limit the voltage difference between the first control node NC1 and the second control node NC2 on either side. Even if the input voltage swing is large, it can be quickly recovered without affecting the comparison speed. It is also worth mentioning that the left and right sides of the comparator body 210 are symmetrical, thus achieving differential output and strong resistance to common-mode fluctuations.

[0029] Figure 3 FIG. 3 is a schematic diagram of a high-speed comparator system 300 according to an embodiment of the present invention. Figure 3In an embodiment of the present application, in addition to the comparator main body 110 (or 210), the high-speed comparator system 300 can further include a voltage regulator 320, a common-mode improvement circuit 330, an analog-to-digital converter (ADC) 340, and a matching calibration circuit 350. The detailed structures and circuit connection manners of the voltage regulator 320, the common-mode improvement circuit 330, the ADC 340, and the matching calibration circuit 350 can be described as follows.

[0030] In an embodiment of the present application, the high-speed comparator system 300 has a different flipping threshold than Figure 2 the flipping thresholds of the two groups of inverters shown in FIG. 1, but can quickly respond to the flipping thresholds of the two groups of inverters, and the flipping thresholds of the two groups of inverters can be different due to circuit mismatch (caused by process).

[0031] Figure 4 A schematic diagram of the voltage regulator 320 described in an embodiment of the present application. The voltage regulator 320 includes an operational amplifier 322, a seventh P-type transistor MP7, an eighth P-type transistor MP8, and an eighth N-type transistor MN8. The operational amplifier 322 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the operational amplifier 322 is used to receive a common-mode voltage VCOM, the negative input terminal of the operational amplifier 322 is coupled to a seventh node N7, and the output terminal of the operational amplifier 322 is coupled to a second bias node NB2. The seventh P-type transistor MP7 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the seventh P-type transistor MP7 is coupled to the second bias node NB2, the first terminal of the seventh P-type transistor MP7 is coupled to a first supply voltage VDD1, and the second terminal of the seventh P-type transistor MP7 is coupled to the seventh node N7. The eighth P-type transistor MP8 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighth P-type transistor MP8 is coupled to an eighth node N8, the first terminal of the eighth P-type transistor MP8 is coupled to the seventh node N7, and the second terminal of the eighth P-type transistor MP8 is coupled to the eighth node N8. The eighth N-type transistor MN8 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighth N-type transistor MN8 is coupled to the eighth node N8, the first terminal of the eighth N-type transistor MN8 is coupled to a ground voltage VSS, and the second terminal of the eighth N-type transistor MN8 is coupled to the eighth node N8.

[0032] In some embodiments, voltage regulator 320 can clamp the voltages at first control node NC1 and second control node NC2 using a common-mode voltage VCOM. This allows the trip threshold of high-speed comparator system 300 to remain substantially constant even when the power supply (first supply voltage VDD1) fluctuates. Therefore, system power consumption and speed can be adjusted by adjusting the common-mode voltage VCOM.

[0033] Figure 5 FIG3 is a schematic diagram of a common-mode improvement circuit 330 according to an embodiment of the present invention. The common-mode improvement circuit 330 includes a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eleventh P-type transistor MP11, a ninth N-type transistor MN9, a tenth N-type transistor MN10, an eleventh N-type transistor MN11, a twelfth N-type transistor MN12, a thirteenth N-type transistor MN13, and a fourteenth N-type transistor MN14.

[0034] The ninth P-type transistor MP9 has a control terminal, a first terminal, and a second terminal. The control terminal of the ninth P-type transistor MP9 is coupled to the second bias node NB2, the first terminal of the ninth P-type transistor MP9 is coupled to the first supply voltage VDD1, and the second terminal of the ninth P-type transistor MP9 is coupled to the ninth node N9. The tenth P-type transistor MP10 has a control terminal, a first terminal, and a second terminal. The control terminal of the tenth P-type transistor MP10 is coupled to the second output node NOUT2, the first terminal of the tenth P-type transistor MP10 is coupled to the ninth node N9, and the second terminal of the tenth P-type transistor MP10 is coupled to the tenth node N10. The eleventh P-type transistor MP11 has a control terminal, a first terminal, and a second terminal. The control terminal of the eleventh P-type transistor MP11 is coupled to the first output node NOUT1, the first terminal of the eleventh P-type transistor MP11 is coupled to the ninth node N9, and the second terminal of the eleventh P-type transistor MP11 is coupled to the eleventh node N11.

[0035] The ninth N-type transistor MN9 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the ninth N-type transistor MN9 is coupled to the first output node NOUT1, the first terminal of the ninth N-type transistor MN9 is coupled to the second output node NOUT2, and the second terminal of the ninth N-type transistor MN9 is coupled to the first output node NOUT1. The tenth N-type transistor MN10 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the tenth N-type transistor MN10 is coupled to the second output node NOUT2, the first terminal of the tenth N-type transistor MN10 is coupled to the first output node NOUT1, and the second terminal of the tenth N-type transistor MN10 is coupled to the second output node NOUT2. The eleventh N-type transistor MN11 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eleventh N-type transistor MN11 is coupled to the eleventh node N11, the first terminal of the eleventh N-type transistor MN11 is coupled to the tenth node N10, and the second terminal of the eleventh N-type transistor MN11 is coupled to the eleventh node N11. The twelfth N-type transistor MN12 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the twelfth N-type transistor MN12 is coupled to the tenth node N10, the first terminal of the twelfth N-type transistor MN12 is coupled to the eleventh node N11, and the second terminal of the twelfth N-type transistor MN12 is coupled to the tenth node N10. The thirteenth N-type transistor MN13 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the thirteenth N-type transistor MN13 is coupled to the tenth node N10, the first terminal of the thirteenth N-type transistor MN13 is coupled to a ground voltage VSS, and the second terminal of the thirteenth N-type transistor MN13 is coupled to the tenth node N10. The fourteenth N-type transistor MN14 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourteenth N-type transistor MN14 is coupled to the eleventh node N11, the first terminal of the fourteenth N-type transistor MN14 is coupled to a ground voltage VSS, and the second terminal of the fourteenth N-type transistor MN14 is coupled to the eleventh node N11.

[0036] In some embodiments, the common mode improvement circuit 330 can increase the common mode portion of the comparison result of the previous stage circuit to facilitate the comparison of the next stage circuit. In addition, the ninth N-type transistor MN9 and the tenth N-type transistor MN10 are added to help limit the swing of the input signal of the current stage, and the eleventh N-type transistor MN11 and the twelfth N-type transistor MN12 are added to help limit the swing of the output signal of the current stage.

[0037] Figure 6FIG1 is a schematic diagram of an analog-to-digital converter 340 according to an embodiment of the present invention. The analog-to-digital converter 340 includes a twelfth P-type transistor MP12, a thirteenth P-type transistor MP13, a fourteenth P-type transistor MP14, a fifteenth N-type transistor MN15, a sixteenth N-type transistor MN16, and a seventeenth N-type transistor MN17. The twelfth P-type transistor MP12 has a control terminal, a first terminal, and a second terminal. The control terminal of the twelfth P-type transistor MP12 is coupled to a twelfth node N12, the first terminal of the twelfth P-type transistor MP12 is coupled to a second supply voltage VDD2, and the second terminal of the twelfth P-type transistor MP12 is coupled to the twelfth node N12. The thirteenth P-type transistor MP13 has a control terminal, a first terminal, and a second terminal. The control terminal of the thirteenth P-type transistor MP13 is coupled to the twelfth node N12, the first terminal of the thirteenth P-type transistor MP13 is coupled to the second supply voltage VDD2, and the second terminal of the thirteenth P-type transistor MP13 is coupled to a thirteenth node N13. The fifteenth N-type transistor MN15 has a control terminal, a first terminal, and a second terminal. The control terminal of the fifteenth N-type transistor MN15 is coupled to the eleventh node N11, the first terminal of the fifteenth N-type transistor MN15 is coupled to the ground voltage VSS, and the second terminal of the fifteenth N-type transistor MN15 is coupled to the twelfth node N12. The sixteenth N-type transistor MN16 has a control terminal, a first terminal, and a second terminal. The control terminal of the sixteenth N-type transistor MN16 is coupled to the tenth node N10, the first terminal of the sixteenth N-type transistor MN16 is coupled to the ground voltage VSS, and the second terminal of the sixteenth N-type transistor MN16 is coupled to the thirteenth node N13. The fourteenth P-type transistor MP14 has a control terminal, a first terminal, and a second terminal. The control terminal of the fourteenth P-type transistor MP14 is coupled to the thirteenth node N13, the first terminal of the fourteenth P-type transistor MP14 is coupled to the second supply voltage VDD2, and the second terminal of the fourteenth P-type transistor MP14 is coupled to the final output node NOUTF to output the final output voltage VOUTF. The seventeenth N-type transistor MN17 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventeenth N-type transistor MN17 is coupled to the thirteenth node N13, the first terminal of the seventeenth N-type transistor MN17 is coupled to the ground voltage VSS, and the second terminal of the seventeenth N-type transistor MN17 is coupled to the final output node NOUTF.

[0038] In some embodiments, the second supply voltage VDD2 is lower than the first supply voltage VDD1. The analog-to-digital converter 340 can convert the comparison result from the high voltage domain to the low voltage domain. Because the output result of the previous stage circuit (acting on the eleventh node N11 and the tenth node N10) has a relatively large swing, the control signal swing received by the fifteenth N-type transistor MN15 and the sixteenth N-type transistor MN16 is relatively large, thereby enabling the analog-to-digital converter 340 to provide relatively low static power consumption.

[0039] Figure 7 This figure is a schematic diagram of a matching correction circuit 350 according to an embodiment of the present invention. Matching correction circuit 350 includes a logic circuit 352, a plurality of first correctors 354, and a plurality of second correctors 356. Logic circuit 352 generates a plurality of first correction voltages VL1 and a plurality of second correction voltages VL2 based on the final output voltage VOUTF. The actual structure and operation method of logic circuit 352 can be adjusted to meet different requirements.

[0040] The first correctors 354 are connected in parallel. Each of the first correctors 354 includes a first correction N-type transistor MCN1 and a second correction N-type transistor MCN2. For example, each correction N-type transistor in this specification may be an N-type metal oxide semiconductor field effect transistor, but is not limited thereto. The first correction N-type transistor MCN1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first correction N-type transistor MCN1 is configured to receive one of the first correction voltages VL1. The first terminal of the first correction N-type transistor MCN1 is coupled to the first connection node NE1, and the second terminal of the first correction N-type transistor MCN1 is coupled to the first control node NC1. The second correction N-type transistor MCN2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second correction N-type transistor MCN2 is coupled to the first bias node NB1. The first terminal of the second correction N-type transistor MCN2 is coupled to the ground voltage VSS, and the second terminal of the second correction N-type transistor MCN2 is coupled to the first connection node NE1. In some embodiments, the total number of the first correctors 354 may be at least 10 to adjust various mismatches of the first control node NC1 caused by differences in process, temperature, and power supply voltage.

[0041] The second correctors 356 are connected in parallel. Each of the second correctors 356 includes a third correction N-type transistor MCN3 and a fourth correction N-type transistor MCN4. The third correction N-type transistor MCN3 has a control terminal, a first terminal, and a second terminal. The control terminal of the third correction N-type transistor MCN3 is configured to receive one of the second correction voltages VL2. The first terminal of the third correction N-type transistor MCN3 is coupled to the second connection node NE2, and the second terminal of the third correction N-type transistor MCN3 is coupled to the second control node NC2. The fourth correction N-type transistor MCN4 has a control terminal, a first terminal, and a second terminal. The control terminal of the fourth correction N-type transistor MCN4 is coupled to the first bias node NB1. The first terminal of the fourth correction N-type transistor MCN4 is coupled to the ground voltage VSS, and the second terminal of the fourth correction N-type transistor MCN4 is coupled to the second connection node NE2. In some embodiments, the total number of the second correctors 356 can be at least ten to adjust for various mismatches with respect to the second control node NC2 caused by variations in process, temperature, and power supply voltage.

[0042] In some embodiments, the matching correction circuit 350 can couple the higher voltage of the first control node NC1 and the second control node NC2 to the ground voltage VSS through a branch current path based on the comparison result of the comparator body 210. This can eliminate the impact on comparison accuracy caused by circuit mismatch caused by differences in process, temperature, and power supply voltage.

[0043] It should be noted that the circuit blocks of the present invention are not limited to the above structure. In other embodiments, the high-speed comparator system 300 may include a comparator body 810, a voltage regulator 820, a common-mode improvement circuit 830, and an analog-to-digital converter 840, which have similar operating principles, as described in detail in the following embodiments.

[0044] Figure 8 FIG. 8 is a schematic diagram of a comparator body 810 according to an embodiment of the present invention. Figure 8 In the embodiment of the present invention, the comparator body 810 includes a voltage input circuit 812 , a voltage-stabilizing current source 814 , a voltage-stabilizing resistor component 816 , and a differential output circuit 818 .

[0045] The voltage input circuit 812 includes a first N-type transistor MN1, a second N-type transistor MN2, and a third N-type transistor MN3. The first N-type transistor MN1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first N-type transistor MN1 is used to receive a first input voltage VIN. The first terminal of the first N-type transistor MN1 is coupled to a first node N1, and the second terminal of the first N-type transistor MN1 is coupled to a second node N2. The second N-type transistor MN2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second N-type transistor MN2 is used to receive a second input voltage VREF. The first terminal of the second N-type transistor MN2 is coupled to the first node N1, and the second terminal of the second N-type transistor MN2 is coupled to a third node N3. The third N-type transistor MN3 has a control terminal, a first terminal, and a second terminal. The control terminal of the third N-type transistor MN3 is coupled to a first bias node NB1. The first terminal of the third N-type transistor MN3 is coupled to a ground voltage VSS, and the second terminal of the third N-type transistor MN3 is coupled to the first node N1.

[0046] The regulated current source 814 includes a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, and a fourth P-type transistor MP4. The first P-type transistor MP1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first P-type transistor MP1 is coupled to the second bias node NB2, the first terminal of the first P-type transistor MP1 is coupled to the first supply voltage VDD1, and the second terminal of the first P-type transistor MP1 is coupled to the second node N2. The second P-type transistor MP2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second P-type transistor MP2 is coupled to the second bias node NB2, the first terminal of the second P-type transistor MP2 is coupled to the first supply voltage VDD1, and the second terminal of the second P-type transistor MP2 is coupled to the third node N3. The third P-type transistor MP3 has a control terminal, a first terminal, and a second terminal. The control terminal of the third P-type transistor MP3 is coupled to the third bias node NB3, the first terminal of the third P-type transistor MP3 is coupled to the second node N2, and the second terminal of the third P-type transistor MP3 is coupled to the first control node NC1 to output the first current I1. The fourth P-type transistor MP4 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth P-type transistor MP4 is coupled to the third bias node NB3, the first terminal of the fourth P-type transistor MP4 is coupled to the third node N3, and the second terminal of the fourth P-type transistor MP4 is coupled to the second control node NC2 to output the second current I2.

[0047] The voltage regulator resistor assembly 816 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is coupled to the first control node NC1 and the second end of the first resistor R1 is coupled to the fourth bias node NB4. The second resistor R2 has a first end and a second end, wherein the first end of the second resistor R2 is coupled to the second control node NC2 and the second end of the second resistor R2 is coupled to the fourth bias node NB4. Alternatively, the first resistor R1 and the second resistor R2 can be combined into one resistor coupled between the first control node NC1 and the second control node NC2.

[0048] The differential output circuit 818 includes a fifth P-type transistor MP5, a sixth P-type transistor MP6, a seventh P-type transistor MP7, an eighth P-type transistor MP8, a ninth P-type transistor MP9, a tenth P-type transistor MP10, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, a seventh N-type transistor MN7, an eighth N-type transistor MN8, a ninth N-type transistor MN9, and a third resistor R3.

[0049] The fifth P-type transistor MP5 has a control terminal, a first terminal, and a second terminal. The control terminal of the fifth P-type transistor MP5 is coupled to the fourth node N4, the first terminal of the fifth P-type transistor MP5 is coupled to the first control node NC1, and the second terminal of the fifth P-type transistor MP5 is coupled to the fifth node N5. The fourth N-type transistor MN4 has a control terminal, a first terminal, and a second terminal. The control terminal of the fourth N-type transistor MN4 is coupled to the fourth node N4, the first terminal of the fourth N-type transistor MN4 is coupled to the fifth bias node NB5, and the second terminal of the fourth N-type transistor MN4 is coupled to the fifth node N5. The sixth P-type transistor MP6 has a control terminal, a first terminal, and a second terminal. The control terminal of the sixth P-type transistor MP6 is coupled to the fifth node N5, the first terminal of the sixth P-type transistor MP6 is coupled to the first control node NC1, and the second terminal of the sixth P-type transistor MP6 is coupled to the fifth node N5. The fifth N-type transistor MN5 has a control terminal, a first terminal, and a second terminal. The control terminal of the fifth N-type transistor MN5 is coupled to the fifth node N5, the first terminal of the fifth N-type transistor MN5 is coupled to the fifth bias node NB5, and the second terminal of the fifth N-type transistor MN5 is coupled to the fifth node N5. The seventh P-type transistor MP7 has a control terminal, a first terminal, and a second terminal. The control terminal of the seventh P-type transistor MP7 is coupled to the fourth node N4, the first terminal of the seventh P-type transistor MP7 is coupled to the first control node NC1, and the second terminal of the seventh P-type transistor MP7 is coupled to the first output node NOUT1 to output the first output voltage VOUT1. The sixth N-type transistor MN6 has a control terminal, a first terminal, and a second terminal. The control terminal of the sixth N-type transistor MN6 is coupled to the fourth node N4, the first terminal of the sixth N-type transistor MN6 is coupled to the fifth bias node NB5, and the second terminal of the sixth N-type transistor MN6 is coupled to the first output node NOUT1.

[0050] The eighth P-type transistor MP8 has a control terminal, a first terminal, and a second terminal. The control terminal of the eighth P-type transistor MP8 is coupled to the fifth node N5, the first terminal of the eighth P-type transistor MP8 is coupled to the second control node NC2, and the second terminal of the eighth P-type transistor MP8 is coupled to the fourth node N4. The seventh N-type transistor MN7 has a control terminal, a first terminal, and a second terminal. The control terminal of the seventh N-type transistor MN7 is coupled to the fifth node N5, the first terminal of the seventh N-type transistor MN7 is coupled to the fifth bias node NB5, and the second terminal of the seventh N-type transistor MN7 is coupled to the fourth node N4. The ninth P-type transistor MP9 has a control terminal, a first terminal, and a second terminal. The control terminal of the ninth P-type transistor MP9 is coupled to the fourth node N4, the first terminal of the ninth P-type transistor MP9 is coupled to the second control node NC2, and the second terminal of the ninth P-type transistor MP9 is coupled to the fourth node N4. The eighth N-type transistor MN8 has a control terminal, a first terminal, and a second terminal. The control terminal of the eighth N-type transistor MN8 is coupled to the fourth node N4, the first terminal of the eighth N-type transistor MN8 is coupled to the fifth bias node NB5, and the second terminal of the eighth N-type transistor MN8 is coupled to the fourth node N4. The tenth P-type transistor MP10 has a control terminal, a first terminal, and a second terminal. The control terminal of the tenth P-type transistor MP10 is coupled to the fifth node N5, the first terminal of the tenth P-type transistor MP10 is coupled to the second control node NC2, and the second terminal of the tenth P-type transistor MP10 is coupled to the second output node NOUT2 to output the second output voltage VOUT2. The ninth N-type transistor MN9 has a control terminal, a first terminal, and a second terminal. The control terminal of the ninth N-type transistor MN9 is coupled to the fifth node N5, the first terminal of the ninth N-type transistor MN9 is coupled to the fifth bias node NB5, and the second terminal of the ninth N-type transistor MN9 is coupled to the second output node NOUT2. The third resistor R3 has a first end and a second end, wherein the first end of the third resistor R3 is coupled to the fifth bias node NB5 , and the second end of the third resistor R3 is coupled to the ground voltage VSS.

[0051] In some embodiments, the sixth P-type transistor MP6 and the fifth N-type transistor MN5 can provide a bias voltage near a flip threshold of the inverter formed by the tenth P-type transistor MP10 and the ninth N-type transistor MN9. Additionally, the ninth P-type transistor MP9 and the eighth N-type transistor MN8 can provide another bias voltage near another flip threshold of another inverter formed by the seventh P-type transistor MP7 and the sixth N-type transistor MN6. With this design, the differential-mode portion of the input signal can be quickly responded to. The fifth P-type transistor MP5 and the fourth N-type transistor MN4, as well as the eighth P-type transistor MP8 and the seventh N-type transistor MN7, can each be used to increase the gain of the comparator 810, improving the comparison accuracy of the comparator 810. The first resistor R1 and the second resistor R2 can be used to limit the voltage difference between the first control node NC1 and the second control node NC2. Even if the input voltage swing is large, it can be quickly recovered without affecting the comparison speed. It is also worth mentioning that the left and right sides of the comparator body 810 are symmetrical in structure, so differential output can be achieved and the ability to resist common-mode fluctuations is strong.

[0052] Figure 9 FIG. 8 is a schematic diagram of a voltage regulator 820 according to an embodiment of the present invention. Figure 9 In the embodiment, the voltage regulator 820 includes an operational amplifier 822, an eleventh P-type transistor MP11, a twelfth P-type transistor MP12, a thirteenth P-type transistor MP13, a fourteenth P-type transistor MP14, a tenth N-type transistor MN10, an eleventh N-type transistor MN11, and a fourth resistor R4.

[0053] The operational amplifier 822 has a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the operational amplifier 822 is used to receive the common-mode voltage VCOM. The negative input terminal of the operational amplifier 822 is coupled to the twelfth node N12. The output terminal of the operational amplifier 822 is coupled to the second bias node NB2. The eleventh P-type transistor MP11 has a control terminal, a first terminal, and a second terminal. The control terminal of the eleventh P-type transistor MP11 is coupled to the second bias node NB2, the first terminal of the eleventh P-type transistor MP11 is coupled to the first supply voltage VDD1, and the second terminal of the eleventh P-type transistor MP11 is coupled to the twelfth node N12. The twelfth P-type transistor MP12 has a control terminal, a first terminal, and a second terminal. The control terminal of the twelfth P-type transistor MP12 is coupled to the thirteenth node N13, the first terminal of the twelfth P-type transistor MP12 is coupled to the twelfth node N12, and the second terminal of the twelfth P-type transistor MP12 is coupled to the thirteenth node N13. The tenth N-type transistor MN10 has a control terminal, a first terminal, and a second terminal. The control terminal of the tenth N-type transistor MN10 is coupled to a thirteenth node N13, the first terminal of the tenth N-type transistor MN10 is coupled to a fourteenth node N14, and the second terminal of the tenth N-type transistor MN10 is coupled to the thirteenth node N13. The fourth resistor R4 has a first terminal and a second terminal. The first terminal of the fourth resistor R4 is coupled to the fourteenth node N14, and the second terminal of the fourth resistor R4 is coupled to the ground voltage VSS.

[0054] The thirteenth P-type transistor MP13 has a control terminal, a first terminal, and a second terminal. The control terminal of the thirteenth P-type transistor MP13 is coupled to the second bias node NB2, the first terminal of the thirteenth P-type transistor MP13 is coupled to the first supply voltage VDD1, and the second terminal of the thirteenth P-type transistor MP13 is coupled to the third bias node NB3. The fourteenth P-type transistor MP14 has a control terminal, a first terminal, and a second terminal. The control terminal of the fourteenth P-type transistor MP14 is coupled to the fifteenth node N15, the first terminal of the fourteenth P-type transistor MP14 is coupled to the third bias node NB3, and the second terminal of the fourteenth P-type transistor MP14 is coupled to the fifteenth node N15. The eleventh N-type transistor MN11 has a control terminal, a first terminal, and a second terminal. The control terminal of the eleventh N-type transistor MN11 is coupled to the fifteenth node N15, the first terminal of the eleventh N-type transistor MN11 is coupled to the ground voltage VSS, and the second terminal of the eleventh N-type transistor MN11 is coupled to the fifteenth node N15.

[0055] In some embodiments, the voltage regulator 820 can clamp the voltages at the first control node NC1 and the second control node NC2 using the common-mode voltage VCOM. Even if the power supply (first supply voltage VDD1) fluctuates, the system's flip-flop threshold can remain substantially constant. Therefore, the system's power consumption and speed can be adjusted by setting the common-mode voltage VCOM. The addition of the thirteenth P-type transistor MP13, the fourteenth P-type transistor MP14, and the eleventh N-type transistor MN11 allows the voltage at node NB3 to serve as the voltage of the third bias node NB3 of the comparator body 810, expanding the range of the common-mode portion of the input voltage that the comparator body 810 can handle. Resistor R4 can be used to regulate the power consumption of the comparator body 810 and the voltage regulator 820. For example, when the current flowing through the twelfth P-type transistor MP12 and the tenth N-type transistor MN10 increases, the voltage difference between the twelfth node N12 and the fourteenth node N14 can be reduced, thereby suppressing power consumption growth.

[0056] Figure 10 FIG. 8 is a schematic diagram of a common mode improvement circuit 830 according to an embodiment of the present invention. Figure 10 In the embodiment, the common-mode improvement circuit 830 includes a fifteenth P-type transistor MP15, a sixteenth P-type transistor MP16, a seventeenth P-type transistor MP17, an eighteenth P-type transistor MP18, a nineteenth P-type transistor MP19, a twentieth P-type transistor MP20, a twenty-first P-type transistor MP21, a twelfth N-type transistor MN12, a thirteenth N-type transistor MN13, a fourteenth N-type transistor MN14, a fifteenth N-type transistor MN15, a sixteenth N-type transistor MN16, a seventeenth N-type transistor MN17, an eighteenth N-type transistor MN18, a nineteenth N-type transistor MN19, and a twentieth N-type transistor MN20.

[0057] The fifteenth P-type transistor MP15 has a control terminal, a first terminal, and a second terminal. The control terminal of the fifteenth P-type transistor MP15 is coupled to a ground node NG, the first terminal of the fifteenth P-type transistor MP15 is coupled to the fourth bias node NB4, and the second terminal of the fifteenth P-type transistor MP15 is coupled to the sixteenth node N16. The sixteenth P-type transistor MP16 has a control terminal, a first terminal, and a second terminal. The control terminal of the sixteenth P-type transistor MP16 is coupled to the second output node NOUT2, the first terminal of the sixteenth P-type transistor MP16 is coupled to the sixteenth node N16, and the second terminal of the sixteenth P-type transistor MP16 is coupled to the seventeenth node N17. The seventeenth P-type transistor MP17 has a control terminal, a first terminal, and a second terminal. The control terminal of the seventeenth P-type transistor MP17 is coupled to the first output node NOUT1, the first terminal of the seventeenth P-type transistor MP17 is coupled to the sixteenth node N16, and the second terminal of the seventeenth P-type transistor MP17 is coupled to the eighteenth node N18. The twelfth N-type transistor MN12 has a control terminal, a first terminal, and a second terminal. The control terminal of the twelfth N-type transistor MN12 is coupled to the first output node NOUT1, the first terminal of the twelfth N-type transistor MN12 is coupled to the second output node NOUT2, and the second terminal of the twelfth N-type transistor MN12 is coupled to the first output node NOUT1. The thirteenth N-type transistor M13 has a control terminal, a first terminal, and a second terminal. The control terminal of the thirteenth N-type transistor MN13 is coupled to the second output node NOUT2, the first terminal of the thirteenth N-type transistor MN13 is coupled to the first output node NOUT1, and the second terminal of the thirteenth N-type transistor MN13 is coupled to the second output node NOUT2. The fourteenth N-type transistor MN14 has a control terminal, a first terminal, and a second terminal. The control terminal of the fourteenth N-type transistor MN14 is coupled to the seventeenth node N17, the first terminal of the fourteenth N-type transistor MN14 is coupled to the fifth bias node NB5, and the second terminal of the fourteenth N-type transistor MN14 is coupled to the seventeenth node N17. The fifteenth N-type transistor MN15 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifteenth N-type transistor MN15 is coupled to the seventeenth node N17, the first terminal of the fifteenth N-type transistor MN15 is coupled to the fifth bias node NB5, and the second terminal of the fifteenth N-type transistor MN15 is coupled to the eighteenth node N18.

[0058] The eighteenth P-type transistor MP18 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighteenth P-type transistor MP18 is coupled to the nineteenth node N19, the first terminal of the eighteenth P-type transistor MP18 is coupled to the fourth bias node NB4, and the second terminal of the eighteenth P-type transistor MP18 is coupled to the nineteenth node N19. The nineteenth P-type transistor MP19 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the nineteenth P-type transistor MP19 is coupled to the nineteenth node N19, the first terminal of the nineteenth P-type transistor MP19 is coupled to the fourth bias node NB4, and the second terminal of the nineteenth P-type transistor MP19 is coupled to the eighteenth node N18. The sixteenth N-type transistor MN16 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixteenth N-type transistor MN16 is coupled to the second output node NOUT2, the first terminal of the sixteenth N-type transistor MN16 is coupled to the twentieth node N20, and the second terminal of the sixteenth N-type transistor MN16 is coupled to the nineteenth node N19. The seventeenth N-type transistor MN17 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the seventeenth N-type transistor MN17 is coupled to the first output node NOUT1, the first terminal of the seventeenth N-type transistor MN17 is coupled to the twentieth node N20, and the second terminal of the seventeenth N-type transistor MN17 is coupled to the eighteenth node N18. The eighteenth N-type transistor MN18 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighteenth N-type transistor MN18 is coupled to the second supply voltage VDD2, the first terminal of the eighteenth N-type transistor MN18 is coupled to the fifth bias node NB5, and the second terminal of the eighteenth N-type transistor is coupled to the twentieth node N20.

[0059] The twentieth P-type transistor MP20 has a control terminal, a first terminal, and a second terminal. The control terminal of the twentieth P-type transistor MP20 is coupled to the eighteenth node N18, the first terminal of the twentieth P-type transistor MP20 is coupled to the fourth bias node NB4, and the second terminal of the twentieth P-type transistor MP20 is coupled to the twenty-first node N21. The nineteenth N-type transistor MN19 has a control terminal, a first terminal, and a second terminal. The control terminal of the nineteenth N-type transistor MN19 is coupled to the eighteenth node N18, the first terminal of the nineteenth N-type transistor MN19 is coupled to the fifth bias node NB5, and the second terminal of the nineteenth N-type transistor MN19 is coupled to the twenty-first node N21. The twenty-first P-type transistor MP21 has a control terminal, a first terminal, and a second terminal. The control terminal of the twenty-first P-type transistor MP21 is coupled to the twenty-first node N21, the first terminal of the twenty-first P-type transistor MP21 is coupled to the fourth bias node NB4, and the second terminal of the twenty-first P-type transistor MP21 is coupled to the twenty-second node N22. The twentieth N-type transistor MN20 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the twentieth N-type transistor MN20 is coupled to the twenty-first node N21, the first terminal of the twentieth N-type transistor MN20 is coupled to the fifth bias node NB5, and the second terminal of the twentieth N-type transistor MN20 is coupled to the twenty-second node N22.

[0060] In some embodiments, the common-mode improvement circuit 830 can further amplify the differential mode portion of the comparison result of the previous stage circuit to facilitate analog-to-digital (voltage domain) conversion in the next stage circuit. Figure 5 The difference between the common-mode improvement circuit 330 and the common-mode improvement circuit 830 is that the common-mode improvement circuit 830 uses the seventeenth P-type transistor MP17 and the seventeenth N-type transistor MN17 to receive the output signal NOUT1 of the previous stage circuit, and uses the sixteenth P-type transistor MP16 and the sixteenth N-type transistor MN16 to receive the output signal NOUT2 of the previous stage circuit. This can be applied to a wider range of differential signals NOUT1 and NOUT2, thereby increasing the input range (as the input of this stage). Furthermore, the common-mode improvement circuit 830 uses the fourth bias node NB4 and the fifth bias node NB5 (i.e. Figure 8 The fourth bias node NB4 and the fifth bias node NB5 shown in FIG2 are used as power supply terminals, so that the swing amplitudes of the signals NOUT1 and NOUT2 are close to the voltage difference between the fourth bias node NB4 and the fifth bias node NB5. The voltage difference is equivalent to Figure 9 The voltage difference between the common mode voltage VCOM and the fourteenth node N14 is shown. The twelfth N-type transistor MN12 and the thirteenth N-type transistor MN13 are used to limit the swing of the input signal NOUT1 and increase the recovery speed. Figure 5The output signals (voltages at the 21st node N21 and the 22nd node N22) of the common-mode improvement circuit 330 and the common-mode improvement circuit 830 shown have larger swings, which facilitates analog-to-digital (voltage domain) conversion in the subsequent circuit.

[0061] Figure 11 FIG. 8 is a schematic diagram of an analog-to-digital converter 840 according to an embodiment of the present invention. Figure 11 In the embodiment, the analog-to-digital converter 840 includes a twenty-second P-type transistor MP22, a twenty-third P-type transistor MP23, a twenty-fourth P-type transistor MP24, a twenty-fifth P-type transistor MP25, a twenty-first N-type transistor MN21, a twenty-second N-type transistor MN22, a twenty-third N-type transistor MN23, and a twenty-first N-type transistor MN24.

[0062] The twenty-second P-type transistor MP22 has a control terminal, a first terminal, and a second terminal. The control terminal of the twenty-second P-type transistor MP22 is coupled to the twenty-third node N23, the first terminal of the twenty-second P-type transistor MP22 is coupled to the second supply voltage VDD2, and the second terminal of the twenty-second P-type transistor MP22 is coupled to the twenty-fourth node N24. The twenty-third P-type transistor MP23 has a control terminal, a first terminal, and a second terminal. The control terminal of the twenty-third P-type transistor MP23 is coupled to the twenty-fourth node N24, the first terminal of the twenty-third P-type transistor MP23 is coupled to the second supply voltage VDD2, and the second terminal of the twenty-third P-type transistor MP23 is coupled to the twenty-third node N23. The twenty-first N-type transistor MN21 has a control terminal, a first terminal, and a second terminal. The control terminal of the twenty-first N-type transistor MN21 is coupled to the twenty-second node N22, the first terminal of the twenty-first N-type transistor MN21 is coupled to the ground voltage VSS, and the second terminal of the twenty-first N-type transistor MN21 is coupled to the twenty-fourth node N24. The 22nd N-type transistor MN22 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the 22nd N-type transistor MN22 is coupled to the 21st node N21, the first terminal of the 22nd N-type transistor MN22 is coupled to the ground voltage VSS, and the second terminal of the 22nd N-type transistor MN22 is coupled to the 23rd node N23.

[0063] The twenty-fourth P-type transistor MP24 has a control terminal, a first terminal, and a second terminal. The control terminal of the twenty-fourth P-type transistor MP24 is coupled to the twenty-third node N23, the first terminal of the twenty-fourth P-type transistor MP24 is coupled to the second supply voltage VDD2, and the second terminal of the twenty-fourth P-type transistor MP24 is coupled to the twenty-fifth node N25. The twenty-third N-type transistor MN23 has a control terminal, a first terminal, and a second terminal. The control terminal of the twenty-third N-type transistor MN23 is coupled to the twenty-third node N23, the first terminal of the twenty-third N-type transistor MN23 is coupled to the ground voltage VSS, and the second terminal of the twenty-third N-type transistor MN23 is coupled to the twenty-fifth node N25. The twenty-fifth P-type transistor MP25 has a control terminal, a first terminal, and a second terminal. The control terminal of the twenty-fifth P-type transistor MP25 is coupled to the twenty-fifth node N25, the first terminal of the twenty-fifth P-type transistor MP25 is coupled to the second supply voltage VDD2, and the second terminal of the twenty-fifth P-type transistor MP25 is coupled to the final output node NOUTF to output the final output voltage VOUTF. The twenty-fourth N-type transistor MN24 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the twenty-fourth N-type transistor MN24 is coupled to the twenty-fifth node N25, the first terminal of the twenty-fourth N-type transistor MN24 is coupled to the ground voltage VSS, and the second terminal of the twenty-fourth N-type transistor MN24 is coupled to the final output node NOUTF.

[0064] In some embodiments, the second supply voltage VDD2 is lower than the first supply voltage VDD1. The analog-to-digital converter 840 can convert the comparison result from the high voltage domain to the low voltage domain. Because the output result of the previous stage circuit (acting on the twenty-first node N21 and the twenty-second node N22) has a relatively large swing, that is, the control signal swing received by the twenty-first N-type transistor MN21 and the twenty-second N-type transistor MN22 is relatively large, the analog-to-digital converter 840 can provide relatively low static power consumption.

[0065] According to actual measurement results, the high-speed comparator system proposed in the present invention has at least the following advantages: (1) fast response speed, high accuracy, and simple structure; (2) insensitive to process influences, power supply voltage, temperature fluctuations, etc.; (3) both high-speed and low-speed signal changes can be monitored; (4) speed and power consumption can be adjusted; (5) suitable for various application conditions without repeated calibration; and (6) comparison results can be output to different voltage domains without significantly increasing power consumption.

[0066] It is worth noting that the voltage, current, resistance, inductance, capacitance, and other component parameters mentioned above are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The high-speed comparator system of the present invention is not limited to Figures 1-11所图示的状态。本发明可以仅包括 Figures 1-11 any one or more features of any one or more embodiments. In other words, not all illustrated features need to be implemented simultaneously in the high-speed comparator system of the present invention. Although the embodiments of the present invention use metal oxide semiconductor field effect transistors as an example, the present invention is not limited thereto. Those skilled in the art may use other types of transistors, such as junction field effect transistors or fin field effect transistors, without affecting the effects of the present invention.

[0067] In this specification and claims, ordinal numbers, such as "first", "second", "third", etc., have no sequential relationship with each other and are only used to distinguish two different components with the same name.

[0068] Although the present invention is disclosed above in terms of preferred embodiments, they are not intended to limit the scope of the invention. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A high-speed comparator system comprising: Comparator body, including: A voltage input circuit receives a first input voltage and a second input voltage and is coupled to the first control node and the second control node; a regulated current source, outputting a first current to the first control node and outputting a second current to the second control node; a voltage-stabilizing resistor component coupled between the first control node and the second control node; and A differential output circuit is coupled to the first control node and the second control node and generates a first output voltage and a second output voltage. The voltage-stabilizing resistor component is used to limit the voltage difference between the first control node and the second control node. The left and right sides of the differential output circuit are symmetrical in structure. A bias voltage provided by a transistor on one side of the differential output circuit is located near a flip threshold of an inverter formed by a transistor on the other side of the differential output circuit. One side of the differential output circuit includes a parallel circuit consisting of a bias voltage circuit provided by a transistor and an inverter circuit formed by a transistor connected in parallel, and the first control node and the second control node are respectively connected to one of the parallel circuits on the left and right sides of the differential output circuit.

2. The high-speed comparator system of claim 1 , wherein the voltage input circuit comprises: a first N-type transistor, wherein a control terminal of the first N-type transistor receives the first input voltage, a first terminal of the first N-type transistor is coupled to the first node, and a second terminal of the first N-type transistor is coupled to the first control node; a second N-type transistor, wherein a control terminal of the second N-type transistor receives the second input voltage, a first terminal of the second N-type transistor is coupled to the first node, and a second terminal of the second N-type transistor is coupled to the second control node; as well as A third N-type transistor has a control terminal coupled to the first bias node, a first terminal coupled to the ground voltage, and a second terminal coupled to the first node.

3. The high-speed comparator system as claimed in claim 1 , wherein the regulated current source comprises: a first P-type transistor, wherein a control terminal of the first P-type transistor is coupled to the second bias node, a first terminal of the first P-type transistor is coupled to the first supply voltage, and a second terminal of the first P-type transistor is coupled to the first control node to output the first current; as well as A second P-type transistor, wherein the control terminal of the second P-type transistor is coupled to the second bias node, the first terminal of the second P-type transistor is coupled to the first supply voltage, and the second terminal of the second P-type transistor is coupled to the second control node to output the second current.

4. The high-speed comparator system as claimed in claim 1 , wherein the voltage-stabilizing resistor component comprises: a first resistor, wherein a first end of the first resistor is coupled to the first control node, and a second end of the first resistor is coupled to the second node; as well as A second resistor has a first end coupled to the second control node and a second end coupled to the second node.

5. The high-speed comparator system of claim 1 , wherein the differential output circuit comprises: a first capacitor, wherein a first terminal of the first capacitor is coupled to the first control node, and a second terminal of the first capacitor is coupled to the third node; a third P-type transistor, wherein a control terminal of the third P-type transistor is coupled to the third node, a first terminal of the third P-type transistor is coupled to the first control node, and a second terminal of the third P-type transistor is coupled to the third node; a fourth N-type transistor, wherein a control terminal of the fourth N-type transistor is coupled to the third node, a first terminal of the fourth N-type transistor is coupled to a ground voltage, and a second terminal of the fourth N-type transistor is coupled to the third node; a fourth P-type transistor, wherein a control terminal of the fourth P-type transistor is coupled to the fourth node, a first terminal of the fourth P-type transistor is coupled to the first control node, and a second terminal of the fourth P-type transistor is coupled to the first output node to output the first output voltage; a fifth N-type transistor, wherein a control terminal of the fifth N-type transistor is coupled to the fourth node, a first terminal of the fifth N-type transistor is coupled to the ground voltage, and a second terminal of the fifth N-type transistor is coupled to the first output node; a second capacitor, wherein a first terminal of the second capacitor is coupled to the second control node, and a second terminal of the second capacitor is coupled to the fourth node; a fifth P-type transistor, wherein a control terminal of the fifth P-type transistor is coupled to the fourth node, a first terminal of the fifth P-type transistor is coupled to the second control node, and a second terminal of the fifth P-type transistor is coupled to the fourth node; a sixth N-type transistor, wherein a control terminal of the sixth N-type transistor is coupled to the fourth node, a first terminal of the sixth N-type transistor is coupled to the ground voltage, and a second terminal of the sixth N-type transistor is coupled to the fourth node; a sixth P-type transistor, wherein a control terminal of the sixth P-type transistor is coupled to the third node, a first terminal of the sixth P-type transistor is coupled to the second control node, and a second terminal of the sixth P-type transistor is coupled to the second output node to output the second output voltage; as well as A seventh N-type transistor has a control terminal coupled to the third node, a first terminal coupled to the ground voltage, and a second terminal coupled to the second output node.

6. The high-speed comparator system of claim 1 , further comprising a voltage regulator, wherein the voltage regulator comprises: an operational amplifier, wherein a positive input terminal of the operational amplifier receives a common mode voltage, a negative input terminal of the operational amplifier is coupled to the seventh node, and an output terminal of the operational amplifier is coupled to the second bias node; a seventh P-type transistor, wherein a control terminal of the seventh P-type transistor is coupled to the second bias node, a first terminal of the seventh P-type transistor is coupled to the first supply voltage, and a second terminal of the seventh P-type transistor is coupled to the seventh node; an eighth P-type transistor, wherein a control terminal of the eighth P-type transistor is coupled to the eighth node, a first terminal of the eighth P-type transistor is coupled to the seventh node, and a second terminal of the eighth P-type transistor is coupled to the eighth node; as well as An eighth N-type transistor has a control terminal coupled to the eighth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the eighth node.

7. The high-speed comparator system of claim 1 , further comprising a common-mode improvement circuit, wherein the common-mode improvement circuit comprises: a ninth P-type transistor, wherein a control terminal of the ninth P-type transistor is coupled to the second bias node, a first terminal of the ninth P-type transistor is coupled to the first supply voltage, and a second terminal of the ninth P-type transistor is coupled to the ninth node; a tenth P-type transistor, wherein a control terminal of the tenth P-type transistor is coupled to the second output node, a first terminal of the tenth P-type transistor is coupled to the ninth node, and a second terminal of the tenth P-type transistor is coupled to the tenth node; an eleventh P-type transistor, wherein a control terminal of the eleventh P-type transistor is coupled to the first output node, a first terminal of the eleventh P-type transistor is coupled to the ninth node, and a second terminal of the eleventh P-type transistor is coupled to the eleventh node; a ninth N-type transistor, wherein a control terminal of the ninth N-type transistor is coupled to the first output node, a first terminal of the ninth N-type transistor is coupled to the second output node, and a second terminal of the ninth N-type transistor is coupled to the first output node; a tenth N-type transistor, wherein a control terminal of the tenth N-type transistor is coupled to the second output node, a first terminal of the tenth N-type transistor is coupled to the first output node, and a second terminal of the tenth N-type transistor is coupled to the second output node; an eleventh N-type transistor, wherein a control terminal of the eleventh N-type transistor is coupled to the eleventh node, a first terminal of the eleventh N-type transistor is coupled to the tenth node, and a second terminal of the eleventh N-type transistor is coupled to the eleventh node; a twelfth N-type transistor, wherein a control terminal of the twelfth N-type transistor is coupled to the tenth node, a first terminal of the twelfth N-type transistor is coupled to the eleventh node, and a second terminal of the twelfth N-type transistor is coupled to the tenth node; a thirteenth N-type transistor, wherein the control terminal of the thirteenth N-type transistor is coupled to the tenth node, the first terminal of the thirteenth N-type transistor is coupled to the ground voltage, and the second terminal of the thirteenth N-type transistor is coupled to the tenth node; as well as A fourteenth N-type transistor has a control terminal coupled to the eleventh node, a first terminal coupled to the ground voltage, and a second terminal coupled to the eleventh node.

8. The high-speed comparator system of claim 1 , further comprising an analog-to-digital converter, wherein the analog-to-digital converter comprises: a twelfth P-type transistor, wherein a control terminal of the twelfth P-type transistor is coupled to the twelfth node, a first terminal of the twelfth P-type transistor is coupled to the second supply voltage, and a second terminal of the twelfth P-type transistor is coupled to the twelfth node; a thirteenth P-type transistor, wherein a control terminal of the thirteenth P-type transistor is coupled to the twelfth node, a first terminal of the thirteenth P-type transistor is coupled to the second supply voltage, and a second terminal of the thirteenth P-type transistor is coupled to the thirteenth node; a fifteenth N-type transistor, wherein a control terminal of the fifteenth N-type transistor is coupled to the eleventh node, a first terminal of the fifteenth N-type transistor is coupled to the ground voltage, and a second terminal of the fifteenth N-type transistor is coupled to the twelfth node; a sixteenth N-type transistor, wherein a control terminal of the sixteenth N-type transistor is coupled to the tenth node, a first terminal of the sixteenth N-type transistor is coupled to the ground voltage, and a second terminal of the sixteenth N-type transistor is coupled to the thirteenth node; a fourteenth P-type transistor, wherein a control terminal of the fourteenth P-type transistor is coupled to the thirteenth node, a first terminal of the fourteenth P-type transistor is coupled to the second supply voltage, and a second terminal of the fourteenth P-type transistor is coupled to the final output node to output the final output voltage; as well as A seventeenth N-type transistor has a control terminal coupled to the thirteenth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the final output node.

9. The high-speed comparator system of claim 1 , further comprising a matching correction circuit, wherein the matching correction circuit comprises: a logic circuit for generating a plurality of first correction voltages and a plurality of second correction voltages according to the final output voltage; A plurality of first correctors are connected in parallel, each of the first correctors comprising: a first correction N-type transistor, a control terminal of the first correction N-type transistor receiving one of the first correction voltages, a first terminal of the first correction N-type transistor coupled to the first connection node, and a second terminal of the first correction N-type transistor coupled to the first control node; and a second correction N-type transistor, wherein a control terminal of the second correction N-type transistor is coupled to the first bias node, a first terminal of the second correction N-type transistor is coupled to the ground voltage, and a second terminal of the second correction N-type transistor is coupled to the first connection node; and A plurality of second correctors are connected in parallel with each other, each of the second correctors comprising: a third correction N-type transistor, a control terminal of the third correction N-type transistor receiving one of the second correction voltages, a first terminal of the third correction N-type transistor coupled to the second connection node, and a second terminal of the third correction N-type transistor coupled to the second control node; and A fourth correction N-type transistor has a control terminal coupled to the first bias node, a first terminal coupled to the ground voltage, and a second terminal coupled to the second connection node.

10. The high-speed comparator system of claim 1 , wherein the voltage input circuit comprises: a first N-type transistor, wherein a control terminal of the first N-type transistor receives the first input voltage, a first terminal of the first N-type transistor is coupled to the first node, and a second terminal of the first N-type transistor is coupled to the second node in the regulated current source; a second N-type transistor, wherein a control terminal of the second N-type transistor receives the second input voltage, a first terminal of the second N-type transistor is coupled to the first node, and a second terminal of the second N-type transistor is coupled to a third node in the regulated current source; as well as A third N-type transistor has a control terminal coupled to the first bias node, a first terminal coupled to the ground voltage, and a second terminal coupled to the first node.

11. The high-speed comparator system of claim 10 , wherein the regulated current source comprises: a first P-type transistor, wherein a control terminal of the first P-type transistor is coupled to the second bias node, a first terminal of the first P-type transistor is coupled to the first supply voltage, and a second terminal of the first P-type transistor is coupled to the second node; as well as a second P-type transistor, wherein a control terminal of the second P-type transistor is coupled to the second bias node, a first terminal of the second P-type transistor is coupled to the first supply voltage, and a second terminal of the second P-type transistor is coupled to the third node; a third P-type transistor, wherein a control terminal of the third P-type transistor is coupled to the third bias node, a first terminal of the third P-type transistor is coupled to the second node, and a second terminal of the third P-type transistor is coupled to the first control node to output the first current; as well as A fourth P-type transistor has a control terminal coupled to the third bias node, a first terminal coupled to the third node, and a second terminal coupled to the second control node to output the second current.

12. The high-speed comparator system as claimed in claim 11 , wherein the voltage-stabilizing resistor component comprises: a first resistor, wherein a first end of the first resistor is coupled to the first control node, and a second end of the first resistor is coupled to a fourth bias node; as well as A second resistor has a first end coupled to the second control node and a second end coupled to the fourth bias node.

13. The high-speed comparator system of claim 11 , wherein the differential output circuit comprises: a fifth P-type transistor, wherein a control terminal of the fifth P-type transistor is coupled to the fourth node, a first terminal of the fifth P-type transistor is coupled to the first control node, and a second terminal of the fifth P-type transistor is coupled to the fifth node; a fourth N-type transistor, wherein a control terminal of the fourth N-type transistor is coupled to the fourth node, a first terminal of the fourth N-type transistor is coupled to the fifth bias node, and a second terminal of the fourth N-type transistor is coupled to the fifth node; a sixth P-type transistor, wherein a control terminal of the sixth P-type transistor is coupled to the fifth node, a first terminal of the sixth P-type transistor is coupled to the first control node, and a second terminal of the sixth P-type transistor is coupled to the fifth node; a fifth N-type transistor, wherein a control terminal of the fifth N-type transistor is coupled to the fifth node, a first terminal of the fifth N-type transistor is coupled to the fifth bias node, and a second terminal of the fifth N-type transistor is coupled to the fifth node; a seventh P-type transistor, wherein a control terminal of the seventh P-type transistor is coupled to the fourth node, a first terminal of the seventh P-type transistor is coupled to the first control node, and a second terminal of the seventh P-type transistor is coupled to the first output node to output the first output voltage; a sixth N-type transistor, wherein a control terminal of the sixth N-type transistor is coupled to the fourth node, a first terminal of the sixth N-type transistor is coupled to the fifth bias node, and a second terminal of the sixth N-type transistor is coupled to the first output node; an eighth P-type transistor, wherein a control terminal of the eighth P-type transistor is coupled to the fifth node, a first terminal of the eighth P-type transistor is coupled to the second control node, and a second terminal of the eighth P-type transistor is coupled to the fourth node; a seventh N-type transistor, wherein a control terminal of the seventh N-type transistor is coupled to the fifth node, a first terminal of the seventh N-type transistor is coupled to the fifth bias node, and a second terminal of the seventh N-type transistor is coupled to the fourth node; a ninth P-type transistor, wherein a control terminal of the ninth P-type transistor is coupled to the fourth node, a first terminal of the ninth P-type transistor is coupled to the second control node, and a second terminal of the ninth P-type transistor is coupled to the fourth node; an eighth N-type transistor, wherein a control terminal of the eighth N-type transistor is coupled to the fourth node, a first terminal of the eighth N-type transistor is coupled to the fifth bias node, and a second terminal of the eighth N-type transistor is coupled to the fourth node; a tenth P-type transistor, wherein a control terminal of the tenth P-type transistor is coupled to the fifth node, a first terminal of the tenth P-type transistor is coupled to the second control node, and a second terminal of the tenth P-type transistor is coupled to the second output node to output the second output voltage; a ninth N-type transistor, wherein a control terminal of the ninth N-type transistor is coupled to the fifth node, a first terminal of the ninth N-type transistor is coupled to the fifth bias node, and a second terminal of the ninth N-type transistor is coupled to the second output node; as well as A third resistor is provided, wherein a first terminal of the third resistor is coupled to the fifth bias node, and a second terminal of the third resistor is coupled to the ground voltage.

14. The high-speed comparator system of claim 1 , further comprising a voltage regulator, wherein the voltage regulator comprises: an operational amplifier, wherein a positive input terminal of the operational amplifier receives a common mode voltage, a negative input terminal of the operational amplifier is coupled to the twelfth node, and an output terminal of the operational amplifier is coupled to the second bias node; an eleventh P-type transistor, wherein a control terminal of the eleventh P-type transistor is coupled to the second bias node, a first terminal of the eleventh P-type transistor is coupled to the first supply voltage, and a second terminal of the eleventh P-type transistor is coupled to the twelfth node; a twelfth P-type transistor, wherein a control terminal of the twelfth P-type transistor is coupled to the thirteenth node, a first terminal of the twelfth P-type transistor is coupled to the twelfth node, and a second terminal of the twelfth P-type transistor is coupled to the thirteenth node; as well as a tenth N-type transistor, wherein a control terminal of the tenth N-type transistor is coupled to the thirteenth node, a first terminal of the tenth N-type transistor is coupled to the fourteenth node, and a second terminal of the tenth N-type transistor is coupled to the thirteenth node; a fourth resistor, wherein a first end of the fourth resistor is coupled to the fourteenth node, and a second end of the fourth resistor is coupled to the ground voltage; a thirteenth P-type transistor, wherein a control terminal of the thirteenth P-type transistor is coupled to the second bias node, a first terminal of the thirteenth P-type transistor is coupled to the first supply voltage, and a second terminal of the thirteenth P-type transistor is coupled to the third bias node; a fourteenth P-type transistor, wherein a control terminal of the fourteenth P-type transistor is coupled to the fifteenth node, a first terminal of the fourteenth P-type transistor is coupled to the third bias node, and a second terminal of the fourteenth P-type transistor is coupled to the fifteenth node; as well as An eleventh N-type transistor, wherein a control terminal of the eleventh N-type transistor is coupled to the fifteenth node, a first terminal of the eleventh N-type transistor is coupled to the ground voltage, and a second terminal of the eleventh N-type transistor is coupled to the fifteenth node.

15. The high-speed comparator system of claim 1 , further comprising a common-mode improvement circuit, wherein the common-mode improvement circuit comprises: a fifteenth P-type transistor, wherein a control terminal of the fifteenth P-type transistor is coupled to the ground node, a first terminal of the fifteenth P-type transistor is coupled to the fourth bias node, and a second terminal of the fifteenth P-type transistor is coupled to the sixteenth node; a sixteenth P-type transistor, wherein a control terminal of the sixteenth P-type transistor is coupled to the second output node, a first terminal of the sixteenth P-type transistor is coupled to the sixteenth node, and a second terminal of the sixteenth P-type transistor is coupled to the seventeenth node; a seventeenth P-type transistor, wherein a control terminal of the seventeenth P-type transistor is coupled to the first output node, a first terminal of the seventeenth P-type transistor is coupled to the sixteenth node, and a second terminal of the seventeenth P-type transistor is coupled to the eighteenth node; a twelfth N-type transistor, wherein a control terminal of the twelfth N-type transistor is coupled to the first output node, a first terminal of the twelfth N-type transistor is coupled to the second output node, and a second terminal of the twelfth N-type transistor is coupled to the first output node; a thirteenth N-type transistor, wherein a control terminal of the thirteenth N-type transistor is coupled to the second output node, a first terminal of the thirteenth N-type transistor is coupled to the first output node, and a second terminal of the thirteenth N-type transistor is coupled to the second output node; a fourteenth N-type transistor, wherein a control terminal of the fourteenth N-type transistor is coupled to the seventeenth node, a first terminal of the fourteenth N-type transistor is coupled to the fifth bias node, and a second terminal of the fourteenth N-type transistor is coupled to the seventeenth node; a fifteenth N-type transistor, wherein a control terminal of the fifteenth N-type transistor is coupled to the seventeenth node, a first terminal of the fifteenth N-type transistor is coupled to the fifth bias node, and a second terminal of the fifteenth N-type transistor is coupled to the eighteenth node; an eighteenth P-type transistor, wherein a control terminal of the eighteenth P-type transistor is coupled to the nineteenth node, a first terminal of the eighteenth P-type transistor is coupled to the fourth bias node, and a second terminal of the eighteenth P-type transistor is coupled to the nineteenth node; a nineteenth P-type transistor, wherein a control terminal of the nineteenth P-type transistor is coupled to the nineteenth node, a first terminal of the nineteenth P-type transistor is coupled to the fourth bias node, and a second terminal of the nineteenth P-type transistor is coupled to the eighteenth node; a sixteenth N-type transistor, wherein a control terminal of the sixteenth N-type transistor is coupled to the second output node, a first terminal of the sixteenth N-type transistor is coupled to the twentieth node, and a second terminal of the sixteenth N-type transistor is coupled to the nineteenth node; a seventeenth N-type transistor, wherein a control terminal of the seventeenth N-type transistor is coupled to the first output node, a first terminal of the seventeenth N-type transistor is coupled to the twentieth node, and a second terminal of the seventeenth N-type transistor is coupled to the eighteenth node; an eighteenth N-type transistor, wherein a control terminal of the eighteenth N-type transistor is coupled to the second supply voltage, a first terminal of the eighteenth N-type transistor is coupled to the fifth bias node, and a second terminal of the eighteenth N-type transistor is coupled to the twentieth node; a 20th P-type transistor, wherein a control terminal of the 20th P-type transistor is coupled to the 18th node, a first terminal of the 20th P-type transistor is coupled to the fourth bias node, and a second terminal of the 20th P-type transistor is coupled to the 21st node; a nineteenth N-type transistor, wherein a control terminal of the nineteenth N-type transistor is coupled to the eighteenth node, a first terminal of the nineteenth N-type transistor is coupled to the fifth bias node, and a second terminal of the nineteenth N-type transistor is coupled to the twenty-first node; a twenty-first P-type transistor, wherein a control terminal of the twenty-first P-type transistor is coupled to the twenty-first node, a first terminal of the twenty-first P-type transistor is coupled to the fourth bias node, and a second terminal of the twenty-first P-type transistor is coupled to the twenty-second node; as well as A 20th N-type transistor has a control terminal coupled to the 21st node, a first terminal coupled to the fifth bias node, and a second terminal coupled to the 22nd node.

16. The high speed comparator system of claim 1 , further comprising an analog-to-digital converter, wherein the analog-to-digital converter comprises: a twenty-second P-type transistor, wherein a control terminal of the twenty-second P-type transistor is coupled to the twenty-third node, a first terminal of the twenty-second P-type transistor is coupled to the second supply voltage, and a second terminal of the twenty-second P-type transistor is coupled to the twenty-fourth node; a twenty-third P-type transistor, wherein a control terminal of the twenty-third P-type transistor is coupled to the twenty-fourth node, a first terminal of the twenty-third P-type transistor is coupled to the second supply voltage, and a second terminal of the twenty-third P-type transistor is coupled to the twenty-third node; a twenty-first N-type transistor, wherein a control terminal of the twenty-first N-type transistor is coupled to the twenty-second node, a first terminal of the twenty-first N-type transistor is coupled to the ground voltage, and a second terminal of the twenty-first N-type transistor is coupled to the twenty-fourth node; a twenty-second N-type transistor, wherein a control terminal of the twenty-second N-type transistor is coupled to the twenty-first node, a first terminal of the twenty-second N-type transistor is coupled to the ground voltage, and a second terminal of the twenty-second N-type transistor is coupled to the twenty-third node; a twenty-fourth P-type transistor, having a control terminal coupled to the twenty-third node, a first terminal coupled to the second supply voltage, and a second terminal coupled to the twenty-fifth node; a twenty-third N-type transistor, wherein a control terminal of the twenty-third N-type transistor is coupled to the twenty-third node, a first terminal of the twenty-third N-type transistor is coupled to the ground voltage, and a second terminal of the twenty-third N-type transistor is coupled to the twenty-fifth node; a twenty-fifth P-type transistor, having a control terminal coupled to the twenty-fifth node, a first terminal coupled to the second supply voltage, and a second terminal coupled to the final output node to output the final output voltage; as well as A twenty-fourth N-type transistor has a control terminal coupled to the twenty-fifth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the final output node.

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