Reset device and power supply device

Abstract

The application provides a reset device and a power supply device. The reset device comprises a first reset circuit, a second reset circuit, an OR gate, a first inverter, a second inverter and a third inverter. The first reset circuit and the second reset circuit are connected to a power supply. The input end of the first inverter is connected to the output end of the first reset circuit, and the output end of the first inverter is connected to the first input end of the OR gate. The input end of the second inverter is connected to the output end of the second reset circuit, and the output end of the second inverter is connected to the second input end of the OR gate. The output end of the OR gate is connected to the input end of the third inverter, and the output end of the third inverter is used for outputting a reset signal. The application can realize effective reset in different scenes and improve the reliability of reset.

Description

Technical Field

[0001] This application relates to semiconductor integrated circuit technology, and more particularly to a reset device and a power supply device. Background Technology

[0002] In integrated circuit design, the power supply system provides power to the digital circuit system, and it takes several milliseconds or tens of milliseconds to reach a stable and normal operating state. Instability in the power supply voltage can cause the digital circuit to malfunction, therefore a power reset circuit is needed to protect the circuit system and ensure stable operation.

[0003] A reset circuit is mainly used in SOC systems. When the chip starts working normally, it can ensure that the chip is reset in a complex electromagnetic environment, protecting the initial state of the entire system. Taking power-on reset as an example, traditional reset circuits can use transistor threshold voltage to achieve power-on reset, or they can use delay circuits. Bandgap reference technology can achieve slow power-on reset functionality.

[0004] The current limitation of reset circuits is that they cannot be applied to reset in various scenarios, which reduces the reliability of reset. Summary of the Invention

[0005] This application provides a reset device and a power supply device to implement reset circuits in different scenarios and improve reliability.

[0006] On one hand, this application provides a reset device, including: a first reset circuit, a second reset circuit, an OR gate, a first inverter, a second inverter, and a third inverter; wherein the first reset circuit and the second reset circuit are both connected to a power supply;

[0007] The first reset circuit is configured to output a first fast power-on reset signal and a first slow power-on reset signal in response to fast power-on and slow power-on; and to output a first slow power-off follow signal and a first fast power-off follow signal in response to slow power-off and fast power-off.

[0008] The second reset circuit is used to output a second slow power-on reset signal, a second slow power-off reset signal, and a second fast power-off reset signal in response to slow power-on, slow power-off, and fast power-off; and to output a second fast power-on follow signal in response to fast power-on.

[0009] The input terminal of the first inverter is connected to the output terminal of the first reset circuit, and the output terminal of the first inverter is connected to the first input terminal of the OR gate; the input terminal of the second inverter is connected to the output terminal of the second reset circuit, and the output terminal of the second inverter is connected to the second input terminal of the OR gate; the output terminal of the OR gate is connected to the input terminal of the third inverter, and the output terminal of the third inverter is used to output a reset signal.

[0010] In one possible design, the first reset circuit includes: a voltage generation circuit and a first comparator circuit; wherein,

[0011] The input terminal of the voltage generation circuit is connected to a power supply. The voltage generation circuit is used to output a first voltage signal and a second voltage signal through a first output terminal and a second output terminal, respectively, based on the power supply. The magnitude relationship between the first voltage signal and the second voltage signal reflects the state of the power supply.

[0012] The first input terminal of the first comparator circuit is connected to the first output terminal of the voltage generation circuit, and the second input terminal of the first comparator circuit is connected to the second output terminal of the voltage generation circuit; the output terminal of the first comparator circuit serves as the output terminal of the first reset circuit and is connected to the input terminal of the first inverter; the first comparator circuit is used to output a signal based on the first voltage signal and the second voltage signal.

[0013] In one possible design, the first comparison circuit includes: a first comparator and a fourth inverter; wherein,

[0014] The first input terminal of the first comparator is connected to the first output terminal of the voltage generation circuit; the second input terminal of the first comparator is connected to the second output terminal of the voltage generation circuit; the output terminal of the first comparator is connected to the input terminal of the fourth inverter; the output terminal of the fourth inverter serves as the output terminal of the first comparator circuit and is connected to the input terminal of the first inverter.

[0015] The voltage generation circuit is configured to output a first voltage signal and a second voltage signal after the power supply is powered on, wherein the first voltage signal is higher than the second voltage signal; and to output a first voltage signal and a second voltage signal after the power supply is powered off, wherein the first voltage signal is lower than the second voltage signal.

[0016] The first comparator is configured to output a low-level signal when the first voltage signal is higher than the second voltage signal, and to output a high-level signal when the first voltage signal is lower than the second voltage signal; the fourth inverter is configured to output an inverted signal based on the signal output by the first comparator.

[0017] In one possible design, the voltage generation circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first impedance element; wherein,

[0018] The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and grounded, and the source of the first PMOS transistor is connected to the source of the second PMOS transistor, serving as the input terminal of the first reset circuit and connected to the power supply.

[0019] The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the second NMOS transistor; the source of the first NMOS transistor is connected to the first terminal of the first impedance element, and the second terminal of the first impedance element is grounded; the source of the second NMOS transistor is grounded.

[0020] The drain of the first NMOS transistor serves as the first output terminal of the voltage generation circuit and is connected to the first input terminal of the first comparator circuit; the drain of the second NMOS transistor serves as the second output terminal of the voltage generation circuit and is connected to the second input terminal of the first comparator circuit.

[0021] In one possible design, the first comparator includes: a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein,

[0022] The source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the power supply. The gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the third NMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and serves as the output terminal of the first comparator, which is connected to the input terminal of the fourth inverter.

[0023] The source of the third NMOS transistor and the source of the fourth NMOS transistor are both grounded; the gate of the fourth NMOS transistor serves as the first input terminal of the first comparator and is connected to the first output terminal of the voltage generation circuit; the gate of the third NMOS transistor serves as the second input terminal of the first comparator and is connected to the second output terminal of the voltage generation circuit.

[0024] In one possible design, the first reset circuit further includes: a first Schmitt trigger disposed between the output terminal of the first comparator circuit and the first reset circuit; wherein...

[0025] The output of the first comparator circuit is connected to the input of the first Schmitt trigger; the output of the first Schmitt trigger is connected to the input of the first inverter.

[0026] In one possible design, the second reset circuit includes: a voltage detection module, a bandgap reference voltage source, and a second comparator circuit; wherein,

[0027] The voltage detection module is connected to the power supply and is used to output a detection voltage based on the power supply; the bandgap reference voltage source is used to provide a reference voltage; wherein, the relationship between the detection voltage and the reference voltage reflects the state of the power supply;

[0028] The first input terminal of the second comparator circuit is connected to the output terminal of the voltage detection module, and the second input terminal of the second comparator circuit is connected to the output terminal of the bandgap reference voltage source; the output terminal of the second comparator circuit is connected to the input terminal of the second inverter; the second comparator circuit is used to output a signal based on the detected voltage and the reference voltage.

[0029] In one possible design, the voltage detection module includes: a second impedance element and a third impedance element; wherein,

[0030] The first end of the second impedance element is connected to the power supply; the second end of the second impedance element is connected to the first end of the third impedance element, serving as the output end of the voltage detection module and connected to the first input end of the second comparison circuit; the second end of the third impedance element is grounded.

[0031] In one possible design, the second comparator circuit includes: a second comparator and a fifth inverter; wherein,

[0032] The inverting input of the second comparator is connected to the output of the voltage detection module, and the non-inverting input of the second comparator is connected to the output of the bandgap reference voltage source; the input of the fifth inverter is connected to the output of the second comparator; the output of the fifth inverter serves as the output of the second comparator circuit.

[0033] In one possible design, the second reset circuit further includes: a second delay filter circuit disposed between the output terminal of the second comparator circuit and the output terminal of the second reset circuit; wherein...

[0034] The input terminal of the second delay filter circuit is connected to the output terminal of the second comparator circuit, and the output terminal of the second delay filter circuit is connected to the input terminal of the second inverter.

[0035] In one possible design, the second reset circuit further includes: a second Schmitt trigger disposed between the output of the second comparator circuit and the output of the second reset circuit; wherein...

[0036] The output of the second comparator circuit is connected to the input of the second Schmitt trigger; the output of the second Schmitt trigger is connected to the input of the second inverter.

[0037] In one possible design, the reset device further includes: a sixth inverter and a level shifting circuit; wherein,

[0038] The input terminal of the sixth inverter is connected to the output terminal of the OR gate, and the output terminal of the sixth inverter is connected to the input terminal of the level conversion circuit. The level conversion circuit is used to perform level conversion on the reset signal output by the sixth inverter and then output it.

[0039] On the other hand, this application provides a power supply device, including: a power supply, and a reset device as described in any of the above; wherein,

[0040] The power supply is connected to the reset device; the reset device responds to the power supply being powered on and off by outputting a corresponding reset signal.

[0041] The reset device and power supply device provided in this application include a first reset circuit and a second reset circuit. The first reset circuit responds to fast power-on and slow power-on, while the second reset circuit responds to slow power-on, slow power-off, and fast power-off. Inverters and OR gates are used to logically process the output signals of the first and second reset circuits to output reset signals for different scenarios. This solution uses multiple reset circuits applicable to different scenarios. By performing logical operations on the signals output by these multiple reset circuits, effective reset in different scenarios is achieved, improving the reliability of the reset. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0043] Figure 1 This is a schematic diagram of a reset circuit in a related technology.

[0044] Figure 2 This is a schematic diagram of a reset device provided in Embodiment 1 of this application;

[0045] Figure 3 This is a schematic diagram of the structure of a first reset circuit provided in Embodiment 2 of this application;

[0046] Figure 4a This is a schematic diagram of the structure of a first reset circuit provided in Embodiment 3 of this application;

[0047] Figure 4b This is a schematic diagram of the DC simulation results of a first reset circuit provided in Embodiment 3 of this application;

[0048] Figure 5 This is a schematic diagram of the structure of a second reset circuit provided in Embodiment 4 of this application;

[0049] Figure 6a This is a schematic diagram of a second reset circuit provided in Embodiment 5 of this application;

[0050] Figure 6b This is a schematic diagram of the DC simulation results of a second reset circuit provided in Embodiment 5 of this application;

[0051] Figure 7 This is a schematic diagram of a delay filter circuit provided in Embodiment 5 of this application;

[0052] Figure 8a This is a schematic diagram of a reset device provided in Embodiment Six of this application;

[0053] Figure 8b This is a schematic diagram of the transient simulation results of a reset device provided in Embodiment Six of this application;

[0054] Figure 8c for Figure 8b Enlarged view of the rapid power-on to rapid power-off process;

[0055] Figure 9 This is a schematic diagram of a power supply device provided in Embodiment 7 of this application.

[0056] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0057] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they represent only examples of apparatuses and methods consistent with some aspects of this application.

[0058] The terms "comprising" and "having" in this application are used to indicate an open-ended inclusion, meaning that additional elements / components / etc. may exist besides those listed. The terms "first" and "second," etc., are used only as designations and are not intended to limit the number of objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic, and therefore this application is not limited to the dimensions or distances shown in the drawings.

[0059] In integrated circuit design, unstable power supply voltage can cause digital circuits to malfunction, so a power reset circuit is needed to protect the circuit system and ensure stable operation. Figure 1 This is a schematic diagram of a reset circuit in related technologies. Figure 1 As shown, it includes: a voltage divider circuit 11, a bandgap reference voltage source circuit 12, a comparator circuit 13, and an output reset signal 14.

[0060] A reset circuit is a circuit device used to restore a circuit to its initial state. Taking power-on reset as an example, there are various scenarios involved, such as power-on reset and power-off reset. Power-on reset scenarios further include fast power-on reset and slow power-on reset, while power-off reset scenarios further include fast power-off reset and slow power-off reset. Generally speaking, in power-on reset scenarios, it is desirable for the reset circuit to output a reset signal after a delay until the voltage stabilizes; in power-off reset scenarios, it is desirable to output a reset signal as soon as possible after the power is turned off.

[0061] Combination such as Figure 1 In the example shown, the first voltage divider is output through the voltage divider circuit 11, and the reference voltage is output through the bandgap reference voltage source 12. The two voltages are compared and analyzed by the comparison circuit 13. When the first voltage divider is greater than the reference voltage, the first voltage divider is transmitted as an output signal to the output reset signal 14. The final reset signal is obtained through the output reset signal 14, thus realizing the power-on reset function.

[0062] However, the limitation of the reset circuit described above is that it cannot be applied to reset in various scenarios, which reduces the reliability of the reset.

[0063] To address this issue, this application provides a reset device and a power supply device to achieve reset in different scenarios. The following will provide a detailed description of this application with reference to examples. The specific embodiments described below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0064] Example 1

[0065] Figure 2 This is a schematic diagram of a reset device provided in Embodiment 1 of this application. The reset device provided in this embodiment is used to achieve reset in different scenarios. Figure 2 As shown, the reset device includes: a first reset circuit 21, a second reset circuit 22, a first inverter 23, a second inverter 24, an OR gate 25, and a third inverter 26. It should be noted that the illustration is merely an example and does not limit the number or position of each structure. Both the first reset circuit 21 and the second reset circuit 22 are connected to a power supply.

[0066] The first reset circuit 21 is configured to output a first fast power-on reset signal and a first slow power-on reset signal in response to fast power-on and slow power-on; and to output a first slow power-off follow signal and a first fast power-off follow signal in response to slow power-off and fast power-off.

[0067] The second reset circuit 22 is used to output a second slow power-on reset signal, a second slow power-off reset signal, and a second fast power-off reset signal in response to slow power-on, slow power-off, and fast power-off; and to output a second fast power-on follow signal in response to fast power-on.

[0068] The input terminal of the first inverter 23 is connected to the output terminal of the first reset circuit 21, and the output terminal of the first inverter 23 is connected to the first input terminal of the OR gate 25; the input terminal of the second inverter 24 is connected to the output terminal of the second reset circuit 22, and the output terminal of the second inverter 24 is connected to the second input terminal of the OR gate 25; the output terminal of the OR gate 25 is connected to the input terminal of the third inverter 26, and the output terminal of the third inverter 26 is used to output a reset signal.

[0069] In one example, a reset output terminal 27 is defined, such as... Figure 2 As shown, the reset output terminal 27 is used to receive the reset signal output by the third inverter 26 to achieve a low-level reset. Based on the illustrated structure, examples of the reset process in different scenarios are provided:

[0070] During the rapid power-on process, the first reset circuit 21 responds to the rapid power-on by outputting a first rapid power-on reset signal; the second reset circuit 22 responds to the rapid power-on by outputting a second rapid power-on follow signal. In one example, the first rapid power-on reset signal is a signal that flips from a low level to a high level in response to the rapid power-on, and is output after the power-on process stabilizes. The second rapid power-on follow signal is a signal that changes in response to the rapid power-on. Subsequently, the first rapid power-on reset signal is inverted by the first inverter 23, and the second rapid power-on follow signal is inverted by the second inverter 24. The signals output by the first inverter 23 and the second inverter 24 are logically ORed by the OR gate 25. The signal output by the OR gate 25 is then inverted by the third inverter 26 to obtain the reset signal for the rapid power-on scenario, which is output via the reset output terminal 27, thus realizing the reset in the rapid power-on scenario.

[0071] During the rapid power-off process

[0072] The first reset circuit 21 responds to the rapid power-down by outputting a first rapid power-down follow signal.

[0073] The second reset circuit 22 responds to the rapid power-down by outputting a second rapid power-down reset signal.

[0074] In one example, the second fast power-down reset signal is a signal that changes from a high level to a low level in response to a rapid power-down, and is output rapidly after the power is turned off. The first fast power-down follower signal is a signal that changes in response to the rapid power-down. Then, the first fast power-down follower signal is inverted by the first inverter 23, and the second fast power-down reset signal is inverted by the second inverter 24. The signals output from the first inverter 23 and the second inverter 24 are logically ORed by the OR gate 25. The signal output from the OR gate 25 is then inverted by the third inverter 26 to obtain the reset signal for the rapid power-down scenario, which is output through the reset output terminal 27 to achieve the reset in the rapid power-down scenario.

[0075] During the slow power-on process, the first reset circuit 21 responds to the slow power-on by outputting a first slow power-on reset signal; the second reset circuit 22 responds to the slow power-on by outputting a second slow power-on reset signal. In one example, the second slow power-on reset signal is triggered by the slow power-on, i.e., it transitions from a low-level signal to a high-level signal, and the second slow power-on reset signal is output stably after the power-on process. The first slow power-on reset signal is triggered by the slow power-on, transitioning from a low-level signal to a high-level signal, and the first slow power-on reset signal is output after the power-on process stabilizes. Subsequently, the first slow power-on reset signal is inverted by the first inverter 23, and the second slow power-on reset signal is inverted by the second inverter 24. The signals output by the first inverter 23 and the second inverter 24 are subjected to a logical OR operation by the OR gate 25. The signal output by the OR gate 25 is inverted by the third inverter 26 to obtain the reset signal under the slow power-on scenario. The signal is then output through the reset output terminal 27 to realize the reset under the slow power-on scenario.

[0076] During the slow power-down process, the first reset circuit 21 responds to the slow power-down by outputting a first slow power-down following signal; the second reset circuit 22 responds to the slow power-down by outputting a second slow power-down reset signal. In one example, the first slow power-down following signal is a signal that changes with the slow power-down. The second slow power-down reset signal responds to the slow power-down by flipping from a high-level signal to a low-level signal, and is output quickly after the power-down. Then, the first slow power-down following signal is inverted by the first inverter 23, and the second slow power-down reset signal is inverted by the second inverter 24. The signals output from the first inverter 23 and the second inverter 24 are then subjected to a logical OR operation by an OR gate 25. The signal output from the OR gate 25 is then inverted by the third inverter 26 to obtain the reset signal for the slow power-down scenario, which is output through the reset output terminal 27, thus realizing the reset function for the slow power-down scenario.

[0077] The reset device provided in this embodiment includes a first reset circuit and a second reset circuit. The first reset circuit responds to rapid power-on and slow power-on, while the second reset circuit responds to slow power-on, slow power-off, and rapid power-off. Inverters and OR gates are used to logically process the output signals of the first and second reset circuits to output reset signals for different scenarios. This embodiment provides multiple reset circuits applicable to different scenarios. By performing logical operations on the signals output by these multiple reset circuits, effective reset in different scenarios is achieved, improving reset reliability.

[0078] Example 2

[0079] Figure 3This is a schematic diagram of a first reset circuit provided in Embodiment 2 of this application. This embodiment provides relevant examples of the structure of the first reset circuit based on Embodiment 1. For example... Figure 3 As shown, based on Embodiment 1, the first reset circuit includes: a voltage generation circuit 31 and a first comparison circuit 32; wherein,

[0080] The input terminal of the voltage generation circuit 31 is connected to the power supply. The voltage generation circuit 31 is used to output a first voltage signal and a second voltage signal through the first output terminal and the second output terminal, respectively, based on the power supply. The magnitude relationship between the first voltage signal and the second voltage signal reflects the state of the power supply.

[0081] The first input terminal of the first comparator circuit 32 is connected to the first output terminal of the voltage generation circuit 31, and the second input terminal of the first comparator circuit is connected to the second output terminal of the voltage generation circuit 31. The output terminal of the first comparator circuit 32 serves as the output terminal of the first reset circuit 21 and is connected to the input terminal of the first inverter 23. The first comparator circuit 32 is used to output a signal based on the first voltage signal and the second voltage signal.

[0082] In one example, the first comparison circuit 32 includes: a first comparator 321 and a fourth inverter 322; wherein,

[0083] The first input terminal of the first comparator 321 is connected to the first output terminal of the voltage generation circuit 31; the second input terminal of the first comparator 321 is connected to the second output terminal of the voltage generation circuit 31; the output terminal of the first comparator 321 is connected to the input terminal of the fourth inverter 322; the output terminal of the fourth inverter 322 serves as the output terminal of the first comparator circuit 32 and is connected to the input terminal of the first inverter 23.

[0084] The voltage generation circuit 31 is used to output a first voltage signal and a second voltage signal after the power supply is turned on, wherein the first voltage signal is higher than the second voltage signal; and to output a first voltage signal and a second voltage signal after the power supply is turned off, wherein the first voltage signal is lower than the second voltage signal.

[0085] The first comparator 321 is used to output a low-level signal when the first voltage signal is higher than the second voltage signal, and to output a high-level signal when the first voltage signal is lower than the second voltage signal; the fourth inverter 322 is used to output an inverted signal based on the signal output by the first comparator 321.

[0086] Referring to the illustration, during the rapid power-on process, the voltage generation circuit 31 generates a first voltage signal and a second voltage signal. At the initial stage of rapid power-on, the first voltage signal is less than the second voltage signal. After comparing the first and second voltage signals with the first comparator 321, a high-level signal is output. Then, the high-level signal output from the first comparator 321 is input to the inverter 322 to obtain a low-level output signal. As the power supply voltage increases, the first voltage signal increases rapidly, while the second voltage signal increases slowly. When the first voltage signal increases to a level greater than the second voltage signal, it is compared with the first comparator 321, resulting in a low-level signal. Then, the low-level signal output from the first comparator 321 is input to the inverter 322 to obtain a high-level output signal. At this point, the output voltage of the first comparator circuit 32 changes from low to high, thus realizing the rapid power-on reset function of the circuit.

[0087] During the slow power-up process, when the voltage generation circuit 31 generates the first voltage signal and the second voltage signal, the first voltage signal is less than the second voltage signal at the beginning. After comparing the first voltage signal and the second voltage signal with the first comparator 321, a high-level signal is output. Then, the high-level signal output by the first comparator 321 is input to the inverter 322 to obtain a low-level output signal. As the power supply voltage slowly rises, the second voltage signal increases slowly, while the first voltage signal increases faster than the second voltage signal. When the first voltage signal increases to be greater than the second voltage signal, it is compared with the first comparator 321 and a low-level signal is output. Then, the low-level signal output by the first comparator 321 is input to the inverter 322 to obtain a high-level output signal. At this time, the output voltage of the first comparator circuit 32 changes from low level to high level, thereby realizing the slow power-up reset function of the circuit.

[0088] In this embodiment, the first reset circuit sets up a voltage generation circuit and a first comparison circuit to output a first voltage signal and a second voltage signal with different magnitudes for the scenarios of fast power-on and slow power-on. The first comparison circuit outputs the corresponding signal and inverts it through an inverter to realize the reset under the scenarios of fast power-on and slow power-on.

[0089] Example 3

[0090] Figure 4a This is a schematic diagram of a first reset circuit provided in Embodiment 3 of this application. Based on Embodiment 2, this embodiment provides specific examples of the structure of each circuit in the first reset circuit. For example... Figure 4aAs shown, based on Embodiment 2, the voltage generation circuit 31 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first impedance element 41; wherein,

[0091] The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and grounded. The source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2. This serves as the input terminal of the first reset circuit 21 and is connected to the power supply.

[0092] The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1; the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2 and the gate of the second NMOS transistor MN2; the source of the first NMOS transistor MN1 is connected to the first end of the first impedance element 41, and the second end of the first impedance element 41 is grounded; the source of the second NMOS transistor MN2 is grounded.

[0093] The drain of the first NMOS transistor MN1 serves as the first output terminal of the voltage generation circuit 31 and is connected to the first input terminal of the first comparator circuit 32; the drain of the second NMOS transistor MN2 serves as the second output terminal of the voltage generation circuit 31 and is connected to the second input terminal of the first comparator circuit 32.

[0094] In one possible implementation, MP1 and MP2 are inverted ratio transistors, for example, their channel length L is much greater than their channel width W; in another possible implementation, the width-to-length ratio W / L of MP1 and MP2 are equal.

[0095] In one example, based on Embodiment 2, the first comparator 321 includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; wherein,

[0096] The source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are both connected to the power supply. The gate of the third PMOS transistor MP3 is connected to the drain of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4, and the drain of the third NMOS transistor MN3. The drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4. This serves as the output of the first comparator 321 and is connected to the input of the fourth inverter 322.

[0097] The source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are both grounded; the gate of the fourth NMOS transistor MN4 serves as the first input terminal of the first comparator 321 and is connected to the first output terminal of the voltage generation circuit 31; the gate of the third NMOS transistor MN3 serves as the second input terminal of the first comparator 321 and is connected to the second output terminal of the voltage generation circuit 31.

[0098] In one example, the first impedance element 41 includes a resistor R1.

[0099] Figure 4b for Figure 4a The diagram shows the DC simulation results of the first reset circuit. To illustrate with a scenario example, Figure 4b This is the simulation result of the first reset circuit during the rapid power-on process. Where I1 is the current in the MP1 path, I2 is the current in the MP2 path; V1 is the drain voltage of MN1, V2 is the drain voltage of MN2; VDD represents the power supply, and POR1 represents the output signal of the first reset circuit. Figure 4a The voltages at the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 are V1 and V2, respectively. Based on the diagram, the specific operation of the first reset circuit is illustrated below:

[0100] During the rapid power-up process: Initially, the gates of MP1 and MP2 are grounded. When the power supply voltage is greater than the threshold voltage VTH of MP1 and MP2, MP1 and MP2 are turned on. In one example, the width-to-length ratio (W / L) of MP1 and MP2 is equal, so the initial currents I1 and I2 flowing through MN1 and MN2 are small and approximately equal. Correspondingly, the voltage VR1 across resistor R1 is initially very small and can be ignored. In another example, the width-to-length ratio (W / L) of MN1 is greater than that of MN2, so the gate-source voltage VGS1 of MN1 is less than the gate-source voltage VGS2 of MN2. Therefore, at the start of rapid power-up, the voltage V1 is approximately VGS1, which is less than VGS2. As the power supply rapidly powers on, the power supply voltage VDD increases, and the currents I1 and I2 gradually increase. Voltage VR1 increases rapidly with increasing current I1, while MN1 and MN2 gradually enter the saturation region. VGS1 and VGS2 increase more slowly with currents I1 and I2 and gradually stabilize. At this point, voltage V1 is VGS1 + VR1 and gradually increases, while voltage V2 is VGS2. When voltage V1 increases to a level greater than voltage V2, the signal output by the comparator circuit flips. Correspondingly, after being inverted by the fourth inverter 322, the voltage of the output signal POR1 changes from low to high. That is, the first reset circuit responds to the rapid power-on and outputs the first rapid power-on reset signal, completing the reset process.

[0101] During the slow power-on process: In the initial stage, voltage V1 is less than voltage V2, at which time the first comparator outputs a high-level signal; the fourth inverter inverts the output to a low-level signal; as the power supply voltage slowly rises, the voltage through resistor R1 slowly rises, and correspondingly, voltage V1 increases; when voltage V1 increases to be greater than V2, the output signal of the first comparator's comparison circuit flips, outputting a low level, which is then inverted by the fourth inverter 322 to output a high-level signal. The output signal POR1 voltage changes from low to high, that is, the first reset circuit responds to the slow power-on and outputs the first slow power-on reset signal, completing the reset process.

[0102] In one possible design, the first reset circuit further includes: a first delay filter circuit 42 disposed between the output terminal of the first comparator circuit and the first reset circuit; wherein,

[0103] The input terminal of the first delay filter circuit 42 is connected to the output terminal of the first comparator circuit 32, and the output terminal of the first delay filter circuit 42 is connected to the input terminal of the first inverter 23.

[0104] In practical applications, during both fast and slow power-on processes, the first reset circuit obtains an output reset signal through a voltage generation circuit and a first comparison circuit. This output reset signal is then connected to the input of the first delay filter circuit 42 as the output signal of the first comparison circuit. After passing through the first delay filter circuit 42, the obtained reset signal undergoes delay filtering to obtain a more stable output signal, thereby further improving the reliability of the reset.

[0105] like Figure 4a As shown, the first reset circuit further includes: a first Schmitt trigger 43 disposed between the output terminals of the first comparator circuit and the first reset circuit; wherein,

[0106] The output of the first comparator circuit is connected to the input of the first Schmitt trigger 43; the output of the first Schmitt trigger 43 is connected to the input of the first inverter.

[0107] In practical applications, during the power-on process of fast and slow power-on, the first reset circuit obtains an output reset signal through the voltage generation circuit and the first comparison circuit. The output reset signal is connected to the input terminal of the first Schmitt trigger 43 as the output signal of the first comparison circuit. After processing by the first Schmitt trigger 43, a reset signal with strong anti-interference capability is obtained and output stably, thereby further improving the accuracy and reliability of the reset.

[0108] The structure shown in the figure is only an example. In actual applications, there are other optional implementation methods. For example, the positions of the first delay filter circuit 42 and the first Schmitt trigger 43 can be interchanged.

[0109] In the reset device provided in this embodiment, the first reset circuit can output a first fast power-on reset signal and a first slow power-on reset signal in scenarios of fast power-on and slow power-on, thereby ensuring the reset function under different scenarios.

[0110] Example 4

[0111] Figure 5 This is a schematic diagram of a second reset circuit provided in Embodiment 4 of this application. This embodiment provides relevant examples of the structure of the second reset circuit based on any other embodiment. Figure 5 As shown, based on any embodiment, the second reset circuit includes: a voltage detection module 51, a bandgap reference voltage source 52, and a second comparison circuit 53; wherein,

[0112] The voltage detection module 51 is connected to the power supply and is used to output a detection voltage based on the power supply. The bandgap reference voltage source 52 is used to provide a reference voltage. The relationship between the detection voltage and the reference voltage reflects the state of the power supply.

[0113] The first input terminal of the second comparison circuit 53 is connected to the output terminal of the voltage detection module 51, and the second input terminal of the second comparison circuit 53 is connected to the output terminal of the bandgap reference voltage source 52; the output terminal of the second comparison circuit 53 is connected to the input terminal of the second inverter 24; the second comparison circuit 53 is used to output a signal based on the detected voltage and the reference voltage.

[0114] Referring to the illustration, during the slow power-on process, the voltage detection module 51 generates a detection voltage, and the bandgap reference voltage source 52 generates a reference voltage. At the initial stage of slow power-on, the detection voltage is less than the reference voltage. A low-level output signal is obtained by comparing the reference voltage signal and the detection voltage signal with the second comparator circuit 53. As the power supply voltage slowly increases, the reference voltage also slowly increases, while the detection voltage increases at a faster rate. When the detection voltage exceeds the reference voltage, it is compared and processed by the second comparator circuit 53, resulting in a high-level output signal. At this point, the output voltage of the second comparator circuit 53 changes from low to high, thus realizing the slow power-on reset function of the circuit.

[0115] During the rapid power-down process, the detection voltage generated by the voltage detection module 51 and the reference voltage generated by the bandgap reference voltage source 52 are initially higher than the reference voltage. A high-level output signal is obtained by comparing the reference voltage signal and the detection voltage signal with the second comparison circuit 53. As the power supply voltage drops rapidly, the detection voltage drops rapidly. When the detection voltage drops below the reference voltage, a low-level output signal is obtained by comparing the detection voltage with the second comparison circuit 53. At this time, the output voltage of the second comparison circuit 53 changes from high level to low level, thereby realizing the rapid power-down reset function of the circuit.

[0116] During the slow power-down process, the detection voltage generated by the voltage detection module 51 and the reference voltage generated by the bandgap reference voltage source 52 are initially higher than the reference voltage. By inputting the reference voltage signal and the detection voltage signal to the second comparison circuit 53 for comparison, a high-level output signal is obtained. As the power supply voltage slowly decreases, the detection voltage drops rapidly. When the detection voltage drops below the reference voltage, it is processed by the second comparison circuit 53, and a low-level output signal is obtained. At this time, the output voltage of the second comparison circuit 53 changes from high level to low level, thereby realizing the slow power-down reset function of the circuit.

[0117] In this embodiment, the second reset circuit, by setting up a voltage detection module, a bandgap reference voltage source, and a second comparator circuit, outputs detection voltages and reference voltages of different magnitudes for scenarios of rapid power-down, slow power-up, and slow power-down. The corresponding signals are then output by the second comparator circuit to achieve reset under these scenarios. While achieving reset under different scenarios, the second reset circuit does not rely on transistor threshold voltage for signal switching, avoiding the influence of PVT variations on the reset and improving reset accuracy.

[0118] Example 5

[0119] Figure 6a This is a schematic diagram of a second reset circuit provided in Embodiment 5 of this application. The embodiment provided in this application is based on Embodiment 4, providing specific examples of the structure of the second reset circuit. The reset device provided in this embodiment is used to achieve circuit reset, improve the effect of voltage variation with PVT, and improve accuracy. Figure 6a As shown, based on Embodiment 4, the voltage detection module 51 includes: a second impedance element and a third impedance element; wherein,

[0120] The first end of the second impedance element is connected to the power supply; the second end of the second impedance element is connected to the first end of the third impedance element, serving as the output end of the voltage detection module, and is connected to the first input end of the second comparison circuit 53; the second end of the third impedance element is grounded.

[0121] In one example, the second comparator circuit 53 includes: a second comparator CMP and a fifth inverter 61; wherein,

[0122] The inverting input of the second comparator CMP is connected to the output of the voltage detection module 51, and the non-inverting input of the second comparator CMP is connected to the output of the bandgap reference voltage source BG; the input of the fifth inverter 61 is connected to the output of the second comparator CMP; the output of the fifth inverter 61 serves as the output of the second comparator circuit 53.

[0123] In one example, the second impedance element includes resistor R2, and the third impedance element includes resistor R3.

[0124] Figure 6b for Figure 6a The diagram shows the DC simulation results of the second reset circuit. To illustrate with a scenario example, Figure 6b This is a simulation result of the second reset circuit during the slow power-on process. In the figure, the voltages at the output terminals of the voltage detection module and the bandgap reference voltage source BG are the detection voltage V3 and the bandgap reference voltage V4, respectively. Figure 6b The diagram shows the correspondence between the detection voltage V3 and the bandgap reference voltage V4. VDD represents the power supply, and POR2 represents the output signal of the second reset circuit. Based on the diagram, the specific operation of the second reset circuit is illustrated below:

[0125] During the slow power-on process: the detection voltage V3 is provided by the voltage divider of resistors R2 and R3, and the bandgap reference voltage V4 is provided by the bandgap reference voltage source BG. Initially, the detection voltage V3 is less than the bandgap reference voltage V4. The detection voltage V3 increases as the power supply voltage increases, while the bandgap reference voltage V4 remains constant after stabilization. When the detection voltage V3 increases to be greater than the bandgap reference voltage V4, the detection voltage V3 is compared with the bandgap reference voltage V4 through the non-inverting input of the second comparator CMP. The output signal changes, and correspondingly, after being inverted by the fifth inverter 61, the output signal POR2 changes from low to high. That is, the second reset circuit responds to the slow power-on by outputting a second slow power-on reset signal, completing the reset process.

[0126] During the rapid power-down process: In the initial stage, the detection voltage V3 is greater than the bandgap reference voltage V4. The detection voltage V3 decreases rapidly as the power supply voltage decreases, while the bandgap reference voltage V4 decreases slowly as the power supply voltage decreases. When the detection voltage V3 decreases to less than the bandgap reference voltage V4, the detection voltage V3 is compared with the bandgap reference voltage V4 through the non-inverting input of the second comparator CMP. The output signal changes, and correspondingly, after being inverted by the fifth inverter 61, the output signal POR2 voltage changes from high to low. That is, the second reset circuit responds to the rapid power-down and outputs the second rapid power-down reset signal, completing the reset process.

[0127] During the slow power-down process: In the initial stage, the detection voltage V3 is greater than the bandgap reference voltage V4. The detection voltage V3 decreases rapidly as the power supply voltage decreases slowly, while the bandgap reference voltage V4 decreases slowly as the power supply voltage decreases. When the detection voltage V3 drops to less than the bandgap reference voltage V4, the detection voltage V3 is compared with the bandgap reference voltage V4 through the non-inverting input of the second comparator CMP. The output signal changes, and correspondingly, after being inverted by the fifth inverter 61, the output voltage POR2 changes from high to low. That is, the second reset circuit responds to the slow power-down by outputting the second slow power-down reset signal, completing the reset process.

[0128] In one possible example, the second reset circuit further includes a second delay filter circuit 62 disposed between the second comparator circuit 53 and the output terminal of the second reset circuit; wherein,

[0129] The input terminal of the second delay filter circuit 62 is connected to the output terminal of the second comparator circuit 53, and the output terminal of the second delay filter circuit 62 is connected to the input terminal of the second inverter.

[0130] In practical applications, during rapid power-down, slow power-up, and slow power-down processes, the second reset circuit obtains a reset signal after passing through the voltage detection module, the bandgap reference voltage source, and the second comparator circuit. This output reset signal is connected to the input of the second delay filter circuit 62 as the output signal of the second comparator circuit. After passing through the second delay filter circuit 62, the obtained reset signal undergoes delay filtering processing to obtain a more stable output signal, further improving the reliability of the reset.

[0131] Optional, such as Figure 7 As shown, the second delay filter circuit includes: a fifth PMOS transistor MP5, a fifth NMOS transistor MN5, and a first capacitor C1. Among them,

[0132] The gate of the fifth PMOS transistor MP5 is connected to the gate of the fifth NMOS transistor MN5 and serves as the input terminal of the second delay filter circuit. The drain of the fifth PMOS transistor MP5 is connected to the drain of the fifth NMOS transistor MN5 and serves as the output terminal of the second delay filter circuit. The source of the fifth PMOS transistor MP5 is connected to the power supply. The source of the fifth NMOS transistor MN5 is connected to the second terminal of the first capacitor C1 and grounded. The first terminal of the first capacitor C1 is connected to the drain of the fifth NMOS transistor MN5.

[0133] In practical applications, the aforementioned first delay filter circuit can adopt a structure similar to the second delay filter circuit in this embodiment.

[0134] For example, in specific scenarios, Figure 7 The structure shown employs an asymmetric RC delay circuit. The PMOS and NMOS transistors have different dimensions; the PMOS is an inverting ratio transistor with a smaller W / L ratio, while the NMOS has a larger W / L ratio. This results in a longer power-on delay during both rapid and slow power-on processes, and a shorter power-off delay during both rapid and slow power-off processes. This enhances the reset effect of the reset circuit in different reset scenarios.

[0135] like Figure 6a As shown, the second reset circuit further includes: a second Schmitt trigger 63 disposed between the output terminal of the second comparator circuit 53 and the second reset circuit; wherein,

[0136] The output of the second comparator circuit 53 is connected to the input of the second Schmitt trigger 63; the output of the second Schmitt trigger 63 is connected to the input of the second inverter 24.

[0137] In practical applications, during rapid power-down, slow power-up, and slow power-down processes, the second reset circuit obtains a reset signal after passing through the voltage detection module, the bandgap reference voltage source, and the second comparator circuit. This output reset signal is connected to the input of the second Schmitt trigger as the output signal of the second comparator circuit. After processing by the second Schmitt trigger, a reset signal with strong anti-interference capability is obtained and output stably, thereby further improving the accuracy and reliability of the reset.

[0138] The structure shown in the figure is only an example. In actual applications, there are other optional implementation methods. For example, the positions of the second delay filter circuit 62 and the second Schmitt trigger 63 can be interchanged.

[0139] In the reset device provided in this embodiment, the second reset circuit can output a second fast power-down reset signal, a second slow power-on reset signal, and a second slow power-down reset signal in scenarios of fast power-down, slow power-on, and slow power-down. This ensures that subsequent resets in different scenarios do not rely on transistor thresholds to achieve signal switching, thus improving reset accuracy.

[0140] Example 6

[0141] Figure 8a This is a schematic diagram of a reset device provided in Embodiment Six of this application. Figure 8a As shown, based on Embodiment 1, this embodiment further includes a sixth inverter 81 and a level conversion circuit 82. It should be noted that the illustration is merely an example and does not limit the quantity or position of the various structures.

[0142] In this circuit, the input of the sixth inverter 81 is connected to the output of the OR gate 25, and the output of the sixth inverter 81 is connected to the input of the level conversion circuit 82. The level conversion circuit 82 is used to perform level conversion on the reset signal output by the sixth inverter 81 before outputting it. In one example, the reset output terminal 27 includes: a reset output terminal POR_HV under high-voltage device environment and a reset output terminal POR_LV under low-voltage device environment.

[0143] Figure 8b This is a schematic diagram of the transient simulation results of a reset device provided in Embodiment Six of this application. Figure 8c for Figure 8b A magnified view of the rapid power-on to rapid power-off process. Figure 8a and 8b In the diagram, VDD represents the power supply, POR1 represents the output signal through the first reset circuit, POR2 represents the output signal through the second reset circuit, POR_HV represents the output signal obtained through the reset device under high-voltage device conditions, and POR_LV represents the output signal obtained through the reset device under low-voltage device conditions. Refer to the specific diagram for further details. Figure 8a The working process of the circuit structure is explained in detail below:

[0144] In a fast power-on scenario, a first fast power-on reset signal is obtained through the first reset circuit 21, while the second reset circuit 22 outputs a second fast power-on follow-up signal in response to the fast power-on. The output signals, after being inverted by the first inverter 23 and the second inverter 24, are logically ORed through the OR gate 25 to obtain the reset signal for the fast power-on scenario. For high-voltage device operating environments, a reset signal POR_HV is obtained through the third inverter 26, realizing the circuit reset function under high-voltage conditions and improving the high reliability of circuit reset. Similarly, for low-voltage device operating environments, the output signal obtained through the sixth inverter 81 is converted from a high-voltage device operating environment to a low-voltage device operating environment by the level conversion circuit 82, resulting in the reset signal POR_LV, realizing the circuit reset under low-voltage device conditions.

[0145] In a scenario of rapid power-down, a first rapid power-down follow-up signal is obtained through the first reset circuit 21, and a second rapid power-down reset signal is output in response to the rapid power-down. After being inverted by the first inverter 23 and the second inverter 24, the output signal is processed by the OR gate 25 to obtain the reset signal for the rapid power-down scenario. For high-voltage device operating environments, a reset signal POR_HV is obtained through the third inverter 26, achieving circuit reset under high-voltage device conditions, improving the reliability and accuracy of circuit reset. Similarly, for low-voltage device operating environments, the output signal is inverted by the sixth inverter 81, and after passing through the level conversion circuit 82, the device operating environment is converted from high voltage to low voltage, resulting in the reset signal POR_LV, achieving circuit reset under low-voltage device conditions, improving the reliability and accuracy of circuit reset.

[0146] In a slow power-on scenario, the first reset circuit 21 outputs a first slow power-on reset signal in response to the slow power-on, and the second reset circuit 22 outputs a second slow power-on reset signal in response to the slow power-on. After being inverted by the first inverter 23 and the second inverter 24, the output signals are processed by the OR gate 25 to obtain the reset signal for the slow power-on scenario. For high-voltage device operating environments, the third inverter 26 obtains the reset signal POR_HV, achieving circuit reset under high-voltage device conditions, improving the reliability and accuracy of circuit reset. Similarly, for low-voltage device operating environments, the output signal is inverted by the sixth inverter 81, and after passing through the level conversion circuit 82, the device operating environment is converted from high voltage to low voltage, resulting in the reset signal POR_LV, achieving circuit reset under low-voltage device conditions, improving the reliability and accuracy of circuit reset.

[0147] Similarly, in the slow power-down scenario, the first reset circuit 21 outputs a first slow power-down follow signal in response to the slow power-down, and the second reset circuit 22 obtains a second slow power-down reset signal in response to the slow power-down. After being inverted by the first inverter 23 and the second inverter 24 respectively, the output signals are processed by the OR gate 25 to obtain the reset signal for the slow power-down scenario. In this case, for high-voltage device operating environments, the third inverter 26 obtains the reset signal POR_HV, achieving circuit reset under high-voltage device conditions, improving the reliability and accuracy of circuit reset. Similarly, for low-voltage device operating environments, after being inverted by the sixth inverter 81, the output signal is processed by the level conversion circuit 82 to change the device operating environment from high voltage to low voltage, obtaining the reset signal POR_LV, achieving circuit reset under low-voltage device conditions, improving the reliability and accuracy of circuit reset.

[0148] The reset device provided in this embodiment obtains different output signals under different power supply voltages through a first reset circuit and a second reset circuit. Utilizing the logic relationship of inverters and OR gates, it obtains reset signals for different scenarios. Furthermore, based on the different operating voltage environments of the devices, an inverter is used to achieve circuit reset under high-voltage device environments; a level shifter is used to achieve circuit reset under low-voltage device environments. The reset device provided in this embodiment achieves circuit reset under different scenarios, and also achieves normal reset in both high-voltage and low-voltage domains, enriching the application scenarios of circuit reset.

[0149] Example 7

[0150] Figure 9 This is a schematic diagram of a power supply device provided in Embodiment Seven of this application. Figure 9 As shown, the power supply device includes: a power supply 91 and a reset device 92 from any of the aforementioned embodiments. Wherein,

[0151] The power supply 91 is connected to the reset device 92; the reset device 92 responds to the power supply 91 when it is powered on and off, and outputs a corresponding reset signal.

[0152] As illustrated in the diagram, during the rapid power-up process of power supply 91, the reset device responds to the rapid power-up of power supply 91 by outputting a reset signal POR1, thereby resetting the circuit in the scenario of rapid power-up.

[0153] During the rapid power-down process of power supply 91, the reset device responds to the rapid power-down of power supply 91 by outputting a reset signal POR2, thereby realizing circuit reset in the scenario of rapid power-down.

[0154] During the slow power-on process of power supply 91, the reset device responds to the fast power-on of power supply 91 by outputting a reset signal POR2, thereby realizing circuit reset in the slow power-on scenario.

[0155] During the slow power-down process of power supply 91, the reset device responds to the slow power-down of power supply 91 by outputting a reset signal POR2, thereby realizing circuit reset in the scenario of slow power-down.

[0156] The power supply device provided in this embodiment, by setting the voltage state of the power supply 91, enables the reset device to respond to the power supply's rapid power-on, rapid power-off, slow power-on, and slow power-off processes, correspondingly outputting a reset signal POR1 under the rapid power-on state, a reset signal POR2 under the rapid power-off state, a reset signal POR2 under the slow power-on state, and a reset signal POR2 under the slow power-off state, thus achieving the output of reset signals for different scenarios. The power supply provided in this embodiment is suitable for multiple reset circuits in different scenarios. By setting the response relationship of the reset device, effective reset in different scenarios can be achieved, improving the reliability and accuracy of reset.

[0157] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0158] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A reset device, characterized in that, include: The system comprises a first reset circuit, a second reset circuit, an OR gate, a first inverter, a second inverter, and a third inverter; wherein the first reset circuit and the second reset circuit are both connected to a power supply. The first reset circuit is configured to output a first fast power-on reset signal and a first slow power-on reset signal in response to fast power-on and slow power-on; and to output a first slow power-off follow signal and a first fast power-off follow signal in response to slow power-off and fast power-off. The second reset circuit is used to output a second slow power-on reset signal, a second slow power-off reset signal, and a second fast power-off reset signal in response to slow power-on, slow power-off, and fast power-off; and to output a second fast power-on follow signal in response to fast power-on. The input terminal of the first inverter is connected to the output terminal of the first reset circuit, and the output terminal of the first inverter is connected to the first input terminal of the OR gate; the input terminal of the second inverter is connected to the output terminal of the second reset circuit, and the output terminal of the second inverter is connected to the second input terminal of the OR gate; the output terminal of the OR gate is connected to the input terminal of the third inverter, and the output terminal of the third inverter is used to output a reset signal. The first reset circuit includes: a voltage generation circuit and a first comparison circuit; wherein, The input terminal of the voltage generation circuit is connected to a power supply. The voltage generation circuit is used to output a first voltage signal and a second voltage signal through a first output terminal and a second output terminal, respectively, based on the power supply. The magnitude relationship between the first voltage signal and the second voltage signal reflects the state of the power supply. The first input terminal of the first comparator circuit is connected to the first output terminal of the voltage generation circuit, and the second input terminal of the first comparator circuit is connected to the second output terminal of the voltage generation circuit; the output terminal of the first comparator circuit serves as the output terminal of the first reset circuit and is connected to the input terminal of the first inverter; the first comparator circuit is used to output a signal based on the first voltage signal and the second voltage signal. The voltage generation circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first impedance element; wherein, The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and grounded, and the source of the first PMOS transistor is connected to the source of the second PMOS transistor, serving as the input terminal of the first reset circuit and connected to the power supply. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the second NMOS transistor; the source of the first NMOS transistor is connected to the first terminal of the first impedance element, and the second terminal of the first impedance element is grounded; the source of the second NMOS transistor is grounded. The drain of the first NMOS transistor serves as the first output terminal of the voltage generation circuit and is connected to the first input terminal of the first comparator circuit; the drain of the second NMOS transistor serves as the second output terminal of the voltage generation circuit and is connected to the second input terminal of the first comparator circuit.

2. The reset device according to claim 1, characterized in that, The first comparison circuit includes: a first comparator and a fourth inverter; wherein, The first input terminal of the first comparator is connected to the first output terminal of the voltage generation circuit; the second input terminal of the first comparator is connected to the second output terminal of the voltage generation circuit; the output terminal of the first comparator is connected to the input terminal of the fourth inverter; the output terminal of the fourth inverter serves as the output terminal of the first comparator circuit and is connected to the input terminal of the first inverter. The voltage generation circuit is configured to output a first voltage signal and a second voltage signal after the power supply is powered on, wherein the first voltage signal is higher than the second voltage signal; and to output a first voltage signal and a second voltage signal after the power supply is powered off, wherein the first voltage signal is lower than the second voltage signal. The first comparator is configured to output a low-level signal when the first voltage signal is higher than the second voltage signal, and to output a high-level signal when the first voltage signal is lower than the second voltage signal; the fourth inverter is configured to output an inverted signal based on the signal output by the first comparator.

3. The reset device according to claim 2, characterized in that, The first comparator includes: a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein, The source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the power supply. The gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the third NMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and serves as the output terminal of the first comparator, which is connected to the input terminal of the fourth inverter. The source of the third NMOS transistor and the source of the fourth NMOS transistor are both grounded; the gate of the fourth NMOS transistor serves as the first input terminal of the first comparator and is connected to the first output terminal of the voltage generation circuit; the gate of the third NMOS transistor serves as the second input terminal of the first comparator and is connected to the second output terminal of the voltage generation circuit.

4. The reset device according to any one of claims 1-3, characterized in that, The first reset circuit further includes: a first delay filter circuit disposed between the output terminal of the first comparator circuit and the first reset circuit; wherein, The input terminal of the first delay filter circuit is connected to the output terminal of the first comparator circuit, and the output terminal of the first delay filter circuit is connected to the input terminal of the first inverter.

5. The reset device according to any one of claims 1-3, characterized in that, The first reset circuit further includes: a first Schmitt trigger disposed between the output terminal of the first comparator circuit and the first reset circuit; wherein, The output of the first comparator circuit is connected to the input of the first Schmitt trigger; the output of the first Schmitt trigger is connected to the input of the first inverter.

6. The reset device according to claim 1, characterized in that, The second reset circuit includes: a voltage detection module, a bandgap reference voltage source, and a second comparison circuit; wherein, The voltage detection module is connected to the power supply and is used to output a detection voltage based on the power supply; the bandgap reference voltage source is used to provide a reference voltage; wherein, the relationship between the detection voltage and the reference voltage reflects the state of the power supply; The first input terminal of the second comparator circuit is connected to the output terminal of the voltage detection module, and the second input terminal of the second comparator circuit is connected to the output terminal of the bandgap reference voltage source; the output terminal of the second comparator circuit is connected to the input terminal of the second inverter; the second comparator circuit is used to output a signal based on the detected voltage and the reference voltage.

7. The reset device according to claim 6, characterized in that, The voltage detection module includes: a second impedance element and a third impedance element; wherein... The first end of the second impedance element is connected to the power supply; the second end of the second impedance element is connected to the first end of the third impedance element, serving as the output end of the voltage detection module and connected to the first input end of the second comparison circuit; the second end of the third impedance element is grounded.

8. The reset device according to claim 6, characterized in that, The second comparison circuit includes: a second comparator and a fifth inverter; wherein, The inverting input of the second comparator is connected to the output of the voltage detection module, and the non-inverting input of the second comparator is connected to the output of the bandgap reference voltage source; the input of the fifth inverter is connected to the output of the second comparator; the output of the fifth inverter serves as the output of the second comparator circuit.

9. The reset device according to any one of claims 6-8, characterized in that, The second reset circuit further includes: a second delay filter circuit disposed between the output terminal of the second comparator circuit and the output terminal of the second reset circuit; wherein, The input terminal of the second delay filter circuit is connected to the output terminal of the second comparator circuit, and the output terminal of the second delay filter circuit is connected to the input terminal of the second inverter.

10. The reset device according to any one of claims 6-8, characterized in that, The second reset circuit further includes: a second Schmitt trigger disposed between the output terminals of the second comparator circuit and the second reset circuit; wherein, The output of the second comparator circuit is connected to the input of the second Schmitt trigger; the output of the second Schmitt trigger is connected to the input of the second inverter.

11. The reset device according to claim 1, characterized in that, The reset device further includes: a sixth inverter and a level conversion circuit; wherein... The input terminal of the sixth inverter is connected to the output terminal of the OR gate, and the output terminal of the sixth inverter is connected to the input terminal of the level conversion circuit. The level conversion circuit is used to perform level conversion on the reset signal output by the sixth inverter and then output it.

12. A power supply device, characterized in that, include: Power supply, and a reset device as described in any one of claims 1-11; wherein, The power supply is connected to the reset device; The reset device responds to the power supply's power-on and power-off states by outputting a corresponding reset signal.

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