Writing and reading method, processor chip, storage medium and electronic device

Abstract

The present disclosure provides a method for writing data into a storage device, the method comprising: writing table writing data to be written into a corresponding main storage module; using a first predetermined algorithm to operate the table writing data in each of the target main storage modules to obtain an auxiliary value, wherein when operating any one of the target main storage modules, the first predetermined algorithm is used to operate the table writing data stored in the target main storage module and the corresponding table writing data stored in at least one of the other main storage modules other than the target main storage module, and the inverse operation of the first predetermined algorithm is used to operate any auxiliary value, so that the table writing data involved in the operation can be obtained; and the auxiliary value is stored in the corresponding auxiliary storage module. The present disclosure also provides a reading method, a computer-readable storage medium, a processing chip, and an electronic device.

Description

Technical Field

[0001] The present invention relates to the field of storage devices, and in particular, to a method for writing data into a storage device, a method for reading data from a storage device, a processor chip, a computer-readable storage medium and an electronic device. Background Art

[0002] As society's requirements for the amount of interactive data and the speed of interaction during information exchange gradually increase, small size and high performance have become important indicators for measuring network equipment. Correspondingly, the processing chips of processors in network equipment are also pursuing small size and high performance.

[0003] Taking the random access memory (RAM) in the processing chip as an example, due to the limitation of RAM bandwidth, when the RAM has only one read port, the table lookup performance can only reach 1 line speed, that is, only the storage value stored at one address can be read in one clock cycle, which limits the performance of the processing chip.

[0004] Therefore, how to improve the performance of processing chips has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0005] The present disclosure provides a method for writing data into a storage device, a method for reading data from a storage device, a storage device, a computer-readable storage medium, and an electronic device.

[0006] As one aspect of the present disclosure, a method for writing data into a storage device is provided, wherein the storage device includes a plurality of storage modules, the plurality of storage modules include a plurality of main storage modules and at least one auxiliary storage module, the plurality of main storage modules include at least one target main storage module, and each of the target main storage modules corresponds to an auxiliary storage module, the method comprising:

[0007] Writing the table writing data to be written into the corresponding main storage module;

[0008] Using a first predetermined algorithm to operate on the table writing data in each of the target main storage modules to obtain an auxiliary value, wherein when operating on any one of the target main storage modules, using the first predetermined algorithm to operate on the table writing data stored in the target main storage module and corresponding table writing data stored in at least one of other main storage modules other than the target main storage module, and using an inverse operation of the first predetermined algorithm to operate on any auxiliary value, the table writing data involved in the operation can be obtained;

[0009] The auxiliary value is stored in a corresponding auxiliary storage module.

[0010] Optionally, according to the writing method of claim 1, after all target main storage modules have been operated using the first predetermined algorithm, the data stored in all the main storage modules participate in the operation.

[0011] Optionally, the plurality of storage modules are formed into a plurality of storage modules in an N*N array, in the first (N-1) rows of storage modules, each row of storage modules includes N main storage modules and one auxiliary storage module, the Nth row of storage modules includes N auxiliary storage modules, N is a positive integer not less than 3, the auxiliary values ​​include a first auxiliary value, a second auxiliary value and a third auxiliary value,

[0012] In the step of using a first predetermined algorithm to operate the table writing data in each of the target main storage modules to obtain an auxiliary value, for the table writing data stored in any address of any of the target main storage modules, the step of obtaining the auxiliary value includes:

[0013] Using the first predetermined algorithm, a table write data stored in a current address of a current target main storage module and table write data stored in corresponding addresses of all other main storage modules located in the same row as the target main storage module are operated to obtain a first auxiliary value;

[0014] Using the first predetermined algorithm, the table writing data stored in the current address of the current target main storage module and the table writing values ​​stored in the corresponding addresses of all other main storage modules located in the same column as the current target main storage module are operated to obtain a second auxiliary value;

[0015] Using the first predetermined algorithm, the table writing data stored in the address of the current target main storage module and the table writing data stored in the corresponding addresses of all the main storage modules except all the target main storage modules, and the data stored in the corresponding addresses of all the auxiliary storage modules except the auxiliary storage module corresponding to the current target main storage module are operated to obtain a third auxiliary value;

[0016] Furthermore, the first auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module, the second auxiliary value is stored in an auxiliary storage module located in the same column as the target main storage module, and the third auxiliary value is stored in a storage module in the Nth row and the Nth column.

[0017] Optionally, in the array, all the master storage modules in the first row are the target master storage modules, and all the master storage modules in the first column are the target master storage modules.

[0018] Optionally, the plurality of storage modules include a plurality of main storage modules formed into a three-dimensional cube of an M*M*M array and three 3*M2 auxiliary storage modules, from the perspective of each coordinate system plane, on the XY plane, each row of storage modules includes M main storage modules and one auxiliary storage module, on the XZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module, on the YZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module, M is a positive integer not less than 1, and the auxiliary values ​​include a first auxiliary value, a second auxiliary value and a third auxiliary value,

[0019] In the step of using a first predetermined algorithm to operate the table writing data in each of the target main storage modules to obtain an auxiliary value, for the table writing data stored in any address of any of the target main storage modules, the step of obtaining the auxiliary value includes:

[0020] Using the first predetermined algorithm, the table writing data stored in the current address of the current target main storage module and the table writing data stored in the corresponding addresses of all other main storage modules located in the same row as the target main storage module in the XY plane are operated to obtain a first auxiliary value;

[0021] Using the first predetermined algorithm, the table writing data stored in the current address of the current target main storage module and the table writing values ​​stored in the corresponding addresses of all other main storage modules located in the same row as the target main storage module in the XZ plane are operated to obtain a second auxiliary value;

[0022] Using the first predetermined algorithm, the table writing data stored in the current address of the current target main storage module and the table writing values ​​stored in the corresponding addresses of all other main storage modules located in the same row as the target main storage module in the YZ plane are operated to obtain a third auxiliary value;

[0023] Furthermore, the first auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module in the XY plane, the second auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module in the XZ plane, and the third auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module in the YZ plane.

[0024] Optionally, the address identification information corresponding to all table writing data participating in the same operation using the first predetermined algorithm is the same.

[0025] Optionally, the first predetermined algorithm is an XOR operation.

[0026] Optionally, when the table writing data stored in the main storage module participating in the budget changes, the writing method further includes:

[0027] Use the changed table write data to participate in the calculation to obtain the corresponding auxiliary value;

[0028] Replace the stored auxiliary value at the corresponding address with the recalculated auxiliary value.

[0029] As a second aspect of the present disclosure, a method for reading data from a storage device is provided, wherein the storage device includes a plurality of storage modules, the plurality of storage modules include a plurality of main storage modules and at least one auxiliary storage module, the plurality of main storage modules include at least one target main storage module, each of the target main storage modules corresponds to an auxiliary storage module, the storage device stores data written by the writing method provided by the first aspect of the present disclosure, and the reading method includes:

[0030] receiving at least one read instruction;

[0031] Determine the location of the table writing data to be read according to the read instruction;

[0032] When the data to be read by at least two read instructions are stored in the same main storage module, and the addresses pointed to by the read instructions correspond to auxiliary values, for the at least two read instructions, the reading method further includes:

[0033] For one of the at least two instructions being a read instruction, directly reading corresponding table writing data from the main storage module;

[0034] For other instructions of the at least two instructions, respectively read the auxiliary value stored in the corresponding address of the auxiliary storage module corresponding to the main storage module, and the table writing data in the corresponding address of the main storage module participating in the auxiliary value calculation;

[0035] Each of the auxiliary values ​​is operated using a second predetermined algorithm and each of the table writing data to obtain the table writing data stored in the main storage module and stored in the address corresponding to the other instructions, wherein the second predetermined algorithm is an inverse operation of the first predetermined algorithm.

[0036] Optionally, the first predetermined algorithm is an exclusive OR operation, and the second predetermined algorithm is an exclusive OR operation.

[0037] As a third aspect of the present disclosure, a computer-readable storage medium is provided, on which an executable program is stored. When the executable program is called, it can implement the writing method provided by the first aspect of the present disclosure and / or the reading method provided by the second aspect of the present disclosure.

[0038] As a third aspect of the present disclosure, a processor chip is provided, comprising a storage device having at least one write port and a plurality of read ports and a computing module,

[0039] The storage device includes a plurality of storage modules, the plurality of storage modules include a first write port, a plurality of first read ports, a plurality of main storage modules and at least one auxiliary storage module, each of the auxiliary storage modules corresponds to a predetermined number of main storage modules, and each of the main storage modules corresponds to at least one auxiliary storage module, and each storage module has a read port and a write port;

[0040] The operation module includes a storage unit and a processing unit. The storage unit stores an executable program. When the executable program is called by the processing unit, it can implement the writing method provided by the first aspect of the present disclosure and the reading method provided by the second aspect of the present disclosure.

[0041] Optionally, the storage depth of the primary storage module is the same as the storage depth of the auxiliary storage module.

[0042] Optionally, the plurality of storage modules are formed into a plurality of storage modules in an N*N array, and in the first (N-1) rows of storage modules, each row of storage modules includes N main storage modules and one auxiliary storage module, and the Nth row of storage modules includes N auxiliary storage modules.

[0043] Optionally, N is 5, the storage device has four read ports, and the storage depth of each of the main storage modules is 1 / 16 of the total storage depth of all the main storage modules.

[0044] Optionally, the plurality of storage modules include a plurality of main storage modules formed into a three-dimensional cube of an M*M*M array and three 3*M 2 auxiliary storage modules. From the perspective of each coordinate system plane, on the XY plane, each row of storage modules includes M main storage modules and one auxiliary storage module. On the XZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module. On the YZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module, and M is a positive integer not less than 1.

[0045] As a fifth aspect of the present disclosure, an electronic device is provided, wherein the electronic device includes the above-mentioned processor chip provided by the present disclosure.

[0046] In the present disclosure, for each table writing data written into the main storage module, the table writing data is not only directly stored in the target address of the target main storage module, but also stored in the auxiliary storage module in another form (i.e., the result obtained after the operation of the first predetermined algorithm). If multiple read instructions for reading the same main storage module are received at the same time, one of the read instructions can be controlled to directly read the relevant data in the auxiliary storage module, and then the table writing data participating in the operation, except for the table writing data stored in the main storage module corresponding to the read instruction, can be used to perform the inverse operation of the first predetermined algorithm, so as to obtain the data required to be read by the read instruction. It can be seen that the use of the writing method provided by the present disclosure, in conjunction with the corresponding reading method, can realize multi-line speed reading of data in the storage device.

[0047] In the present disclosure, in order to achieve multiple table lookup line speeds, the table write data is not directly stored in the auxiliary storage module at the same time, but is stored in the auxiliary storage module after the first operation. Each operation result is related to the data in multiple main storage modules. By storing an auxiliary value, it is realized to store data of multiple addresses in one address, thereby reducing the storage space required for backup storage of data in multiple addresses. Obviously, in the writing method provided by the present disclosure, in order to achieve multi-line speed reading, less storage space is used, which is conducive to the miniaturization and integration of the storage device and the chip including the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a flowchart of an implementation of the writing method provided by the first aspect of the present disclosure;

[0049] Figure 2 is a flowchart of an implementation of step S120;

[0050] Figure 3 is a schematic diagram of one embodiment of a storage device;

[0051] Figure 4 is a schematic diagram of another embodiment of a storage device;

[0052] Figure 5 is a flowchart of an implementation of the reading method provided by the second aspect of the present disclosure;

[0053] Figure 6 It is a logic diagram for obtaining the value of the data stored at address 1 of RAM0 in a specific implementation mode provided by the present disclosure;

[0054] Figure 7 It is a logic diagram for obtaining the value of the data stored at address 2 of RAM0 in a specific implementation mode provided by the present disclosure;

[0055] Figure 8 It is a logic diagram for obtaining the value of the data stored at address 2 of RAM0 in a specific implementation manner provided by the present disclosure. DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the following detailed description is given of a method for writing data into a storage device, a method for reading data from a storage device, a storage device, a computer-readable storage medium, and an electronic device provided by the present disclosure in conjunction with the accompanying drawings.

[0057] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0058] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0059] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0060] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0062] The storage device involved in the present disclosure includes multiple storage modules, which include at least two types of storage modules, namely main storage modules and auxiliary storage modules. Each auxiliary storage module corresponds to a predetermined number of main storage modules, and each main storage module corresponds to at least one auxiliary storage module.

[0063] As a first aspect of the present disclosure, a method for writing data into a storage device is provided, such as Figure 1 As shown, the method includes:

[0064] In step S110, the table writing data to be written is written into the corresponding main storage module;

[0065] In step S120, the table writing data in each of the target main storage modules is operated by using a first predetermined algorithm to obtain an auxiliary value, wherein when operating on any one of the target main storage modules, the table writing data stored in the target main storage module and the corresponding table writing data stored in at least one of the other main storage modules other than the target main storage module are operated by using the first predetermined algorithm, and any auxiliary value is operated by using an inverse operation of the first predetermined algorithm to obtain the table writing data involved in the operation;

[0066] In step S130, the auxiliary value is stored in a corresponding auxiliary storage module.

[0067] It should be noted that, in the present disclosure, the main storage module is used to store table writing data, while the auxiliary storage module is used to store auxiliary values.

[0068] In the present disclosure, for each table writing data written into the main storage module, the table writing data is not only directly stored in the target address of the target main storage module, but also stored in the auxiliary storage module in another form (i.e., the result obtained after the operation of the first predetermined algorithm). If multiple read instructions for reading the same main storage module are received at the same time, one of the read instructions can be controlled to directly read the relevant data in the auxiliary storage module, and then the table writing data participating in the operation, except for the table writing data stored in the main storage module corresponding to the read instruction, can be used to perform the inverse operation of the first predetermined algorithm, so as to obtain the data required to be read by the read instruction. It can be seen that the use of the writing method provided by the present disclosure, in conjunction with the corresponding reading method, can realize multi-line speed reading of data in the storage device.

[0069] It should be noted that any storage module can only be accessed by one read instruction in the same clock cycle, while for the storage device, multiple read instructions can be allowed to access different storage modules in the same clock cycle.

[0070] In the present disclosure, there is no special limitation on the "corresponding table writing data", as long as it can be used to determine the address of the table writing data in which the auxiliary value corresponding to the table writing data to be read is calculated when the table writing data to be read is stored in the main storage module in the subsequent reading. For example, the address where the "corresponding table writing data" is stored in the main storage module to which it belongs is the same as the address where the "table writing data to be written" is about to be written.

[0071] In the present disclosure, each auxiliary value is a result of a plurality of table writing data stored in the storage device being operated by a first predetermined algorithm. Therefore, for any table writing data (for ease of description, it may be referred to as table writing data A), the table writing data A may be obtained by the inverse operation of the first operation, provided that the operation mode of the inverse operation of the first operation and other table writing data that participate in the operation together with the table writing data A are known.

[0072] Therefore, under the premise of receiving two read instructions for respectively reading data at different addresses in the same main storage module, the corresponding table write data in the storage module corresponding to one read instruction can be directly read in the main storage module, and the table write data required by the other read instruction can be obtained by reading the auxiliary value corresponding to the address pointed to by another read instruction stored in the auxiliary storage module, and the data in other main storage modules participating in the auxiliary value operation, using the inverse operation of the first operation.

[0073] For example, two read requests for accessing the main storage module numbered 0 are received, one of which is to read the data stored at address 1 in the main storage module numbered 0, and the other is to read the address stored at address 2 in the main storage module numbered 0.

[0074] Then, a read request is controlled to directly read the data stored in address No. 1 of the main storage module numbered 0, and another read request is used to read the auxiliary value stored in the address corresponding to address No. 2 in the auxiliary storage module corresponding to the main storage module numbered 0, and the data stored in the corresponding addresses in other main storage modules participating in the auxiliary value calculation are read, and then the inverse operation of the first predetermined algorithm is performed on the auxiliary value and the data used to obtain the auxiliary value, so that the address stored in address No. 2 in the main storage module numbered 0 can be obtained.

[0075] In the related art, in order to increase the speed of reading data, an additional storage module is added on the basis of the original storage module of the processor chip. However, this method often increases the area occupied by the storage device in the processor chip, thereby increasing the volume of the processor chip, which is not conducive to the miniaturization of the processor chip. For example, in order to make the RAM of the processor chip meet the four-times table lookup line speed, it is necessary to add three RAMs with the same storage depth as the original RAM on the basis of the original RAM. When writing data, the same data is written into the four RAMs respectively (that is, one data is copied four times). Each RAM corresponds to a read port (that is, each RAM is a 1r1w RAM), so the storage device including four RAMs can achieve four-times table lookup line speed.

[0076] In the present disclosure, in order to achieve multiple table lookup line speeds, the table write data is not directly stored in the auxiliary storage module at the same time, but is stored in the auxiliary storage module after the first operation. Each operation result is related to the data in multiple main storage modules. By storing an auxiliary value, it is realized to store data of multiple addresses in one address, thereby reducing the storage space required for backup storage of data in multiple addresses. Obviously, in the writing method provided by the present disclosure, in order to achieve multi-line speed reading, less storage space is used, which is conducive to the miniaturization and integration of the storage device and the chip including the storage device.

[0077] For example, one auxiliary value may be related to four table writing data, which is equivalent to using one address of the auxiliary storage module to store four table writing data. However, in the solution of the related art, the four backup table writing data can only be written into four addresses.

[0078] In the present disclosure, there is no special limitation on the number of main storage modules involved in the operation, as long as multi-line speed access can be achieved to the data stored in at least some of the storage modules.

[0079] In order to improve the processing capability of the processor including the storage device, optionally, after all target main storage modules are operated using the first predetermined algorithm, the data stored in all main storage modules participate in the operation. That is, all auxiliary values ​​involve the data stored in all main storage modules, so that multi-line speed access can be achieved for all storage modules.

[0080] In the present disclosure, there is no special limitation on which read instruction among multiple read instructions simultaneously accessing the same main storage module directly reads the data in the main storage module. For example, the read instruction pointing to the smallest address number can be used to directly read the data stored in the main storage module. For example, two read instructions simultaneously access the main storage module 1, one read instruction reads the data in address 1, and the other read instruction reads the data in address 2. Then, the read instruction that reads the data in address 1 directly reads the data stored in the main storage module. Of course, the present disclosure is not limited to this, and a read instruction can also be randomly selected from multiple read instructions to directly read data.

[0081] The data stored in each main storage module of the non-target main storage module (for the convenience of description, it can be referred to as the target external main storage module) participates in the calculation of the auxiliary value. Therefore, when multiple read instructions simultaneously read the data stored in different addresses in a target external main storage module, one read instruction can first read the data in the target external main storage module, and then read the auxiliary value participated in the calculation of the data stored in the address pointed to by another read instruction, as well as the data in the target main storage module participating in the calculation of the auxiliary value, and other data stored in the non-current target external main storage module participating in the calculation of the auxiliary value, and use the auxiliary value and these data to perform the inverse operation of the first operation, so as to obtain the data stored in the address pointed to by the other read instruction.

[0082] In the present disclosure, the specific form and structure of the storage device are not particularly limited. As an optional implementation, the plurality of storage modules are formed into a plurality of storage modules in an N*N array, and in the first (N-1) rows of storage modules, each row of storage modules includes N main storage modules and one auxiliary storage module, and the Nth row of storage modules includes N auxiliary storage modules, where N is a positive integer not less than 3. Accordingly, the auxiliary values ​​include a first auxiliary value, a second auxiliary value, and a third auxiliary value.

[0083] In step S120 of calculating the table write data in each of the target main storage modules using the first predetermined algorithm to obtain the auxiliary value, as shown in FIG. Figure 2 As shown, for the table write data stored in any address (hereinafter referred to as the current address) of any target main storage module (hereinafter referred to as the current target main storage module), the step of obtaining the auxiliary value includes:

[0084] In step S121, the first predetermined algorithm is used to calculate the table writing data stored in the current address of the current target main storage module and the table writing data stored in the corresponding addresses of all other main storage modules located in the same row as the current target main storage module to obtain a first auxiliary value;

[0085] In step S122, the first predetermined algorithm is used to calculate the table writing data stored in the address of the current target main storage module and the table writing values ​​stored in the corresponding addresses of all other main storage modules located in the same column as the current target main storage module to obtain a second auxiliary value;

[0086] In step S123, the first predetermined algorithm is used to operate the table write data stored in the current address of the current target main storage module and the table write data stored in the corresponding addresses of all main storage modules except all target main storage modules, and the data stored in the corresponding addresses of all auxiliary storage modules except the auxiliary storage module located in the same row as the current target main storage module and the storage module in the Nth row and Nth column, so as to obtain a third auxiliary value.

[0087] Furthermore, the first auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module, the second auxiliary value is stored in an auxiliary storage module located in the same column as the target main storage module, and the third auxiliary value is stored in the storage module in the Nth row and Nth column (it is easy to understand that this storage module is an auxiliary storage module).

[0088] The above implementation supports the situation where four access instructions simultaneously access the same main storage module. That is, one of the four access instructions directly accesses the corresponding main storage module. In order to obtain the data required by the other three access instructions, the corresponding first auxiliary value, the table writing data of other main storage modules participating in the first auxiliary value calculation, the corresponding second auxiliary value, the table writing data of other main storage modules participating in the second auxiliary value calculation, the corresponding third auxiliary value, the table writing data of other main storage modules participating in the third auxiliary value calculation, and the data stored in the auxiliary storage module participating in the third auxiliary value calculation can be read respectively. Then, the corresponding inverse operation is performed to obtain the data required by the other three access instructions.

[0089] In the present disclosure, there is no special limitation on the position of the target main storage module in the storage device. For the convenience of calculation, optionally, the first N-1 main storage modules in the first row of the N*N array can be used as the target main storage modules, and the first N-1 main storage modules in the first column can be used as the target main storage modules.

[0090] In the present disclosure, there is no special limitation on the "corresponding address". As an optional implementation, the "corresponding address" may be an address that satisfies a specific mapping relationship with the address where the table writing data to be calculated is stored, or may be an address whose identification information is the same as the table writing data to be calculated. As an optional implementation, the "identification information" of the address may be the number of the address in the corresponding storage module.

[0091] To facilitate calculation, optionally, all table writing data participating in the same operation using the first predetermined algorithm respectively correspond to the same address identification information.

[0092] In the present disclosure, there is no special limitation on the specific value of N. As an optional implementation, N may be 5. Taking N as 5 as an example, the writing method provided by the present disclosure is described in detail below.

[0093] like Figure 3 As shown in , the storage device includes 16 main storage modules and 9 auxiliary storage modules, which are arranged in a 5*5 array. The 16 main storage modules are respectively main storage module 0, main storage module 1, main storage module 2, main storage module 3, main storage module 4, main storage module 5, main storage module 6, main storage module 7, main storage module 8, main storage module 9, main storage module 10, main storage module 11, main storage module 12, main storage module 13, main storage module 14, and main storage module 15. The 9 auxiliary storage modules are respectively auxiliary storage module XOR0, auxiliary storage module XOR1, auxiliary storage module XOR2, auxiliary storage module XOR3, auxiliary storage module XOR4, auxiliary storage module XOR5, auxiliary storage module XOR6, auxiliary storage module XOR7, and auxiliary storage module XOR8.

[0094] In the array, main storage module 0, main storage module 1, main storage module 2, main storage module 3, and auxiliary storage module XOR0 are located in the first row, main storage module 4, main storage module 5, main storage module 6, main storage module 7, and auxiliary storage module XOR1 are located in the second row, main storage module 8, main storage module 9, main storage module 10, main storage module 11, and auxiliary storage module XOR2 are located in the third row, main storage module 12, main storage module 13, main storage module 14, main storage module 15, and auxiliary storage module XOR3 are located in the fourth row, and auxiliary storage module XOR4, auxiliary storage module XOR5, auxiliary storage module XOR6, auxiliary storage module XOR7, and auxiliary storage module XOR8 are located in the fifth row.

[0095] As an optional implementation, the main storage module and the auxiliary storage module can both be RAM. Of course, the main storage module and the auxiliary storage module can also be other forms of storage devices.

[0096] In the described embodiment, the main storage modules in the first row (including main storage module 0, main storage module 1, main storage module 2, main storage module 3) and the main storage modules in the first column (including main storage module 0, main storage module 4, main storage module 8, main storage module 12) are the target main storage modules.

[0097] The writing method includes three stages: a table data writing stage (corresponding to step S110 ), an auxiliary value calculation stage (corresponding to step S120 ), and an auxiliary value writing stage (corresponding to step S130 ).

[0098] In the table writing data writing phase, the data to be written is written into the corresponding address in the corresponding main storage module (which may be the target main storage module or may not be the target main storage module).

[0099] Taking the first auxiliary value corresponding to the 0# address of each storage module as an example, the auxiliary value calculation stage and the auxiliary value writing stage are introduced:

[0100] The table write data in the 0# address of the main storage module 0 is operated with the table write data in the 0# address of other main storage modules located in the same row as the main storage module 0 (including the 0# address of the main storage module 1, the 0# address of the main storage module 2, and the 0# address of the main storage module 3) by using the first predetermined algorithm to obtain the first auxiliary value corresponding to the 0# address, and the first auxiliary value is stored in the 0# address of the auxiliary storage module XOR0.

[0101] The table write data in the 0# address of the main storage module 1 is calculated by using the first predetermined algorithm with the table write data in the 0# address of other main storage modules located in the same row as the main storage module 1 (including the 0# address of the main storage module 0, the 0# address of the main storage module 2, and the 0# address of the main storage module 3) to obtain a first auxiliary value corresponding to the 0# address, and the first auxiliary value is stored in the 0# address of the auxiliary storage module XOR1.

[0102] The table write data in the 0# address of the main storage module 2 is operated with the table write data in the 0# address of other main storage modules located in the same row as the main storage module 2 (including the 0# address of the main storage module 1, the 0# address of the main storage module 2, and the 0# address of the main storage module 3) by using the first predetermined algorithm to obtain the first auxiliary value corresponding to the 0# address, and the first auxiliary value is stored in the 0# address of the auxiliary storage module XOR2.

[0103] The first predetermined algorithm is used to operate the table write data in the 0# address of the main storage module 3 and the table write data in the 0# address of other main storage modules located in the same row as the main storage module 3 (including the 0# address of the main storage module 0, the 0# address of the main storage module 1, and the 0# address of the main storage module 2) to obtain a first auxiliary value corresponding to the 0# address, and the first auxiliary value is stored in the 0# address of the auxiliary storage module XOR3.

[0104] Taking the second auxiliary value corresponding to the 0# address of each storage module as an example, the auxiliary value calculation stage and the auxiliary value access stage are introduced:

[0105] The first predetermined algorithm is used to operate the table write data in the 0# address of the main storage module 0 (including the 0# address of the main storage module 4, the 0# address of the main storage module 8, and the 0# address of the main storage module 12) and the table write data in the 0# address of other main storage modules located in the same column as the main storage module 0 to obtain a second auxiliary value corresponding to the 0# address, and the second auxiliary value is stored in the 0# address of the auxiliary storage module XOR4.

[0106] The first predetermined algorithm is used to operate the table write data in the 0# address of the main storage module 4 and the table write data in the 0# address of other main storage modules located in the same column as the main storage module 0 (including the 0# address of the main storage module 0, the 0# address of the main storage module 8, and the 0# address of the main storage module 12) to obtain a second auxiliary value corresponding to the 0# address, and the second auxiliary value is stored in the 0# address of the auxiliary storage module XOR5.

[0107] The first predetermined algorithm is used to operate the table write data in the 0# address of the main storage module 8 and the table write data in the 0# address of other main storage modules located in the same column as the main storage module 0 (including the 0# address of the main storage module 0, the 0# address of the main storage module 4, and the 0# address of the main storage module 12) to obtain a second auxiliary value corresponding to the 0# address, and the second auxiliary value is stored in the 0# address of the auxiliary storage module XOR6.

[0108] The first predetermined algorithm is used to operate the table write data in the 0# address of the main storage module 12 and the table write data in the 0# address of other main storage modules located in the same column as the main storage module 0 (including the 0# address of the main storage module 0, the 0# address of the main storage module 4, and the 0# address of the main storage module 8) to obtain a second auxiliary value corresponding to the 0# address, and the second auxiliary value is stored in the 0# address of the auxiliary storage module XOR7.

[0109] The following takes the third auxiliary value corresponding to the 0# address of each storage module as an example to introduce the auxiliary value calculation stage and the auxiliary value access stage:

[0110] A first predetermined algorithm is used to calculate the table writing data in the 0# address of the main storage module 0 and the table writing data stored in the corresponding addresses of all the main storage modules except all the target main storage modules (including the 0# address of the main storage module 5, the 0# address of the main storage module 6, the 0# address of the main storage module 7, the 0# address of the main storage module 9, the 0# address of the main storage module 10, the 0# address of the main storage module 11, the 0# address of the main storage module 13, the 0# address of the main storage module 14, and the 0# address of the main storage module 15), and the data stored in the corresponding addresses of all the auxiliary storage modules except the auxiliary storage module corresponding to the current target main storage module (including the 0# address of the auxiliary storage module 1, the 0# address of the auxiliary storage module 2, the 0# address of the auxiliary storage module 3, the 0# address of the auxiliary storage module 5, the 0# address of the auxiliary storage module 6, and the 0# address of the auxiliary storage module 7) to obtain a third auxiliary value corresponding to the 0# address, and the third auxiliary value is stored in the 0# address of the auxiliary storage module XOR8.

[0111] The calculation method of the third auxiliary value corresponding to the addresses of other main storage modules is similar to the calculation method of the third auxiliary value corresponding to the 0# address of the main storage module 0 mentioned above, and will not be repeated here.

[0112] Furthermore, the calculation method of the auxiliary values ​​corresponding to other addresses is similar to the calculation method of the auxiliary values ​​corresponding to the 0# address, and will not be repeated here.

[0113] In the writing method mentioned above, the multiple storage modules of the storage device form a two-dimensional array. As another embodiment of the present disclosure, the multiple storage modules of the storage device can also form a three-dimensional array.

[0114] Specifically, Figure 4 As shown, the plurality of storage modules are formed into a plurality of main storage modules of an M*M*M array and a 3*M 2 auxiliary storage modules, from the perspective of each coordinate system plane, on the XY plane, each row of storage modules includes M main storage modules and one auxiliary storage module, on the XZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module, on the YZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module, M is a positive integer not less than 1, and the auxiliary values ​​include a first auxiliary value, a second auxiliary value and a third auxiliary value,

[0115] In the step of using a first predetermined algorithm to operate the table writing data in each of the target main storage modules to obtain an auxiliary value, for the table writing data stored in any address of any of the target main storage modules, the step of obtaining the auxiliary value includes:

[0116] Using the first predetermined algorithm, the table writing data stored in the current address of the current target main storage module and the table writing data stored in the corresponding addresses of all other main storage modules located in the same row as the target main storage module in the XY plane are operated to obtain a first auxiliary value;

[0117] Using the first predetermined algorithm, the table writing data stored in the current address of the current target main storage module and the table writing values ​​stored in the corresponding addresses of all other main storage modules located in the same row as the target main storage module in the XZ plane are operated to obtain a second auxiliary value;

[0118] Using the first predetermined algorithm, the table writing data stored in the current address of the current target main storage module and the table writing values ​​stored in the corresponding addresses of all other main storage modules located in the same row as the target main storage module in the YZ plane are operated to obtain a third auxiliary value;

[0119] Furthermore, the first auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module in the XY plane, the second auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module in the XZ plane, and the third auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module in the YZ plane.

[0120] exist Figure 4 In the embodiment shown in , M is 2, and the storage device includes 8 main storage modules and 12 auxiliary storage modules. The 8 main storage modules are arranged in a 2*2*2 three-dimensional array, and the 8 main storage modules are respectively main storage module 0, main storage module 1, main storage module 2, main storage module 3, main storage module 4, main storage module 5, main storage module 6, main storage module 7, auxiliary storage module XOR0, auxiliary storage module XOR1, auxiliary storage module XOR2, auxiliary storage module XOR3, auxiliary storage module XOR4, auxiliary storage module XOR5, auxiliary storage module XOR6, auxiliary storage module XOR7, auxiliary storage module XOR8, auxiliary storage module XOR9, auxiliary storage module XOR10, and auxiliary storage module XOR11.

[0121] In the present disclosure, there is no special limitation on the first predetermined algorithm, as long as the first predetermined algorithm has an inverse operation. In order to simplify the calculation steps, optionally, the first predetermined algorithm is an XOR operation. And the inverse operation of the XOR operation is still an XOR operation.

[0122] It should be noted that the inverse operation of the XOR operation is still the XOR operation. For example, using A and B to perform an XOR operation can get C, using B and C to perform an XOR operation can get A, and using A and C to perform an XOR operation can get B.

[0123] It can be seen that by performing an XOR operation on L table writing data to obtain an auxiliary value, when L-1 table writing data and the auxiliary value are known, an XOR operation is performed on L-1 table writing data and the auxiliary value to determine the value of the remaining unknown table writing data.

[0124] As a second aspect of the present disclosure, a method for reading data from a storage device is provided, wherein the storage device includes a plurality of storage modules, the plurality of storage modules include a plurality of main storage modules and at least one auxiliary storage module, the plurality of main storage modules include at least one target main storage module, each of the target main storage modules corresponds to an auxiliary storage module, the storage device stores data written by the writing method provided by the first aspect of the present disclosure, and the reading method includes:

[0125] In step S210, at least one read instruction is received;

[0126] In step S220, the location of the data to be read is determined according to the read instruction;

[0127] When the data to be read by at least two read instructions are stored in the same main storage module, and the addresses pointed to by the read instructions correspond to auxiliary values, for the at least two read instructions, the reading method further includes:

[0128] In step S230, for one of the at least two instructions, which is a read instruction, directly read corresponding data from the main storage module;

[0129] In step S240, for other instructions in the at least two instructions, the auxiliary value stored in the corresponding address of the auxiliary storage module corresponding to the main storage module and the data in the corresponding address of the main storage module participating in the auxiliary value calculation are read respectively;

[0130] In step S250, each of the auxiliary values ​​is operated using a second predetermined algorithm and each of the table write data to obtain data stored in the main storage module at an address corresponding to the other instructions, wherein the second predetermined algorithm is an inverse operation of the first predetermined algorithm.

[0131] In one clock cycle, although two read instructions are not allowed to access the same main storage module, multiple read instructions are allowed to access multiple different main storage modules. The execution basis of the read method provided in the second aspect of the present disclosure is that the write table data stored in the storage device is written into the storage device using the write method provided in the first aspect of the present disclosure.

[0132] Since, when writing the table write data, not only the table write data is written into the corresponding address of the main storage module, but also the auxiliary value obtained by calculating the table write data and the corresponding addresses of other main storage modules is written into the auxiliary storage module, the table write data is allowed to be stored in the form of auxiliary values ​​in the corresponding addresses of other storage modules except for the above-mentioned "corresponding addresses of the main storage module".

[0133] In the reading method provided in the second aspect of the present disclosure, after receiving multiple read instructions for accessing different addresses of the same main storage module, the storage address of the data involved in the auxiliary value in the address can be determined according to the address to be read by each read instruction, and then the corresponding address is accessed to obtain the data involved in the auxiliary value operation. The auxiliary value and the data involved in the auxiliary value operation are operated by a second predetermined algorithm, so that the data stored in the address to be read by the read instruction can be obtained, thereby realizing fast data reading (or fast table lookup).

[0134] As an implementation manner of the present disclosure, the first predetermined algorithm is an XOR operation, and the second predetermined algorithm is an inverse operation of the XOR operation.

[0135] It should be noted that the inverse operation of the XOR operation is still the XOR operation. For example, using A and B to perform an XOR operation can get C, using B and C to perform an XOR operation can get A, and using A and C to perform an XOR operation can get B.

[0136] The following describes a specific implementation of steps S230 to S250 of the reading method when the writing method includes steps S121 to S122.

[0137] When four read instructions (for the convenience of description, these read instructions are represented as the first read instruction, the second read instruction, the third read instruction and the fourth read instruction respectively, it should be pointed out that the "first", "second", "third" and "fourth" here are only used to distinguish the read instructions, rather than to limit the sequence or priority of the read instructions) access the same main storage module at the same time:

[0138] Step S230 may include: for a first read instruction, directly reading data from an address pointed to by the first read instruction of the main storage module;

[0139] Step S240 may include: for the second read instruction, reading the first auxiliary value stored in the corresponding address of the auxiliary storage module corresponding to the main storage module (that is, the address with the same number as the address pointed to by the second read instruction), and the data in the corresponding address of the main storage module participating in the first auxiliary value operation; for the third read instruction, reading the second auxiliary value stored in the corresponding address of the auxiliary storage module corresponding to the main storage module (that is, the address with the same number as the address pointed to by the third read instruction), and the data in the corresponding address of the main storage module participating in the second auxiliary value operation; for the fourth read instruction, reading the third auxiliary value stored in the corresponding address of the auxiliary storage module corresponding to the main storage module (that is, the address with the same number as the address pointed to by the fourth read instruction), and the data in the corresponding address of the main storage module participating in the third auxiliary value operation;

[0140] Step S250 may include: using a second predetermined algorithm to operate the first auxiliary value and the data in the corresponding address of the main storage module participating in the first auxiliary value operation, and the obtained value is the data stored in the address pointed to by the second read instruction; using a second predetermined algorithm to operate the second auxiliary value and the data in the corresponding address of the main storage module participating in the second auxiliary value operation, and the obtained value is the data stored in the address pointed to by the third read instruction; using a second predetermined algorithm to operate the third auxiliary value and the data in the corresponding address of the main storage module participating in the third auxiliary value operation, and the obtained value is the data stored in the address pointed to by the fourth read instruction.

[0141] The following is a specific example of a RAM with a depth of 2048 and a bit width of 128 bits. At the same time, the most extreme RAM read conflict is considered, that is, the address of the four table read requests are all on the same 1r1w RAM. Therefore, four table read requests are set here to read the values ​​at addresses 0, 1, 126, and 127 in RAM0 respectively. The depth of each 1r1w RAM from RAM0 to RAM15 is 2048 / 16=128, and 9 1r1w RAMs with a depth of 128 are placed as XOR0 to XOR8. The entire table read process is as follows:

[0142] (1) Figure 6 As shown, the read request from port Port0 is to read the value of address 0 of RAM0, which can be directly read out and returned.

[0143] (2) Figure 6As shown, the read request from port Port1 is to read the value of address 1 of RAM0. If address 1 in RAM0 is read directly, there will be a read conflict with step (1), which will cause a large return delay. Therefore, the value of address 1 of RAM2, RAM3, RAM4, and XOR0 can be read (that is, four instructions with raddr=1 are generated and sent to RAM2, RAM3, RAM4, and XOR0 respectively), and the read value is XORed to obtain the value of address 1 of RAM0 and return it.

[0144] (3) Figure 7 As shown, the read request from port Port2 is to read address 126 of RAM0. Similarly, if address 126 in RAM0 is directly read at this time, there will be a read conflict with step (1), which will cause a large return delay. Therefore, address 126 of RAM4, RAM8, RAM12, and XOR4 can be read (that is, 4 instructions of raddr=126 are generated and sent to RAM4, RAM8, RAM12, and XOR4 respectively), and the read value is XORed to obtain the value of address 126 of RAM0 and return it.

[0145] (4) Figure 8 As shown, the read request from port Port3 is to read the value of address 127 of RAM0. For the same reason as above, when address 127 of RAM0 cannot be read directly, the values ​​of address 127 of the remaining 15 RAM blocks are read out, namely RAM5, RAM6, RAM7, RAM9, RAM10, RAM11, RAM13, RAM14, RAM15, XOR1, XOR2, XOR3, XOR5, XOR6, XOR7 (i.e., 15 instructions of raddr=127 are generated and sent to RAM5, RAM6, RAM7, RAM9, RAM10, RAM11, RAM13, RAM14, RAM15, XOR1, XOR2, XOR3, XOR5, XOR6, XOR7 respectively), and the read values ​​are XORed together to obtain the value of address 127 in RAM0 and return it.

[0146] As a third aspect of the present disclosure, a computer-readable storage medium is provided, on which an executable program is stored. When the executable program is called, it can implement the writing method provided by the first aspect of the present disclosure and / or the reading method provided by the second aspect of the present disclosure.

[0147] As a fourth aspect of the present disclosure, a processor chip is provided, including a storage device and a computing module.

[0148] The storage device includes multiple storage modules, the multiple storage modules include multiple main storage modules and at least one auxiliary storage module, each of the auxiliary storage modules corresponds to a predetermined number of main storage modules, and each of the main storage modules corresponds to at least one auxiliary storage module.

[0149] The operation module includes a storage unit and a processing unit. The storage unit stores an executable program. When the executable program is called by the processing unit, it can implement the writing method provided by the first aspect of the present disclosure and the reading method provided by the second aspect of the present disclosure.

[0150] The storage device has at least one write port and a plurality of read ports, and each storage module has one read port and one write port.

[0151] Therefore, the storage device can receive multiple read instructions at the same time.

[0152] In the present disclosure, each storage module may be a RAM.

[0153] Figure 3 The figure shows a schematic diagram of a processor chip, wherein the processing unit includes a writing unit, a reading control unit, and an output control unit. The writing unit is used to write data into each storage module according to the writing method provided by the present disclosure. The reading control unit is used to Figure 3 The read control in the read unit is used to allocate the received multiple read instructions to obtain data according to the read method provided by the present disclosure. That is, it is determined which read instruction is used to directly read the data stored in the corresponding address, and which instruction is used to read the corresponding auxiliary value and the data associated with the auxiliary value. Figure 3 Among them, rd0, rd1, rd2, and rd3 represent four different read instructions respectively.

[0154] Output control unit Figure 3 The output control in the command is used to control the output of the data obtained by each read instruction. Figure 3 Among them, rdata0, rdata1, rdata2, and rdata3 are the output instructions corresponding to rd0, rd1, rd2, and rd3 respectively.

[0155] Optionally, the storage depth of the primary storage module is the same as the storage depth of the auxiliary storage module.

[0156] Optionally, the plurality of storage modules are formed into a plurality of storage modules in an N*N array, and in the first (N-1) rows of storage modules, each row of storage modules includes N main storage modules and one auxiliary storage module, and the Nth row of storage modules includes N auxiliary storage modules.

[0157] Optionally, N is 5, and the storage depth of each of the main storage modules is 1 / 16 of the total storage depth of all the main storage modules.

[0158] In the present disclosure, the plurality of main storage modules can be obtained by dividing the existing RAM into 16 parts. Therefore, the storage space of the storage device provided by the present disclosure is only increased by 1.526 times of the RAM in the related art. In the storage device provided by the present disclosure, the storage space of the auxiliary storage module is small and the area occupied is also small.

[0159] Of course, the present disclosure is not limited thereto, and the plurality of main storage modules may also form a three-dimensional array. Specifically, the plurality of storage modules include a plurality of main storage modules formed into a three-dimensional cube of an M*M*M array and three 3*M*M arrays in the positive direction of the plane. 2 auxiliary storage modules. From the perspective of each coordinate system plane, on the XY plane, each row of storage modules includes M main storage modules and one auxiliary storage module. On the XZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module. On the YZ plane, each row of storage modules includes M main storage modules and one auxiliary storage module, and M is a positive integer not less than 1.

[0160] As a fifth aspect of the present disclosure, an electronic device is provided, wherein the electronic device includes the processor chip provided in the fourth aspect of the present disclosure.

[0161] The advantages and beneficial effects of the reading method and the writing method have been described in detail above and will not be repeated here.

[0162] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0163] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for writing data into a storage device, wherein the storage device comprises a plurality of storage modules, the plurality of storage modules comprises a plurality of main storage modules and at least one auxiliary storage module, the plurality of main storage modules comprises at least one target main storage module, each of the target main storage modules corresponds to an auxiliary storage module, the method comprising: Writing the table writing data to be written into the corresponding main storage module; Using a first predetermined algorithm to operate on the table writing data in each of the target main storage modules to obtain an auxiliary value, wherein when operating on any one of the target main storage modules, using the first predetermined algorithm to operate on the table writing data stored in the target main storage module and corresponding table writing data stored in at least one of other main storage modules other than the target main storage module, and using an inverse operation of the first predetermined algorithm to operate on any auxiliary value, the table writing data involved in the operation can be obtained; storing the auxiliary value in a corresponding auxiliary storage module; The plurality of storage modules are formed into a plurality of storage modules in an N*N array, in the first (N-1) rows of storage modules, each row of storage modules includes (N-1) main storage modules and one auxiliary storage module, the Nth row of storage modules includes N auxiliary storage modules, N is a positive integer not less than 3; the auxiliary values ​​include a first auxiliary value, a second auxiliary value and a third auxiliary value, and in the step of using a first predetermined algorithm to operate the table write data in each of the target main storage modules to obtain the auxiliary value, for the table write data stored in any address of any one of the target main storage modules, the step of obtaining the auxiliary value includes: Using the first predetermined algorithm, a table write data stored in a current address of a current target main storage module and table write data stored in corresponding addresses of all other main storage modules located in the same row as the target main storage module are operated to obtain a first auxiliary value; Using the first predetermined algorithm, a table write data stored in a current address of a current target main storage module and table write data stored in corresponding addresses of all other main storage modules located in the same column as the current target main storage module are operated to obtain a second auxiliary value; Using the first predetermined algorithm, a calculation is performed on the table writing data stored in the address of the current target main storage module, the table writing data stored in the corresponding addresses of all main storage modules except all target main storage modules, and the data stored in the corresponding addresses of all auxiliary storage modules except the auxiliary storage module corresponding to the current target main storage module, so as to obtain a third auxiliary value; Furthermore, the first auxiliary value is stored in an auxiliary storage module located in the same row as the target main storage module, the second auxiliary value is stored in an auxiliary storage module located in the same column as the target main storage module, and the third auxiliary value is stored in a storage module in the Nth row and the Nth column.

2. The writing method according to claim 1, wherein: After all target main storage modules have been operated using the first predetermined algorithm, the data stored in all the main storage modules have participated in the operation.

3. The writing method according to claim 1, wherein: In the array, all the master storage modules in the first row are the target master storage modules, and all the master storage modules in the first column are the target master storage modules.

4. The writing method according to any one of claims 1 to 3, wherein: The address identification information corresponding to all the table writing data participating in the same operation using the first predetermined algorithm is the same.

5. The writing method according to any one of claims 1 to 3, wherein: The first predetermined algorithm is an exclusive OR operation.

6. The writing method according to any one of claims 1 to 3, wherein: When the table writing data stored in the main storage module participating in the operation changes, the writing method further includes: Use the changed table write data to participate in the calculation to obtain the corresponding auxiliary value; Replace the stored auxiliary value at the corresponding address with the recalculated auxiliary value.

7. A method for reading data from a storage device, wherein the storage device comprises a plurality of storage modules, the plurality of storage modules comprises a plurality of main storage modules and at least one auxiliary storage module, the plurality of main storage modules comprises at least one target main storage module, each of the target main storage modules corresponds to an auxiliary storage module, the storage device stores data written by the writing method according to any one of claims 1 to 6, the reading method comprising: receiving at least one read instruction; Determine the location of the table writing data to be read according to the read instruction; When the data to be read by at least two read instructions are stored in the same main storage module, and the addresses pointed to by the read instructions correspond to auxiliary values, for the at least two read instructions, the reading method further includes: For one of the at least two instructions being a read instruction, directly reading corresponding table writing data from the main storage module; For other instructions of the at least two instructions, respectively read the auxiliary value stored in the corresponding address of the auxiliary storage module corresponding to the main storage module, and the table writing data in the corresponding address of the main storage module participating in the auxiliary value calculation; Each of the auxiliary values ​​is operated using a second predetermined algorithm and each of the table writing data to obtain the table writing data stored in the main storage module and stored in the address corresponding to the other instructions, wherein the second predetermined algorithm is an inverse operation of the first predetermined algorithm.

8. The reading method according to claim 7, wherein: The first predetermined algorithm is an exclusive OR operation, and the second predetermined algorithm is an exclusive OR operation.

9. A computer-readable storage medium having an executable program stored thereon, which, when called, can implement the writing method described in any one of claims 1 to 6 and / or the reading method described in claim 7 or 8.

10. A processor chip comprising a storage device having at least one write port and a plurality of read ports and a computing module, The storage device includes a plurality of storage modules, the plurality of storage modules are formed into a plurality of storage modules of an N*N array, in the first (N-1) rows of storage modules, each row of storage modules includes (N-1) main storage modules and one auxiliary storage module, the Nth row of storage modules includes N auxiliary storage modules, N is a positive integer not less than 3; the plurality of storage modules include a first write port, a plurality of first read ports, a plurality of main storage modules and at least one auxiliary storage module, each of the auxiliary storage modules corresponds to a predetermined number of main storage modules, and each of the main storage modules corresponds to at least one auxiliary storage module, and each storage module has one first read port and one first write port; The operation module includes a storage unit and a processing unit. An executable program is stored in the storage unit. When the executable program is called by the processing unit, the writing method described in any one of claims 1 to 6 and the reading method described in claim 7 or 8 can be implemented.

11. The processor chip according to claim 10, wherein: The storage depth of the primary storage module is the same as the storage depth of the auxiliary storage module.

12. The processor chip according to claim 10, wherein: N is 5, the storage device has four read ports, and the storage depth of each of the main storage modules is 1 / 16 of the total storage depth of all the main storage modules.

13. An electronic device, comprising the processor chip according to any one of claims 10 to 12.

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