Method and device for generating verification use case

Abstract

The present disclosure relates to a method, apparatus, device, computer program product, and computer-readable storage medium for generating a verification case. The method comprises: for each of a plurality of general registers, using a first load instruction to load a random value into the general register; randomly obtaining one instruction at a time from an instruction library as a verification instruction, executing the verification instruction, and determining whether the verification instruction is suitable for the verification case based on the execution result of the verification instruction; selecting at least a portion of the first load instructions based on the execution result of the verification instruction suitable for the verification case; and constructing the verification case using the at least a portion of the load instructions and the verification instructions suitable for the verification case.

Description

Technical Field

[0001] The present disclosure relates to the field of processor verification, and more particularly, to a method, apparatus, device, computer program product, and storage medium for generating a verification case. Background Art

[0002] As the computing and control core of a computer system, the processor is responsible for reading, decoding, and executing instructions. It is the final execution unit for information processing and program execution. Since its inception, processors have made significant progress in logical structure, operational efficiency, and functional extension. Iterative updates to processor architecture design and continuous improvements in integrated circuit technology have driven their continuous development and improvement.

[0003] Processor verification plays a crucial role throughout the processor design lifecycle. While processor manufacturers need to verify their products, processor users sometimes modify the processors by using extended instructions to control their own integrated chip functions. Consequently, the need for processor verification is increasing. The main steps in processor verification typically include: developing a verification plan based on design and functional requirements; designing and setting up the verification environment; designing verification use cases according to the verification plan; running the verification use cases and collecting verification results.

[0004] In the process of designing verification cases, the original verification cases generated completely randomly will inevitably contain verification instructions that will cause abnormal execution results. In this case, the process of running the verification case will end, be interrupted, or enter the exception handler, hindering the normal execution of the verification process. Figure 2 The method described in the specific embodiment of the prior art for eliminating anomalies to generate new verification cases based on the original verification case still has the disadvantage of destroying the original verification instruction order, which causes the processor to be unable to execute the instructions in the verification case in sequence, and may miss certain verification instructions that need to be executed continuously to achieve the verification function. In addition, inserting instructions into the original verification instruction order may cause the execution result of the previous verification instruction to be lost in the transmission network and cannot be used for the subsequent verification instructions due to the operating principle of the processor. Summary of the Invention

[0005] In order to solve the above problems, the present disclosure proposes a method for generating verification use cases. While constructing the verification use cases with verification instructions, it introduces judgment logic for whether an exception occurs and what type of exception it is, as well as different subsequent processing methods. With complete method steps and logical flow, a verification use case is generated that eliminates exceptions while maintaining a continuous instruction sequence, avoids the verification program from ending or entering an exception handler, and enables the processor to execute the verification instructions in the verification use case according to the desired instruction sequence.

[0006] Embodiments of the present disclosure provide a method, apparatus, device, computer program product, and computer-readable storage medium for generating a verification case.

[0007] An embodiment of the present disclosure provides a method for generating a verification case, comprising: for each general register among a plurality of general registers, using a first load instruction to load a random value for the general register; randomly obtaining one instruction at a time from an instruction library as a verification instruction, executing the verification instruction, and judging whether the verification instruction is suitable for the verification case based on the execution result of the verification instruction; selecting at least a portion of the load instructions in the first load instructions based on the execution result of the verification instruction suitable for the verification case; and constructing the verification case using the at least a portion of the load instructions and the verification instructions suitable for the verification case.

[0008] According to an embodiment of the present disclosure, one instruction is randomly obtained each time from the instruction library as a verification instruction until it is determined that the verification use case termination condition is met, wherein the number of verification instructions judged to be suitable for the verification use case is a first number, and the verification use case termination condition includes: the first number reaches a threshold.

[0009] According to an embodiment of the present disclosure, the determining whether the verification instruction is suitable for the verification use case includes: for the verification instruction, determining whether an exception occurs in the execution result of the verification instruction; if an exception occurs in the execution result of the verification instruction, determining whether the exception is eliminable; if an exception occurs in the execution result of the verification instruction and the exception is not eliminable, determining that the verification instruction is not suitable for the verification use case.

[0010] According to an embodiment of the present disclosure, determining whether the exception is eliminable includes: determining whether a source operation register corresponding to a source operand involved in the verification instruction has not been updated, wherein the source operation register is one of the plurality of general registers; if the source operation register has not been updated, determining that the exception can be eliminated; and if the source operation register has been updated, determining that the exception cannot be eliminated.

[0011] According to an embodiment of the present disclosure, the determining whether the exception is eliminateable further includes: in the case where it is determined that the exception can be eliminated, using a second load instruction to load a specified value for the general register corresponding to the source operation register, wherein the specified value represents a value that does not cause an exception when any instruction is executed, wherein the utilizing at least a portion of the load instruction and the verification instruction suitable for the verification use case to construct the verification use case includes: utilizing at least a portion of the load instruction, the second load instruction, and the verification instruction suitable for the verification use case to construct the verification use case.

[0012] According to an embodiment of the present disclosure, the determining whether the verification instruction is suitable for the verification use case further includes: when it is determined that the exception can be eliminated or when no exception occurs in the execution result of the verification instruction, determining whether the plurality of general registers have all been updated; and when it is determined that the plurality of general registers have all been updated, for each of the plurality of general registers, using a first load instruction to load a random value into the general register.

[0013] According to an embodiment of the present disclosure, determining whether the plurality of general registers have all been updated includes at least one of the following situations: determining whether the general register has been updated as a destination operation register by a verification instruction whose execution result did not produce an abnormality; or determining whether the general register has been loaded with a non-random value as a source operation register.

[0014] According to an embodiment of the present disclosure, the determination of whether the verification instruction is suitable for use in the verification use case further includes: saving the register states of the plurality of general registers before executing the verification instruction obtained each time; and sequentially including each randomly obtained verification instruction in the verification use case, and the method further includes: restoring the most recently saved register state of each general register when it is determined that the exception is eliminable.

[0015] According to an embodiment of the present disclosure, the saving of the register states of the plurality of general registers further includes: for each randomly acquired verification instruction, when an exception occurs in the execution of the verification instruction and the exception is not eliminateable, restoring the register state of each general register saved most recently, wherein the constructing of the verification use case using the at least a portion of the load instruction and the verification instruction suitable for the verification use case includes: deleting the verification instruction whose execution result has an exception and the exception is not eliminateable.

[0016] According to an embodiment of the present disclosure, the method further includes: setting a register operation flag for each general register respectively.

[0017] According to an embodiment of the present disclosure, the register operation identifier includes: a symbolic execution identifier, an instruction write identifier, and an execution value, wherein the symbolic execution identifier is used to indicate whether the corresponding general register has been loaded with the specified value, the instruction write identifier is used to indicate whether the corresponding general register has been updated as a destination operation register, and the execution value represents the value calculated when the verification instruction corresponding to the general register is executed.

[0018] According to an embodiment of the present disclosure, constructing the verification use case using the at least a portion of the load instructions and the verification instructions suitable for the verification use case also includes: for a general register among the multiple general registers that has been updated as a destination operation register, and / or a general register that has not been loaded with the specified value as a source operation register, deleting the first load instruction that performs the load operation on it.

[0019] According to an embodiment of the present disclosure, the register operation identifier is set correspondingly for each general register, and further includes: for a general register among the multiple general registers whose instruction write identifier is equal to a first value and / or whose symbolic execution identifier is equal to a second value, deleting the first load instruction performing a load operation on it, wherein the first value indicates that the corresponding general register has been updated as a destination operation register, and the second value indicates that the corresponding general register has not been loaded with the specified value as a source operation register.

[0020] An embodiment of the present disclosure provides a device for generating a verification case, the device comprising: a loading module, configured to load a random value for each general register of a plurality of general registers using a first loading instruction; an acquisition module, configured to randomly acquire one instruction at a time from an instruction library as a verification instruction; an execution module, configured to execute the verification instruction; a judgment module, configured to judge whether the verification instruction is suitable for the verification case based on an execution result of the verification instruction, until it is judged that a verification case end condition is met; a construction module, configured to select at least a portion of the loading instructions from the first loading instruction based on the execution result of the verification instruction suitable for the verification case, and then construct the verification case using the at least a portion of the loading instructions and the verification instruction suitable for the verification case.

[0021] An embodiment of the present disclosure provides a device for generating a verification case, the device comprising: one or more processors; and one or more memories, wherein a computer executable program is stored in the one or more memories, and when the computer executable program is executed by the processor, the method described in any one of claims 1 to 13 is executed.

[0022] An embodiment of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon. When the instructions are executed by a processor, the instructions are used to implement the method according to any one of claims 1 to 13.

[0023] Embodiments of the present disclosure provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a method according to an embodiment of the present disclosure.

[0024] Embodiments of the present disclosure provide a method, apparatus, device, computer program product, and computer-readable storage medium for generating a verification case.

[0025] The method provided by the embodiments of the present disclosure, while constructing a verification case using verification instructions, introduces logic for determining whether an exception has occurred and what type of exception it is, and the different subsequent handling methods adopted accordingly. This method, with a complete set of steps and logical flow, generates a verification case that eliminates exceptions while maintaining a continuous instruction sequence. In subsequent applications, the verification case generated according to the embodiments of the present disclosure can be run on a processor reference model and a designed processor to achieve a verification process that executes smoothly and ensures the verification instructions are fully functional.

[0026] Through the method disclosed in the present invention, when verification instructions are randomly obtained from the instruction library to form verification use cases, it is possible to generate verification use cases that can be subsequently run without abnormalities for different instruction situations. Moreover, through appropriate adjustments to the method disclosed in the present invention, the instruction library can be designed and restricted, so that users' choices are more diverse and the application scenarios of verification use cases are richer and more specific. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some exemplary embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0028] Figure 1 is an exemplary diagram illustrating verification of a design processor using verification use cases;

[0029] Figure 2 This is an exemplary schematic diagram illustrating an exception that occurs during the execution of a verification case and how the exception is handled in the prior art;

[0030] Figure 3is a schematic flowchart illustrating a first embodiment of a method for generating a verification case according to an embodiment of the present disclosure;

[0031] Figure 4 It shows that according to Figure 3 Schematic flow chart of an extension of step S140.

[0032] Figure 5 is a schematic flow chart illustrating a second embodiment of a method for generating a verification case according to an embodiment of the present disclosure;

[0033] Figure 6 It shows that according to Figure 5 A schematic flow chart of an extended solution of steps S8, S81, and S7;

[0034] Figure 7 The method for generating a verification case according to an embodiment of the present disclosure is based on Figure 6 A schematic flow chart of a third embodiment of the present invention;

[0035] Figure 8 is a schematic diagram illustrating an apparatus 800 for generating a verification case according to an embodiment of the present disclosure;

[0036] Figure 9 is a schematic diagram illustrating a verification case generation device 2000 according to an embodiment of the present disclosure;

[0037] Figure 10 is a schematic diagram illustrating the architecture of a computing device according to an embodiment of the present disclosure; and

[0038] Figure 11 is a schematic diagram illustrating a storage medium according to the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present disclosure more apparent, the exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0040] In this specification and the accompanying drawings, substantially the same or similar steps and elements are denoted by the same or similar reference numerals, and repeated descriptions of these steps and elements will be omitted. At the same time, in the description of the present disclosure, the terms "first", "second", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance or ranking.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0042] To facilitate description of the present disclosure, concepts related to the present disclosure are introduced below.

[0043] Registers: In computing, registers are components within the processor, including general-purpose registers, special-purpose registers, and control registers. Registers are crucial data storage resources, used to temporarily store data and addresses. They are one of the hardware resources directly accessible to assembly programmers. Registers have very high read and write speeds, allowing for rapid data transfer between registers. Registers are often used to store intermediate program results and quickly provide operands for subsequent instructions, eliminating the need to store intermediate results in memory and then read them from memory.

[0044] General registers: General registers include integer registers, floating-point registers, etc. The processor includes 8, 16, or other number of general registers depending on the number of bits.

[0045] Instruction: An instruction consists of two parts: an opcode and an operand. The opcode indicates what type of operation the instruction should perform, such as a load operation, an addition operation, a division operation, etc. Different operation types are represented by different opcodes. The operand represents the number or the storage address of the number participating in the operation specified by the instruction. The operand is mainly stored in a register or memory. Among the operands, the first operand is the destination operand / first source operand, and the second operand is the second source operand. The destination operand is a general register, and the source operand can be an immediate number, a general register or a memory location. The result after the instruction is executed is placed in the destination operand. In the present disclosure, the general register corresponding to the destination operand is also called the destination operation register, and the general register corresponding to the source operand is also called the source operation register. For example:

[0046] ADDPS X1, X2: ADDPS represents a single-precision floating-point addition operation. X1 and X2 are general registers. X1 represents the destination operand and also the first source operand. X2 represents the second source operand. This instruction adds X1 and X2 and puts the result into X1. X1 is both the destination and source registers, and X2 is the source register.

[0047] DIVPS X1, X2: DIVPS represents a single-precision floating-point division operation. X1 and X2 are general registers. X1 represents the destination operand and also the first source operand. X2 represents the second source operand. This instruction divides X1 by X2 and places the result into X1. X1 is both the destination and source registers, and X2 is the source register. Here, if the value of X2 is 0, the processor will report a divide-by-zero exception.

[0048] MOVPS X1

[1000] : MOVPS indicates a single-precision load operation, X1 indicates the destination operand, and

[1000] indicates the first source operand. This instruction indicates that the data at memory address 1000 is loaded into register X1, where X1 is the destination operation register.

[0049] Verification Use Case: A sequence of multiple instructions used to verify a processor design to implement one or more specific functions.

[0050] Exceptions: Exceptions may occur after performing an operation. For example, IEEE 754 proposes five types of floating-point exceptions: inexact exception (PE), indicating loss of precision; underflow exception (UE), indicating that the minimum normalized value representable by the target floating-point format is exceeded; overflow exception (OE), indicating that the maximum normalized value representable by the target floating-point format is exceeded; divide by zero exception (ZE); and invalid operation exception (IE), which generally occurs when the operand is NaN (Not a Number, an undefined or unrepresentable value).

[0051] For each exception type, the processing process that requires modifying the register value includes: for exceptions such as OE, UE, and PE that occur after the instruction is executed, all operands of the instruction must be modified, that is, new values ​​must be set for all operands to eliminate the exception; for ZE, it only occurs on division instructions, so the second source operand needs to be set to a non-zero value; for IE, the value of the corresponding operand needs to be set to a normalized number.

[0052] Register state: In this disclosure, register state refers to the general term for the internal state of the register itself that changes as instructions are executed (for example, shifting occurs when reading instructions), which is stored in the memory.

[0053] Register update: Under the framework of the present disclosure, the update of a general register includes: the result is written after the general register is executed as the destination operation register by an operation instruction (such as an ADDPS instruction); and the general register is loaded with a value by a MOVPS instruction as a source operation register.

[0054] In summary, the solutions provided by the embodiments of the present disclosure involve technologies such as processor verification, verification use cases, and register updates. The embodiments of the present disclosure will be further described below in conjunction with the accompanying drawings.

[0055] Figure 1 FIG. 1 is an exemplary diagram illustrating verification of a design processor using verification use cases.

[0056] As can be seen from the above background technology, after a design processor is designed according to functional requirements, it is necessary to verify the design processor to determine whether the relevant design functions meet the requirements. Figure 1 As shown, the usual practice for processor verification is to randomly generate verification cases based on constraints, and then run the verification cases on both the processor reference model and the design processor and compare the results of the processor reference model and the design processor when executing each verification instruction in the verification case in the checker. If the execution results of the design processor and the processor reference model are consistent, it means that the execution of the verification instruction is correct and the design processor meets the relevant functional requirements. Among them, the processor reference model represents a reference processor that meets the functional requirements, which can output results that meet the design framework when running the verification case. However, for completely randomly generated verification cases, some verification instructions will cause the execution results to have the above-mentioned exceptions, thereby causing the verification process to be interrupted or enter the exception handler. For the exceptions in the execution results caused by individual verification instructions, the solutions in the prior art are as follows. Figure 2 shown.

[0057] Figure 2 The present invention is an exemplary schematic diagram showing an exception that occurs during the execution of a verification case and how the exception is handled in the prior art.

[0058] from Figure 2 As can be seen, after obtaining the instructions to be executed from the verification case, if the execution result is abnormal, the instruction execution process enters the exception handler, and then obtains another instruction from the exception handler for execution until the processor's execution result of the instructions no longer encounters an abnormality, and then returns to the normal instruction execution process. Even if the exception handler can obtain an instruction that can result in a normal execution result at one time, the entire instruction execution process is still interrupted by the exception handler, and the original sequence of verification instructions in the verification case is disrupted by the newly inserted instruction.

[0059] For example, the following is a verification use case example 1 for verifying the alternate execution of the ADDPS instruction and the DIVPS instruction:

[0060] Instruction 0: ADDPS R1, R0

[0061] Instruction 1: DIVPS R3, R2 / / -> R2 value is an irregular number, IE occurs

[0062] Instruction 2: ADDPS R5, R4

[0063] Instruction 3: DIVPS R7, R6 / / -> R6 value is ZERO, ZE occurs

[0064] Instruction 4: ADDPS R9, R8 / / -> R8+R9 result occurs PE

[0065] Instruction 5: DIVPS R11, R10 / / -> R11÷R10 The result is OE

[0066] Instruction 6: ADDPS R13, R12

[0067] Instruction 7: DIVPS R15, R14

[0068] In this verification case, verification instructions 1, 3, 4, and 5 respectively generate IE, ZE, PE, and OE exceptions, and each time an exception occurs in the execution result, the verification process will enter the exception handler. The original verification case expects to execute the ADDPS instruction and the DIVPS instruction alternately, and does not expect an exception handler to exist between instruction executions. According to the solution of the prior art, after entering the exception handler, another instruction is obtained from the exception handler for execution. Usually, a MOVPS instruction is inserted before the instruction that causes the execution result to be abnormal in the verification case, thereby modifying the value in the register that originally caused the exception to a value that will not cause the exception. That is, in the logical flow, the source operation register corresponding to the source operand of the instruction that caused the exception is loaded with a value that will not cause an exception, thereby eliminating the exception that would have occurred. After inserting the MOVPS instruction, the newly generated verification case based on the above verification case is as follows:

[0069] Instruction 0: ADDPS R1, R0

[0070] Instruction x: MOVPS R2,

[1000] / / MOVPS instruction inserted to eliminate exception

[0071] Instruction 1: DIVPS R3, R2 / / -> Load the rule number for R2 and eliminate IE

[0072] Instruction 2: ADDPS R5, R4

[0073] Instruction x: MOVPS R6,

[1008] / / MOVPS instruction inserted to eliminate exception

[0074] Instruction 3: DIVPS R7, R6 / / -> Load non-zero value into R6, eliminate ZE

[0075] Instruction x: MOVPS R8,

[1018] / / MOVPS instruction inserted to eliminate exception

[0076] Instruction x: MOVPS R9,

[1020] / / MOVPS instruction inserted to eliminate exception

[0077] Instruction 4: ADDPS R9, R8 / / -> Load R8 and R9 with values ​​that do not send exceptions, eliminating PE

[0078] Instruction x: MOVPS R10,

[1018] / / MOVPS instruction inserted to eliminate exception

[0079] Instruction x: MOVPS R11,

[1020] / / MOVPS instruction inserted to eliminate exception

[0080] Instruction 5: DIVPS R11, R10 / / -> Load R10 and R11 with values ​​that do not send an exception, eliminating OE

[0081] Instruction 6: ADDPS R13, R12

[0082] Instruction 7: DIVPS R15, R14

[0083] The non-exceptional value is a pre-given value stored in a specific address, which does not cause any exception in the execution result of any instruction. In this example, the specific address includes

[1018] ,

[1020] , etc., which represents a direct addressing operand fetching method.

[0084] After generating a new verification case in the above manner, it is then run on the processor reference model and the design processor for the subsequent processor verification process. This new verification case does avoid exceptions when executing the verification case, but it has the following disadvantages: the instruction sequence in the original verification case is changed, and a specific MOVPS instruction is placed before each instruction that causes an exception in the execution result. This is inconsistent with the original verification case's expectation of verifying the scenario of alternating ADDPS and DIVPS instructions. It may miss design issues that require multiple alternating executions of ADDPS and DIVPS. In addition, new operation instructions are inserted into the original verification instruction sequence. Due to the operating principle of the processor, this may cause the execution results of the previous verification instructions to be lost in the transmission network and cannot be used for subsequent verification instructions.

[0085] Figure 3is a schematic flowchart illustrating a first embodiment of a method for generating a verification case according to an embodiment of the present disclosure.

[0086] According to the first embodiment, in step S110, for each general register of a plurality of general registers (for example, 16), a random value is loaded into the general register using a first load instruction;

[0087] Next, in step S120, one instruction is randomly obtained from the instruction library as a verification instruction at a time;

[0088] Next, in step S130, the verification instruction is executed;

[0089] Next, in step S140, it is determined whether the verification instruction is suitable for the verification use case based on the execution result of the verification instruction;

[0090] Next, in step S150, at least a portion of the first load instructions is selected according to the execution result of the verification instruction suitable for the verification case, and then the verification case is constructed using the at least a portion of the load instructions and the verification instruction suitable for the verification case.

[0091] Optionally, one instruction at a time is randomly retrieved from the instruction library as a verification instruction until a verification case termination condition is determined to be satisfied, wherein the number of verification instructions determined to be suitable for the verification case is a first number, and the verification case termination condition includes: the first number reaching a threshold. For example, if the threshold is 1000, then when the number of verification instructions determined to be suitable for the verification case, i.e., the first number, reaches 1000, the verification case termination condition is satisfied, and the verification case is generated and output.

[0092] Figure 4 It shows that according to Figure 3 Schematic flow chart of an extension of step S140.

[0093] exist Figure 4 The extended judgment logic of step S140 is shown in FIG. , wherein judging whether the verification instruction is suitable for the verification use case based on the execution result of the verification instruction includes: for the verification instruction, judging whether the execution result of the verification instruction is abnormal. In the case that the execution result of the verification instruction is abnormal, judging whether the abnormality is resolvable. In the case that the execution result of the verification instruction is abnormal and the abnormality is irresolvable, judging that the verification instruction is not suitable for the verification use case; in the case that the execution result of the verification instruction is not abnormal and the execution result is abnormal and the abnormality is resolvable, judging that the verification instruction is suitable for the verification use case.

[0094] Optionally, the determining whether the exception is eliminable includes: determining whether the source operation register corresponding to the source operand involved in the verification instruction has not been updated; if the source operation register has not been updated, determining that the exception can be eliminated; if the source operation register has been updated, determining that the exception cannot be eliminated.

[0095] Optionally, when it is determined that the exception can be eliminated, a second load instruction is used to load a specified value into the general register corresponding to the source operation register, wherein the specified value represents a value that does not cause an exception when any instruction is executed, and then a verification use case is constructed using at least a portion of the first load instruction, the second load instruction, and the verification instruction suitable for the verification use case.

[0096] Figure 5 is a schematic flowchart illustrating a second embodiment of a method for generating a verification case according to an embodiment of the present disclosure.

[0097] According to the second embodiment, in step S1, for each general register of a plurality of general registers (for example, 16 general registers), a random value is loaded into the general register using a first load instruction;

[0098] Next, in step S2, the register states of the plurality of general registers are saved. In other words, before executing each acquired verification instruction, the register states of the plurality of general registers are saved so that if an abnormality occurs in the execution result of the verification instruction, the plurality of general registers can be restored to the state before the execution of the verification instruction.

[0099] Next, in step S3, one instruction at a time is randomly obtained from the instruction library as a verification instruction;

[0100] Then, in step S4, the verification instruction is executed;

[0101] Next, in step S5, it is determined whether an exception occurs in the execution result of the verification instruction. If the determination result is no, that is, the execution result is not abnormal, then the verification instruction is considered to be suitable for the verification use case, and then step SW is executed. In this step, the verification instruction is written into the verification use case, and then step S6 is executed; if the determination result is yes, that is, the execution result is abnormal, then step S8 is executed;

[0102] In step S6, it is determined whether a limited number of verification instructions have been written into the verification case, that is, whether a first number of verification instructions suitable for the verification case has reached a threshold. If the determination result is yes, step SE is executed, in which the generated verification case is output and the method ends. If the determination result is no, step S7 is executed.

[0103] In step S7, it is determined whether each general register has been updated. If so, the method returns to step S1, reloads the random value for each general register, and then continues to execute a new cycle of the method for the next verification instruction. If not, the method returns to step S2, and continues to execute a new cycle of the method for the next verification instruction.

[0104] In step S8, it is determined whether the exception is eliminable. If so, step S81 is executed, in which the exception is eliminated and the register state of each general register saved most recently is restored, and then step SW is executed; if not, step S82 is executed, in which the register state of each general register saved most recently is restored and the verification instruction is deleted, and then the method returns to step S1, random values ​​are reloaded for each general register, and then a new cycle of the method is continued for the next verification instruction.

[0105] Optionally, each randomly acquired verification instruction is sequentially included in the verification case, and then the generated verification case is constructed using at least a portion of the first load instruction and the verification instruction suitable for the verification case.

[0106] Figure 6 It shows that according to Figure 5 Schematic flow chart of an extension of steps S8, S81, and S7.

[0107] from Figure 6 It can be seen that in the extended scheme of step S8, the determination of whether the exception is eliminable includes: determining whether the source operation register corresponding to the source operand involved in the verification instruction has not been updated. In the case that the source operation register has not been updated, it is considered that the exception can be eliminated, and the determination result is yes; in the case that the source operation register has been updated, it is considered that the exception cannot be eliminated, and the determination result is no.

[0108] In an extended solution of step S81, eliminating the exception includes: using a second load instruction to load a specified value into a general register corresponding to a source operation register involved in a source operand of the verification instruction, wherein the specified value represents a value that does not cause an exception when executing any instruction.

[0109] Optionally, a verification case is constructed using at least a portion of the first loading instruction, the second loading instruction, and the verification instruction suitable for the verification case.

[0110] In an extended solution of step S7, the determining whether the plurality of general-purpose registers have been updated includes at least one of the following situations: determining whether the general-purpose register has been updated as a destination operation register by a verification instruction whose execution result did not produce an abnormality; or determining whether the general-purpose register has been loaded with a non-random value as a source operation register. If the determination result is yes, it is considered that the plurality of general-purpose registers have all been updated, and then, for each of the plurality of general-purpose registers, a random value is loaded into the general-purpose register using a first load instruction. If the determination result is no, it is considered that not every general-purpose register has been updated, and then the register state is saved, and the next verification instruction is obtained and executed.

[0111] Optionally, step S821 is performed between step S81 and step S1. In this step, for a general register among the multiple general registers that has been updated as a destination operation register and / or a general register that has not been loaded with the specified value as a source operation register, the first load instruction for performing the load operation on it is deleted.

[0112] Figure 7 The method for generating a verification case according to an embodiment of the present disclosure is based on Figure 6 A schematic flow chart of a third embodiment of the present invention.

[0113] In a third embodiment, a register operation flag is set correspondingly for each general register. The register operation flag is not stored in the register, but is stored outside the register, and changes accordingly as the method steps are executed. The register operation flag includes: a symbolic execution flag, an instruction write flag, and an execution value, wherein the symbolic execution flag is used to indicate whether the corresponding general register has been loaded with the specified value, the instruction write flag is used to indicate whether the corresponding general register has been updated as a destination operation register, and the execution value represents the value calculated when the verification instruction corresponding to the general register is executed, wherein the first value is used to indicate that the corresponding general register has been updated as a destination operation register, and the second value is used to indicate that the corresponding general register has not been loaded with the specified value as a source operation register. In this embodiment, for example, the instruction write flag is 1 or 0, the first value is equal to 1, the symbolic execution flag is 1 or 0, and the second value is equal to 1.

[0114] from Figure 7 It can be seen that in Figure 6On the basis of, in step S1, for each general register of a plurality of general registers (for example, 16), using a first load instruction to load a random value into the general register, further comprising: setting a register operation flag of each general register to have a symbolic execution flag equal to 1 and an instruction write flag equal to 0, indicating that each general register has neither been updated as a destination operation register nor loaded with a specified value as a source operation register.

[0115] Step S51 is executed between step S5 and step SW. In this step, the register operation identifier of the destination operation register corresponding to the destination operand involved in the verification instruction is modified to an instruction write identifier equal to 1, which means that when there is no abnormality in the execution result of the verification instruction, the destination operation register has been successfully written, that is, it has been updated.

[0116] In step S7, determining whether the general register has been updated as a destination operation register by a verification instruction whose execution result did not result in an exception, or determining whether the general register has been loaded with a non-random value as a source operation register, includes determining whether the register operation flag of each general register is a symbolic execution flag equal to 0 and / or an instruction write flag equal to 1. If the determination result is yes, it means that each general register has been updated, and the method then returns to step S1 to continue a new cycle. If the determination result is no, it means that not every general register has been updated, and the method then returns to step S2 to continue a new cycle.

[0117] In step S8, determining whether the source operation register corresponding to the source operand involved in the verification instruction has not been updated includes: determining whether the register operation flag of the source operation register corresponding to the source operand involved in the verification instruction is a symbolic execution flag equal to 1 and an instruction write flag equal to 0; if the determination result is yes, it means that the source operation register has not been updated, and then step S81 is executed; if the determination result is no, it means that the source operation register has been updated, and then step S82 is executed;

[0118] In step S81, the process further includes: modifying the register execution flag of the source operation register corresponding to the source operand involved in the verification instruction to a symbolic execution flag equal to 0, which indicates that the source operation register has been loaded with a specified value.

[0119] In step S821 , it includes: deleting a first load instruction that performs a load operation on a general register having an instruction write flag equal to 1 and / or a symbolic execution flag equal to 1.

[0120] For Figure 2The verification use case example 1 described in the above, generated according to the embodiment of the present disclosure is as follows:

[0121] Instruction x: MOVPS R2,

[1000] / / MOVPS instruction inserted to eliminate instruction 1 exception

[0122] Instruction x: MOVPS R6,

[1008] / / MOVPS instruction inserted to eliminate instruction 3 exception

[0123] Instruction x: MOVPS R8,

[1018] / / MOVPS instruction inserted to eliminate instruction 4 exception

[0124] Instruction x: MOVPS R9,

[1020] / / MOVPS instruction inserted to eliminate instruction 4 exception

[0125] Instruction x: MOVPS R10,

[1018] / / MOVPS instruction inserted to eliminate instruction 5 exception

[0126] Instruction x: MOVPS R11,

[1020] / / MOVPS instruction inserted to eliminate instruction 5 exception

[0127] Instruction 0: ADDPS R1, R0

[0128] Instruction 1: DIVPS R3, R2

[0129] Instruction 2: ADDPS R5, R4

[0130] Instruction 3: DIVPS R7, R6

[0131] Instruction 4: ADDPS R9, R8

[0132] Instruction 5: DIVPS R11, R10

[0133] Instruction 6: ADDPS R13, R12

[0134] Instruction 7: DIVPS R15, R14

[0135] It can be seen that the verification instruction sequence in the verification case generated according to the embodiment of the present disclosure is continuous and will not be interrupted by the MOVPS instruction inserted to eliminate the exception.

[0136] Figure 8 8 is a schematic diagram illustrating an apparatus 800 for generating a verification case according to an embodiment of the present disclosure.

[0137] According to an embodiment of the present disclosure, an apparatus 800 for generating a verification case may include a loading module (801), an acquisition module (802), an execution module (803), a judgment module (804) and a construction module (805).

[0138] The loading module (801) may be configured to load a random value into each of the plurality of general registers using a first loading instruction.

[0139] Optionally, the loading module (801) may also be configured to use a second loading instruction in the relevant method steps to load a specified value into the general register corresponding to the source operation register.

[0140] The acquisition module (802) is configured to randomly acquire one instruction at a time from the instruction library as a verification instruction.

[0141] The execution module (803) may be configured to execute the verification instruction.

[0142] The judgment module (804) can be configured to judge whether the verification instruction is suitable for the verification use case based on the execution result of the verification instruction, until it is judged that the verification use case end condition is met, wherein the number of verification instructions judged to be suitable for the verification use case is a first number.

[0143] Optionally, the verification case termination condition is that the first quantity reaches a threshold.

[0144] Optionally, the judgment module may include a first judgment module (8041), which may be configured to judge whether an exception occurs in the execution result of the verification instruction; if an exception occurs in the execution result of the verification instruction, judge whether the exception is eliminateable; if an exception occurs in the execution result of the verification instruction and the exception is not eliminateable, judge that the verification instruction is not suitable for the verification use case.

[0145] Optionally, the judgment module may include a second judgment module (8042), which may be configured to judge whether the source operation register corresponding to the source operand involved in the verification instruction has not been updated; if the source operation register has not been updated, it is judged that the exception can be eliminated; if the source operation register has been updated, it is judged that the exception cannot be eliminated.

[0146] Optionally, when it is determined that the exception can be eliminated, a second load instruction is used to load a specified value into the general register corresponding to the source operation register, wherein the specified value represents a value that does not cause an exception when any instruction is executed.

[0147] Optionally, the judgment module may include a third judgment module (8043), which may be configured to, when it is determined that the exception can be eliminated or when no exception occurs in the execution result of the verification instruction, determine whether the multiple general registers have all been updated; when it is determined that the multiple general registers have all been updated, for each of the multiple general registers, use the first load instruction to load a random value into the general register.

[0148] Optionally, the determining whether the plurality of general registers have been updated includes at least one of the following situations: determining whether the general register has been updated as a destination operation register by a verification instruction whose execution result did not produce an exception; or determining whether the general register has been loaded with a non-random value as a source operation register.

[0149] Optionally, the judgment module may include a fourth judgment module (8044), which may be configured to judge whether the verification case end condition is met.

[0150] The construction module (805) can be configured to select at least a portion of the first loading instructions based on the execution result of the verification instruction suitable for the verification case, and then construct the verification case using the at least a portion of the loading instructions and the verification instruction suitable for the verification case.

[0151] Optionally, the verification case is constructed using the at least part of the loading instruction, the second loading instruction, and the verification instruction suitable for the verification case.

[0152] According to yet another aspect of the present disclosure, a device for generating a verification case is provided. Figure 9 A schematic diagram of a verification case generation device 2000 according to an embodiment of the present disclosure is shown.

[0153] like Figure 9 As shown, the verification case generating device 2000 may include one or more processors 2010 and one or more memories 2020. The memory 2020 stores computer-readable code, which, when executed by the one or more processors 2010, may execute the method described above.

[0154] The processor in the embodiments of the present disclosure may be an integrated circuit chip having signal processing capabilities. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor, and may be an X86 architecture or an ARM architecture.

[0155] In general, various example embodiments of the present disclosure may be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device. When various aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other graphical representation, it will be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented, as non-limiting examples, in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or a controller or other computing device, or some combination thereof.

[0156] For example, the method or apparatus according to the embodiment of the present disclosure may also be implemented by Figure 10 The architecture of the computing device 3000 shown in FIG. Figure 10 As shown, the computing device 3000 may include a bus 3010, one or more CPUs 3020, a read-only memory (ROM) 3030, a random access memory (RAM) 3040, a communication port 3050 connected to a network, an input / output component 3060, a hard disk 3070, etc. The storage device in the computing device 3000, such as the ROM 3030 or the hard disk 3070, may store various data or files used for processing and / or communication of the method provided in the present disclosure, as well as program instructions executed by the CPU. The computing device 3000 may also include a user interface 3080. Of course, Figure 9 The architecture shown is only exemplary and can be omitted according to actual needs when implementing different devices. Figure 10 One or more components of a computing device are shown.

[0157] According to yet another aspect of the present disclosure, a computer-readable storage medium is provided. Figure 11 A schematic diagram 4000 of a storage medium according to the present disclosure is shown.

[0158] like Figure 11As shown, the computer storage medium 4020 stores computer-readable instructions 4010. When the computer-readable instructions 4010 are executed by the processor, the method according to the embodiment of the present disclosure described with reference to the above figures can be executed. The computer-readable storage medium in the embodiment of the present disclosure can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. The non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct memory bus random access memory (DR RAM). It should be noted that memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory. It should be noted that memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0159] Embodiments of the present disclosure also provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a method according to an embodiment of the present disclosure.

[0160] Embodiments of the present disclosure provide a method, apparatus, device, computer program product, and computer-readable storage medium for generating a verification case.

[0161] The method provided by the embodiments of the present disclosure, while constructing a verification case using verification instructions, introduces logic for determining whether an exception has occurred and what type of exception it is, and the different subsequent handling methods adopted accordingly. This method, with a complete set of steps and logical flow, generates a verification case that eliminates exceptions while maintaining a continuous instruction sequence. In subsequent applications, the verification case generated according to the embodiments of the present disclosure can be run on a processor reference model and a designed processor to achieve a verification process that executes smoothly and ensures the verification instructions are fully functional.

[0162] Through the method disclosed in the present invention, when verification instructions are randomly obtained from the instruction library to form verification use cases, it is possible to generate verification use cases that can be subsequently run without abnormalities for different instruction situations. Moreover, through appropriate adjustments to the method disclosed in the present invention, the instruction library can be designed and restricted, so that users' choices are more diverse and the application scenarios of verification use cases are richer and more specific.

[0163] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of the code, and the module, program segment, or a part of the code contains at least one executable instruction for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions.

[0164] In general, various example embodiments of the present disclosure may be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device. When various aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other graphical representation, it will be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented, as non-limiting examples, in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or a controller or other computing device, or some combination thereof.

[0165] The exemplary embodiments of the present disclosure described in detail above are merely illustrative and not restrictive. Those skilled in the art will appreciate that various modifications and combinations may be made to these embodiments or their features without departing from the principles and spirit of the present disclosure, and such modifications should fall within the scope of the present disclosure.

Claims

1. A method for generating a verification case, comprising: For each general register of the plurality of general registers, using a first load instruction to load a random value into the general register; Randomly obtaining one instruction at a time from an instruction library as a verification instruction, executing the verification instruction, and judging whether the verification instruction is suitable for the verification use case based on the execution result of the verification instruction, wherein judging whether the verification instruction is suitable for the verification use case includes: judging whether an exception occurs in the execution result of the verification instruction; if an exception occurs in the execution result of the verification instruction, judging whether the exception is resolvable; if an exception occurs in the execution result of the verification instruction and the exception is irresolvable, judging that the verification instruction is not suitable for the verification use case; selecting at least a portion of the first load instructions based on an execution result of a verification instruction suitable for the verification case; and The verification case is constructed using the at least a portion of the load instructions and the verification instructions suitable for the verification case.

2. The method according to claim 1, wherein An instruction is randomly obtained from the instruction library as a verification instruction each time until it is determined that a verification case end condition is met, wherein the number of verification instructions determined to be suitable for the verification case is a first number, and the verification case end condition includes: the first number reaches a threshold.

3. The method according to claim 2, wherein: Determining whether the anomaly is resolvable includes: Determining whether a source operation register corresponding to a source operand involved in the verification instruction has not been updated, wherein the source operation register is one of the plurality of general registers; If the source operation register has not been updated, determining that the exception can be eliminated; and In the case where the source operation register has been updated, it is determined that the exception cannot be eliminated.

4. The method according to claim 3, further comprising: If it is determined that the exception can be eliminated, a second load instruction is used to load a specified value into the general register corresponding to the source operation register, wherein the specified value represents a value that does not cause an exception when any instruction is executed; The constructing the verification case by using the at least part of the load instructions and the verification instructions suitable for the verification case includes: The verification case is constructed using the at least part of the load instruction, the second load instruction, and the verification instruction suitable for the verification case.

5. The method according to claim 3 or 4, further comprising: When it is determined that the exception can be eliminated or when no exception occurs in the execution result of the verification instruction, determining whether all of the plurality of general registers have been updated; as well as When it is determined that all the general registers have been updated and the first number has not reached a threshold, a random value is loaded into each of the general registers using a first load instruction.

6. The method according to claim 5, wherein: Determining whether all of the plurality of general registers have been updated includes at least one of the following situations: Determining whether the general register has been updated as a destination operation register by a verification instruction whose execution result is not abnormal; or It is determined whether the general register has been loaded with a non-random value as a source operation register.

7. The method according to claim 1, further comprising: Before executing each acquired verification instruction, saving register states of the plurality of general registers; as well as For each randomly obtained verification instruction, include it in the verification case in sequence. The method further includes: if it is determined that the exception is resolvable, restoring the register state of each general register saved most recently.

8. The method according to claim 7, further comprising: For each randomly acquired verification instruction, if an exception occurs during the execution of the verification instruction and the exception is irreversible, restore the register state of each general register that was saved the most recently. The constructing the verification case by using the at least part of the load instruction and the verification instruction suitable for the verification case includes: Delete the verification instructions whose execution results result in an exception and the exception cannot be eliminated.

9. The method according to claim 7, further comprising: A register operation flag is set correspondingly for each general register.

10. The method according to claim 9, wherein: The register operation identifier includes: a symbolic execution identifier, an instruction write identifier, and an execution value, wherein the symbolic execution identifier is used to indicate whether the corresponding general register has been loaded with a specified value, the instruction write identifier is used to indicate whether the corresponding general register has been updated as a destination operation register, and the execution value represents the value calculated when the verification instruction corresponding to the general register is executed.

11. The method according to claim 1, wherein The constructing the verification case by using the at least a portion of the load instructions and the verification instructions suitable for the verification case further includes: For a general register among the plurality of general registers that has been updated as a destination operation register and / or a general register that has not been loaded with a specified value as a source operation register, the first load instruction for performing the load operation on the general register is deleted.

12. The method according to claim 10, further comprising: For a general register among the plurality of general registers whose instruction write flag is equal to the first value and / or whose symbolic execution flag is equal to the second value, deleting a first load instruction performing a load operation on the general register; The first value indicates that the corresponding general register has been updated as a destination operation register, and the second value indicates that the corresponding general register has not been loaded with the specified value as a source operation register.

13. A device for generating a verification case, the device comprising: a loading module configured to load a random value into each of the plurality of general registers using a first load instruction; An acquisition module is configured to randomly acquire one instruction at a time from the instruction library as a verification instruction; an execution module, configured to execute the verification instruction; a judgment module configured to judge whether the verification instruction is suitable for the verification use case based on the execution result of the verification instruction, wherein the judging whether the verification instruction is suitable for the verification use case includes: judging whether an exception occurs in the execution result of the verification instruction; if an exception occurs in the execution result of the verification instruction, judging whether the exception is resolvable; if an exception occurs in the execution result of the verification instruction and the exception is irresolvable, judging that the verification instruction is not suitable for the verification use case; A construction module is configured to select at least a portion of the first loading instructions based on the execution result of the verification instruction suitable for the verification case, and then use the at least a portion of the loading instructions and the verification instruction suitable for the verification case to construct the verification case.

14. A device for generating a verification case, comprising: one or more processors; as well as One or more memories storing a computer executable program, wherein when the computer executable program is executed by the processor, the method according to any one of claims 1 to 12 is performed.

15. A computer program product, comprising computer software code, wherein the computer software code is configured to implement the method according to any one of claims 1 to 12 when executed by a processor. 16 . A computer-readable storage medium having computer-executable instructions stored thereon, wherein the instructions are used to implement the method according to claim 1 when executed by a processor.

Images