Simulation System and Its Method

Abstract

A simulation system and its method, by connecting a system power transmission model, an analog current time-domain model and a digital current time-domain model, and obtaining the power supply noise generated after obtaining the supply current; based on the transmission of the clock signal output by a phase-locked loop, obtaining the jitter time-domain information of each interface connection circuit model under the power supply noise through a simulation program; simulating, through the simulation program, the voltage step response of the voltage measurement point when each interface connection circuit model receives an ideal signal at the clock terminal, and then generating a corresponding first voltage time-domain model; and based on the jitter time-domain information of each interface connection circuit model under the power supply noise, its corresponding first voltage time-domain model and data transmission, generating a corresponding system waveform, and then obtaining a corresponding eye diagram and time-domain jitter distribution.

Description

Technical Field

[0001] The present invention relates to a simulation system and a method thereof, in particular to a simulation system and a method thereof for integrating signal and power integrity. Background Art

[0002] In recent years, high-order applications such as the Internet of Things, handheld systems, automotive electronics, high-speed computing, and AI chips have emerged. More and more functional blocks are integrated into a system-on-a-chip (SoC). The operating speed of the application-specific integrated circuit (ASIC) in the system-on-a-chip and the data transmission rate of each input / output block are getting higher and higher, making signal integrity and power integrity increasingly affect each other.

[0003] Power integrity covers the power supply of the ASIC core and the power supply of each input / output block, and depends to a large extent on the mode in the SoC. Generally, the ASIC core power supply will be used to supply power to each input / output block, and the activities of the ASIC will affect the signal quality in each input / output block through the core power supply.

[0004] Due to the increasing data transmission rate of each input / output block and the limited system bandwidth, the jitter in the package and printed circuit board will be amplified. Therefore, this impact also needs to be considered in system performance. In addition, the crosstalk impact from the package and printed circuit board is also related to the mode in the SoC.

[0005] However, the traditional method is to conduct quantitative analysis on the respective independent performance requirements of the input / output interfaces (i.e., these input / output blocks), the package, and the printed circuit board, and finally conduct an integrated design of the full-chip system, which has problems of consuming a large amount of unnecessary manpower and material resources and causing waste of area / power consumption. Therefore, it is necessary to propose improved technical means to solve this problem. Summary of the Invention

[0006] The present invention discloses a simulation system and a method thereof.

[0007] First, the present invention discloses a simulation system, which includes: a memory module and a processor. The memory module is used to store a plurality of instructions; and the processor is used to execute the instructions stored in the memory module to perform a simulation analysis program on the full-chip system, and the full-chip system includes a package structure, a printed circuit board, and a system-on-a-chip (SoC). Among them, the simulation analysis program includes: a modeling module for generating a signal channel model corresponding to each input / output power domain based on the design layout of the package structure and the printed circuit board; generating a system power transmission model based on the design layout of the package structure and the printed circuit board and the distribution of a plurality of power supply nodes on the layout of the system-on-a-chip; establishing an interface connection circuit model for each input / output power domain, where each interface connection circuit model includes a transmitter, its corresponding signal channel model, a receiver, a current measurement point, and a voltage measurement point. In each interface connection circuit model, the two sides of the signal channel model are respectively connected to the transmitter and the receiver. The transmitter has a data input terminal, a clock terminal, and an input / output power supply terminal. The current measurement point is set on the input / output power supply terminal, and the voltage measurement point is set at the connection between the signal channel model and the receiver; generating a corresponding second current time-domain model based on the response of the current measurement point when receiving random data in the first current time-domain model corresponding to each interface connection circuit model; and generating a third current time-domain model based on the current change of each power supply node in the digital circuit corresponding to the digital power domain. The simulation module is connected to the modeling module and is used to simulate the current step response of the current measurement point in each interface connection circuit model through a simulation program for integrated circuits (SPICE), thereby generating a corresponding first current time-domain model; and simulating the voltage step response of the voltage measurement point in each interface connection circuit model when receiving an ideal signal at the clock terminal through the simulation program for integrated circuits, thereby generating a corresponding first voltage time-domain model. The power noise module is connected to the modeling module and the simulation module and is used to connect the system power transmission model, each second current time-domain model, and each third current time-domain model to generate a complete power transmission model and obtain the power noise generated after obtaining the supply current from the complete power transmission model. The storage module is used to record a clock output by the phase-locked loop, and the phase-locked loop is connected to each interface connection circuit model. The jitter module is connected to the storage module and the power noise module and is used to simulate the sensitivity of each interface connection circuit model to the power supply based on the transmission of the clock signal output by the phase-locked loop through the simulation program for integrated circuits, thereby obtaining the jitter time-domain information of each interface connection circuit model under power noise.The analysis module is connected to the modeling module, the jitter module, and the simulation module, and is used to generate the system waveform corresponding to each interface-connected circuit model based on the jitter time-domain information of each interface-connected circuit model under power supply noise, the first voltage time-domain model corresponding to each interface-connected circuit model, and the data transmission in each interface-connected circuit model, and then obtain the eye diagram and the time-domain jitter distribution corresponding to each interface-connected circuit model.

[0008] In addition, the present invention discloses a simulation method for simulating and analyzing a full-chip system. The full-chip system includes a package structure, a printed circuit board, and a system-on-chip. The simulation method includes the following steps: (a) generating a signal channel model corresponding to each input / output power domain based on the design layout of the package structure and the printed circuit board; (b) generating a system power transmission model based on the design layout of the package structure and the printed circuit board and the distribution of multiple power supply nodes on the layout of the system-on-chip; (c) establishing an interface connection circuit model for each input / output power domain, where each interface connection circuit model includes a transmitter, its corresponding signal channel model, a receiver, a current measurement point, and a voltage measurement point. In each interface connection circuit model, the two sides of the signal channel model are respectively connected to the transmitter and the receiver. The transmitter has a data input terminal, a clock terminal, and an input / output power supply terminal. The current measurement point is set on the input / output power supply terminal, and the voltage measurement point is set at the connection between the signal channel model and the receiver; (d) simulating the current step response of the current measurement point in each interface connection circuit model through a simulation program with integrated circuit emphasis (SPICE), and then generating a corresponding first current time-domain model; (e) generating a corresponding second current time-domain model based on the response of the current measurement point when random data is received at the data input terminal in the first current time-domain model corresponding to each interface connection circuit model; (f) generating a third current time-domain model based on the current change of each power supply node in the digital circuit corresponding to the digital power domain; (g) connecting the system power transmission model, each second current time-domain model, and each third current time-domain model to generate a complete power transmission model, and obtaining the power noise generated after obtaining the supply current of the complete power transmission model; (h) recording the clock signal output by the phase-locked loop, and the phase-locked loop is connected to each interface connection circuit model; (i) simulating the power sensitivity of each interface connection circuit model through a simulation program with integrated circuit emphasis based on the transmission of the clock signal output by the phase-locked loop, and then obtaining the jitter time-domain information of each interface connection circuit model under power noise; (j) simulating the voltage step response of the voltage measurement point in each interface connection circuit model when an ideal signal is received at the clock terminal through a simulation program with integrated circuit emphasis, and then generating a corresponding first voltage time-domain model; and (k) generating a system waveform corresponding to each interface connection circuit model based on the jitter time-domain information of each interface connection circuit model under power noise, the first voltage time-domain model corresponding to each interface connection circuit model, and the transmission of data in each interface connection circuit model, and then obtaining the eye diagram and the time-domain jitter distribution corresponding to each interface connection circuit model.

[0009] The system and method disclosed by the present invention are as above. The difference from the prior art is that the present invention connects the system power supply transmission model, the analog current time domain model and the digital current time domain model, and obtains the power supply noise generated after obtaining the supply current; based on the transmission of the clock signal output by the phase-locked loop, the jitter time domain information of each interface connection circuit model under the power supply noise is obtained through focusing on the simulation program of the integrated circuit; by focusing on the simulation program of the integrated circuit, the voltage step response of the voltage measurement point at the clock terminal of each interface connection circuit model when receiving an ideal signal is simulated, and then the corresponding first voltage time domain model is generated; and based on the jitter time domain information of each interface connection circuit model under the power supply noise, the first voltage time domain model corresponding to each interface connection circuit model and the data transmission in each interface connection circuit model, the system waveform corresponding to each interface connection circuit model is generated, and then the eye diagram and the time domain jitter distribution corresponding to each interface connection circuit model are obtained.

[0010] Through the above technical means, the present invention can abstractly model the full-chip system to perform simulation analysis of signal integrity and power integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A It is a schematic diagram of components of an embodiment of the simulation system of the present invention.

[0012] Figure 1B It is a system architecture diagram of an embodiment of the simulation system of the present invention.

[0013] Figure 2A AND Figure 2B IS Figure 1B It is a flowchart of a method of an embodiment in which the simulation system executes a simulation analysis program.

[0014] Figure 3 It is a schematic diagram of an embodiment of the interface connection circuit model of the present invention.

[0015] Among them, the reference numerals

[0016] 50 Current measurement point

[0017] 60 Voltage measurement point

[0018] 72 Data input terminal

[0019] 74 Clock terminal

[0020] 76 Input / output power supply terminal

[0021] 100 Simulation system

[0022] 101 Processor

[0023] 102 Memory module

[0024] 103 Bus

[0025] 110 Modeling Module

[0026] 120 Simulation Module

[0027] 130 Power Supply Noise Module

[0028] 140 Storage Module

[0029] 150 Jitter Module

[0030] 160 Analysis Module

[0031] 170 Optimization Module

[0032] 180 Setting Module

[0033] 410 Transmitter

[0034] 420 Signal Channel Model

[0035] 430 Receiver

[0036] Step 210: Generate a signal channel model corresponding to each input / output power supply domain based on the design layout of the package structure and the printed circuit board

[0037] Step 220: Generate a system power transmission model based on the design layout of the package structure and the printed circuit board and the distribution of multiple power supply nodes on the layout of the system-on-chip

[0038] Step 230: Establish an interface connection circuit model for each input / output power supply domain. Each interface connection circuit model includes a transmitter, its corresponding signal channel model, a receiver, a current measurement point, and a voltage measurement point. In each interface connection circuit model, the signal channel model is connected to the transmitter and the receiver on both sides. The transmitter has a data input terminal, a clock terminal, and an input / output power supply terminal. The current measurement point is set on the input / output power supply terminal, and the voltage measurement point is set at the connection between the signal channel model and the receiver

[0039] Step 240: Simulate the current step response of the current measurement point in each interface connection circuit model through a simulation program focusing on the integrated circuit, and then generate a corresponding first current time-domain model

[0040] Step 250: Generate a corresponding second current time-domain model based on the response of the current measurement point when random data is received at the data input terminal in the first current time-domain model corresponding to each interface connection circuit model

[0041] Step 260: Generate a third current time-domain model based on the current change of each power supply node in the digital circuit corresponding to the digital power supply domain

[0042] Step 270: Connect the system power transmission model, each second current time-domain model, and each third current time-domain model to generate a complete power transmission model, and obtain the power noise generated after the complete power transmission model obtains the supply current.

[0043] Step 280: Record the clock signal output by the phase-locked loop, and the phase-locked loop is connected to each interface connection circuit model.

[0044] Step 290: Based on the transmission of the clock signal output by the phase-locked loop, simulate the power sensitivity of the interface connection circuit model through a simulation program focusing on the integrated circuit, and then obtain the jitter time-domain information of the interface connection circuit model under power noise.

[0045] Step 300: Simulate the voltage step response of the voltage measurement point at the clock terminal of each interface connection circuit model when receiving an ideal signal through a simulation program focusing on the integrated circuit, and then generate a corresponding first voltage time-domain model.

[0046] Step 310: Based on the jitter time-domain information of each interface connection circuit model under power noise, the first voltage time-domain model corresponding to each interface connection circuit model, and the data transmission in each interface connection circuit model, generate a system waveform corresponding to each interface connection circuit model, and then obtain the eye diagram and time-domain jitter distribution corresponding to each interface connection circuit model. Detailed implementation manner

[0047] The following will be described in detail the implementation manner of the present invention in conjunction with the drawings and embodiments, so as to fully understand how the present invention uses technical means to solve technical problems and achieve the implementation process of technical effects and implement accordingly.

[0048] Please first refer to Figure 1A and Figure 1B , Figure 1A which is a schematic diagram of components of an embodiment of the simulation system of the present invention, Figure 1B and

[0049] is a system architecture diagram of an embodiment of the simulation system of the present invention. In this embodiment, the simulation system 100 may include, but is not limited to, one or more processors 101, one or more memory modules 102, a bus 103, and other hardware components, where the bus 103 can connect different hardware components. Through the included multiple hardware components, the simulation system 100 can be applied to a computing device to execute corresponding software or program applications.Among them, the bus 103 may include one or more types, such as data bus, address bus, control bus, expansion bus, and / or local bus. The buses of the computing device include, but are not limited to, the parallel Industry Standard Architecture (ISA) bus, Peripheral Component Interconnect (PCI) bus, Video Electronics Standards Association (VESA) local bus, serial Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-E) bus, etc.

[0050] In this embodiment, the processor 101 may be coupled to the bus 103. The processor 101 may include a register group or register space, which may be completely set on the processing chip, or all or part of it may be set outside the processing chip and coupled to the processor 101 via dedicated electrical connections and / or via the bus 103. Among them, the processor 101 may be a processing unit, a microprocessor, or any suitable processing element. When the simulation system 100 includes multiple processors, these processors may be the same or similar processors, and are coupled and communicate via the bus 103. The processor 101 can interpret a series of multiple instructions to perform specific operations or operations, such as: mathematical operations, logical operations, data comparison, copying / moving data, etc., so as to execute various program applications, modules, and / or components.

[0051] In addition, the processor 101 may be coupled to the chipset or electrically connected to the chipset via the bus 103. Among them, the chipset is composed of one or more integrated circuits (ICs), including a memory controller and a peripheral input / output (I / O) controller. That is to say, the memory controller and the peripheral input / output controller may be included in one integrated circuit, or may be implemented using two or more integrated circuits. The chipset usually provides input / output and memory management functions, as well as provides multiple general-purpose and / or special-purpose registers, timers, etc. Among them, the above-mentioned general-purpose and / or special-purpose registers and timers can be accessed or used by one or more processors 101 coupled or electrically connected to the chipset.

[0052] In addition, the processor 101 can also access the data in the memory module 102 and the mass storage area installed on the simulation system 100 through the memory controller. The above-mentioned memory module 102 includes any type of volatile memory and / or non-volatile (non-volatile memory, NVRAM) memory, such as: static random access memory (SRAM), dynamic random access memory (DRAM), flash memory (Flash), read-only memory (ROM), etc. The above-mentioned mass storage area can include any type of storage device or storage medium, such as: hard disk drive, optical disc, USB flash drive (flash memory), memory card, solid state disk (Solid State Disk, SSD) or any other storage device, etc. That is to say, the memory controller can access the data in the static random access memory, dynamic random access memory, flash memory, hard disk drive, and solid state disk.

[0053] Furthermore, the processor 101 can also be connected and communicate with peripheral devices or interfaces such as peripheral output devices, peripheral input devices, communication interfaces, and GPS receivers via the bus 103 through the peripheral input / output controller. The peripheral input device can be any type of input device, such as: keyboard, mouse, trackball, touchpad, joystick, etc. The peripheral output device can be any type of output device, such as: monitor, printer, etc. The peripheral input device and the peripheral output device can also be the same device, such as a touch screen, etc. The communication interface can include a wireless communication interface and / or a wired communication interface. The wireless communication interface can include interfaces that support wireless local area networks such as Wi-Fi, Zigbee, Bluetooth, infrared, near field communication (NFC), mobile communication networks such as 3G / 4G / 5G, or other wireless data transmission protocols. The wired communication interface can be an Ethernet device, an asynchronous transfer mode (ATM) device, a DSL modem, a cable modem, etc. The processor 101 can periodically poll various peripheral devices and interfaces, so that the simulation system 100 can perform data input and output through various peripheral devices and interfaces.

[0054] As Figure 1BAs shown, the simulation system 100 includes a modeling module 110, a simulation module 120, a power noise module 130, a storage module 140, a jitter module 150, and an analysis module 160, as well as an optional optimization module 170 and a setting module 180. Among them, the modeling module 110, the simulation module 120, the power noise module 130, the storage module 140, the jitter module 150, the analysis module 160, the optimization module 170, and the setting module 180 are usually generated after the processor 101 executes a specific program loaded into the memory module 102, or are included in the processor 101. In actual implementation, the simulation system 100 can be applied to, but is not limited to, tablet computers, desktop computers, or laptop computers.

[0055] Next, please refer to Figure 2A and Figure 2B , Figure 2A and Figure 2B are Figure 1BFlowchart of a method for implementing one embodiment of a simulation analysis program in a simulation system. The simulation analysis program can be used to perform simulation analysis on a full-chip system, which includes a package structure, a printed circuit board, and a system-on-chip. The simulation analysis program includes the following steps: generating a signal channel model corresponding to each input / output power domain based on the design layouts of the package structure and the printed circuit board (step 210); generating a system power transmission model based on the design layouts of the package structure and the printed circuit board and the distribution of multiple power supply nodes on the layout of the system-on-chip (step 220); establishing an interface connection circuit model for each input / output power domain. Each interface connection circuit model includes a transmitter, its corresponding signal channel model, a receiver, a current measurement point, and a voltage measurement point. In each interface connection circuit model, the two sides of the signal channel model are respectively connected to the transmitter and the receiver. The transmitter has a data input terminal, a clock terminal, and an input / output power supply terminal. The current measurement point is set on the input / output power supply terminal, and the voltage measurement point is set at the connection between the signal channel model and the receiver (step 230); simulating the current step response of the current measurement point in each interface connection circuit model through a simulation program for integrated circuits (SPICE), and then generating a corresponding first current time-domain model (step 240); generating a corresponding second current time-domain model based on the response of the current measurement point when random data is received at the data input terminal of each interface connection circuit model corresponding to the first current time-domain model (step 250); generating a third current time-domain model based on the current change of each power supply node in the digital circuit corresponding to the digital power domain (step 260); connecting the system power transmission model, each second current time-domain model, and each third current time-domain model to generate a complete power transmission model, and obtaining the power noise generated after obtaining the supply current of the complete power transmission model (step 270); recording the clock signal output by the phase-locked loop, and the phase-locked loop is connected to each interface connection circuit model (step 280); based on the transmission of the clock signal output by the phase-locked loop, simulating the sensitivity of each interface connection circuit model to the power supply through a simulation program for integrated circuits, and then obtaining the jitter time-domain information of each interface connection circuit model under power noise (step 290); simulating the voltage step response of the voltage measurement point in each interface connection circuit model when an ideal signal is received at the clock terminal through a simulation program for integrated circuits, and then generating a corresponding first voltage time-domain model (step 300); generating a system waveform corresponding to each interface connection circuit model based on the jitter time-domain information of each interface connection circuit model under power noise, the first voltage time-domain model corresponding to each interface connection circuit model, and the transmission of data in each interface connection circuit model, and then obtaining the eye diagram and the time-domain jitter distribution corresponding to each interface connection circuit model.

[0056] In step 210, the modeling module 110 can use scattering parameters (S-parameters) or a one- to multi-order RLCG (resistance-inductance-capacitance-conductance) circuit to describe the package structure and the printed circuit board, so that the package structure and the printed circuit board are abstractly modeled. More specifically, the modeling module 110 can establish an electrical performance model corresponding to the package structure (i.e., the first power transmission model and the first signal transmission model) based on the design layout of the package structure. The model formats of the first power transmission model and the first signal transmission model can be S-parameters or RLCG circuits; the modeling module 110 can establish an electrical performance model corresponding to the printed circuit board (i.e., the second power transmission model and the second signal transmission model) based on the design layout of the printed circuit board. The model formats of the second power transmission model and the second signal transmission model can be S-parameters or RLCG circuits; then, the modeling module 110 can connect the first signal transmission model and the second signal transmission model based on the connection relationship between the package structure and the printed circuit board, and divide them according to different input / output power domains in the input / output interface, and then generate a signal channel model corresponding to each input / output power domain. At this time, the model format of the signal channel model corresponding to each input / output power domain can be S-parameters.

[0057] In step 220, the modeling module 110 can use a one- to multi-order RLCG circuit to describe the layout of the system-on-chip, so that the system-on-chip is abstractly modeled; therefore, the modeling module 110 can establish a third power transmission model corresponding to the system-on-chip by using an RLCG circuit based on the distribution of multiple power supply nodes on the layout of the system-on-chip (i.e., the parasitic resistance, parasitic capacitance, and parasitic inductance of the metal wires in the system-on-chip). Then, based on the power connection relationship between the package structure, the printed circuit board, and the system-on-chip (i.e., the actual channel of the power supply), connect the first power transmission model, the second power transmission model, and the third power transmission model to generate a system power transmission model. At this time, the model format of the system power transmission model can be S-parameters, but this embodiment is not intended to limit the present invention. For example, the model format of the system power transmission model can also be impedance parameters (Z-parameters).

[0058] In step 230, the modeling module 110 can establish a corresponding interface connection circuit model for each input / output power domain of the system-on-chip (as Figure 3 shown, Figure 3FIG. is a schematic diagram of an embodiment of the interface connection circuit model of the present invention. In each interface connection circuit model, it includes a transmitter 410, its corresponding signal channel model 420, a receiver 430, a current measurement point 50, and a voltage measurement point 60. In each interface connection circuit model, the two sides of the signal channel model 420 are respectively connected to the transmitter 410 and the receiver 420. The transmitter 410 has a data input terminal 72, a clock terminal 74, and an input / output power supply terminal 76. The current measurement point 50 is set on the input / output power supply terminal 76, and the voltage measurement point 60 is set at the connection between the signal channel model 420 and the receiver 430. The data input terminal 72 is used to receive the data to be transmitted through the transmitter 410, the clock terminal 74 is used to receive the clock signal, and the input / output power supply terminal 76 is used to receive the power from the input / output power supply domain.

[0059] In step 240, the simulation module 120 can simulate the current step response of the current measurement point 50 in each interface connection circuit model established by the modeling module 110 through a simulation program (SPICE) focusing on integrated circuits, and then generate a corresponding first current time domain model. More specifically, when the modeling module 110 establishes each interface connection circuit model, the simulation module 120 can simulate the current change of the current measurement point 50 when the data received by its data input terminal 72 changes from 0 to 1 (i.e., the data rising edge); and the current change of the current measurement point 50 when the data received by its data input terminal 72 changes from 1 to 0 (i.e., the data falling edge); Therefore, the simulation module 120 can simulate the current step response of each current measurement point 50 and generate a first current time domain model corresponding to each interface connection circuit model based on the current step response of each current measurement point 50.

[0060] In step 250, the modeling module 110 can generate a corresponding second current time-domain model based on the response of the current measurement point 50 of each interface-connected circuit model at its data input terminal 72 when receiving random data. More specifically, when the simulation module 120 generates a first current time-domain model corresponding to each interface-connected circuit model and its data input terminal 72 receives random data (e.g., 010010010001…), the modeling module 110 can compare the current data bit in the random data with the previous data bit to obtain the interface data change corresponding to each first current time-domain model; and based on the first current time-domain model corresponding to each interface-connected circuit model, the current step response of the current measurement point 50 of each first current time-domain model generated in step 240 (i.e., the simulation data in step 240), and the interface data change corresponding to each first current time-domain model, generate a second current time-domain model corresponding to each first current time-domain model. Among them, when the current data bit in the random data is the same as the previous data bit (i.e., there is no change), the current of the current measurement point 50 of the first current time-domain model is zero.

[0061] In step 260, the modeling module 110 can generate a third current time-domain model based on the current change of each power supply node in the digital circuit corresponding to the digital power domain. More specifically, the modeling module 110 can use the VCD file to find the data change of each power supply node in the digital circuit; use the standard cell library to find the current step response of each power supply node in any standard cell (i.e., the current change when the data of each power supply node changes from 0 to 1 or from 1 to 0), to generate the current time-domain model of each power supply node in the standard cell under its data change; and based on multiple standard cells to which each power supply node belongs, use the linear superposition method to obtain the current change of each power supply node, and then generate the third current time-domain model.

[0062] In step 270, the power noise module 130 can connect the system power transmission model, each second current time-domain model, and each third current time-domain model to generate a complete power transmission model, and obtain the power noise generated after the complete power transmission model obtains the supply current. In other words, when the complete power transmission model is generated, the power noise module 130 can make the complete power transmission model obtain the supply current, and then obtain the corresponding generated power noise.

[0063] In step 280, the storage module 140 can record the clock signal output by the phase-locked loop of the system single-chip, and the phase-locked loop is connected to each interface-connected circuit model. In other words, the storage module 140 can record the time-domain information corresponding to the clock edge of the clock signal output by the phase-locked loop, that is, record the clock edge for the actual waveform output by the phase-locked loop. Among them, the clock edge is the rising edge and the falling edge of the clock signal.

[0064] In step 290, the jitter module 150 can, based on the transmission of the clock signal output by the phase-locked loop (i.e., the clock signal transmitted from the phase-locked loop to the transmitter 410), simulate the sensitivity of each interface connection circuit model to the power supply through SPICE, and thereby obtain the jitter time-domain information of each interface connection circuit model under power supply noise. Among them, the jitter module 150 can also superimpose all the jitter time-domain information on the time-domain information corresponding to the clock edge of the clock signal output by the phase-locked loop in step 280 to generate the actual jitter time-domain information of the entire system.

[0065] In step 300, the simulation module 120 can simulate the voltage step response of the voltage measurement point 60 of each interface connection circuit model when its clock terminal 74 receives an ideal signal (i.e., an ideal clock signal) through SPICE, and thereby generate a corresponding first voltage time-domain model. More specifically, the simulation module 120 can simulate the voltage change of the voltage measurement point 60 when the data received by the data input terminal 72 of each interface connection circuit model changes from 0 to 1 while its clock terminal 74 receives an ideal clock signal; and the voltage change of the voltage measurement point 60 when the data received by the data input terminal 72 of each interface connection circuit model changes from 1 to 0 while its clock terminal 74 receives an ideal clock signal; Therefore, the simulation module 120 can simulate the voltage step response of the voltage measurement point 60 of each interface connection circuit model when its clock terminal 74 receives an ideal signal (i.e., an ideal clock signal), and generate a corresponding first voltage time-domain model based on the voltage step response of each voltage measurement point 60.

[0066] In step 310, the analysis module 160 can, based on the jitter time-domain information of each interface connection circuit model under power supply noise in step 290, the corresponding first voltage time-domain model of each interface connection circuit model generated in step 300, and the data transmission in each interface connection circuit model, generate a corresponding system waveform for each interface connection circuit model, and thereby obtain the eye diagram and time-domain jitter distribution corresponding to each interface connection circuit model.

[0067] Through the above steps, the full-chip system abstract model can be modeled to perform simulation analysis of its signal integrity and power integrity. In other words, quantitative analysis can be performed according to the performance requirements of the full-chip system (i.e., quantitative analysis of the overall system performance requirements for input / output interfaces, packages, and printed circuit boards), avoiding waste of area / power consumption during final integration due to the respective independent performance requirements of input / output interfaces, packages, and printed circuit boards.

[0068] In addition, in this embodiment, a setting program may be performed before executing the simulation analysis program (i.e., steps 210 to 310). The setting program may include: receiving and setting the capacitance value of the de-coupling capacity between the input / output circuit and the digital circuit corresponding to each input / output power domain in the system-on-chip, and the preset eye diagram standard corresponding to each input / output circuit. The setting module 180 may be connected to the modeling module 110 and execute the above setting program. The de-coupling capacitance of the system-on-chip is used to reduce the impact of power supply jitter.

[0069] In addition, in this embodiment, an optimization program may be performed after executing the simulation analysis program (i.e., steps 210 to 310). The optimization program includes: determining whether the eye diagram corresponding to each input / output circuit meets the corresponding preset eye diagram standard; and when it is determined that the eye diagram corresponding to a certain input / output circuit does not meet the corresponding preset eye diagram standard, adjusting the capacitance value of the de-coupling capacitance between the input / output circuit and the digital circuit, and re-executing the simulation analysis program until it is determined that the eye diagram corresponding to the input / output circuit meets the corresponding preset eye diagram standard. The optimization module 170 may be connected to the analysis module 160 and the setting module 180 and execute the above optimization program. Each preset eye diagram standard includes an eye width standard and / or an eye height standard.

[0070] Through the above optimization program, the impact of power supply jitter can be reduced by adjusting the capacitance value of each de-coupling capacitance of the system-on-chip, the number of de-coupling capacitances used in the traditional simulation method can be reduced, and thus the area waste caused by setting too many de-coupling capacitances can be avoided.

[0071] In summary, it can be seen that the differences between the present invention and the prior art lie in connecting the system power transmission model, the analog current time-domain model and the digital current time-domain model, and obtaining the power noise generated after obtaining the supply current; based on the transmission of the clock signal output by the phase-locked loop, obtaining the jitter time-domain information of each interface connection circuit model under power noise through focusing on the simulation program of the integrated circuit; simulating the voltage step response of the voltage measurement point at the clock terminal of each interface connection circuit model when receiving an ideal signal through focusing on the simulation program of the integrated circuit, and then generating a corresponding first voltage time-domain model; and generating a system waveform corresponding to each interface connection circuit model based on the jitter time-domain information of each interface connection circuit model under power noise, the first voltage time-domain model corresponding to each interface connection circuit model, and the data transmission in each interface connection circuit model, and then obtaining the eye diagram and the time-domain jitter distribution corresponding to each interface connection circuit model. Through this technical means, the full-chip system abstract model can be established to perform signal integrity and power integrity simulation analysis on it. In other words, quantitative analysis can be carried out according to the performance requirements of the full-chip system (that is, quantitative analysis is carried out for the overall system performance requirements of the input / output interface, package and printed circuit board), avoiding the waste of area / power consumption caused by the respective independent performance requirements of the input / output interface, package and printed circuit board during the final integration.

[0072] In addition, the optimization program of the present invention can reduce the influence of power jitter by adjusting the capacitance value of the isolation capacitor of the system single chip, can reduce the number of isolation capacitors used, and thus avoid the area waste caused by setting too many isolation capacitors.

[0073] Although the present invention is disclosed as above in the foregoing embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be subject to the content defined in the appended claims of this specification.

Claims

1. A simulation system, characterized in that, The simulation system includes: a memory module for storing a plurality of instructions; and a processor for executing the instructions stored in the memory module to perform a simulation analysis program on a full-chip system, the full-chip system including a packaging structure, a printed circuit board, and a system-on-chip, the simulation analysis program including: a modeling module for generating a signal channel model corresponding to each input / output power domain based on the design layout of the packaging structure and the printed circuit board; generating a system power transmission model based on the design layout of the packaging structure and the printed circuit board and the distribution of a plurality of power supply nodes on the layout of the system-on-chip; establishing an interface connection circuit model for each of the input / output power domains, wherein each interface connection circuit model includes a transmitter, the signal channel model corresponding to each input / output power domain, a receiver, a current measurement point, and a voltage measurement point. In each interface connection circuit model, the two sides of the signal channel model are respectively connected to the transmitter and the receiver. The transmitter has a data input terminal, a clock terminal, and an input / output power supply terminal. The current measurement point is disposed on the input / output power supply terminal, and the voltage measurement point is disposed at the connection between the signal channel model and the receiver; generating a corresponding second current time-domain model based on the response of the current measurement point when a random data is received at the data input terminal according to a first current time-domain model corresponding to each interface connection circuit model; and generating a third current time-domain model based on the current change of each power supply node in a digital circuit corresponding to a digital power domain; a simulation module connected to the modeling module for simulating a current step response of the current measurement point in each interface connection circuit model through a simulation program focusing on integrated circuits, thereby generating a corresponding first current time-domain model; and simulating a voltage step response of the voltage measurement point in each interface connection circuit model when an ideal signal is received at the clock terminal through the simulation program focusing on integrated circuits, thereby generating a corresponding first voltage time-domain model; a power noise module connected to the modeling module and the simulation module for connecting the system power transmission model, each of the second current time-domain models, and each of the third current time-domain models to generate a complete power transmission model, and obtaining a power noise generated after a supply current is obtained from the complete power transmission model; a storage module for recording a clock signal output by a phase-locked loop, the phase-locked loop being connected to each interface connection circuit model; a jitter module connected to the storage module and the power noise module for simulating the sensitivity of each interface connection circuit model to power through the simulation program focusing on integrated circuits based on the transmission of the clock signal output by the phase-locked loop, thereby obtaining a jitter time-domain information of each interface connection circuit model under the power noise; and An analysis module, connected to the modeling module, the jitter module, and the simulation module, is used to generate a system waveform corresponding to each interface-connected circuit model based on the jitter time-domain information of each interface-connected circuit model under the power noise, the first voltage time-domain model corresponding to each interface-connected circuit model, and the data transmission in each interface-connected circuit model, and then obtain an eye diagram and a time-domain jitter distribution corresponding to each interface-connected circuit model.

2. The simulation system according to claim 1, characterized in that, The format of each signal channel model is S-parameter, and the format of the system power transmission model is S-parameter or Z-parameter.

3. The simulation system according to claim 1, characterized in that, The modeling module uses a VCD file to find the data changes of each power supply node in the digital circuit; uses a standard cell library to find the current step response of each power supply node in any standard cell to generate the current change of each power supply node in the standard cell under its data change; and based on multiple standard cells to which each power supply node belongs, uses the linear superposition method to obtain the current change of each power supply node, and then generates the third current time-domain model.

4. The simulation system according to claim 1, characterized in that, When the first current time-domain model corresponding to each interface-connected circuit model receives the random data at the data input end, the modeling module compares the current data bit in the random data with the previous data bit to obtain an interface data change corresponding to each first current time-domain model; and based on the first current time-domain model corresponding to each interface-connected circuit model, the current step response of the current measurement point that generates each first current time-domain model, and the interface data change corresponding to each first current time-domain model, generates the second current time-domain model corresponding to each first current time-domain model, where when the current data bit in the random data is the same as the previous data bit, the current of the current measurement point of the first current time-domain model is zero.

5. The simulation system according to claim 1, characterized in that, The processor also executes the instructions stored in the memory module to perform a setting program before executing the simulation analysis program. The setting program includes: a setting module, connected to the modeling module, used to receive and set a capacitance value of a blocking capacitor between an input / output circuit corresponding to each input / output power supply domain in the system-on-chip and the digital circuit, and a preset eye diagram standard corresponding to each input / output circuit; the processor also executes the instructions stored in the memory module to perform an optimization program after executing the simulation analysis program. The optimization program includes: an optimization module, connected to the analysis module and the setting module, used to determine whether the eye diagram corresponding to each input / output circuit meets the corresponding preset eye diagram standard; and when it is determined that the eye diagram corresponding to a certain input / output circuit does not meet the corresponding preset eye diagram standard, adjust the capacitance value of the blocking capacitor between the input / output circuit and the digital circuit, and re-execute the simulation analysis program until it is determined that the eye diagram corresponding to the input / output circuit meets the corresponding preset eye diagram standard.

6. A simulation method, characterized in that, The simulation method is used to perform a simulation analysis on a full-chip system, which includes a packaging structure, a printed circuit board, and a system-on-chip. The simulation method includes the following steps: Based on the design layouts of the packaging structure and the printed circuit board, generate a signal channel model corresponding to each input / output power domain; Based on the design layouts of the packaging structure and the printed circuit board and the distribution of multiple power supply nodes on the layout of the system-on-chip, generate a system power transmission model; Establish an interface connection circuit model for each input / output power domain. Each interface connection circuit model includes a transmitter, its corresponding signal channel model, a receiver, a current measurement point, and a voltage measurement point. In each interface connection circuit model, the two sides of the signal channel model are respectively connected to the transmitter and the receiver. The transmitter has a data input terminal, a clock terminal, and an input / output power supply terminal. The current measurement point is set on the input / output power supply terminal, and the voltage measurement point is set at the connection between the signal channel model and the receiver; Through a simulation program focusing on integrated circuits, simulate a current step response of the current measurement point in each interface connection circuit model, and then generate a corresponding first current time-domain model; Based on the response of the current measurement point when a random data is received at the data input terminal in the first current time-domain model corresponding to each interface connection circuit model, generate a corresponding second current time-domain model; Based on the current changes of each power supply node in a digital circuit corresponding to a digital power domain, generate a third current time-domain model; Connect the system power transmission model, each second current time-domain model, and each third current time-domain model to generate a complete power transmission model, and obtain a power supply noise generated after obtaining a supply current by the complete power transmission model; Record a clock output by a phase-locked loop, and the phase-locked loop is connected to each interface connection circuit model; Based on the transmission of the clock output by the phase-locked loop, through the simulation program focusing on integrated circuits, simulate the sensitivity of each interface connection circuit model to the power supply, and then obtain a jitter time-domain information of each interface connection circuit model under the power supply noise; Through the simulation program focusing on integrated circuits, simulate a voltage step response of the voltage measurement point when an ideal signal is received at the clock terminal in each interface connection circuit model, and then generate a corresponding first voltage time-domain model; and Based on the jitter time-domain information of each interface connection circuit model under the power supply noise, the first voltage time-domain model corresponding to each interface connection circuit model, and the data transmission in each interface connection circuit model, generate a system waveform corresponding to each interface connection circuit model, and then obtain an eye diagram and a time-domain jitter distribution corresponding to each interface connection circuit model.

7. The simulation method according to claim 6, characterized in that, The format of each signal channel model is S-parameter, and the format of the system power transmission model is S-parameter or Z-parameter.

8. The simulation method according to claim 6, wherein, The steps of generating the third current time-domain model further include: Find the data changes of each power supply node in the digital circuit using a VCD file; Find the current step response of each power supply node in any standard cell using a standard cell library to generate the current change of each power supply node in the standard cell under its data change; and Based on multiple standard cells to which each power supply node belongs, obtain the current change of each power supply node using the linear superposition method, and then generate the third current time-domain model.

9. The simulation method according to claim 6, characterized in that,The steps of generating the corresponding second current time-domain model further include: When each interface connection circuit model connects the corresponding first current time-domain model and receives the random data at the data input end, compare the current data bit in the random data with the previous data bit to obtain an interface data change corresponding to each first current time-domain model, where when the current data bit in the random data is the same as the previous data bit, the current of the current measurement point of the first current time-domain model is zero; and Based on the first current time-domain model corresponding to each interface connection circuit model, the current step response of the current measurement point for generating each first current time-domain model, and the interface data change corresponding to each first current time-domain model, generate the second current time-domain model corresponding to each first current time-domain model.

10. The simulation method according to claim 6, characterized in that, Before the step of generating the signal channel model corresponding to each input / output power supply domain, the simulation method further includes: receiving and setting a capacitance value of a isolation capacitance between an input / output circuit corresponding to each input / output power supply domain in the system-on-chip and the digital circuit; after the step of obtaining the eye diagram and the time-domain jitter distribution corresponding to each interface connection circuit model, the simulation method further includes: determining whether the eye diagram corresponding to each input / output circuit meets a corresponding preset eye diagram standard; and when it is determined that the eye diagram corresponding to a certain input / output circuit does not meet the corresponding preset eye diagram standard, adjust the capacitance value of the isolation capacitance between the input / output circuit and the digital circuit, and re-execute the steps of generating the signal channel model corresponding to each input / output power supply domain to the step of obtaining the eye diagram and the time-domain jitter distribution corresponding to each interface connection circuit model until it is determined that the eye diagram corresponding to the input / output circuit meets the corresponding preset eye diagram standard.

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