Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. A device includes a master latch, a slave latch and a holding latch coupled to each other. The holding latch includes a first active region and a second active region, a first gate structure and a second gate structure. The first active region and the second active region extend in a first direction. The first gate structure extends in a second direction, and the first gate structure includes a first portion and a second portion separated from each other. The first portion is arranged above the first active region, and the second portion is arranged above the second active region. The second gate structure extends in the second direction and is arranged above the first active region. In the layout diagram, the second gate structure is separated from the second active region and the first gate structure. An end portion of the second active region is between the first gate structure and the second gate structure.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Electronic devices sometimes include one or more parts that are powered down when not in use to save energy and extend battery life. To provide continuity, data bits are often saved before the power-down event and then restored to their previous circuit positions once the powered-down parts are powered up again. Latch circuits are often used to save data bits. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a master latch; a slave latch coupled to the master latch; and a holding latch coupled to the master latch and the slave latch, and including: a first active region extending in a first direction; a second active region extending in the first direction; a first gate structure extending in a second direction different from the first direction, the first gate structure including a first portion and a second portion separated from each other, wherein the first portion is arranged above the first active region, and the second portion is arranged above the second active region; and a second gate structure extending in the second direction and arranged above the first active region, wherein, in a layout diagram, the second gate structure is separated from the second active region and the first gate structure, wherein an end portion of the second active region is between the first gate structure and the second gate structure.

[0004] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: generating a layout of a trigger device based on an electronic architecture design of a memory device, wherein the trigger device comprises a master latch, a slave latch and a holding latch coupled to each other; and manufacturing the trigger device based on the layout; wherein generating the layout of the trigger device comprises: arranging a first active area and a second active area separated from each other; arranging a plurality of first gates across the first active area and the second active area; arranging a second gate, wherein in the layout diagram, the second gate spans the first active area and is separated from the second active area; and cutting a first of the first gates into a first gate portion and a second gate portion, wherein the first gate portion is arranged above the first active area, and the second gate portion is arranged above the second active area.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a master latch; a slave latch coupled to the master latch; and a holding latch coupled to the master latch and the slave latch, and including: a first active region to a fourth active region extending in a first direction and separated from each other; and a first gate structure to a fourth gate structure extending in a second direction different from the first direction, wherein the first gate structure includes a first gate portion to a fourth gate portion, the first gate portion to the fourth gate portion are separated from each other and are respectively arranged on the first active region to the fourth active region, wherein, in a layout diagram, the second gate structure is arranged on the first active region and the fourth active region, and is separated from the second active region and the third active region, wherein the third gate structure includes a fifth gate portion and a sixth gate portion separated from each other, wherein the fifth gate portion is arranged on the first active region and the second active region, and the sixth gate portion is arranged on the third active region and the fourth active region, wherein the fourth gate structure is arranged on the third active region and the fourth active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a device according to some embodiments of the present disclosure.

[0008] Figure 2 According to some embodiments of the present disclosure Figure 1 Schematic diagram of circuit 110 .

[0009] Figure 3 According to some embodiments of the present disclosure Figure 2 A circuit diagram of the circuit 110 is shown.

[0010] Figure 4 is a schematic layout 400 of an integrated circuit according to some embodiments of the present disclosure, including Figure 3 The structure of the latch unit 310 in the holding latch 112 corresponds to the structure of the holding latch unit 310 in the holding latch 112.

[0011] Figure 5 is a schematic layout 500 of an integrated circuit according to some embodiments of the present disclosure, including Figure 3 The latch unit 310 and the transmission unit 320 in the holding latch 112 correspond to each other. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, materials, values, steps, and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features are formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spatially relative terms, such as "under," "below," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. The terms mask, photolithography mask, photomask, and reticle are used to refer to the same item.

[0014] The terms used throughout the following description and claims generally have their ordinary meanings in the art or as clearly established in the specific context in which each term is used. One of ordinary skill in the art will appreciate that a component or process may be referred to by different names. The many different embodiments detailed in this specification are illustrative only and in no way limit the scope and spirit of the disclosure or any exemplary term.

[0015] It is noteworthy that the terms (e.g., "first" and "second") used herein to describe various elements or processes are intended to distinguish one element or process from another element or process. However, elements, processes, and their order should not be limited by these terms. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and a second element may be similarly referred to as a first element.

[0016] In the following discussion and claims, the terms "including," "comprising," "containing," "having," "involving," etc. should be understood as open ended, i.e., interpreted to include, but not limited to. As used herein, the term "and / or" is not mutually exclusive and includes any associated listed items and all combinations of one or more of the associated listed items.

[0017] Figure 1 is a schematic diagram of a device according to some embodiments of the present disclosure. Figure 1 As shown schematically, device 100 includes circuits 110, 120, 130, and 140. In some embodiments, device 100 is configured in a retention flip-flop device. In some embodiments, device 100 is used to retain a state in a retention mode by latching a data bit on a retention latch.

[0018] In some embodiments, each of circuits 110, 120, 130, and 140 includes a holding latch and a register. Figure 1 As shown, circuits 110, 120, 130, and 140 include holding latches 112, 122, 132, and 142, respectively, and also include registers 114, 124, 134, and 144, respectively. In some embodiments, the term "holding latch" is also referred to as a "balloon latch."

[0019] The registers 114, 124, 134, and 144 are configured to operate according to the clock signal CLK and the latched bits of the data signal D1. The retention latches 112, 122, 132, and 142 are configured to receive the bits of the data signal D1 from the corresponding registers 114, 124, 134, and 144, and latch the bits of the data signal D1 when the device 100 enters the retention mode. When the retention mode ends, the retention latches 112, 122, 132, and 142 are configured to output the bits of the data signal D1 back to the corresponding registers 114, 124, 134, and 144 according to the recovery signal NRS.

[0020] In some embodiments, holding latch 112 is configured to latch bits of data signal D1 when circuit 110 is in holding mode, and to send bits of data signal D1 back to register 114 to restore the state of the output signal of register 114 when circuit 110 changes from holding mode to activation mode.

[0021] For illustrative purposes, Figure 1 The number of devices, holding latches, and registers in the MCU. Figure 1 Various numbers of devices, retention latches, and registers in the device 100 are within the contemplated scope of the present disclosure. For example, to increase the number of bits that can be latched by the device 100, in some embodiments, the number of devices, retention latches, or registers is a positive integer greater than four.

[0022] Figure 2 According to some embodiments of the present disclosure Figure 1 A schematic diagram of the circuit 110 is shown. Figure 2 In FIG. 1 , circuit 110 includes holding latch 112, register 114, and switches SW1 and SW2.

[0023] In some embodiments, switch SW1 is coupled between power supply voltage terminal VDD1 and node 213, and switch SW2 is coupled between power supply voltage terminal VDD1 and node 215. In some embodiments, power supply voltage terminal VDD1 is configured to receive a power supply voltage. Register 114 is coupled to power supply voltage terminal VDD2 at nodes 213 and 215. When switches SW1 and SW2 are turned on, power supply voltage terminal VDD2 is powered on to convert register 114 to an active mode, and when switches SW1 and SW2 are turned off, register 114 is converted to a hold mode. In some embodiments, switches SW1 and SW2 are configured to be controlled by signal SLP. In other words, circuit 110 operates in a hold mode or an active mode based on signal SLP.

[0024] In some embodiments, the holding latch 122 includes a master latch 202 and a slave latch 204, and the master latch 202 is coupled to the slave latch 204. The master latch 202 is configured to receive the data signal D1 and send the data signal D1 to the slave latch 204. The slave latch 204 is configured to output a signal Q1 according to the clock signal CLK and the data signal D1. In some embodiments, the signal Q1 has the state of the data signal D1 at the moment of the positive edge (or negative edge, depending on the type of the slave latch 204) of the clock signal CLK. Otherwise, the signal Q1 maintains the previous state. In other words, when the register 114 is not triggered by the clock signal CLK, the slave latch 204 latches the bit of the data signal D1 and outputs the latched bit corresponding to the signal Q1.

[0025] In some embodiments, the master latch 202 and the slave latch 204 are coupled to the power supply voltage terminal VDD2 at nodes 213 and 215, respectively. The switch SW1 is coupled between the power supply voltage terminal VDD1 and the node 213, and the switch SW2 is coupled between the power supply voltage terminal VDD1 and the node 215. When the switches SW1 and SW2 are turned off, the master latch 202 and the slave latch 204 are powered off and switched to the holding mode. When the switches SW1 and SW2 are turned on, the master latch 202 and the slave latch 204 are powered on and switched to the activation mode. In some embodiments, the holding latch 112 is configured to latch a bit of the data signal D1 in the holding mode, and when the circuit 110 is switched from the holding mode to the activation mode, the bit of the data signal D1 is sent back to the master latch 202 and the slave latch 204 through the through hole 217 to restore the state of the signal Q1.

[0026] Figure 3 According to some embodiments of the present disclosure Figure 2 The circuit diagram of the circuit 110 is shown in FIG. Figure 3 As schematically shown, circuit 110 includes holding latch 112 , master latch 202 , and slave latch 204 .

[0027] like Figure 3 As shown schematically, the holding latch 112 includes a latch unit 310 and a transmission unit 320. The latch unit 310 is configured to latch a bit of the data signal D1. The transmission unit 320 is configured to transmit a bit of the data signal D1 between the slave latch 204 and the holding latch 112 according to the signal S1.

[0028] like Figure 3 As shown schematically, latch unit 310 includes p-type transistors P11-P13 and n-type transistors N11-N13. Transistors P11 and N11 are coupled in series between power supply voltage terminal VDD1 and reference voltage terminal VSS. Sources of transistors P11 and N11 are coupled to power supply voltage terminal VDD1 and reference voltage terminal VSS, respectively. Drains of transistors P11 and N11 are coupled to each other at node 311. Control terminals of transistors P11 and N11 are coupled to each other at node 313. In some embodiments, transistors P11 and N11 are configured to act as inverters coupled between nodes 311 and 313. In some embodiments, reference voltage terminal VSS is configured to receive a ground voltage.

[0029] like Figure 3As shown schematically, transistors P12, P13, N13 and N12 are coupled in series between a power supply voltage terminal VDD1 and a reference voltage terminal VSS. The sources of transistors P12 and N12 are coupled to the power supply voltage terminal VDD1 and the reference voltage terminal VSS, respectively. The drains of transistors P13 and N13 are coupled to each other at a node 313. The control terminals of transistors P12 and N12 are coupled to each other at a node 311. The drain of transistor P12 and the source of transistor P13 are coupled to each other at a node 315. The drain of transistor N12 and the source of node N13 are coupled to each other at a node 317. In some embodiments, the control terminal of transistor P13 is configured to receive a signal S1, and the control terminal of transistor N13 is configured to receive a signal S1b as a complementary signal of signal S1. In some embodiments, transistors P12, P13, N13 and N12 are configured to be used as an inverter coupled to a transmission gate between nodes 311 and 313. In these embodiments, transistors P12 and N12 correspond to inverters, and transistors P13 and N13 correspond to transmission gates.

[0030] like Figure 3 As shown schematically, the transmission unit 320 includes p-type transistors P21-P23 and n-type transistors N21-N23. Transistors P23 and N23 are coupled in series between the power supply voltage terminal VDD1 and the reference voltage terminal VSS. The sources of transistors P23 and N23 are coupled to the power supply voltage terminal VDD1 and the reference voltage terminal VSS, respectively. The control terminals of transistors P23 and N23 are coupled to each other at a node 327 corresponding to signal S1. The drains of transistors P23 and N23 are coupled to each other at a node 329 corresponding to a signal S1b that is complementary to signal S1. In some embodiments, transistors P23 and N23 are configured to be used as an inverter that inverts signal S1 into signal S1b. In some embodiments, an inverter including transistors P23 and N23 is coupled between the control terminals of transistors P13 and N13, and is also coupled between the control terminals of transistors P22 and N22.

[0031] like Figure 3As shown schematically, transistors P21, P22, N22 and N21 are coupled in series between a power supply voltage terminal VDD1 and a reference voltage terminal VSS. The sources of transistors P21 and N21 are coupled to the power supply voltage terminal VDD1 and the reference voltage terminal VSS, respectively. The drains of transistors P22 and N22 are coupled to each other at a node 313. The control terminals of transistors P21 and N21 are coupled to each other at a node 321. The drain of transistor P21 and the source of transistor P22 are coupled to each other at a node 323. The drain of transistor N21 and the source of transistor N22 are coupled to each other at a node 325. The control terminal of transistor N22 is configured to receive a signal S1, and the control terminal of transistor P22 is configured to receive a signal S1b. In some embodiments, transistors P21, P22, N22 and N21 are configured to be used as an inverter coupled to a transmission gate between nodes 321 and 313. In these embodiments, transistors P12 and N12 correspond to inverters, and transistors P13 and N13 correspond to transmission gates.

[0032] like Figure 3 As shown schematically, the master latch 202 is configured to operate according to signals SI, SIb, CLKb, and CLKbb. The signal CLKb is the complement of the clock signal CLK. The signals SIb and CLKbb are the complements of the signals SI and CLKb, respectively. Figure 3 As schematically shown, the slave latch 204 is configured to operate according to the restored signal NRS and a signal NRSb, which is the complement of the restored signal NRS.

[0033] In some embodiments, Figure 1 Each of the circuits 120, 130 and 140 in Figure 2 and / or Figure 3 For example, circuit 120 includes a configuration similar to circuit 110 shown in FIG. Figure 2 The circuit 110 shown in FIG. 1 is configured to hold latches, master latches, slave latches, and switches (not shown) in the same configuration, and thus will not be described in detail herein. In some embodiments, the master latch of the circuit 120 is configured to hold latches, master latches, slave latches, and switches (not shown) in the same configuration as the circuit 110 shown in FIG. Figure 3 Receive signal SI1 at node 331 in the circuit 120. For another example, the holding latch of the circuit 120 includes Figure 3 The latch unit and the transmission unit (not shown) of the shown maintenance latch 112 have the same configuration, and thus are not described in detail here.

[0034] Figure 4 is a schematic layout 400 of an integrated circuit according to some embodiments of the present disclosure, including Figure 3The structure corresponding to the latch unit 310 in the holding latch 112. In some embodiments, the schematic layout 400 is implemented by a CAD (computer-aided design) layer of a static random access memory (SRAM) bit cell. In some embodiments, the CAD layer of the SRAM bit cell is also called a standard cell of the SRAM, and the standard cell is selected from a cell library for SRAM design. For simplicity of explanation, the schematic layout 400 only shows a portion of the structure, and a person of ordinary skill in the art can understand that the other portions of the structure are shown in FIG. Figure 4 Not described in detail.

[0035] like Figure 4 As shown schematically, schematic layout 400 includes active areas AA1, AA2 and gate structures GS1-GS4. In some embodiments, active areas AA1 and AA2 extend in, for example, the X direction, and gate structures GS1-GS4 extend in, for example, the Y direction which is different from the X direction. Figure 4 As shown schematically, gate structures GS1, GS3, and GS4 span active areas AA1 and AA2. Gate structure GS2 spans active area AA1 and is separated from active area AA2. In some embodiments, active areas AA1 and AA2 are formed by using semiconductor materials as doped regions. In some embodiments, gate structures GS1-GS4 are implemented by polysilicon, metal, doped polysilicon, or other suitable materials. In some embodiments, a fin structure including gate structures GS1-GS4 is formed on active areas AA1 and AA2 to form a fin field effect transistor (FinFET).

[0036] In some embodiments, each of the active areas AA1, AA2 has at least one doped region corresponding to a source or a drain of a transistor. Figure 4 As schematically shown, the active area AA1 includes doped areas NA1 - NA4 , and the active area AA2 includes doped areas PA1 - PA4 .

[0037] In some embodiments, the schematic layout 400 shares the CAD layer of the SRAM bit cell design. Therefore, the schematic layout 400 has the same size and approximately the same layout pattern as the SRAM design. Figure 4 In the schematic layout diagram, the gate structures GS1, GS3, and GS4 are arranged across the active areas AA1 and AA2, while the gate structure GS2 is arranged across the active area AA1 but separated from the active area AA2. In the layout diagram, the doped area PA1 corresponding to the end portion of the active area AA2 is arranged between the gate structures GS1 and GS2. In some embodiments, the distance between the gate structures GS1 and GS2 is the gate spacing, and in the example Figure 4In the schematically shown layout, the distance between the gate structure GS2 and the doped region PA1 is shorter than the gate pitch.

[0038] In some embodiments, the gate structures GS1, GS3, GS4 are arranged to form Figure 3 The gate structure GS1 is cut by the cutting section CR1 and separated into gate parts GP1 and GP2. The gate part GP1 is arranged on the active area AA1, and the gate part GP2 is arranged on the active area AA2. The doped areas NA1 and NA2 are located on two opposite sides of the gate part GP1. The doped areas PA1 and PA2 are located on two opposite sides of the gate part GP2.

[0039] For reference Figure 3 illustrate Figure 4 , the doping regions NA1 and NA2 and the gate portion GP1 of the active region AA1 correspond to the transistor N13. Accordingly, the doping regions PA1 and PA2 and the gate portion GP2 of the active region AA2 correspond to the transistor P13.

[0040] like Figure 4 As shown schematically, the gate structure GS3 is a continuous gate arranged on the active areas AA1 and AA2. The doped areas NA2 and NA3 of the active area AA1 are located on two opposite sides of the gate structure GS3. The doped areas PA2 and PA3 of the active area AA2 are also located on two opposite sides of the gate structure GS3.

[0041] For reference Figure 3 illustrate Figure 4 , the doping regions NA2 and NA3 and the gate structure GS3 of the active area AA1 correspond to the transistor N12. The doping regions PA2 and PA3 and the gate structure GS3 of the active area AA2 correspond to the transistor P12.

[0042] like Figure 4 As shown schematically, the gate structure GS4 is a continuous gate arranged on the active areas AA1 and AA2. The doped areas NA4 and NA3 of the active area AA1 are located on two opposite sides of the gate structure GS4. The doped areas PA4 and PA3 of the active area AA2 are also located on two opposite sides of the gate structure GS4.

[0043] For reference Figure 3 illustrate Figure 4 , the doping regions NA3 and NA4 and the gate structure GS4 of the active area AA1 correspond to the transistor N11. The doping regions PA3 and PA4 and the gate structure GS4 of the active area AA2 correspond to the transistor P11.

[0044] For reference Figure 3illustrate Figure 4 In some embodiments, doped region NA2 is shared by the source of transistor N13 and the drain of transistor N12, which corresponds to node 317. Doped region PA2 is shared by the source of transistor P13 and the drain of transistor P12, which corresponds to node 315.

[0045] For reference Figure 3 illustrate Figure 4 In some embodiments, the gate portion GP1 corresponding to the control terminal of the transistor N13 is configured to receive the signal S1b through the via NG1. In some embodiments, the gate portion GP2 corresponding to the control terminal of the transistor P13 is configured to receive the signal S1 through the via PG1. The doped region NA3 is coupled to the reference voltage terminal VSS through the via NC2 corresponding to the sources of the transistors N11 and N12. The doped region PA3 is coupled to the power supply voltage terminal VDD1 through the via PC2 corresponding to the sources of the transistors P11 and P12.

[0046] For reference Figure 3 illustrate Figure 4 In some embodiments, the doped regions PA1 and NA1 and the gate structure GS4 are coupled to each other through vias PC1, NC1, and NG2 corresponding to transistors P13 and N13. Figure 3 Doped regions PA4 and NA4 and gate structure GS3 are coupled to each other via nodes NC3, PC3 and PG2 corresponding to transistors P11 and N11, and P12 and N12 are coupled to each other at nodes 313 in FIG. Figure 3 The nodes 311 in are coupled to each other.

[0047] In some methods, a device corresponding to device 100 as described above is provided by corresponding to, for example, Figure 1 The latch of the holding latch 112 is operated in the holding mode. In order to reduce the leakage generated in the holding mode, the latch in the above method is implemented by an element with a higher threshold voltage. However, manufacturing an element with a higher threshold voltage requires an additional mask in the manufacturing process.

[0048] Compared with the above method, in some embodiments of the present disclosure, a CAD layer using SRAM bit cells is introduced to achieve, for example Figure 1 The concept of the holding latch 112. For example, the SRAM bit cell corresponding to Figure 4 The schematic layout 400 is configured to implement the Figure 3The latch unit 310 in the holding latch 112 of the device 100 is shown in FIG. 1 . Since the SRAM design has a relatively high threshold voltage performance, which results in low leakage, the circuit of the device 100 can be implemented using the schematic layout 400 corresponding to the SRAM bit cell to reduce leakage, as described above, and does not require the additional mask in the above method. In some embodiments, the embodiments of the present disclosure are used to implement, for example, Figure 1 At least one of the holding latches 112, 122, 132, 142 can reduce the leakage generated in the above method by 75%.

[0049] In some embodiments, Figure 1 Each of the holding latches 112, 122, 132, 142 can be manufactured by one or more masks associated with the SRAM design. In such an embodiment, Figure 1 The number of masks required in the manufacturing process of each holding latch 112, 122, 132, 142 is less than the number of masks required by the above method. In various embodiments, Figure 1 The number of masks required for each holding latch 112, 122, 132, 142 is 50% of the number of masks required for the above method.

[0050] In some embodiments, the dimensional parameters L1-L5 of the schematic layout 400 of the SRAM design are smaller than the corresponding dimensional parameters of the above-mentioned method. The dimensional parameters L1-L5 correspond to the surrounding contact space of the active area AA1, the gate spacing between the gate structures GS1 and GS2, the distance between the active areas AA1 and AA2, the width of the cutting section CR1, and the width of the active area AA2. In various embodiments, Figure 1 The area required for each holding latch 112, 122, 132, 142 is less than the area required for the above method.

[0051] In some embodiments, the retention latch 112 is implemented by a CAD layer of an SRAM design including at least one SRAM block. In some embodiments, the distance between the retention latch 112 and at least one SRAM block on the bit cell CAD layer is in the range of 10-500 gate pitches. In some other embodiments, the distance between the retention latch 112 and at least one SRAM block is greater than 500 gate pitches. Various distances between the retention latch 112 and at least one SRAM block are within the intended scope of the present disclosure.

[0052] Figure 5 is a schematic layout 500 of an integrated circuit according to some embodiments of the present disclosure, including Figure 3The structure corresponding to the latch unit 310 and the transmission unit 320 in the holding latch 112. In some embodiments, the schematic layout 500 is implemented by the CAD layer of the SRAM bit cell. For simplicity of explanation, the schematic layout 500 only shows a part of the structure, and a person skilled in the art can understand that the other parts of the structure are in FIG. Figure 5 Not described in detail.

[0053] For reference Figure 4 illustrate Figure 5 , the upper portion of schematic layout 500 is similar to schematic layout 400 . Figure 5 Follow and Figure 4 Similar notation conventions. For the sake of brevity, the discussion will focus more on Figure 4 and Figure 5 differences, not similarities.

[0054] like Figure 5 As shown schematically, schematic layout 500 includes active areas AA1-AA4 and gate structures GS1-GS4. In some embodiments, active areas AA1-AA4 extend in, for example, the X direction, and gate structures GS1-GS4 extend in, for example, the Y direction which is different from the X direction. Figure 5 As shown schematically, gate structures GS1, GS3 and GS4 span active areas AA1-AA4. Gate structure GS2 spans active areas AA1, AA4 and is separated from active areas AA2, AA3. In some embodiments, active areas AA1-AA4 are formed by using semiconductor materials as doped regions. In some embodiments, gate structures GS1-GS4 are implemented by polysilicon, metal, doped polysilicon, or other suitable materials. In some embodiments, a fin structure including gate structures GS1-GS4 is formed on active areas AA1-AA4 to form a fin field effect transistor (FinFET).

[0055] In some embodiments, each of the active areas AA1-AA4 has at least one doped region corresponding to a source or drain of a transistor. Figure 5 As schematically shown, the active area AA1 includes doped areas NA1 - NA4 , the active area AA2 includes doped areas PA1 - PA4 , the active area AA3 includes doped areas PA5 - PA8 , and the active area AA4 includes doped areas NA5 - NA8 .

[0056] In some embodiments, schematic layout 500 shares the bit cell CAD layer of an SRAM design. Thus, schematic layout 500 has the same size and approximately the same layout pattern as the SRAM design. Figure 5In the schematic layout diagram, gate structures GS1, GS3, and GS4 are arranged across active areas AA1-AA4, while gate structure GS2 is arranged across active areas AA1 and AA4 but separated from active areas AA2 and AA3. In the layout diagram, doped area PA1 corresponding to the end portion of active area AA2 is arranged between gate structures GS1 and GS2. In the layout diagram, doped area PA5 corresponding to the end portion of active area AA3 is arranged between gate structures GS1 and GS2. In some embodiments, in the example Figure 5 In the schematically shown layout, the distance between the gate structures GS1 and GS2 is the gate pitch, and the distance between the gate structure GS2 and the doped region PA1 and the distance between the gate structure GS2 and the doped region PA5 are both shorter than the gate pitch.

[0057] In some embodiments, the gate structures GS1, GS3, GS4 are arranged to form Figure 3 The transistors P11-P13, P21-P23, N11-N13 and N21-N23 in the gate structure GS1 are cut and separated into gate parts GP1, GP2, GP5 and GP6 by cutting segments CR1-CR3. The gate parts GP1, GP2, GP5 and GP6 are arranged on active areas AA1-AA4, respectively. Doped regions NA1 and NA2 are located on two opposite sides of the gate part GP1. Doped regions PA1 and PA2 are located on two opposite sides of the gate part GP2. Doped regions NA5 and NA6 are located on two opposite sides of the gate part GP6. Doped regions PA5 and PA6 are located on two opposite sides of the gate part GP5.

[0058] For reference Figure 3 illustrate Figure 5 , the doping regions NA1 and NA2 and the gate portion GP1 of the active area AA1 correspond to the transistor N13. Correspondingly, the doping regions PA1 and PA2 and the gate portion GP2 of the active area AA2 correspond to the transistor P13. The doping regions PA5 and PA6 and the gate portion GP5 of the active area AA3 correspond to the transistor P22. The doping regions NA5 and NA6 and the gate portion GP6 of the active area AA4 correspond to the transistor N22.

[0059] like Figure 5 As shown schematically, the gate structure GS3 is cut and separated into gate parts GP3 and GP7 by the cutting segment CR2. The gate part GP3 ​​is arranged on the active areas AA1 and AA2. The doped areas NA2 and NA3 of the active area AA1 are located on two opposite sides of the gate part GP3. The doped areas PA2 and PA3 of the active area AA2 are also located on two opposite sides of the gate part GP3.

[0060] For reference Figure 3 illustrate Figure 5 , the doping regions NA2 and NA3 and the gate portion GP3 of the active region AA1 correspond to the transistor N12. The doping regions PA2 and PA3 and the gate portion GP3 of the active region AA2 correspond to the transistor P12.

[0061] like Figure 5 As schematically shown, gate portion GP7 is arranged above active areas AA3 and AA4. Doped areas PA6 and PA7 of active area AA3 are located on two opposite sides of gate portion GP7. Doped areas NA6 and NA7 of active area AA4 are also located on two opposite sides of gate portion GP7.

[0062] For reference Figure 3 illustrate Figure 5 , the doping regions NA6 and NA7 and the gate portion GP7 of the active region AA4 correspond to the transistor N21. The doping regions PA6 and PA7 and the gate portion GP7 of the active region AA3 correspond to the transistor P21.

[0063] like Figure 5 As shown schematically, the gate structure GS4 is cut by the cutting segment CR2 and separated into gate portions GP4 and GP8. The gate portion GP4 is arranged on the active areas AA1 and AA2. The doped areas NA3 and NA4 of the active area AA1 are located on two opposite sides of the gate portion GP4. The doped areas PA3 and PA4 of the active area AA2 are also located on two opposite sides of the gate portion GP4.

[0064] For reference Figure 3 illustrate Figure 5 , the doping regions NA3 and NA4 and the gate portion GP4 of the active region AA1 correspond to the transistor N11. The doping regions PA3 and PA4 and the gate portion GP3 of the active region AA2 correspond to the transistor P11.

[0065] like Figure 5 As schematically shown, gate portion GP8 is arranged above active areas AA3 and AA4. Doped areas PA7 and PA8 of active area AA3 are located on two opposite sides of gate portion GP8. Doped areas NA7 and NA8 of active area AA4 are also located on two opposite sides of gate portion GP8.

[0066] For reference Figure 3 illustrate Figure 5 , the doping regions NA7 and NA8 and the gate portion GP8 of the active region AA4 correspond to the transistor N23. The doping regions PA7 and PA8 and the gate portion GP8 of the active region AA3 correspond to the transistor P23.

[0067] In with Figure 4 The above embodiments described in connection with the gate portions GP1-GP4, the active regions AA1-AA2, and the transistors P11-P13, N11-N13 are described in detail. Figure 5 These descriptions will not be repeated in the associated embodiments.

[0068] For reference Figure 3 illustrate Figure 5 In some embodiments, doped region NA6 is shared by the source of transistor N22 and the drain of transistor N21, which corresponds to node 325. Doped region PA6 is shared by the source of transistor P22 and the drain of transistor P21, which corresponds to node 323.

[0069] For reference Figure 3 illustrate Figure 5 In some embodiments, the gate portion GP5 corresponding to the control terminal of the transistor P22 is configured to receive the signal S1b through the through hole PG3. The gate portion GP6 corresponding to the control terminal of the transistor N22 is configured to receive the signal S1 through the through hole NG3. The gate portion GP8 corresponding to the control terminals of the transistors N23 and P23 is configured to receive the signal S1 through the through hole NG4. The doped region NA7 corresponding to the sources of the transistors N21 and N23 is coupled to the reference voltage terminal VSS through the through hole NC5. The doped region PA7 is coupled to the power supply voltage terminal VDD1 through the through hole PC5 corresponding to the sources of the transistors P21 and P23.

[0070] For reference Figure 3 illustrate Figure 5 In some embodiments, doped regions PA5, NA5, NA1, PA1 and gate portion GP4 are coupled to each other through vias PC4, NC4, PC1, NC1 and NG2 corresponding to transistors P22, N22, P13, N13, P11 and N11 in Figure 3 The gate portion GP7 is coupled to the node 313 in the Figure 3 The via PG4 corresponding to the node 321 of the slave latch 204 in the embodiment is coupled to the slave latch 204. The gate portion GP8 corresponding to the control terminal of the transistors N23 and P23 is configured to be connected to the slave latch 204 through the via PG4 corresponding to the node 321 of the slave latch 204 in the embodiment. Figure 3 The via NG4 corresponding to the node 327 in the doped regions PA8 and NA8 is configured to receive the signal S1. Figure 3 The vias PC6 and NC6 corresponding to the node 329 in receive the signal S1b and are coupled to each other.

[0071] In some embodiments, regarding the use of SRAM design Figure 4 and Figure 5 The schematic layouts 400 and 500 are used to design and manufacture Figure 1 The circuit 110 in the embodiment reduces the leakage of the holding latch 112 without increasing the number of masks required. In addition, in some embodiments, the size of the holding latch 112 of the schematic layouts 400 and 500 designed using SRAM is reduced.

[0072] A device is also disclosed, including a master latch, a slave latch and a holding latch. The slave latch is coupled to the master latch. The holding latch is coupled to the master latch and the slave latch, and includes a first active region, a second active region, a first gate structure, and a second gate structure. The first active region extends in a first direction. The second active region extends in the first direction. The first gate structure extends in a second direction different from the first direction, and the first gate structure includes a first portion and a second portion separated from each other. The first portion is arranged on the first active region, and the second portion is arranged on the second active region. The second gate structure extends in the second direction and is arranged on the first active region. In the layout diagram, the second gate structure is separated from the second active region and the first gate structure. The end portion of the second active region is between the first gate structure and the second gate structure.

[0073] A method is also disclosed, including: generating a layout of a trigger device based on an electronic architecture design of a memory device, wherein the trigger device includes a master latch, a slave latch, and a holding latch coupled to each other; manufacturing the trigger device based on the layout; wherein generating the layout of the trigger device includes: arranging a first active area and a second active area separated from each other; arranging a plurality of first gates across the first active area and the second active area; arranging a second gate, which in the layout diagram spans the first active area and is separated from the second active area; cutting the first first gate into a first gate portion and a second gate portion, wherein the first gate portion is arranged above the first active area, and the second gate portion is arranged above the second active area.

[0074] A device is also disclosed, including a master latch, a slave latch and a holding latch. The slave latch is coupled to the master latch. The holding latch is coupled to the master latch and the slave latch, and includes a first active region to a fourth active region and a first gate structure to a fourth gate structure. The first active region to the fourth active region extend in a first direction and are separated from each other. The first gate structure to the fourth gate structure extend in a second direction different from the first direction. The first gate structure includes a first gate portion to a fourth gate portion, which are separated from each other and are respectively arranged on the first active region to the fourth active region. In the layout diagram, the second gate structure is arranged on the first active region and the fourth active region, and is separated from the second active region and the third active region. The third gate structure includes a fifth gate portion and a sixth gate portion separated from each other. The fifth gate portion is arranged on the first active region and the second active region, and the sixth gate portion is arranged on the third active region and the fourth active region. The fourth gate structure is arranged on the third active region and the fourth active region.

[0075] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0076] Example 1 is a semiconductor device, comprising: a master latch; a slave latch coupled to the master latch; and a holding latch coupled to the master latch and the slave latch, and comprising: a first active region extending in a first direction; a second active region extending in the first direction; a first gate structure extending in a second direction different from the first direction, the first gate structure comprising a first portion and a second portion separated from each other, wherein the first portion is arranged above the first active region and the second portion is arranged above the second active region; and a second gate structure extending in the second direction and arranged above the first active region, wherein, in a layout diagram, the second gate structure is separated from the second active region and the first gate structure, wherein an end portion of the second active region is between the first gate structure and the second gate structure.

[0077] Example 2 is a device described in Example 1, wherein the holding latch further includes: a third gate structure extending in the second direction and arranged above the first active region and the second active region; and a fourth gate structure extending in the second direction and arranged above the first active region and the second active region; wherein the third gate structure is arranged between the first gate structure and the fourth gate structure.

[0078] Example 3 is the device described in Example 2, wherein the first portion of the first gate structure corresponds to the control terminal of the first transistor; the second portion of the first gate structure corresponds to the control terminal of the second transistor; the third gate structure corresponds to the control terminals of the third transistor and the fourth transistor; the fourth gate structure corresponds to the control terminals of the fifth transistor and the sixth transistor, and the first transistor to the sixth transistor are configured to latch data bits.

[0079] Example 4 is the device of Example 1, wherein the first portion of the first gate structure is configured to receive a first operating signal, and the second portion of the first gate structure is configured to receive a second operating signal complementary to the first operating signal.

[0080] Example 5 is the device of Example 1, wherein, in the layout diagram, a distance between the second gate structure and the second active region is shorter than a gate pitch.

[0081] Example 6 is a device described in Example 1, wherein the holding latch further includes: a third active region extending in the first direction and separated from the second gate structure; and a fourth active region extending in the first direction, wherein the second gate structure is arranged above the fourth active region; wherein the first gate structure further includes a third portion arranged above the third active region and a fourth portion arranged above the fourth active region, and wherein the first to fourth portions of the first gate are separated from each other.

[0082] Example 7 is the device of Example 6, wherein a distance between the second gate structure and the third active region is shorter than a gate pitch.

[0083] Example 8 is the device described in Example 6, wherein the holding latch further includes: a third gate structure extending in the second direction and arranged above the third active region and the fourth active region; wherein the first gate structure is arranged between the second gate structure and the third gate structure.

[0084] Example 9 is the device described in Example 8, wherein the third part and the fourth part correspond to control terminals of the first transistor and the second transistor, respectively, and the third gate structure corresponds to control terminals of the third transistor and the fourth transistor, and the first transistor to the fourth transistor are configured to function as inverters coupled to a transmission gate.

[0085] Example 10 is the device described in Example 6, wherein the holding latch further includes: a third gate structure extending in the second direction and including a fifth portion and a sixth portion separated from each other, wherein the fifth portion is arranged above the first active region and the second active region, and the sixth portion is arranged above the third active region and the fourth active region, and wherein the first gate structure is arranged between the second gate structure and the third gate structure.

[0086] Example 11 is the device described in Example 10, wherein the first to fourth portions of the first gate structure correspond to control terminals of the first to fourth transistors, respectively, the fifth portion of the third gate structure corresponds to control terminals of the fifth and sixth transistors, the sixth portion of the third gate structure corresponds to control terminals of the seventh and eighth transistors, the first transistor, the second transistor, the fifth transistor, and the sixth transistor are configured to function as a first inverter coupled to a first transmission gate, and the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are configured to function as a second inverter coupled to a second transmission gate.

[0087] Example 12 is a method for manufacturing a semiconductor device, comprising: generating a layout of a trigger device based on an electronic architecture design of a memory device, wherein the trigger device includes a master latch, a slave latch, and a holding latch coupled to each other; and manufacturing the trigger device based on the layout; wherein generating the layout of the trigger device includes: arranging a first active area and a second active area separated from each other; arranging a plurality of first gates across the first active area and the second active area; arranging a second gate, in the layout diagram, the second gate spans the first active area and is separated from the second active area; and cutting the first of the first gates into a first gate portion and a second gate portion, wherein the first gate portion is arranged above the first active area, and the second gate portion is arranged above the second active area.

[0088] Example 13 is the method described in Example 12, further comprising: latching data bits through a first transistor to a sixth transistor, wherein the first gate portion and the second gate portion correspond to control terminals of the first transistor and the second transistor, respectively, a second first gate portion corresponds to control terminals of a third transistor and a fourth transistor, and a third first gate portion corresponds to control terminals of a fifth transistor and a sixth transistor.

[0089] Example 14 is the method of Example 12, wherein generating a layout of the flip-flop device further comprises: arranging an end portion of the second active region between the second gate portion and the second gate.

[0090] Example 15 is the method of Example 12, further comprising: selecting the electronic architecture design of the memory device from a cell library used to design the layout, wherein the memory device corresponds to a static random access memory device.

[0091] Example 16 is the method described in Example 12, wherein generating the layout of the trigger device also includes: arranging a third active region and a fourth active region separated from each other, wherein the second active region and the third active region are arranged between the first active region and the fourth active region; cutting the first first gate into a third gate portion and a fourth gate portion, wherein the third gate portion is arranged above the third active region, and the fourth gate portion is arranged above the fourth active region; and cutting the second first gate into a fifth gate portion and a sixth gate portion, wherein the fifth gate portion is arranged above the first active region and the second active region, and the sixth gate portion is arranged above the third active region and the fourth active region.

[0092] Example 17 is the method described in Example 16, further including: receiving a first operating signal through the third gate portion; receiving a second operating signal complementary to the first operating signal through the fourth gate portion; wherein the third gate portion and the fourth gate portion correspond to control terminals of the first transistor and the second transistor, respectively, wherein the sixth gate portion corresponds to control terminals of the third transistor and the fourth transistor, and wherein the first transistor to the fourth transistor are configured to function as inverters coupled to a transmission gate.

[0093] Example 18 is a semiconductor device, comprising: a master latch; a slave latch coupled to the master latch; and a holding latch coupled to the master latch and the slave latch, and comprising: a first active region to a fourth active region extending in a first direction and separated from each other; and a first gate structure to a fourth gate structure extending in a second direction different from the first direction, wherein the first gate structure comprises a first gate portion to a fourth gate portion, the first gate portion to the fourth gate portion are separated from each other and are respectively arranged on the first active region to the fourth active region, wherein, in the layout diagram, the second gate structure is arranged on the first active region and the fourth active region, separated from the second active region and the third active region, wherein the third gate structure comprises a fifth gate portion and a sixth gate portion separated from each other, wherein the fifth gate portion is arranged on the first active region and the second active region, and the sixth gate portion is arranged on the third active region and the fourth active region, wherein the fourth gate structure is arranged on the third active region and the fourth active region.

[0094] Example 19 is a device described in Example 18, wherein the first gate portion to the fourth gate portion correspond to control terminals of the first transistor to the fourth transistor respectively, the fifth gate portion corresponds to the control terminals of the fifth transistor and the sixth transistor, the sixth gate portion corresponds to the control terminals of the seventh transistor and the eighth transistor, and the fourth gate structure corresponds to the control terminals of the ninth transistor and the tenth transistor, wherein the first transistor, the second transistor, the fifth transistor and the sixth transistor are configured to serve as a first inverter coupled to a first transmission gate, wherein the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are configured to serve as a second inverter coupled to a second transmission gate, wherein the ninth transistor and the tenth transistor are configured to serve as a third inverter coupled between the first control terminal and the second control terminal of the second transmission gate.

[0095] Example 20 is the device described in Example 19, wherein the holding latch further includes: a fifth gate structure extending in the second direction and arranged above the first active region and the second active region; wherein the fifth gate structure is configured to serve as a first terminal of a fourth inverter, wherein the first terminal of the fourth inverter is coupled to the first terminals of the first transmission gate and the second transmission gate, and the second terminal of the fourth inverter is coupled to the first terminal of the first inverter.

Claims

1. A semiconductor device, comprising: Master latch; a slave latch coupled to the master latch; as well as A holding latch coupled to the master latch and the slave latch and comprising: a first active region extending in a first direction; a second active region extending in the first direction; a first gate structure extending in a second direction different from the first direction, the first gate structure comprising a first portion and a second portion separated from each other, wherein the first portion is arranged on the first active region, and the second portion is arranged on the second active region; and a second gate structure extending in the second direction and arranged on the first active region, wherein in the layout diagram, the second gate structure is separated from the second active region and the first gate structure, An end portion of the second active region is between the first gate structure and the second gate structure.

2. The device according to claim 1, wherein The holding latch further comprises: a third gate structure extending in the second direction and arranged on the first active region and the second active region; and a fourth gate structure extending in the second direction and arranged on the first active region and the second active region; Wherein, the third gate structure is arranged between the first gate structure and the fourth gate structure.

3. The device according to claim 2, wherein The first portion of the first gate structure corresponds to a control terminal of the first transistor; The second portion of the first gate structure corresponds to a control terminal of a second transistor; The third gate structure corresponds to the control terminals of the third transistor and the fourth transistor; The fourth gate structure corresponds to the control terminals of the fifth transistor and the sixth transistor, and The first to sixth transistors are configured to latch a data bit.

4. The device according to claim 1, wherein A first portion of the first gate structure is configured to receive a first operating signal, and a second portion of the first gate structure is configured to receive a second operating signal complementary to the first operating signal.

5. The device according to claim 1, wherein In the layout diagram, a distance between the second gate structure and the second active region is shorter than a gate pitch.

6. The device according to claim 1, wherein The holding latch further comprises: a third active region extending in the first direction and separated from the second gate structure; and a fourth active region extending in the first direction, wherein the second gate structure is arranged on the fourth active region; The first gate structure further includes a third portion arranged on the third active region and a fourth portion arranged on the fourth active region, and The first part to the fourth part of the first gate structure are separated from each other.

7. The device according to claim 6, wherein A distance between the second gate structure and the third active region is shorter than a gate pitch.

8. The device according to claim 6, wherein The holding latch further comprises: a third gate structure extending in the second direction and arranged on the third active region and the fourth active region; Wherein, the first gate structure is arranged between the second gate structure and the third gate structure.

9. The device according to claim 8, wherein The third portion and the fourth portion correspond to control terminals of the first transistor and the second transistor, respectively, and The third gate structure corresponds to control terminals of third and fourth transistors, the first to fourth transistors being configured to function as inverters coupled to a transmission gate.

10. The device according to claim 6, wherein The holding latch further comprises: a third gate structure extending in the second direction and comprising a fifth portion and a sixth portion separated from each other, wherein the fifth portion is arranged on the first active region and the second active region, and the sixth portion is arranged on the third active region and the fourth active region, and Wherein, the first gate structure is arranged between the second gate structure and the third gate structure.

11. The device according to claim 10, wherein The first to fourth portions of the first gate structure correspond to control terminals of the first to fourth transistors, respectively. The fifth portion of the third gate structure corresponds to the control terminals of the fifth transistor and the sixth transistor, The sixth portion of the third gate structure corresponds to the control terminals of the seventh transistor and the eighth transistor, The first transistor, the second transistor, the fifth transistor, and the sixth transistor are configured to function as a first inverter coupled to a first transmission gate, and The third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are configured to function as a second inverter coupled to a second transmission gate.

12. A method for manufacturing a semiconductor device, comprising: Based on the electronic architecture design of the memory device, generating a layout of a flip-flop device, wherein the flip-flop device includes a master latch, a slave latch, and a holding latch coupled to each other; and manufacturing the trigger device based on the layout; Wherein, generating the layout of the trigger device includes: arranging a first active region and a second active region separated from each other; Arranging a plurality of first gates across the first active region and the second active region; Arranging a second gate, wherein in the layout diagram, the second gate crosses the first active region and is separated from the second active region; and A first of the first gates is cut into a first gate portion and a second gate portion, wherein the first gate portion is arranged on the first active region, and the second gate portion is arranged on the second active region.

13. The method according to claim 12, further comprising: The data bit is latched by the first transistor to the sixth transistor, wherein, The first gate portion and the second gate portion correspond to control terminals of the first transistor and the second transistor, respectively, The second of the first gates corresponds to control terminals of the third transistor and the fourth transistor, and A third of the first gates corresponds to control terminals of the fifth transistor and the sixth transistor.

14. The method according to claim 12, wherein: Generating the layout of the trigger device also includes: An end portion of the second active region is disposed between the second gate portion and the second gate.

15. The method according to claim 12, further comprising: The electronic architecture design of the memory device is selected from a cell library used to design the layout, wherein the memory device corresponds to a static random access memory device.

16. The method according to claim 12, wherein: Generating the layout of the trigger device also includes: Arranging a third active region and a fourth active region separated from each other, wherein the second active region and the third active region are arranged between the first active region and the fourth active region; cutting a first of the first gates into a third gate portion and a fourth gate portion, wherein the third gate portion is arranged on the third active region, and the fourth gate portion is arranged on the fourth active region; and The second first gate is cut into a fifth gate portion and a sixth gate portion, wherein the fifth gate portion is arranged on the first active region and the second active region, and the sixth gate portion is arranged on the third active region and the fourth active region.

17. The method according to claim 16, further comprising: receiving a first operation signal through the third gate portion; receiving a second operating signal complementary to the first operating signal through the fourth gate portion; wherein the third gate portion and the fourth gate portion correspond to control terminals of the first transistor and the second transistor, respectively, wherein the sixth gate portion corresponds to the control terminals of the third transistor and the fourth transistor, The first to fourth transistors are configured to function as inverters coupled to a transmission gate.

18. A semiconductor device comprising: Master latch; a slave latch coupled to the master latch; as well as A holding latch coupled to the master latch and the slave latch and comprising: First to fourth active regions extending in a first direction and separated from each other; and The first gate structure to the fourth gate structure extend in a second direction different from the first direction, The first gate structure includes a first gate portion to a fourth gate portion, the first gate portion to the fourth gate portion are separated from each other and are respectively arranged on the first active region to the fourth active region, In the layout diagram, the second gate structure is arranged on the first active region and the fourth active region, and is separated from the second active region and the third active region. wherein the third gate structure includes a fifth gate portion and a sixth gate portion separated from each other, wherein the fifth gate portion is arranged on the first active region and the second active region, and the sixth gate portion is arranged on the third active region and the fourth active region, The fourth gate structure is arranged on the third active region and the fourth active region.

19. The device according to claim 18, wherein The first to fourth gate portions correspond to control terminals of the first to fourth transistors, respectively, The fifth gate portion corresponds to a control terminal of the fifth transistor and the sixth transistor, The sixth gate portion corresponds to control terminals of the seventh transistor and the eighth transistor, and The fourth gate structure corresponds to the control terminals of the ninth transistor and the tenth transistor, wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor are configured to function as a first inverter coupled to a first transmission gate, wherein the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are configured to function as a second inverter coupled to a second transmission gate, The ninth transistor and the tenth transistor are configured to function as a third inverter coupled between the first control terminal and the second control terminal of the second transmission gate.

20. The device according to claim 19, wherein The holding latch further comprises: a fifth gate structure extending in the second direction and arranged on the first active region and the second active region; wherein the fifth gate structure is configured to serve as a first terminal of a fourth inverter, The first terminal of the fourth inverter is coupled to the first terminals of the first transmission gate and the second transmission gate, and the second terminal of the fourth inverter is coupled to the first terminal of the first inverter.

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