Packaging structure and manufacturing method thereof

Abstract

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first chip, a mold, a first circuit structure, a second circuit structure, a conductive connector, a second chip, and a filler. The mold covers the first chip and has a first surface and a second surface facing each other. The first circuit structure is located on the first surface. The second circuit structure is located on the second surface. The conductive connector extends through the mold. The second chip is disposed on the second circuit structure. The second chip has an optical signal transmission area. The filler is located between the second chip and the second circuit structure. The upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area located on opposite sides of the groove. The filler directly contacts the first area. The filler is spaced away from the second area.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a packaging structure with grooves on a redistribution circuit structure and a manufacturing method thereof. Background Art

[0002] With the increase in data volume and / or data center requirements, the demand for silicon photonic integrated circuits (SiPICs) is also increasing. Therefore, how to improve the quality and applicability of SiPIC packaging structures has become an urgent issue. Summary of the Invention

[0003] The present invention is directed to a packaging structure and a manufacturing method thereof, which can have better quality.

[0004] According to an embodiment of the present invention, a packaging structure includes a first chip, a molded body, a first redistribution wiring structure, a second redistribution wiring structure, a conductive connector, a second chip and a filler. The molded body covers the first chip. The molded body has a first molded surface and a second molded surface opposite to the first molded surface. The first redistribution wiring structure is located on the first molded surface of the molded body. The second redistribution wiring structure is located on the second molded surface of the molded body and is electrically connected to the first chip. The conductive connector passes through the molded body and is electrically connected to the first redistribution wiring structure and the second redistribution wiring structure. The second chip is configured on the second redistribution wiring structure and is electrically connected to the second redistribution wiring structure. The second chip has an optical signal transmission area. The filler is located between the second chip and the second redistribution wiring structure. The upper surface of the second redistribution wiring structure has a groove. The upper surface includes a first area and a second area located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area.

[0005] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps: providing a preliminary structure, which includes a first chip, a molding body, a first redistribution wiring structure, a second redistribution wiring structure and a conductive connector, wherein the molding body covers the first chip, wherein the molding body has a first molding surface and a second molding surface relative to the first redistribution wiring structure, wherein the first redistribution wiring structure is located on the first molding surface of the molding body, wherein the second redistribution wiring structure is located on the second molding surface of the molding body and is electrically connected to the first chip, wherein the upper surface of the second redistribution wiring structure has a groove, wherein the upper surface includes a first area and a second area located on opposite sides of the groove, wherein the conductive connector passes through the molding body and is electrically connected to the first redistribution wiring structure and the second redistribution wiring structure; configuring a second chip on the preliminary structure and electrically connected to the second redistribution wiring structure, wherein the second chip has an optical signal transmission area; forming a filling body between the second chip and the second redistribution wiring structure, wherein the filling body directly contacts the first area, and the filling body is away from the second area.

[0006] Based on the above, the manufacturing method of the package structure of the present invention can make the package structure have better quality, and / or the package structure of the present invention can have better quality.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1F is a partial cross-sectional schematic diagram of a partial manufacturing method of a packaging structure according to the first embodiment of the present invention;

[0009] Figure 1G is a partial cross-sectional schematic diagram of a packaging structure according to a first embodiment of the present invention;

[0010] Figure 1H is a partial top view schematically illustrating a packaging structure according to a first embodiment of the present invention;

[0011] Figure 2 is a partial top view schematically illustrating a packaging structure according to a second embodiment of the present invention;

[0012] Figures 3A to 3D is a partial cross-sectional schematic diagram of a partial manufacturing method of a packaging structure according to a third embodiment of the present invention;

[0013] Figures 4A to 4C FIG. 4 is a partial cross-sectional schematic diagram of a partial manufacturing method of a package structure according to a fourth embodiment of the present invention.

[0014] Description of Reference Numerals

[0015] 100, 200, 300, 400: packaging structure;

[0016] 101: Preliminary structure;

[0017] 110: first chip;

[0018] 110a: first active surface;

[0019] 110b: first back side;

[0020] 112: Metal bump;

[0021] 112a: upper surface;

[0022] 120: second chip;

[0023] 120w: size;

[0024] 120a: second active surface;

[0025] 120c: side;

[0026] 120h: thickness;

[0027] 122: optical signal transmission area;

[0028] 124: second chip connection member;

[0029] 130: conductive connector;

[0030] 130a: upper surface;

[0031] 140: Molded body;

[0032] 140a: first mold sealing surface;

[0033] 140b: second mold sealing surface;

[0034] 140w: size;

[0035] 150, 350, 450: second layer wiring structure;

[0036] 150a, 350a, 450a: upper surface;

[0037] 150a1, 350a1, 450a1: first zone;

[0038] 150a2, 350a2, 450a2: second zone;

[0039] 150w: size;

[0040] 151a, 151b, 151c, 161, 351b, 351c, 451b, 451c: insulating layer;

[0041] 357c: Insulation material;

[0042] 152a, 152b, 152c, 162: conductive layer;

[0043] 160: First redistribution line structure;

[0044] 160w: size;

[0045] 170: filling body;

[0046] 170h: altitude range;

[0047] 91: carrier board;

[0048] 92: release layer;

[0049] D1, D2: direction;

[0050] dp: dummy pad;

[0051] G1, G2, G3, G4: groove;

[0052] OP1, OP2: opening;

[0053] R1: Region. DETAILED DESCRIPTION

[0054] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0055] Unless expressly stated otherwise, directional terms used herein (eg, up, down, left, right, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.

[0056] Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0057] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size, or dimensions of layers or regions in the accompanying drawings may be exaggerated for clarity.

[0058] Figures 1A to 1F FIG1 is a partial cross-sectional schematic diagram of a partial manufacturing method of a package structure according to the first embodiment of the present invention. Figure 1G is a partial cross-sectional schematic diagram of a packaging structure according to a first embodiment of the present invention. Figure 1H FIG. 1 is a partial top view of a packaging structure according to a first embodiment of the present invention. Figure 1G Can be Figure 1F Schematic diagram of the enlarged area R1. Figure 1H Can be Figure 1F In addition, for the sake of clarity, the accompanying drawings (such as: Figure 1H ) in which part of the film layer or component is omitted, and / or another part of the film layer or component is shown in a perspective manner.

[0059] Please refer to Figure 1A , forming a first redistribution circuit structure 160 on the carrier 91. The present invention has no particular limitation on the carrier 91, as long as the carrier 91 can be suitable for carrying the film layer formed thereon or the components disposed thereon.

[0060] In one embodiment, the carrier 91 may have a release layer 92, but the present invention is not limited thereto. The release layer 92 may be, for example, a light to heat conversion (LTHC) adhesive layer or other similar release layers, but the present invention is not limited thereto.

[0061] In this embodiment, the first redistribution wiring structure 160 may include an insulating layer 161 and a conductive layer 162. The first redistribution wiring structure 160 may be formed by commonly used semiconductor processes (such as coating processes, deposition processes, photolithography processes and / or etching processes), so they are not described in detail here. The number of layers of the insulating layer 161 and / or the conductive layer 162 is not limited in the present invention. In addition, Figure 1A In the embodiment, the forms of insulating layer 161 and / or conductive layer 162 are shown for exemplary purposes only. For example, corresponding portions of conductive layer 162 may constitute corresponding circuits. Furthermore, the layout design of the aforementioned circuits may be adjusted based on design requirements and is not limited in the present invention.

[0062] Please continue to refer to Figure 1A In this embodiment, a plurality of conductive connectors 130 may be configured or formed on the first redistribution wiring structure 160. Corresponding conductive connectors 130 may be electrically connected to corresponding wirings in the first redistribution wiring structure 160.

[0063] In one embodiment, the conductive connection member 130 may include a pre-formed conductive member, such as a pre-formed conductive pillar, but the present invention is not limited thereto.

[0064] In one embodiment, the conductive connector 130 may be formed by a commonly used semiconductor process (e.g., a photolithography process, a sputtering process, an electroplating process, and / or an etching process), but the present invention is not limited thereto. For example, the conductive connector 130 may include a plating core layer and a seed layer surrounding the plating core layer, but the present invention is not limited thereto.

[0065] Please refer to Figure 1B , configuring the first chip 110 on the first redistribution circuit structure 160.

[0066] The first chip 110 has a first active surface 110a and a first back surface 110b. The first back surface 110b is opposite to the first active surface 110a. In this embodiment, the first chip 110 is disposed on the first redistribution wiring structure 160 with its first back surface 110b facing the carrier 91.

[0067] In this embodiment, a plurality of metal bumps 112 may be formed on the first active surface 110 a of the first chip 110 . The metal bumps 112 may reduce damage to the first active surface 110 a of the first chip 110 in subsequent steps.

[0068] In one embodiment, an adhesive layer (not shown) may be provided on the first back surface 110 b of the first chip 110 . The adhesive layer may be, for example, a die attach film (DAF). The first chip 110 may be fixed to the first redistribution wiring structure 160 via the adhesive layer.

[0069] In this embodiment, the first chip 110 does not have through silicon vias (TSVs), but the present invention is not limited thereto.

[0070] It is worth noting that the present invention does not limit the order of forming the conductive connection member 130 and configuring the first chip 110. Figure 1A As shown, the conductive connection 130 is formed first, and then Figure 1B As shown, the first chip 110 is configured. In an embodiment not shown, the first chip 110 may be configured first, and then the conductive connection 130 may be formed.

[0071] Please refer to Figures 1B to 1C , forming a molded body 140 on the first redistribution wiring structure 160. The molded body 140 can cover the first chip 110 and the conductive connector 130. The molded body 140 has a first molded surface 140a and a second molded surface 140b opposite to the first molded surface 140a. The first molded surface 140a is the surface facing the first redistribution wiring structure 160.

[0072] In one embodiment, a molding material (not shown) can be formed on the first redistribution circuit structure 160. Furthermore, after the molding material is solidified, a planarization process can be performed to form a molding body 140. The planarization process can be, for example, grinding, polishing, or other suitable planarization steps. The molding body 140 can expose the upper surface 112a of the metal bump 112 of the first chip 110 and the upper surface 130a of the conductive connector 130. In other words, the second molding surface 140b of the molding body 140 can be coplanar with the upper surface 112a of the metal bump 112 of the first chip 110 and the upper surface 130a of the conductive connector 130.

[0073] In one embodiment, since the first active surface 110 a of the first chip 110 has the metal bumps 112 , the possibility of damaging the first active surface 110 a of the first chip 110 during the planarization step can be reduced.

[0074] Please refer to Figure 1C to Figure 1D , forming a second redistribution wiring structure 150 on the second molding surface 140b of the molding body 140. The second redistribution wiring structure 150 can be formed by a commonly used semiconductor process, so it will not be described in detail here. In addition, the present invention does not limit the number of film layers in the second redistribution wiring structure 150 and the wiring design of the circuit. For example, in Figure 1D In the diagram shown, the second redistribution wiring structure 150 includes three insulating layers 151a, 151b, and 151c and three conductive layers 152a, 152b, and 152c.

[0075] In one embodiment, the insulating layer 151 a , the insulating layer 151 b and / or the insulating layer 151 c may be made of an organic insulating material (such as, but not limited to, polyimide (PI)), but the present invention is not limited thereto.

[0076] A groove G1 is formed on the upper surface 150a of the second redistribution wiring structure 150 (i.e., the surface furthest from the first redistribution wiring structure 160). Groove G1 penetrates at least the top insulating layer 151c of the second redistribution wiring structure 150 (i.e., the insulating layer furthest from the first redistribution wiring structure 160 in the second redistribution wiring structure 150). Groove G1 exposes insulating layer 151b located below (e.g., below) and directly contacting top insulating layer 151c.

[0077] In one embodiment, the trench G1 does not expose any conductive layer in the second redistribution wiring structure 150 (not shown or labeled because there is no conductive layer), but the present invention is not limited thereto.

[0078] In one embodiment, the formation method of the groove G1 of the second redistribution wiring structure 150 is exemplified as follows. An insulating material can be formed on the insulating layer 151b by coating. The aforementioned insulating material, for example, includes a material that can be photocured or heat-cured. Then, a portion of the insulating material coated on the insulating layer 151b can be cured. Then, the uncured insulating material is removed to form the insulating layer 151c. The insulating layer 151c has a groove G1 that exposes a portion of the insulating layer 151b and an opening that exposes a portion of the conductive layer 152b. Then, a conductive layer 152c is formed on the insulating layer 151c. Part of the conductive layer 152c can be filled into the corresponding opening in the insulating layer 151c to connect (including: electrically connected or directly connected) the conductive layer 152b. In addition, the conductive layer 152c is not filled into the groove G1.

[0079] Please refer to Figures 1D to 1E After the second redistribution wiring structure 150 is formed, the carrier 91 can be removed and / or a cutting step can be performed to form a plurality of preliminary structures 101. The cutting step can be performed, for example, using a rotating blade or a laser beam, but the present invention is not limited thereto. It is worth noting that the present invention does not limit the order of removing the carrier 91 and performing the cutting step.

[0080] It is worth noting that after the cutting step, similar component symbols will be used for the preliminary structure 101 after the cutting step. For example, a plurality of first chips 110 (such as Figure 1D As shown) after cutting, it can be a plurality of first chips 110 (as shown Figure 1E As shown), a plurality of conductive connecting members 130 (as Figure 1D As shown) after cutting, it can be a plurality of conductive connecting members 130 (such as Figure 1E As shown), the first redistribution line structure 160 (as shown Figure 1D As shown) after cutting, it can be a plurality of first redistribution circuit structures 160 (as shown Figure 1E As shown), the molded body 140 (as Figure 1D As shown) after cutting, it can be a plurality of molded bodies 140 (as shown Figure 1E As shown), the second redistribution wiring structure 150 (as shown Figure 1D As shown) after cutting, it can be a plurality of second redistribution wiring structures 150 (as shown Figure 1E As shown), multiple grooves G1 (as Figure 1D As shown) after cutting, it can be a plurality of grooves G1 (as shown Figure 1E ), and so on. Components in other preliminary structures will follow the same component symbol rules as above and will not be described or specifically shown here.

[0081] Please refer to Figures 1E to 1FThe second chip 120 is disposed on the preliminary structure 101 and electrically connected to the second redistribution wiring structure 150. The second chip 120 has a second active surface 120a. The second chip 120 is disposed on the second redistribution wiring structure 150 with its second active surface 120a facing the second redistribution wiring structure 150.

[0082] The second active surface 120a of the second chip 120 has an optical signal transmission area 122. The optical signal transmission area 122 can be suitable for receiving or transmitting optical signals. In the direction D1 perpendicular to the first mold surface 140a or the second mold surface 140b, the optical signal transmission area 122 does not overlap with the mold body 140, the second redistribution circuit structure 150 and / or the first redistribution circuit structure 160. In other words, at least a portion of the second chip 120 (such as: a portion having the optical signal transmission area 122) is overhanging. In one embodiment, the second chip 120 can be referred to as a silicon photonics integrated circuit (silicon photonics integrated circuit), a photonic integrated circuit (PIC) or an integrated optical circuit, but the present invention is not limited thereto.

[0083] It is worth noting that in Figure 1F In the figure, the optical signal transmission area 122 is shown for exemplary purposes only. The shape, film layer or material of the optical signal transmission area 122 can be adjusted according to the needs, and the present invention is not limited thereto.

[0084] In one embodiment, the second chip 120 and the second redistribution wiring structure 150 may be electrically connected via the second chip connector 124. The second chip connector 124 may be, for example, a solder ball, a conductive pillar, or other suitable conductive connector, but the present invention is not limited thereto.

[0085] Please continue to refer to Figure 1F , a filler 170 is formed on the second redistribution wiring structure 150. Furthermore, after the second chip 120 is placed on the preliminary structure 101 and the filler 170 is formed, the filler 170 can be located between the second chip 120 and the second redistribution wiring structure 150. The filler 170 can be, for example, capillary underfill (CUF) or other suitable filling materials, but the present invention is not limited thereto.

[0086] In this embodiment, the second chip 120 can be first configured on the preliminary structure 101, and then a filling body 170 can be formed between the second chip 120 and the second redistribution wiring structure 150. For example, after the second chip 120 is configured on the preliminary structure 101, a suitable filling material can be injected from the side 120c of the second chip 120 onto the upper surface 150a of the second redistribution wiring structure 150 via a suitable device (such as, but not limited to, a syringe (syringe / dispenser / injector)), wherein the side 120c of the second chip 120 is opposite to the optical signal transmission area 122. The uncured filling material can be filled into the space between the second chip 120 and the second redistribution wiring structure 150 from the side 120c of the second chip 120, and further flow to the groove G1. The filling speed and / or filling amount of the filling material can be controlled in a suitable manner. Furthermore, the grooves G1 of the second redistribution wiring structure 150 can prevent the aforementioned filling material from covering the optical signal transmission region 122 of the second chip 120. Thereafter, the filling material can be cured by a suitable method to form a filling body 170.

[0087] In this embodiment, the filler 170 may also cover a portion of the side surface 120c of the second chip 120. This can improve the bonding between the second chip 120 and the second redistribution wiring structure 150 and reduce the possibility of the partially suspended second chip 120 being peeled off from the second redistribution wiring structure 150.

[0088] In this embodiment, the height 170h of the filler 170 covering a portion of the side surface 120c of the second chip 120 can be greater than half the thickness 120h of the second chip 120. This can further enhance the bonding between the second chip 120 and the second redistribution wiring structure 150. In one embodiment, the filler 170 can completely cover the side surface 120c of the second chip 120.

[0089] In this embodiment, the filler 170 can cover a greater area than half of the second active surface 120a of the second chip 120. This can further enhance the bonding between the second chip 120 and the second redistribution wiring structure 150. However, it is worth noting that the filler 170 does not cover the optical signal transmission area 122 of the second chip 120. In other words, the filler 170 does not completely cover the second active surface 120a of the second chip 120.

[0090] In one embodiment, the height range 170h of the filler 170 covering the partial side surface 120c of the second chip 120 can be greater than half of the thickness 120h of the second chip 120, and the range of the filler 170 covering the second active surface 120a of the second chip 120 can be greater than half of the second active surface 120a of the second chip 120.

[0091] In one embodiment, conductive terminals (not shown) may be formed on the first redistribution wiring structure 160 and electrically connected to corresponding lines in the first redistribution wiring structure 160, but the present invention is not limited thereto. The conductive terminals may be formed before or after the cutting process, and the present invention is not limited thereto.

[0092] After the above processes, the manufacturing of the package structure 100 of this embodiment is substantially completed.

[0093] Please refer to Figures 1F to 1H The package structure 100 includes a first chip 110, a molded body 140, a first redistribution wiring structure 160, a second redistribution wiring structure 150, a conductive connector 130, a second chip 120, and a filler 170. The molded body 140 covers the first chip 110. The molded body 140 has a first molded surface 140a and a second molded surface 140b opposite to the first molded surface 140a. The first redistribution wiring structure 160 is located on the first molded surface 140a of the molded body 140. The second redistribution wiring structure 150 is located on the second molded surface 140b of the molded body 140. The corresponding lines in the second redistribution wiring structure 150 are electrically connected to the first chip 110. The conductive connector 130 passes through the molded body 140 and is electrically connected to the corresponding lines in the first redistribution wiring structure 160 and the corresponding lines in the second redistribution wiring structure 150. The second chip 120 is configured on the second redistribution wiring structure 150. The second chip 120 is electrically connected to the corresponding circuit in the second redistribution wiring structure 150. The second chip 120 has an optical signal transmission area 122. The filler 170 is located between the second chip 120 and the second redistribution wiring structure 150. The upper surface 150a of the second redistribution wiring structure 150 has a groove G1. The upper surface 150a of the second redistribution wiring structure 150 includes a first area 150a1 and a second area 150a2 located on opposite sides of the groove G1. The filler 170 directly contacts the first area 150a1, and the filler 170 is away from the second area 150a2.

[0094] In one embodiment, the first chip 110 may be, for example, an electronic integrated circuit (EIC), an application-specific integrated circuit (ASIC), a control chip, or a chip including other suitable components, but the present invention is not limited thereto. In one embodiment, the plurality of first chips 110 may be homogeneous chips or heterogeneous chips, and the present invention is not limited thereto.

[0095] In this embodiment, first chip 110 can be electrically connected to corresponding circuits in first redistribution wiring structure 160 via corresponding circuits in second redistribution wiring structure 150 and / or corresponding conductive connectors 130, thereby enabling signal and / or power transmission, but the present invention is not limited thereto. In one embodiment, first chip 110 does not have through silicon vias (TSVs).

[0096] In this embodiment, the second chip 120 can be electrically connected to the corresponding line in the first redistribution wiring structure 160 via the corresponding second chip connector 124, the corresponding line in the second redistribution wiring structure 150 and / or the corresponding conductive connector 130, and signal and / or power transmission can be performed; and / or the second chip 120 can transmit signals and / or power to the first chip 110 via the corresponding second chip connector 124 and / or the corresponding line in the second redistribution wiring structure 150, but the present invention is not limited to this.

[0097] In this embodiment, the groove G1 may be strip-shaped, but the present invention is not limited thereto. The sidewalls of the groove G1 may be inclined. In an extension direction D2 of the groove G1, the dimension G1w of the groove G1 is greater than the dimension 120w of the second chip 120. The dimension G1w of the groove G1 is smaller than the dimension 140w of the first molded body 140, the overall dimension 150w of the second redistribution wiring structure 150, and / or the overall dimension 160w of the first redistribution wiring structure 160.

[0098] In this embodiment, the filler 170 can also fill the groove G1. In other words, the filler 170 can directly contact the first area 150a1 and the groove G1, but not the second area 150a2. In this way, the filler 170 between the second chip 120 and the second redistribution wiring structure 150 can use the groove G1 as a boundary, preventing the filler 170 from overflowing the edge of the second redistribution wiring structure 150 and possibly further covering the optical signal transmission area 122. In this way, the package structure 100 can have better quality or yield.

[0099] In one embodiment, the filling body 170 may not fill in or partially fill in the trench G1 , and the filling body 170 does not contact the second region 150 a 2 .

[0100] In this embodiment, when viewed in a direction D1 perpendicular to the first molding surface 140a or the second molding surface 140b (eg, Figure 1H As shown, a groove G1 is provided between any point on the optical signal transmission area 122 and any point on the filling body 170. That is, when manufacturing the package structure 100, the groove G1 can ensure that the filling body 170 does not cover the optical signal transmission area 122 of the second chip 120.

[0101] In one embodiment, the package structure 100 may further include conductive terminals (not shown) disposed on the first redistribution wiring structure 160 so that corresponding circuits in the first redistribution wiring structure 160 can be electrically connected to external conductive members via the conductive terminals.

[0102] It is worth noting that in this embodiment, only three first chips 110 and one second chip 120 are exemplarily shown in the package structure 100. However, the present invention does not limit the number of first chips 110 and second chips 120 configured in the package structure 100, which can be adjusted according to design requirements.

[0103] In this embodiment, the number of the trenches G1 may be the same as the number of the second chips 120 , but the present invention is not limited thereto.

[0104] In an exemplary application, a light-guiding component (such as, but not limited to, an optical fiber) can be brought into contact (such as, in direct contact; or, in indirect contact via optical glue; or, in partial direct contact and partial indirect contact) with the optical signal transmission area 122 of the second chip 120 of the package structure 100, so that the second chip 120 can receive or transmit the corresponding optical signal via the aforementioned light-guiding component. Therefore, by configuring the filler 170 (such as, making the filler 170 have the aforementioned covering method for the second chip 120), the possibility of the second chip 120 peeling off from the second redistribution wiring structure 150 can be reduced when the light-guiding component contacts the optical signal transmission area 122 of the second chip 120 of the package structure 100. In addition, the groove G1 of the second redistribution wiring structure 150 can prevent the aforementioned filling material from covering the optical signal transmission area 122 of the second chip 120. In this way, the package structure 100 can have better quality.

[0105] Figure 21 is a partial top view of a package structure according to the second embodiment of the present invention. The package structure 200 and its manufacturing method of this embodiment are similar to the package structure 100 and its manufacturing method of the first embodiment. Similar components are represented by the same reference numerals and have similar functions, materials or formation methods, and their descriptions are omitted. In addition, for the sake of clarity, Figure 2 Part of the film layer or component is omitted, and / or another part of the film layer or component is shown in a perspective manner.

[0106] Please refer to Figure 2 In this embodiment, the groove G2 is annular.

[0107] In this embodiment, viewed in a direction D1 perpendicular to the first molding surface 140 a or the second molding surface 140 b , the groove G2 may surround the second chip connector 124 .

[0108] In this embodiment, viewed in a direction D1 perpendicular to the first molding surface 140 a or the second molding surface 140 b , the range of the filling body 170 may be smaller than or equal to the range surrounded by the groove G2 .

[0109] Figures 3A to 3D 1 is a partial cross-sectional diagram of a method for manufacturing a package structure according to a third embodiment of the present invention. The package structure 300 and its manufacturing method of this embodiment are similar to the package structure 100 and its manufacturing method of the first embodiment. Similar components are represented by the same reference numerals and have similar functions, materials or formation methods, and their descriptions are omitted. For example, Figure 3A Show connection Figure 1C A partial cross-sectional diagram of a method for manufacturing a packaging structure according to the steps of FIG. Figures 3A to 3C Repeated units may be omitted. For example, Figures 3A to 3C For continued Figure 1C Steps for the left or right structure. It should be understood that Figures 3A to 3C The same or similar steps may also be applied to repeating units that may not be shown. Figure 3D The area shown may be similar to Figure 1F Region R1 in.

[0110] In this embodiment, the second redistribution wiring structure 350 (marked at Figure 3C or Figure 3D ) are formed as follows.

[0111] Please refer to Figure 3A, an insulating material can be formed on the insulating layer 151a by coating. The aforementioned insulating material includes, for example, a material that can be photocured or heat-cured. Then, a portion of the insulating material coated on the insulating layer 151a can be cured. Then, the uncured insulating material is removed to form the insulating layer 351b. The insulating layer 351b has an opening OP1 that exposes a portion of the insulating layer 151a and an opening that exposes a portion of the conductive layer 152a. Then, a conductive layer 152b is formed on the insulating layer 351b. Part of the conductive layer 152b can be filled into the opening of the insulating layer 351b to connect (including: electrically connect or directly connect) the conductive layer 152a. Then, an insulating material 357c can be formed on the insulating layer 351b by coating. The insulating material 357c can be filled into the opening OP1 of the insulating layer 351b. The insulating material 357c includes, for example, a material that can be photocured or heat-cured.

[0112] Please refer to Figures 3A to 3B , a portion of the insulating material 357c can be cured. Then, the uncured insulating material 357c is removed to form an insulating layer 351c. The insulating layer 351c has an opening OP2 and an opening that exposes a portion of the conductive layer 152b. The opening OP2 of the insulating layer 351c corresponds to the opening OP1 of the insulating layer 351b. The opening area of the opening OP2 can be larger than the opening area of the opening OP1. Moreover, in the direction D1 perpendicular to the first molding surface 140a or the second molding surface 140b, the opening range of the opening OP1 can be located within the opening range of the opening OP2.

[0113] Please refer to Figures 3B to 3C , a conductive layer 152c is formed on the insulating layer 351c. Part of the conductive layer 152c can fill the opening of the insulating layer 351c to connect (including: electrically connect or directly connect) to the conductive layer 152b.

[0114] Please refer to Figure 3C After the above processes, the second redistribution wiring structure 350 of this embodiment is substantially completed. The trench G3 of the second redistribution wiring structure 350 can be formed by at least the opening OP2 of the insulating layer 351c and the opening OP1 of the insulating layer 351b.

[0115] Please refer to Figures 3C to 3D , then, you can use the same or similar Figures 1E to 1F The steps shown are used to substantially complete the fabrication of the package structure 300 of this embodiment.

[0116] It should be understood that Figure 3D For similar Figure 1F Therefore, although Figure 3DSome components or some film layers are not shown, but in other places not shown, there may be the same or similar ones as those shown in FIG. Figure 1F Components or layers shown.

[0117] Please refer to Figure 3D The packaging structure 300 includes a first chip (not directly shown, which may be the first chip 110 of the aforementioned embodiment), a molded body 140, a first redistribution wiring structure (not directly shown, which may be the first redistribution wiring structure 160 of the aforementioned embodiment), a second redistribution wiring structure 350, a conductive connector 130, a second chip (not directly shown, which may be the second chip 120 of the aforementioned embodiment), and a filler 170. The second redistribution wiring structure 350 is located on the second molding surface 140b of the molded body 140. The corresponding circuits in the second redistribution wiring structure 350 are electrically connected to the first chip. The conductive connector 130 passes through the molded body 140 and is electrically connected to the corresponding circuits in the first redistribution wiring structure and the corresponding circuits in the second redistribution wiring structure 350. The second chip is configured on the second redistribution wiring structure 350. The second chip is electrically connected to the corresponding circuits in the second redistribution wiring structure 350. The filler 170 is located between the second chip and the second redistribution wiring structure 350. The upper surface 350a of the second redistribution wiring structure 350 has a groove G3. The upper surface 350a of the second redistribution wiring structure 350 includes a first region 350a1 and a second region 350a2 located on opposite sides of the groove G3. The filler 170 directly contacts the first region 350a1 and is away from the second region 350a2.

[0118] In this embodiment, the sidewall of the trench G3 may have a stepped structure.

[0119] In this embodiment, the groove G3 of the package structure 300 may be strip-shaped (eg Figure 1H In one embodiment, the groove similar to the groove G3 (eg, a groove with a sidewall having a stepped structure) may be annular (eg, Figure 2 shown).

[0120] Figures 4A to 4C 1 is a partial cross-sectional diagram of a method for manufacturing a package structure according to a fourth embodiment of the present invention. The package structure 400 and its manufacturing method of this embodiment are similar to the package structure 100 and its manufacturing method of the first embodiment. Similar components are represented by the same reference numerals and have similar functions, materials or formation methods, and their descriptions are omitted. For example, Figure 4A Show connection Figure 1C A partial cross-sectional diagram of a method for manufacturing a packaging structure according to the steps of FIG. Figures 4A to 4B Repeated units may be omitted. For example, Figures 4A to 4B For continued Figure 1C Steps for the left or right structure. It should be understood that Figures 4A to 4B The same or similar steps may also be applied to repeating units that may not be shown. Figure 4C The area shown may be similar to Figure 1F Region R1 in.

[0121] In this embodiment, the second redistribution wiring structure 450 (marked at Figure 4C ) are formed as follows.

[0122] Please refer to Figure 4A , the conductive layer 152a may include a dummy pad dp. Then, an insulating layer 451b, a conductive layer 152b, and an insulating layer 451c may be formed on the insulating layer 151a by deposition, photolithography, and / or etching processes.

[0123] In one embodiment, the material of the insulating layer 451 b and / or the material of the insulating layer 451 c may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but the present invention is not limited thereto.

[0124] In one embodiment, the material of the insulating layer 451 b and the material of the insulating layer 451 c may be the same or similar, but the present invention is not limited thereto.

[0125] Please refer to Figures 4A to 4B An opening exposing a portion of the conductive layer 152b and a trench G4 may be formed by etching. The trench G4 may correspond to the dummy pad dp. In one embodiment, the dummy pad dp may be referred to as an etching stop layer, but the present invention is not limited thereto.

[0126] Please refer to Figures 4B to 4C After forming the trench G4, a conductive layer 152c is formed on the insulating layer 451c. Part of the conductive layer 152c may fill the opening of the insulating layer 451c to connect (including electrically connecting or directly connecting) to the conductive layer 152b.

[0127] In this embodiment, the dummy pad dp is a portion of the conductive layer 152a, but the present invention is not limited thereto. In one embodiment, the dummy pad dp can be a portion of any conductive layer in the second redistribution wiring structure 450 except the top conductive layer (eg, conductive layer 152c).

[0128] After the above processes, the second redistribution wiring structure 450 of this embodiment is substantially completed. The groove G4 of the second redistribution wiring structure 450 can be located on the dummy pad dp.

[0129] Please continue to refer to Figure 4C , then, you can use the same or similar Figures 1E to 1F The steps shown are used to substantially complete the fabrication of the package structure 400 of this embodiment.

[0130] It should be understood that Figure 4C For similar Figure 1F Therefore, although Figure 4C Some components or some film layers are not shown, but in other places not shown, there may be the same or similar ones as those shown in FIG. Figure 1F Components or layers shown.

[0131] Please refer to Figure 4C The packaging structure 400 includes a first chip (not directly shown, but may be the first chip 110 of the aforementioned embodiment), a molded body 140, a first redistribution wiring structure (not directly shown, but may be the first redistribution wiring structure 160 of the aforementioned embodiment), a second redistribution wiring structure 450, a conductive connector 130, a second chip (not directly shown, but may be the second chip 120 of the aforementioned embodiment), and a filler 170. The second redistribution wiring structure 450 is located on the second molding surface 140b of the molded body 140. The corresponding circuits in the second redistribution wiring structure 450 are electrically connected to the first chip. The conductive connector 130 passes through the molded body 140 and is electrically connected to the corresponding circuits in the first redistribution wiring structure and the corresponding circuits in the second redistribution wiring structure 450. The second chip is configured on the second redistribution wiring structure 450. The second chip is electrically connected to the corresponding circuits in the second redistribution wiring structure 450. The filler 170 is located between the second chip and the second redistribution wiring structure 450. The upper surface 450a of the second redistribution wiring structure 450 has a groove G4. The upper surface 450a of the second redistribution wiring structure 450 includes a first region 450a1 and a second region 450a2 located on opposite sides of the groove G4. The filler 170 directly contacts the first region 450a1 and is away from the second region 450a2.

[0132] In this embodiment, the groove G4 of the package structure 400 may be strip-shaped (eg Figure 1H In one embodiment, a trench similar to the trench G4 (eg, a trench penetrating multiple insulating layers and having inclined sidewalls) may be annular (eg, Figure 2 shown).

[0133] In summary, the manufacturing method of the package structure of the present invention can make the package structure have better quality, and / or the package structure of the present invention can have better quality.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that: include: First Chip; A molding body covering the first chip, wherein the molding body has a first molding surface and a second molding surface opposite to the first molding surface; A first redistribution circuit structure is located on the first molded surface of the molded body; a second redistribution circuit structure, located on the second molding surface of the molding body and electrically connected to the first chip; a conductive connector, passing through the molded body and electrically connected to the first redistribution circuit structure and the second redistribution circuit structure; A second chip is disposed on the second redistribution wiring structure and electrically connected to the second redistribution wiring structure, wherein the second chip has an optical signal transmission area; as well as A filling body is located between the second chip and the second redistribution wiring structure, wherein: The upper surface of the second redistribution wiring structure has a groove, and the upper surface includes a first area and a second area located on opposite sides of the groove; The filling body directly contacts the first region; The filling body is away from the second zone; The height range of the filling body covering part of the side surface of the second chip is greater than half of the thickness of the second chip; and The range in which the filling body covers the second active surface of the second chip is greater than half of the second active surface of the second chip.

2. The packaging structure according to claim 1, wherein: In a direction perpendicular to the first molding surface or the second molding surface, the optical signal transmission region of the second chip does not overlap with the molding body.

3. The packaging structure according to claim 1, wherein: The groove is strip-shaped, and in the extension direction of the groove, the size of the groove is larger than the size of the second chip, and the size of the groove is smaller than the size of the molded body, the size of the first redistribution wiring structure or the size of the second redistribution wiring structure.

4. The packaging structure according to claim 1, wherein: Also includes: A plurality of second chip connectors are located between the second chip and the second redistribution wiring structure and are electrically connected to the second chip and the second redistribution wiring structure, wherein the groove is annular and surrounds the plurality of second chip connectors.

5. The packaging structure according to claim 1, wherein: The second redistribution line structure includes: a top insulating layer, wherein the trench penetrates the top insulating layer; and The top conductive layer is located on the top insulating layer, and a portion of the top conductive layer is further embedded in the top insulating layer.

6. The packaging structure according to claim 1, wherein: The sidewall of the groove is an inclined surface.

7. The packaging structure according to claim 6, wherein: The second redistribution wiring structure includes a dummy pad, and the groove exposes the surface of the dummy pad.

8. The packaging structure according to claim 1, wherein: The sidewall of the trench has a stepped structure.

9. A method for manufacturing a packaging structure, characterized in that: include: Provide preliminary structure, including: First Chip; A molding body covering the first chip, wherein the molding body has a first molding surface and a second molding surface opposite to the first molding surface; A first redistribution circuit structure is located on the first molded surface of the molded body; A second redistribution wiring structure is located on the second molding surface of the molding body and is electrically connected to the first chip, wherein the upper surface of the second redistribution wiring structure has a groove, and the upper surface includes a first area and a second area located on opposite sides of the groove; and a conductive connector, passing through the molded body and electrically connected to the first redistribution circuit structure and the second redistribution circuit structure; disposing a second chip on the preliminary structure and electrically connected to the second redistribution wiring structure, wherein the second chip has an optical signal transmission area; and A filler is formed between the second chip and the second redistribution wiring structure, wherein the filler directly contacts the first area and is away from the second area, wherein the height range of the partial side surface of the second chip covered by the filler is greater than half of the thickness of the second chip, and the range of the second active surface of the second chip covered by the filler is greater than half of the second active surface of the second chip.

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