Switching frequency control system and control method

Abstract

The present invention discloses a switching frequency control system and a control method. The system includes a first phase-locked loop and a second oscillator. The first phase-locked loop includes a phase detector, a loop filter and a first oscillator. The second oscillator and the first oscillator form a second phase-locked loop by switching. The second oscillator can output a clock signal synchronized to an external clock signal, and the second oscillator can provide a control voltage corresponding to the frequency of the external clock signal. The first oscillator is in PLL mode and switches from a first working state to a second working state. The control voltage enables the clock signal output by the first oscillator after exiting the first working state to skip the abnormal state and synchronize to the external clock signal. The switching frequency control system of the present invention effectively realizes the control of the dual-mode switching frequency in the switching power supply, ensures the stability of the output state of each oscillator in different working modes and working states, and the stability of the output state of each oscillator when different modes are switched to each other.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a switching frequency control system and a control method. Background Art

[0002] Switching power supplies are widely used in the field of integrated circuits. Switching power supplies are high-frequency power conversion devices that convert a voltage level into the voltage or current required by the user through different forms of architecture. Switching power supplies have high operating frequencies and need to switch between different frequencies. When the output state of the switching frequency control system in the existing switching power supply is switched, the frequency of the output signal is not stable enough, which can easily affect the operation of the switching power supply.

[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a switching frequency control system and a control method, the frequency of the output signal of which can remain stable when the output state is switched.

[0005] To achieve the above object, an embodiment of the present invention provides a switching frequency control system, comprising: a first phase-locked loop and a second phase-locked loop. The first phase-locked loop comprises a phase detector, a loop filter and a first oscillator; the second oscillator and the first oscillator can form a second phase-locked loop by switching.

[0006] The first oscillator outputs a clock signal CLOCK of a corresponding frequency in the PLL mode and in the first working state, while the second oscillator outputs a clock signal CLK_OSC2 that can be synchronized to an external clock signal CLK_SYNC, and the second oscillator provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC.

[0007] The first oscillator is in the PLL mode and switches from the first working state to the second working state. The control voltage VCONT enables the clock signal CLOCK output by the first oscillator after exiting the first working state to skip the abnormal state and be synchronized to the external clock signal CLK_SYNC.

[0008] In one or more embodiments of the present invention, the first oscillator can output clock signals CLOCK of different frequencies in RT mode and in different working states; the first oscillator switches from RT mode to PLL mode in the second working state, and can output a clock signal CLOCK synchronized to an external clock signal CLK_SYNC.

[0009] In one or more embodiments of the present invention, the switching frequency control system also includes a first selector and a second selector, the I0 input and output of the first selector are connected to the first oscillator, the I1 input of the first selector is connected to the second oscillator, the I0 input of the second selector is connected to the output of the first oscillator, the I1 input of the second selector is connected to the output of the second oscillator, and the output of the second selector is connected to the input of the phase detector, and switching between the first oscillator and the second oscillator can be achieved through the first selector and the second selector.

[0010] In one or more embodiments of the present invention, the first oscillator includes a mode conversion circuit, a first current mirror circuit, a minimum frequency circuit, a frequency maintaining circuit, a first ramp voltage generating circuit, a first comparator, a first logic circuit and a buffer BUFFER1, the mode conversion circuit, the first ramp voltage generating circuit and the first comparator are all connected to the first current mirror circuit, and the first current mirror circuit, the minimum frequency circuit and the frequency maintaining circuit are all connected to the first selector;

[0011] The mode conversion circuit is used to cut off or switch to the RT mode, and output the corresponding mirror current through the first current mirror circuit; the minimum frequency circuit is used to make the first oscillator output the minimum frequency; the frequency maintenance circuit is used to maintain the frequency corresponding to the control voltage VCONT in the RT mode; the first ramp voltage generating circuit is used to output the corresponding ramp voltage V according to the mirror current output by the first current mirror circuit. RAMP1 The first comparator is used to convert the ramp voltage V RAMP1 and reference voltage V REF_OSC After comparison, the clock signal CLOCK is output through the first logic circuit and the buffer BUFFER1.

[0012] In one or more embodiments of the present invention, the mode conversion circuit includes an operational amplifier, a switch S3, a resistor R SET and NMOS tube N5;

[0013] The positive input terminal of the op amp is connected to the reference voltage V REF The negative input terminal of the operational amplifier is connected to the resistor R through the switch S3. SET One end of the resistor R SETThe other end of the operational amplifier is grounded, the negative input end of the operational amplifier is connected to the source of the NMOS tube N5, the gate of the NMOS tube N5 is connected to the output end of the operational amplifier, the drain of the NMOS tube N5 is connected to the first current mirror circuit, and in the RT mode, the switch S3 is in a closed state.

[0014] In one or more embodiments of the present invention, the first current mirror circuit includes a PMOS tube P5 and a PMOS tube P8, the source of the PMOS tube P5 is connected to the power supply VDD, the drain and the gate of the PMOS tube P5 are short-circuited and connected to the I0 input terminal of the first selector, the gate of the PMOS tube P8 is connected to the output terminal of the first selector, the source of the PMOS tube P8 is connected to the power supply VDD, and the drain of the PMOS tube P8 is connected to the positive input terminal of the first comparator.

[0015] In one or more embodiments of the present invention, the minimum frequency circuit includes a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6 and a bias current source IBIAS2_FMIN;

[0016] Among them, the drain of the PMOS tube P9 is grounded through the resistor R3, the gate of the PMOS tube P9 is grounded through the bias current source IBIAS2_FMIN and connected to the power supply VDD through the capacitor C3, the source of the PMOS tube P9 is connected to the I0 input end of the first selector, the gate of the PMOS tube P9 is connected to the drain of the PMOS tube P6, the gate of the PMOS tube P6 is connected to the I0 input end of the first selector, and the source of the PMOS tube P6 is connected to the power supply VDD.

[0017] In one or more embodiments of the present invention, the frequency maintaining circuit includes a PMOS transistor P7, a switch S4, an NMOS transistor N6 and a resistor R4;

[0018] Among them, the source of the PMOS tube P7 is connected to the power supply VDD, the gate of the PMOS tube P7 is connected to the I0 input end of the first selector, the drain of the PMOS tube P7 is connected to one end of the switch S4 and the output end of the loop filter, the drain and the gate of the NMOS tube N6 are short-circuited and connected to the other end of the switch S4, the source of the NMOS tube N6 is grounded through the resistor R4, and in the RT mode, the switch S4 is in a closed state.

[0019] In one or more embodiments of the present invention, the first ramp voltage generating circuit includes an NMOS tube N7 and a capacitor C OSC1 , the capacitor C OSC1One end is connected to the drain of the NMOS tube N7 and the positive input end of the first comparator, the other end is connected to the source of the NMOS tube N7 and is grounded at the same time, and the gate of the NMOS tube N7 is connected to the output end of the first logic circuit.

[0020] In one or more embodiments of the present invention, the second oscillator includes an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, a capacitor C OSC2 , a second comparator, a second logic circuit and a buffer BUFFER2;

[0021] The gate of the NMOS tube N3 is connected to the output end of the loop filter, the source of the NMOS tube N3 is grounded through the resistor R2, the source of the NMOS tube N3 is connected to the input end I1 of the first selector, the drain and gate of the PMOS tube P3 are short-circuited and connected to the drain of the NMOS tube N3 and the gate of the PMOS tube P4, the source of the PMOS tube P3 is connected to the power supply VDD, the source of the PMOS tube P4 is connected to the power supply VDD, the drain of the PMOS tube P4 is connected to the positive input end of the second comparator, and the capacitor C OSC2 One end of the capacitor C is connected to the drain of the NMOS tube N4 and the positive input terminal of the second comparator. OSC2 The other end of the NMOS tube N4 is connected to the source and grounded, the gate of the NMOS tube N4 is connected to the output end of the second logic circuit, and the negative input end of the second comparator is connected to the reference voltage V REF_OSC The output end of the second comparator is connected to the input end of the buffer BUFFER2 through the second logic circuit, and the output end of the buffer BUFFER2 is connected to the I1 input end of the second selector.

[0022] An embodiment of the present invention further provides a switching frequency control method, comprising:

[0023] Mode determination;

[0024] If it is the PLL mode, when the first oscillator works in the first working state, the first oscillator outputs a clock signal CLOCK of a corresponding frequency, and the second oscillator outputs a clock signal CLK_OSC2 that can be synchronized to an external clock signal CLK_SYNC, and the second oscillator provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC;

[0025] When the first oscillator is converted from the first operating state to the second operating state, the first oscillator outputs the clock signal CLOCK capable of skipping an abnormal state and being synchronized to the external clock signal CLK_SYNC by receiving the control voltage VCONT.

[0026] In one or more embodiments of the present invention, the switching frequency control method, if in RT mode, the first oscillator can output clock signals CLOCK of different frequencies in different working states;

[0027] When the first oscillator operates in the second operating state and the RT mode is switched to the PLL mode, the first oscillator can output a clock signal CLOCK synchronized to an external clock signal CLK_SYNC.

[0028] Compared with the prior art, the switching frequency control system of the embodiment of the present invention provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC while outputting the clock signal CLK_OSC2 that can be synchronized to the external clock signal CLK_SYNC through the second oscillator, so that the clock signal CLOCK output by the first oscillator when it is in the PLL mode and switches from the first working state to the second working state can be quickly synchronized to the external clock signal CLK_SYNC. The switching frequency control system of the present invention effectively realizes the control of the dual-mode switching frequency in the switching power supply, ensures the stability of the output state of each oscillator in different working modes and working states, and the stability of the output state of each oscillator when different modes are switched to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a circuit schematic diagram of a switching frequency control system according to an embodiment of the present invention;

[0030] Figure 2 is a circuit schematic diagram of a phase detector according to an embodiment of the present invention;

[0031] Figure 3 is a circuit diagram of a loop filter according to an embodiment of the present invention;

[0032] Figure 4 is a circuit diagram of a first oscillator according to an embodiment of the present invention;

[0033] Figure 5 is a circuit diagram of a second oscillator according to an embodiment of the present invention;

[0034] Figure 6 is a flow chart of a system control mode of a switching frequency control system according to an embodiment of the present invention;

[0035] Figure 7is a circuit timing diagram when a switching frequency control system according to an embodiment of the present invention is powered on;

[0036] Figure 8 4 is a circuit timing diagram after the switching frequency control system according to one embodiment of the present invention is started. DETAILED DESCRIPTION

[0037] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0038] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0039] Example 1

[0040] like Figure 1 As shown, a switching frequency control system includes: a first phase-locked loop and a second phase-locked loop. The first phase-locked loop includes a phase detector 100, a loop filter 200 and a first oscillator 300; the second oscillator 400 and the first oscillator 300 can form a second phase-locked loop by switching, that is, the first phase-locked loop and the second phase-locked loop share the phase detector 100 and the loop filter 200.

[0041] The switching frequency control system also includes a first selector and a second selector, wherein the I0 input terminal and the output terminal of the first selector are connected to the first oscillator 300, and the I1 input terminal of the first selector is connected to the second oscillator 400. The I0 input terminal of the first selector receives the signal PG, and the output terminal of the first selector outputs the signal PGATE. The I0 input terminal of the second selector is connected to the output terminal of the first oscillator 300 to receive the clock signal CLOCK, and the I1 input terminal of the second selector is connected to the output terminal of the second oscillator 400 to receive the clock signal CLK_OSC2. The output terminal of the second selector is connected to the input terminal of the phase detector 100 to output the signal CLK_IN to the phase detector 100, and the switching between the first oscillator 300 and the second oscillator 400 can be realized by the first selector and the second selector.

[0042] The first oscillator 300 is in the PLL mode and in the first working state, outputting a clock signal CLOCK of a corresponding frequency, and the second oscillator 400 outputs a clock signal CLK_OSC2 that can be synchronized to an external clock signal CLK_SYNC. At the same time, the second oscillator 400 provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC; the first oscillator 300 is in the PLL mode and switches from the first working state to the second working state. Through the control voltage VCONT, the clock signal CLOCK output by the first oscillator 300 after exiting the first working state can skip the abnormal state and be synchronized to the external clock signal CLK_SYNC.

[0043] The first oscillator 300 can output clock signals CLOCK of different frequencies in RT mode and in different working states; the first oscillator 300 switches from RT mode to PLL mode in the second working state, and can output a clock signal CLOCK synchronized to the external clock signal CLK_SYNC.

[0044] In this embodiment, the RT mode and the PLL mode are two working modes. In the first working state, there are two signal output modes, including the lowest frequency output mode corresponding to the system just powered on and counting, at which time the first oscillator 300 outputs the lowest frequency clock signal CLOCK; and the system frequency reduction output mode corresponding to the system frequency reduction after the system is started, at which time the first oscillator 300 outputs the system frequency reduction clock signal CLOCK. The second working state is the normal output mode after the system is started, and in the RT mode, the first oscillator 300 outputs the resistor R SET The clock signal CLOCK of the preset frequency, the resistor R SET In the PLL mode, the first oscillator 300 outputs a clock signal CLOCK whose frequency can be synchronized to the external clock signal CLK_SYNC.

[0045] Therefore, the first oscillator 300 outputs the lowest frequency clock signal CLOCK in the RT mode and the lowest frequency output mode, the first oscillator 300 outputs the system reduced frequency clock signal CLOCK in the RT mode and the system reduced frequency output mode, and the first oscillator 300 outputs the resistor R in the second working state. SET The first oscillator 300 switches from the RT mode to the PLL mode in the second working state, and can output the clock signal CLOCK synchronized with the external clock signal CLK_SYNC.

[0046] The first oscillator 300 outputs a clock signal CLOCK of the lowest frequency or the system frequency reduction frequency in the PLL mode and in the lowest frequency output mode or the system frequency reduction output mode. The second oscillator 400 outputs a clock signal CLK_OSC2 that can be synchronized to the external clock signal CLK_SYNC. At the same time, the second oscillator 400 provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC.

[0047] The first oscillator 300 is in PLL mode and switches from the first working state to the second working state. By controlling the voltage VCONT, the clock signal CLOCK output by the first oscillator 300 after exiting the lowest frequency output mode or the system frequency reduction output mode can skip the abnormal state and synchronize to the external clock signal CLK_SYNC.

[0048] like Figure 1 As shown, the switching frequency control system also includes a mode determination circuit and an enable circuit. The mode determination circuit has an RT / SYNC input, an EN input, a CLK_SYNC output, an RT_MODE output, and a PLL_MODE output. The enable circuit has an EN_CK input, a FORCE_FMIN input, a LOCK_OSC1 input, an EN output, an EN1 output, and an EN2 output. The EN output of the enable circuit is connected to the EN input of the mode determination circuit. The enable circuit receives an input signal FORCE_FMIN through the FORCE_FMIN input, and the input signal FORCE_FMIN is used to indicate whether the circuit operates in the lowest frequency output mode.

[0049] The enable circuit receives the input signal EN_CK according to the EN_CK input terminal and outputs the enable signal EN according to the EN output terminal, outputs the enable signal EN1 according to the EN1 output terminal, and outputs the enable signal EN2 according to the EN2 output terminal. The enable signal EN is equal to the input signal EN_CK. The enable signal EN is used to control the working state of the switching frequency control system. When the enable signal EN is "1", the switching frequency control system works normally. The analysis in this embodiment is based on the premise that the enable signal EN is "1". The enable signal EN1 and the enable signal EN2 correspond to the working state of some circuits in the switching frequency control system respectively. When the enable signal EN1 and the enable signal EN2 are "0", the corresponding parts of the circuit do not work. When the enable signal EN1 and the enable signal EN2 are "1", the corresponding parts of the circuit work.

[0050] The mode determination circuit determines the working mode of each oscillator through the state of the RT / SYNC input terminal. The mode determination circuit outputs the external clock signal CLK_SYNC through the CLK_SYNC output terminal, the control signal RT_MODE for switching the first oscillator 300 to the RT mode through the RT_MODE output terminal, and the control signal PLL_MODE for switching the first oscillator 300 to the PLL mode through the PLL_MODE output terminal.

[0051] In this embodiment, when only resistor RSET is connected between the RT / SYNC input terminal and the ground, the mode determination circuit outputs the control signal RT_MODE as "1" and the control signal PLL_MODE as "0". At this time, the first oscillator 300 operates in the RT mode; at this time, if the input signal FORCE_FMIN is "0" and there is no system frequency reduction, the frequency of the clock signal CLOCK output by the first oscillator 300 is determined by the value of the resistor RSET. When the external clock signal CLK_SYNC is directly connected to the RT / SYNC terminal, the mode determination circuit outputs the control signal PLL_MODE as "1" and the control signal RT_MODE as "0". At this time, the first oscillator 300 operates in the PLL mode. Similarly, if the input signal FORCE_FMIN is "0" and there is no system frequency reduction, the clock signal CLOCK output by the first oscillator 300 is synchronized to the external clock signal CLK_SYNC through the first phase-locked loop. If both exist at the same time, the PLL mode will cover the RT mode through automatic detection, the mode determination circuit outputs the control signal PLL_MODE as "1" and the control signal RT_MODE as "0", and the first oscillator 300 operates in the PLL mode.

[0052] like Figure 2 As shown, the phase detector 100 is a phase comparison module, and the phase detector 100 includes a D flip-flop D1, a D flip-flop D2, an AND gate AND1, an inverter INV3, a PMOS tube P1, a PMOS tube P2, an NMOS tube N1, an NMOS tube N2, a switch S1, a switch S2 and a unit gain amplifier A1.

[0053] Specifically, the input CK terminal of the D flip-flop D1 is connected to the CLK_SYNC output terminal of the mode determination circuit to receive the external clock signal CLK_SYNC, and the input D terminal of the D flip-flop D1 is connected to the power supply VDD. The input CK terminal of the D flip-flop D2 is connected to the output terminal of the second selector to receive the signal CLK_IN, and the input D terminal of the D flip-flop D2 is connected to the power supply VDD. The output Q terminal of the D flip-flop D1 is connected to the A1 input terminal of the AND gate AND1, and the output Q terminal of the D flip-flop D2 is connected to the A2 input terminal of the AND gate AND1. The output terminal of the AND gate AND1 is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 is simultaneously connected to the R reset terminal of the D flip-flop D1 and the D flip-flop D2. The output QN terminal of the D flip-flop D1 is connected to the gate of the PMOS tube P2, and the output Q terminal of the D flip-flop D2 is connected to the gate of the NMOS tube N1. The source of the PMOS tube P2 is connected to the drain of the PMOS tube P1, the source of the PMOS tube P1 is connected to the power supply VDD, and the gate of the PMOS tube P1 is connected to the bias voltage VB1. The source of the NMOS tube N1 is connected to the drain of the NMOS tube N2, the source of the NMOS tube N2 is grounded, and the gate of the NMOS tube N2 is connected to the bias voltage VB2. The source of the PMOS tube P2 is connected to one end of the switch S1, the drain of the NMOS tube N2 is connected to one end of the switch S2, and the other end of the switch S1 is connected to the other end of the switch S2 and connected to the output end of the unit gain amplifier A1. The drain of the NMOS tube N1 is connected to the drain of the PMOS tube P2 and is connected to the input end of the unit gain amplifier A1 and the loop filter 200, so as to output an error voltage corresponding to the phase difference between the clock signal CLOCK or the clock signal CLK_OSC2 and the external clock signal CLK_SYNC to the loop filter 200.

[0054] The phase detector 100 can compare the clock signal CLOCK output by the first oscillator 300 with the external clock signal CLK_SYNC in the PLL mode, and generate an error voltage corresponding to the phase difference between the clock signal CLOCK and the external clock signal CLK_SYNC. At the same time, the phase detector 100 can also compare the clock signal CLK_OSC2 output by the second oscillator 400 with the external clock signal CLK_SYNC, and generate an error voltage corresponding to the phase difference between the clock signal CLK_OSC2 and the external clock signal CLK_SYNC.

[0055] like Figure 3 As shown, the loop filter 200 is used to eliminate the high-frequency signal and the noise signal in the error voltage and output the control voltage VCONT_PRE for controlling the first oscillator 300 or the second oscillator 400. The high-frequency signal and the noise signal in the error voltage are eliminated to meet the performance required by each phase-locked loop in the PLL mode, thereby increasing the stability of the system.

[0056] Specifically, the loop filter 200 includes a resistor R1, a capacitor C1, and a capacitor C2. Specifically, one end of the capacitor C1 and the capacitor C2 are both grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the other end of the capacitor C2 and connected to the drain of the PMOS tube P2 and the drain of the NMOS tube N1 to receive the error voltage, and is also connected to the second oscillator 400 to output the control voltage VCONT_PRE.

[0057] like Figure 4 As shown, the first oscillator 300 can operate in an RT mode or a PLL mode, and the RT mode and the PLL mode can be switched with each other. In the RT mode or the PLL mode, the switching frequency of the switching power supply can be generated.

[0058] Specifically, the first oscillator 300 includes a mode conversion circuit 310, a first current mirror circuit 320, a minimum frequency circuit 330, a frequency maintaining circuit 340, a first slope voltage generating circuit 350, a first comparator, a first logic circuit and a buffer BUFFER1. The mode conversion circuit 310, the first slope voltage generating circuit 350 and the first comparator are all connected to the first current mirror circuit 320, and the first current mirror circuit 320, the minimum frequency circuit 330 and the frequency maintaining circuit 340 are all connected to the first selector.

[0059] like Figure 4 As shown, the mode conversion circuit 310 is used to cut off or switch to the RT mode, and output the corresponding mirror current through the first current mirror circuit 320.

[0060] Specifically, the mode conversion circuit 310 includes an operational amplifier, a switch S3, a resistor R SET , NMOS tube N5. The positive input terminal of the op amp is connected to the reference voltage V REF The negative input terminal of the op amp is connected to the resistor R through switch S3. SET Connect one end of the resistor R SET The other end is grounded. The drain of NMOS tube N5 is connected to the current mirror circuit, the gate of NMOS tube N5 is connected to the output of the operational amplifier, and the source of NMOS tube N5 is connected to the negative input of the operational amplifier. The operational amplifier is controlled by the enable signal EN1. When the enable signal EN1 is "1", the operational amplifier works normally. When the enable signal EN1 is "0", the operational amplifier does not work.

[0061] In the RT mode, the switch S3 is in a closed state. The switch S3 is controlled by the control signal RT_MODE. When the control signal RT_MODE is "1" and the control signal PLL_MODE is "0", the switch S3 is closed, so that the mode conversion circuit 310 enters the RT mode. When the control signal RT_MODE is "0" and the control signal PLL_MODE is "1", the switch S3 is open.

[0062] like Figure 4 As shown, the first current mirror circuit 320 includes a PMOS tube P5 and a PMOS tube P8. The source of the PMOS tube P5 is connected to the power supply VDD, the drain and the gate of the PMOS tube P5 are short-circuited and connected to the drain of the NMOS tube N5 and the I0 input terminal of the first selector. The drain of the PMOS tube P8 is connected to the first ramp voltage generating circuit 350 and the positive input terminal of the first comparator, the gate of the PMOS tube P8 is connected to the output terminal of the first selector, and the source of the PMOS tube P8 is connected to the power supply VDD.

[0063] like Figure 4 As shown, the minimum frequency circuit 330 includes a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6 and a bias current source IBIAS2_FMIN.

[0064] The drain of the PMOS tube P9 is grounded through the resistor R3, the gate of the PMOS tube P9 is grounded through the bias current source IBIAS2_FMIN and connected to the power supply VDD through the capacitor C3, the source of the PMOS tube P9 is connected to the I0 input terminal of the first selector and the drain and gate short-circuit terminal of the PMOS tube P5, and the gate of the PMOS tube P9 is connected to the drain of the PMOS tube P6. The gate of the PMOS tube P6 is connected to the I0 input terminal of the first selector, and the source of the PMOS tube P6 is connected to the power supply VDD.

[0065] like Figure 4 As shown, the frequency maintaining circuit 340 includes a PMOS transistor P7, a switch S4, an NMOS transistor N6 and a resistor R4.

[0066] The source of the PMOS tube P7 is connected to the power supply VDD, the gate of the PMOS tube P7 is connected to the I0 input terminal of the first selector, the drain of the PMOS tube P7 is connected to one end of the switch S4 and the connecting end of the resistor R1 and the capacitor C2, the drain and the gate of the NMOS tube N6 are short-circuited and connected to the other end of the switch S4, and the source of the NMOS tube N6 is grounded through the resistor R4.

[0067] In RT mode, switch S4 is in a closed state. Switch S4 is controlled by the control signal RT_MODE. When the control signal RT_MODE is "1" and the control signal PLL_MODE is "0", switch S4 is closed, so that the frequency maintenance circuit 340 enters the RT mode. At this time, the control voltage VCONT_PRE output by the loop filter 200 is consistent with the drain voltage of the PMOS tube P7. When the first oscillator 300 switches from the RT mode to the PLL mode in the second working state, the control voltage VCONT_PRE does not need to gradually increase from "0", which speeds up the establishment of the phase-locked loop and shortens the establishment time required for the frequency of the clock signal CLOCK output by the first oscillator 300 to be synchronized to the frequency of the external clock signal CLK_SYNC when the first oscillator 300 switches between the two modes.

[0068] like Figure 4 As shown, the first slope voltage generating circuit 350 is used to output a corresponding slope voltage V according to the current output by the current mirror circuit. RAMP1 .

[0069] Specifically, the first ramp voltage generating circuit 350 includes an NMOS transistor N7 and a capacitor C OSC1 Capacitor C OSC1 One end is connected to the drain of the NMOS tube N7 and the positive input end of the first comparator, the other end is connected to the source of the NMOS tube N7 and is grounded at the same time, and the gate of the NMOS tube N7 is connected to the output end of the first logic circuit.

[0070] like Figure 4 As shown, the first comparator is used to convert the ramp voltage V RAMP1 and reference voltage V REF_OSC After comparison, the clock signal CLOCK is output through the first logic circuit and the buffer BUFFER1, the output end of the buffer BUFFER1 is connected to the I0 input end of the second selector, the output end of the first comparator is connected to the input end of the first logic circuit, and the output end of the first logic circuit is connected to the input end of the buffer BUFFER1.

[0071] like Figure 4As shown, the first selector has a control end for receiving a control signal SEL_PLL, the control end of the first selector is connected to the output end of the AND gate circuit AND2, the A1 input end of the AND gate circuit AND2 is connected to the output end of the inverter INV1, the A2 input end of the AND gate circuit AND2 is connected to the input end of the first logic circuit and transmits the control signal PLL_MODE at the same time, and the input end of the inverter INV1 is connected to the input end of the first logic circuit and transmits the input signal FORCE_FMIN at the same time. The first logic circuit is also connected to the input signal CONT, and the input signal CONT is used to characterize whether the system has frequency reduction. In other embodiments, the system frequency reduction situation may not be considered, that is, the first logic circuit may not be connected to the input signal CONT. The first logic circuit also outputs a control signal LOCK_OSC1. The control signal LOCK_OSC1 will also serve as an input signal of the enable circuit and the inverter INV2.

[0072] like Figure 5 As shown, the second oscillator 400 includes an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, and a capacitor C OSC2 , a second comparator, a second logic circuit and a buffer BUFFER2. PMOS tube P3 and PMOS tube P4 form a second current mirror circuit. NMOS tube N4, capacitor C OSC2 A second slope voltage generating circuit is formed.

[0073] Among them, the gate of the NMOS tube N3 is connected to the connection end where the resistor R1 and the capacitor C2 are connected, the source of the NMOS tube N3 is grounded through the resistor R2, the source of the NMOS tube N3 is connected to the input end I1 of the first selector, the drain and the gate of the PMOS tube P3 are short-circuited and connected to the drain of the NMOS tube N3 and the gate of the PMOS tube P4, the source of the PMOS tube P3 is connected to the power supply VDD, the source of the PMOS tube P4 is connected to the power supply VDD, the drain of the PMOS tube P4 is connected to the positive input end of the second comparator, and the capacitor C OSC2 One end of the capacitor C is connected to the drain of the NMOS tube N4 and the positive input terminal of the second comparator. OSC2 The other end is connected to the source of NMOS tube N4 and grounded, the gate of NMOS tube N4 is connected to the output of the second logic circuit, the negative input of the second comparator is connected to the reference voltage VREF_OSC, the output of the second comparator is connected to the input of buffer BUFFER2 through the second logic circuit to output the clock signal CLK_OSC2, and the output of buffer BUFFER2 is connected to the I1 input of the second selector. The second comparator is controlled by the enable signal EN2. When the enable signal EN2 is "1", the second comparator works normally, and when the enable signal EN2 is "0", the second comparator does not work.

[0074] like Figure 2 As shown, the control end of the second selector is connected to the output end of the inverter INV2, and the input end of the inverter INV2 is connected to the LOCK_OSC1 input end of the enabling circuit and receives the control signal LOCK_OSC1.

[0075] In this embodiment, the first selector connects the signal PG at the input end of I0 to the output end by default, and the signal PGATE outputted by it is used as the gate input signal of the PMOS tube P8. Therefore, if there is no system frequency reduction at this time, the frequency of the clock signal CLOCK outputted by the first oscillator 300 is set by the resistance value of the resistor RSET in the RT mode or the minimum frequency corresponding to when the input signal FORCE_FMIN is "1". When the input signal FORCE_FMIN is "0" and the control signal PLL_MODE is "1", the control signal SEL_PLL is set to "1", and the first selector connects the control voltage VCONT at the input end of I1 to the output end, and the signal PGATE outputted by it is used as the gate input signal of the PMOS tube P8. Therefore, if there is no system frequency reduction at this time, the frequency of the clock signal CLOCK outputted by the first oscillator 300 will be synchronized to the frequency of the external clock signal CLK_SYNC through phase-locked loop adjustment.

[0076] The second selector connects the signal at the input terminal I0 (i.e., the clock signal CLOCK output by the first oscillator 300) to the output terminal by default, and the output signal CLK_IN is used as the input clock signal of the D flip-flop D2 in the phase detector 100. At this time, the first phase-locked loop synchronizes the frequency of the clock signal CLOCK output by the first oscillator 300 to the frequency of the external clock signal CLK_SYNC. When the LOCK_OSC1 signal is "0", the second selector connects the signal at the input terminal I1 (i.e., the output frequency CLK_OSC2 of the second oscillator 400) to the output terminal, and the output signal CLK_IN is used as the input clock signal of the D flip-flop D2 in the phase detector 100. At this time, the second phase-locked loop synchronizes the frequency of the clock signal CLK_OSC2 output by the second oscillator 400 to the frequency of the external clock signal CLK_SYNC.

[0077] When the oscillator works in the PLL mode, if it encounters some special conditions, such as when the switching power supply is just powered on and works at the lowest frequency, that is, when the FORCE_FMIN signal is "1", the LOCK_OSC1 signal is set to "0" and the enable signal EN2 is set to "1"; or when the system frequency is reduced after startup, the input signal CONT passes through the first logic circuit, and the control signal LOCK_OSC1 is set to "0" and the enable signal EN2 is set to "1". At this time, the frequency of the clock signal CLOCK output by the first oscillator 300 is equal to the lowest frequency or the system frequency reduction frequency, and the frequency of the clock signal CLK_OSC2 output by the second oscillator 400 is fed back to the input CK terminal of the D flip-flop D2 in the phase detector 100, so the second phase-locked loop synchronizes the frequency of the clock signal CLK_OSC2 output by the second oscillator 400 to the frequency of the external clock signal CLK_SYNC, so that the voltage value of the control voltage VCONT is maintained at the voltage value of the control voltage VCONT determined by the frequency of the external clock signal CLK_SYNC. In this way, when the system exits these special conditions, that is, when the control signal LOCK_OSC1 is set to "1" and the enable signal EN2 is set to "0", the frequency of the clock signal CLOCK output by the first oscillator 300 is fed back to the input CK terminal of the D flip-flop D2 in the phase detector 100. Since the frequency corresponding to the control voltage VCONT is always maintained, the first phase-locked loop will immediately synchronize the frequency of the clock signal CLOCK output by the first oscillator 300 to the frequency of the external clock signal CLK_SYNC, thereby accelerating the establishment of the phase-locked loop.

[0078] When the first oscillator 300 operates in the RT mode, the voltage value of the control voltage VCONT_PRE is maintained at the corresponding frequency through the frequency maintaining circuit 340, which actually means that the voltage value of the control voltage VCONT at the source of the NMOS tube is maintained at the corresponding frequency. In this way, when the first oscillator 300 switches from the RT mode to the PLL mode, the VCONT voltage does not need to be gradually increased from "0", which speeds up the establishment of the phase-locked loop and shortens the time required for the frequency of the clock signal CLOCK to be synchronized to the frequency of the external clock signal CLK_SYNC when the first oscillator 300 switches between the two modes.

[0079] When the input signal FORCE_FMIN is "1", the enable signal EN1 is set to "0", and the SEL_PLL signal is set to "0", the first oscillator 300 is adjusted to operate at the lowest frequency by the lowest frequency circuit 330, that is, the frequency of the clock signal CLOCK output by the first oscillator 300 is the lowest frequency. The lowest frequency is the lowest frequency supported by the first oscillator 300.

[0080] A switching frequency control method in this embodiment includes:

[0081] Mode determination;

[0082] If it is RT mode, the first oscillator 300 can output clock signals CLOCK of different frequencies in different working states;

[0083] When the first oscillator 300 operates in the second operating state and switches from the RT mode to the PLL mode, the first oscillator 300 can output the clock signal CLOCK synchronized with the external clock signal CLK_SYNC.

[0084] If it is the PLL mode, when the first oscillator 300 works in the first working state, the first oscillator 300 outputs the clock signal CLOCK of the corresponding frequency, and the second oscillator 400 outputs the clock signal CLK_OSC2 that can be synchronized to the external clock signal CLK_SYNC, and the second oscillator 400 provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC;

[0085] When the first oscillator 300 is converted from the first operating state to the second operating state, the first oscillator outputs the clock signal CLOCK capable of skipping the abnormal state and synchronizing to the external clock signal CLK_SYNC by receiving the control voltage VCONT.

[0086] like Figure 6 As shown, the input signal EN_CK is "1". It can be seen that when the system is just powered on, a mode determination will be performed first, and the system will determine whether it is working in RT mode or PLL mode based on the state of the RT / SYNC input terminal. If it is determined to be working in RT mode, the control signal RT_MODE is "1", and the control signal PLL_MODE, control signal SEL_PLL, enable signal EN2, and control signal LOCK_OSC1 are all "0". In the counting stage when power is just turned on, the input signal FORCE_FMIN is "1", and the enable signal EN1 is set to "0". At this time, the frequency of the clock signal CLOCK is equal to the minimum frequency. After the counting is completed, the input signal FORCE_FMIN becomes "0", the system starts, and the enable signal EN1 is set to "1". At this time, the frequency of the clock signal CLOCK is controlled by the resistor R SET After startup, the system will constantly determine whether there is a frequency reduction. If there is, the frequency of the clock signal CLOCK is equal to the frequency of the system frequency reduction; if not, the frequency of the clock signal CLOCK is determined by the resistor R SET The value of is determined.

[0087] If it is determined to work in PLL mode, the control signal PLL_MODE is "1", and the control signal RT_MODE and the enable signal EN1 are both "0". Similarly, in the counting stage when power is just turned on, the input signal FORCE_FMIN is "1", the control signal SEL_PLL is set to "0", the enable signal EN2 is set to "1", and the control signal LOCK_OSC1 is set to "0". At this time, the frequency of the clock signal CLOCK is equal to the minimum frequency, and the frequency of the clock signal CLK_OSC2 is synchronized to the frequency of the external clock signal CLK_SYNC. After the counting is completed, the input signal FORCE_FMIN becomes "0". When the system starts, the control signal SEL_PLL is set to "1", the enable signal EN2 is set to "0", and the control signal LOCK_OSC1 is set to "1". At this time, the frequency of the clock signal CLOCK is synchronized to the frequency of the external clock signal CLK_SYNC. After the system starts, the system will continuously determine whether there is a frequency reduction. If so, after the input signal CONT passes through the first logic circuit, the control signal LOCK_OSC1 is set to "0", and the enable signal EN2 is set to "1". At this time, the frequency of the clock signal CLOCK is equal to the frequency of the system downclocking, and the frequency of the clock signal CLK_OSC2 is synchronized to the frequency of the external clock signal CLK_SYNC; if not, after the input signal CONT passes through the first logic circuit, the control signal LOCK_OSC1 is set to "1", and the enable signal EN2 is set to "0". At this time, the frequency of the clock signal CLOCK is synchronized to the frequency of the external clock signal CLK_SYNC.

[0088] like Figure 7 As shown, the input signal EN_CK is "1" and the enable signal EN is also "1". It can be seen that if the system is powered on in RT mode, the control signal RT_MODE is "1", the control signal PLL_MODE is "0", the control signal SEL_PLL is "0", the control signal LOCK_OSC1 is "0", and the enable signal EN2 is "0". When the power is just turned on, when the input signal FORCE_FMIN is "1", the enable signal EN1 is "0", and the frequency of the clock signal CLOCK is equal to the minimum frequency. The voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage VCONT corresponding to the minimum frequency. Then, when the input signal FORCE_FMIN is "0", the enable signal EN1 becomes "1", the frequency of the clock signal CLOCK is set by the value of the resistor RSET, and the voltage value of the control voltage VCONT is established and maintained at the corresponding frequency.

[0089] If the system is powered on in PLL mode, the control signal RT_MODE is "0", the control signal PLL_MODE is "1", and the enable signal EN1 is "0". When the system is just powered on and the input signal FORCE_FMIN is "1", the control signal SEL_PLL is "0", the control signal LOCK_OSC1 is "0", the enable signal EN2 is "1", the frequency of the clock signal CLOCK is equal to the minimum frequency, the frequency of the clock signal CLOCK_OSC2 is synchronized to the frequency of the external clock signal CLK_SYNC, and at this time, the voltage value of the control voltage VCONT will be established and maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC. Then, when the input signal FORCE_FMIN is "0", the control signal SEL_PLL is "1", the control signal LOCK_OSC1 is "1", and the enable signal EN2 is "0". Since the voltage value of the control voltage VCONT has been established and maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC, the frequency of the clock signal CLOCK will be immediately synchronized to the frequency of the external clock signal CLK_SYNC. It can be seen that when the first oscillator 300 operates in the PLL mode, even if the system operates at the lowest frequency when it is just powered on, that is, the input signal FORCE_FMIN is "1", and the frequency of the clock signal CLOCK output by the first oscillator 300 is equal to the lowest frequency, because the control signal LOCK_OSC1 is set to "0" and the enable signal EN2 is set to "1" at this time, the frequency of the clock signal CLK_OSC2 output by the second oscillator 400 will be fed back to the input CK terminal of the D flip-flop D2 in the phase detector 100. At this time, the second phase-locked loop synchronizes the frequency of the clock signal CLK_OSC2 output by the second oscillator 400 to the frequency of the external clock signal CLK_SYNC, so that the voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage VCONT determined by the frequency of the external clock signal CLK_SYNC. In this way, when the first oscillator 300 exits the lowest frequency output mode, the frequency of the clock signal CLOCK output by the first oscillator 300 will be immediately synchronized to the frequency of the external clock signal CLK_SYNC through the first phase-locked loop circuit, thereby accelerating the establishment of the phase-locked loop.

[0090] It should be noted that if there is no clock signal CLOCK_OSC2 that is synchronized to the frequency of the external clock signal CLK_SYNC, the frequency of the control voltage VCONT cannot be maintained at a frequency corresponding to the frequency of the external clock signal CLK_SYNC, which is equivalent to reducing the function of the second oscillator 400. Then when the input signal FORCE_FMIN changes from "1" to "0", the frequency of the clock signal CLOCK will be higher than the frequency of the external clock signal CLK_SYNC at the beginning, and then gradually decrease and synchronize to the frequency of the external clock signal CLK_SYNC. The reason is that in the PLL mode, since the input signal FORCE_FMIN is "1" at the beginning, the frequency of the clock signal CLOCK output by the first oscillator 300 is equal to the minimum frequency. Since the frequency is less than the frequency of the external clock signal CLK_SYNC at this time, when it is fed back to the input CK terminal of the D flip-flop D2 in the phase-locked loop 100, the value of the control voltage VCONT is continuously increased through the first phase-locked loop regulation. Thus, when exiting the lowest frequency output mode, since the voltage value of the control voltage VCONT is very high, the first oscillator 300 will work in an abnormal state of a high frequency determined by the voltage value of the control voltage VCONT, and then gradually reduce and synchronize to the frequency of the external clock signal CLK_SYNC through the adjustment of the first phase-locked loop. Therefore, the control voltage VCONT that can be synchronized to the frequency of the external clock signal CLK_SYNC enables the clock signal CLOCK output by the first oscillator 300 after exiting the lowest frequency output mode to skip the abnormal state and quickly synchronize to the external clock signal CLK_SYNC. Of course, the same principle applies when exiting from the system frequency reduction output mode.

[0091] like Figure 8 As shown, the input signal EN_CK is "1", and the enable signal EN is also "1". It can be seen that after the system is started, the input signal FORCE_FMIN is "0". When the system works in RT mode, the control signal RT_MODE is "1", the control signal PLL_MODE is "0", the enable signal EN1 is "1", and the control signal SEL_PLL, the control signal LOCK_OSC1, and the enable signal EN2 are all "0". If the system is not down-clocked, the frequency of the clock signal CLOCK is determined by the resistor R SET The voltage value of the control voltage VCONT is established and maintained at the corresponding frequency; if there is frequency reduction, the frequency of the clock signal CLOCK is equal to the frequency of the system frequency reduction, and the voltage value of the control voltage VCONT is established and maintained at the corresponding frequency reduction. After exiting the system frequency reduction output mode, the frequency of the clock signal CLOCK is determined by the value of the resistor RSET.

[0092] When the system works in PLL mode, the control signal PLL_MODE is "1", the control signal RT_MODE is "0", the enable signal EN1 is "0", and the control signal SEL_PLL is "1". If the system does not reduce the frequency, the control signal LOCK_OSC1 is "1", the enable signal EN2 is "0", and the frequency of the clock signal CLOCK is synchronized to the frequency of the external clock signal CLK_SYNC; if there is a reduction in frequency, the control signal LOCK_OSC1 is "0", the enable signal EN2 is "1", the frequency of the clock signal CLK_OSC2 is synchronized to the frequency of the external clock signal, and the frequency of the clock signal CLOCK is equal to the frequency of the system reduction in frequency. In the system reduction in frequency stage, the voltage value of the control voltage VCONT is also always maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC, so that after exiting from the system reduction in frequency output mode, the frequency of the clock signal CLOCK will be immediately synchronized to the frequency of the external clock signal CLK_SYNC.

[0093] It can be seen that when the first oscillator 300 works in the PLL mode, even if the system frequency is reduced, because at this time the input signal CONT passes through the first logic circuit, the control signal LOCK_OSC1 is set to "0", and the enable signal EN2 is set to "1", so the clock signal CLK_OSC2 output by the second oscillator 400 will be fed back to the input CK terminal of the D flip-flop D2 in the phase detector 100. At this time, the second phase-locked loop synchronizes the frequency of the clock signal CLK_OSC2 output by the second oscillator 400 to the frequency of the external clock signal CLK_SYNC, so that the voltage value of the control voltage VCONT is maintained at the voltage value of the control voltage VCONT determined by the frequency of the external clock signal CLK_SYNC. At this time, the frequency of the clock signal CLOCK output by the first oscillator 3001 is equal to the system frequency reduction frequency. As shown in FIG. Figure 8 As shown, in the system frequency reduction output mode, since the voltage value of the control voltage VCONT is always maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC, when the system exits the system frequency reduction output mode, the frequency of the clock signal CLOCK output by the first oscillator 300 will be immediately synchronized to the frequency of the external clock signal CLK_SYNC through the first phase-locked loop, thereby speeding up the establishment of the phase-locked loop.

[0094] like Figure 8As shown, when the first oscillator 300 operates in the RT mode, the voltage value of the control voltage VCONT is established and maintained at the corresponding frequency. Therefore, when the first oscillator 300 switches from the RT mode to the PLL mode, the control voltage VCONT voltage does not need to be gradually increased from "0", and the frequency of the clock signal CLOCK output by the first oscillator 300 will be immediately synchronized to the frequency of the external clock signal CLK_SYNC, which speeds up the establishment of the phase-locked loop and shortens the establishment time when the frequency of the clock signal CLOCK output by the first oscillator 300 is synchronized to the frequency of the external clock signal CLK_SYNC when switching between the two modes.

[0095] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A switching frequency control system, characterized in that: include: A first phase-locked loop, the first phase-locked loop comprising a phase detector, a loop filter and a first oscillator; A second oscillator, capable of forming a second phase-locked loop with the first oscillator through switching; The first oscillator can output a clock signal CLOCK of a corresponding frequency in the PLL mode and in the first working state, and the second oscillator can output a clock signal CLK_OSC2 synchronized to an external clock signal CLK_SYNC, and the second oscillator provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC; The first oscillator is in the PLL mode and switches from the first working state to the second working state. The control voltage VCONT enables the clock signal CLOCK output by the first oscillator after exiting the first working state to skip the abnormal state and be synchronized to the external clock signal CLK_SYNC.

2. The switching frequency control system according to claim 1, characterized in that: The first oscillator can output clock signals CLOCK of different frequencies in RT mode and in different working states; the first oscillator switches from RT mode to PLL mode in the second working state, and can output a clock signal CLOCK synchronized to an external clock signal CLK_SYNC.

3. The switching frequency control system according to claim 1, characterized in that: The switching frequency control system also includes a first selector and a second selector, the I0 input and output of the first selector are connected to the first oscillator, the I1 input of the first selector is connected to the second oscillator, the I0 input of the second selector is connected to the output of the first oscillator, the I1 input of the second selector is connected to the output of the second oscillator, and the output of the second selector is connected to the input of the phase detector, and switching between the first oscillator and the second oscillator can be achieved through the first selector and the second selector.

4. The switching frequency control system according to claim 3, characterized in that: The first oscillator includes a mode conversion circuit, a first current mirror circuit, a minimum frequency circuit, a frequency maintaining circuit, a first ramp voltage generating circuit, a first comparator, a first logic circuit and a buffer BUFFER1, the mode conversion circuit, the first ramp voltage generating circuit and the first comparator are all connected to the first current mirror circuit, and the first current mirror circuit, the minimum frequency circuit and the frequency maintaining circuit are all connected to the first selector; The mode conversion circuit is used to cut off or switch to the RT mode, and output the corresponding mirror current through the first current mirror circuit; the minimum frequency circuit is used to make the first oscillator output the minimum frequency; the frequency maintenance circuit is used to maintain the frequency corresponding to the control voltage VCONT in the RT mode; the first ramp voltage generating circuit is used to output the corresponding ramp voltage V according to the mirror current output by the first current mirror circuit. RAMP1 The first comparator is used to convert the ramp voltage V RAMP1 and reference voltage V REF_OSC After comparison, the clock signal CLOCK is output through the first logic circuit and the buffer BUFFER1.

5. The switching frequency control system according to claim 4, characterized in that: The mode conversion circuit includes an operational amplifier, a switch S3, a resistor R SET and NMOS tube N5; The positive input terminal of the op amp is connected to the reference voltage V REF The negative input terminal of the operational amplifier is connected to the resistor R through the switch S3. SET One end of the resistor R SET The other end of the operational amplifier is grounded, the negative input end of the operational amplifier is connected to the source of the NMOS tube N5, the gate of the NMOS tube N5 is connected to the output end of the operational amplifier, the drain of the NMOS tube N5 is connected to the first current mirror circuit, and in the RT mode, the switch S3 is in a closed state.

6. The switching frequency control system according to claim 4, characterized in that: The first current mirror circuit includes a PMOS tube P5 and a PMOS tube P8, the source of the PMOS tube P5 is connected to the power supply VDD, the drain and gate of the PMOS tube P5 are short-circuited and connected to the I0 input end of the first selector, the gate of the PMOS tube P8 is connected to the output end of the first selector, the source of the PMOS tube P8 is connected to the power supply VDD, and the drain of the PMOS tube P8 is connected to the positive input end of the first comparator.

7. The switching frequency control system according to claim 4, characterized in that: The minimum frequency circuit includes a PMOS tube P9, a resistor R3, a capacitor C3, a PMOS tube P6 and a bias current source IBIAS2_FMIN; Among them, the drain of the PMOS tube P9 is grounded through the resistor R3, the gate of the PMOS tube P9 is grounded through the bias current source IBIAS2_FMIN and connected to the power supply VDD through the capacitor C3, the source of the PMOS tube P9 is connected to the I0 input end of the first selector, the gate of the PMOS tube P9 is connected to the drain of the PMOS tube P6, the gate of the PMOS tube P6 is connected to the I0 input end of the first selector, and the source of the PMOS tube P6 is connected to the power supply VDD.

8. The switching frequency control system according to claim 4, characterized in that: The frequency maintaining circuit includes a PMOS tube P7, a switch S4, an NMOS tube N6 and a resistor R4; Among them, the source of the PMOS tube P7 is connected to the power supply VDD, the gate of the PMOS tube P7 is connected to the I0 input end of the first selector, the drain of the PMOS tube P7 is connected to one end of the switch S4 and the output end of the loop filter, the drain and the gate of the NMOS tube N6 are short-circuited and connected to the other end of the switch S4, the source of the NMOS tube N6 is grounded through the resistor R4, and in the RT mode, the switch S4 is in a closed state.

9. The switching frequency control system according to claim 4, characterized in that: The first ramp voltage generating circuit includes an NMOS tube N7 and a capacitor C OSC1 , the capacitor C OSC1 One end is connected to the drain of the NMOS tube N7 and the positive input end of the first comparator, the other end is connected to the source of the NMOS tube N7 and is grounded at the same time, and the gate of the NMOS tube N7 is connected to the output end of the first logic circuit.

10. The switching frequency control system according to claim 3, characterized in that: The second oscillator includes an NMOS tube N3, a resistor R2, a PMOS tube P3, a PMOS tube P4, an NMOS tube N4, a capacitor C OSC2 , a second comparator, a second logic circuit and a buffer BUFFER2; The gate of the NMOS tube N3 is connected to the output end of the loop filter, the source of the NMOS tube N3 is grounded through the resistor R2, the source of the NMOS tube N3 is connected to the input end I1 of the first selector, the drain and gate of the PMOS tube P3 are short-circuited and connected to the drain of the NMOS tube N3 and the gate of the PMOS tube P4, the source of the PMOS tube P3 is connected to the power supply VDD, the source of the PMOS tube P4 is connected to the power supply VDD, the drain of the PMOS tube P4 is connected to the positive input end of the second comparator, and the capacitor C OSC2 One end of the capacitor C is connected to the drain of the NMOS tube N4 and the positive input terminal of the second comparator. OSC2 The other end is connected to the source of the NMOS tube N4 and grounded, the gate of the NMOS tube N4 is connected to the output end of the second logic circuit, the negative input end of the second comparator is connected to the reference voltage VREF_OSC, the output end of the second comparator is connected to the input end of the buffer BUFFER2 through the second logic circuit, and the output end of the buffer BUFFER2 is connected to the I1 input end of the second selector.

11. A switching frequency control method, characterized in that: include: Mode determination; If it is the PLL mode, when the first oscillator works in the first working state, the first oscillator outputs a clock signal CLOCK of a corresponding frequency, and the second oscillator outputs a clock signal CLK_OSC2 that can be synchronized to an external clock signal CLK_SYNC, and the second oscillator provides a control voltage VCONT corresponding to the frequency of the external clock signal CLK_SYNC; When the first oscillator is converted from the first operating state to the second operating state, the first oscillator outputs the clock signal CLOCK capable of skipping an abnormal state and being synchronized to the external clock signal CLK_SYNC by receiving the control voltage VCONT.

12. The switching frequency control method according to claim 11, characterized in that: If it is RT mode, the first oscillator can output clock signals CLOCK of different frequencies in different working states; When the first oscillator operates in the second operating state and the RT mode is switched to the PLL mode, the first oscillator can output a clock signal CLOCK synchronized to an external clock signal CLK_SYNC.

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