Nonlinear digital-to-analog converter

Abstract

A digital-to-analog converter includes a plurality of reference modules, an output capacitor for outputting an analog voltage, and a common switch coupled between the output capacitor and the reference modules. Each reference module includes a plurality of reference capacitors and a plurality of reference switches. The reference modules are connected in parallel to each other. Each reference module includes a reference capacitor and a reference switch connected in series. The reference capacitors have substantially the same reference capacitance. The reference switches are controlled by a plurality of control signals. The control signals correspond to a control code. The digital-to-analog converter generates the analog voltage based on the control code. An analog difference between a first analog voltage corresponding to a first control code and a second analog voltage corresponding to a second control code monotonically increases or monotonically decreases as a first value corresponding to the first control code increases.

Description

TECHNICAL FIELD

[0001] The present application relates to a digital-to-analog converter, and more particularly, to a non-linear digital-to-analog converter. BACKGROUND

[0002] Piezoelectric-actuated speakers (piezo-speakers) are gaining popularity in recent times. Due to the capacitive nature of the thin film piezo-actuator, these piezo-speakers impose a high capacitive load on the amplifier. However, conventional drive circuits (e.g. class AB, class D, class G, class H amplifiers) are developed under the assumption that the load (a coil made of very thin wire) is mainly resistive with a slight inductive nature, and hence these amplifiers are inefficient when driving a high capacitive load such as piezo-speakers.

[0003] Furthermore, due to the capacitive nature of the load, the current is approximately 90° out of phase with the drive voltage. As such, the piezo-speaker does not actually consume much power during the charging phase (cycle). Most of the energy drawn during the charging phase is stored in the capacitance of the load. However, during the recovery / discharging phase (cycle), when the voltage across the speaker is reduced, conventional class AB, class D, class G, class H amplifiers merely draw energy from the capacitance of the load to ground (or to the negative supply) and cause wastage.

[0004] Therefore, there is a need to improve the prior art. SUMMARY

[0005] Accordingly, the main object of the present application is to provide a non-linear digital-to-analog converter to improve the drawbacks of the prior art.

[0006] The application discloses a digital-to-analog converter, comprising a plurality of reference modules, a plurality of reference capacitors and a plurality of reference switches, wherein the plurality of reference modules are connected in parallel with each other, each reference module comprises a reference capacitor and a reference switch connected in series; an output capacitor for outputting an analog voltage; and a common switch coupled between the output capacitor and the plurality of reference modules; wherein the plurality of reference capacitors have substantially the same reference capacitance value; wherein the plurality of reference switches are controlled by a plurality of control signals, and the plurality of control signals correspond to a control code; wherein the digital-to-analog converter generates the analog voltage according to the control code; wherein an analog difference between a first analog voltage corresponding to a first control code and a second analog voltage corresponding to a second control code monotonously increases or monotonously decreases as a first value corresponding to the first control code increases; and the first control code is continuous to the second control code. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0008] Figure 1 FIG. 1 is a schematic diagram of a drive circuit according to an embodiment of the present application.

[0009] Figure 2 FIG. 2 is a schematic diagram of a conventional biquad filter.

[0010] Figure 3 FIG. 3 is a schematic diagram of a pulse width modulation control circuit according to an embodiment of the present application.

[0011] Figure 4 FIG. 4 is a timing diagram of the operation of the pulse width modulation control circuit according to an embodiment of the present application.

[0012] Figure 5 FIG. 5 is a schematic diagram of another pulse width modulation control circuit according to an embodiment of the present application.

[0013] Figure 6 FIG. 6 is another timing diagram of the operation of the pulse width modulation control circuit according to an embodiment of the present application.

[0014] Figure 7 FIG. 7 is another schematic diagram of the operation of the pulse width modulation control circuit according to an embodiment of the present application.

[0015] Figure 8 FIG. 8 is a schematic diagram of a digital-to-analog converter according to an embodiment of the present application.

[0016] Figure 9 is an embodiment of the present application Figure 8 is an operation timing diagram of a digital-to-analog converter shown in the embodiment of the present application.

[0017] Figure 10 is a schematic diagram of a transistor circuit structure disclosed in the prior art.

[0018] Figure 11 、 12 are schematic diagrams of the flow of the embodiments of the present application, respectively.

[0019] Explanation of Reference Signs:

[0020] 10, A0: driving circuit

[0021] 11: voltage source

[0022] 12: charging circuit

[0023] 13: load

[0024] 14: discharging circuit

[0025] 16: pulse width modulation controller

[0026] 101: up-sampler

[0027] 102: up-sampling filter

[0028] 103: control circuit

[0029] 104: phase-locked loop

[0030] 105: clock divider

[0031] 106: filter

[0032] 107: analog-to-digital converter

[0033] 108: differential amplifier

[0034] 124, A24: bidirectional circuit

[0035] 151, 155: pulse width modulation control circuit

[0036] 201: charging pulse width lookup table

[0037] 202: discharging pulse width lookup table

[0038] 203: memory

[0039] 204: sawtooth waveform generator

[0040] 205: digital-to-analog converter

[0041] 206: comparator

[0042] 208: multiplexer

[0043] S1, S2, S3: switch

[0044] D1, D2: diode

[0045] L1, L2: inductor

[0046] I ch : charging current

[0047] I dis : discharging current

[0048] V L ,V S : voltage

[0049] SU, SD: pulse width modulation signal

[0050] IN: input signal

[0051] FB1: feedback signal

[0052] CK0: clock signal

[0053] CK1: clock signal

[0054] IN^: up-sampled input signal

[0055] Vp2n: single-ended feedback signal

[0056] STA: state control signal

[0057] FB: digital feedback signal

[0058] SD*: control signal

[0059] NSTP: step value

[0060] k: scaling control signal

[0061] a1, a2, b1, b2, b3: coefficient

[0062] z-1: state

[0063] CY t-2 ~ CY t+2 : period

[0064] 24: decoding circuit

[0065] M0 ~ M63: reference module

[0066] SC: pre-charge switch

[0067] CS: output capacitor

[0068] ST: Shared switch

[0069] SP: Discharge switch

[0070] S0-S63: Reference switch

[0071] C0-C63: Reference capacitor

[0072] VA: Analog voltage

[0073] VREF: Reference voltage

[0074] TC: Cycle

[0075] T0, T1: Time period

[0076] SP1-SP4: Pulse width modulation control signal

[0077] T1-T4: Transistor DETAILED DESCRIPTION

[0078] In this application, the term "coupled to" can refer to either a direct or indirect connection. "Coupling element A to element B" can mean that element A is either directly connected to element B, or that element A is connected to element B through some element C. Also, in the context of charging pulse width look-up table and discharge pulse width look-up table, the term "pulse width" can refer to a control code that is used to control the pulse width of a pulse through an analog way with a digital-to-analog converter (DAC), a sawtooth waveform, and an analog comparator, or through a digital way with a counter, a clock, and a digital comparator.

[0079] In the following description, the term "substantially" generally means that there can be minor variations or deviations. For example, the term "substantially the same" means that the variation is within 10% of a given value or range, or that the variation is within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. That is, two quantities a and b that are substantially the same mean that |a-b| < ε x |a| or |a-b| < ε x |b|, where ε represents a small quantity, such as 10 -1 , 10 -2 , 10 -3 or less, and |a| outputs the absolute value or magnitude of a. For example, an output signal V LProportional (e.g., direct) to the input signal IN means that ||IN(t) - c · V L (t)| 2 ≤ ε · ||IN(t)| 2 where ||s(t)| 2 may represent the energy of any signal s(t), IN(t) and V L (t) represent time-varying functions of the input signal and the output signal, respectively, c represents a constant, which can be positive or negative, and ε represents a small quantity, which can be, for example, 10 -1 , 10 -2 , 10 -3 , or smaller.

[0080] To recover the energy stored in a capacitive load, the Applicant provided in U.S. Application No. 17 / 022,106 a method of a driving circuit with energy recovery capability to utilize a DC-DC converter circuit as a charging circuit to charge a capacitive load; utilize another DC-DC converter circuit as a discharging circuit to recover the energy stored in the capacitive load; and utilize a pulse width modulation (PWM) controller to compensate for the imbalance of the charge transfer capability of the charging circuit and the discharging circuit. However, due to the adoption of an analog (real-time) feedback loop, overshooting and close-loop stability make it difficult to increase the open-loop gain, which must suppress the residual error to obtain good total harmonic distortion (THD) performance. Furthermore, as shown in U.S. Patent Application No. 17 / 022,106, the capability of the charging circuit and the charge transfer capability of the discharging circuit have diametrically opposite trends with respect to the output voltage level, making the analog pulse width modulation controller severely compromised in design, resulting in subpar performance. Figure 12

[0081] ​To solve this problem, an embodiment based on digital n-bit modulation is proposed in this application, which uses an analog-to-digital converter (ADC) to digitize the control loop, and the control loop is performed in the digital domain, with a look-up table storing pre-computed pulse width modulation pulse width control information (i.e. pulse width control code (PWCC)), and a pulse width modulation pulse generator to convert the digitally encoded pulse width modulation pulse width (i.e. pulse width control code) into actual pulse width modulation pulses. Furthermore, to solve the problem that the charging circuit's capability and the discharging circuit's charge transfer capability have opposite trends with respect to the output voltage level, by having one pulse width control code table (PWCC table) dedicated to charging operation and another pulse width control code table dedicated to discharging operation, the control of charging operation and the control of discharging operation can be separated (in practice, separation is only conceptual, and the two pulse width control code tables can reside in a continuous memory address space).

[0082] In an embodiment, before each direct-current-to-direct-current switching cycle (or simply "switching cycle"), the state of each switching cycle is determined to be charging, discharging or idle, according to the difference between the expected output signal (typically the input signal multiplied by a gain) and the feedback signal in the digital domain. For non-idle switching cycles, the width of the pulse width modulation is controlled to generate a charge transfer such that in each cycle, a unit voltage change (e.g. ΔV) or an integer multiple of a unit voltage change (e.g. ±n x ΔV) is generated according to a look-up table, where the charge transfer is compensated for factors such as the relationship between a supply / source voltage and a load voltage; the relationship between the amplitude of the current and circuit parameters such as resistance, inductor core saturation, etc.; the direction of current flow (charging or discharging); and the relationship between permittivity and load voltage.

[0083] Please refer to Figure 1 , Figure 1 Figure 1 is a schematic diagram of an embodiment of a drive circuit 10 of the present application. The drive circuit 10 is coupled between a voltage source 11 and a load 13, and receives an input signal IN to drive the load 13 according to the input signal IN. The input signal IN can be an input audio signal.

[0084] The voltage source 11 is a power source that can have energy storage capability. For example, the voltage source 11 can include a battery (which can or can not be a rechargeable battery) or a direct current (DC) power supply, such as a DC-to-DC switching power supply. In an embodiment, the voltage source 11 (e.g., a DC-to-DC switching power supply) can include a capacitor or have capacitive properties.

[0085] In an embodiment, the load 13 can include a loudspeaker, or equivalently, a sound producing device or an acoustic transducer. In this case, the input signal IN can be an audio signal. In an embodiment, the loudspeaker within the load 13 can include a piezoelectric actuated speaker. Specifically, the drive circuit 10 can be connected to a driver piezoelectric driver of the piezoelectric actuated speaker. The driver piezoelectric driver within the load 13 can include a piezoelectric layer sandwiched between a first / top electrode and a second / bottom electrode. Further, the drive circuit 10 can be connected to the electrodes of the driver. It is noted that there is a significant capacitance between the first / top electrode and the second / bottom electrode such that the load 13 can be referred to as a capacitive load, a speaker, or a capacitive speaker load.

[0086] The drive circuit 10 is configured to not only form a charging current from the voltage source 11 to the load 13 during the charging phase, but also to form a discharging current from the load 13 back to the voltage source 11 during the discharging phase. In this regard, the energy stored into the capacitance within the load 13 during the charging phase is recovered back into the capacitance within (or alongside) the voltage source 11 during the discharging phase, thereby reducing the overall energy consumed.

[0087] Specifically, the drive circuit 10 includes a bidirectional circuit 124 that includes a charging circuit 12, a discharging circuit 14, and a pulse width modulation controller 16. The pulse width modulation controller 16 can be implemented by an application specific integrated circuit (ASIC), but is not limited thereto. The first end of the charging circuit 12 and the discharging circuit 14 are coupled to the voltage source 11, and the second end is coupled to the load 13. The charging circuit 12 is configured to form a first / charging current I ch (or provide a first / charging current path) from the voltage source 11 to the load 13; and the discharging circuit 14 is configured to form a second / discharge current I dis (or provide a second / discharge current path) from the load 13 back to the voltage source 11.

[0088] With the capacitance within the load 13, the charging circuit 12 forms a first / charging current I L from V to VS The boost converter (a type of DC-DC converter) has a discharge circuit 14 that forms a voltage drop from V during the discharge phase. S To V L This is a buck converter (another type of DC-DC converter). In other words, the drive circuit 10 can be viewed as using a boost converter (charging circuit 12) to charge the capacitor in the load 13, thereby increasing the voltage V across the load 13. L The voltage converter (discharge circuit 14) is used to discharge the capacitor in the load 13 to reduce the voltage V across the load 13. L .

[0089] In one embodiment, during the charging phase, at voltage V L During the time interval corresponding to the rising portion of the voltage, the charging circuit 12 provides a charging current I from the voltage source 11 to the load 13. ch To perform the charging operation. During the discharging phase, at voltage V L During the time interval corresponding to the decreasing portion of the discharge current, the discharge circuit 14 discharges the discharge current I. dis The discharge operation is performed by directing the current from load 13 back to voltage source 11.

[0090] exist Figure 1 In the illustrated embodiment, the charging circuit 12 includes a switch S1, a diode D1, and an inductor L1; the discharging circuit 14 includes a switch S2, a diode D2, and an inductor L2. Switch S1 is controlled by a first pulse width modulation (PWM) signal SU, while switch S2 is controlled by a second PWM signal SD. The PWM signals SU and SD are generated by a PWM controller 16. The PWM controller 16 has a first input terminal to receive an input signal IN, and a second input terminal coupled to a load 13 to receive a feedback signal FB1. The PWM controller 16 generates PWM signals SU and SD based on the input signal IN and the feedback signal FB1, causing the drive circuit 10 to drive the load 13 according to the input signal IN. Diodes D1 and D2 are used as rectifying components, which will be described in detail later.

[0091] The connections between the components within the drive circuit 10 are detailed below. In the charging circuit 12, the anode of diode D1 is coupled to voltage source 11 via inductor L1, and the cathode of diode D1 is coupled to load 13. The first terminal of switch S1 is coupled to the anode of diode D1. That is, the first terminal of inductor L1 is coupled to voltage source 11, while the second terminal of inductor L1 is coupled to the anode of diode D1 and the first terminal of switch S1. In one embodiment, as... Figure 1As shown, the second terminal of switch S1 can be coupled to a ground terminal, but is not limited thereto. In the discharging circuit 14, the first terminal of switch S2 is coupled to the voltage source 11 via inductor L2, the second terminal of switch S2 is coupled to the load 13, and the cathode of diode D2 is coupled to the first terminal of switch S2. That is, the first terminal of inductor L2 is coupled to the voltage source 11, and the second terminal of inductor L2 is coupled to the cathode of diode D2 and the first terminal of switch S2. In an embodiment, as shown, the anode of diode D2 can be coupled to a ground terminal, but is not limited thereto. Figure 1

[0092] In an embodiment, diodes D1 and D2 can be replaced by synchronous rectifiers (SRs), including switches / metal-oxide-semiconductor field-effect transistors (MOSFETs) with appropriate (gate) control signals, as will be described later. In an embodiment, as an alternative to the dedicated inductors L1 and L2, these two inductors can be combined into a common inductor. In an embodiment, as an alternative to a dedicated circuit 12 (a boost converter) for the charging operation and a dedicated circuit 14 (a buck converter) for the discharging operation, both charging and discharging can be implemented by a buck-boost converter circuit, with appropriate driving signals.

[0093] In an embodiment, as shown, the load 13 can be directly coupled to a ground terminal. In an alternative embodiment, the load 13 can be coupled to a direct current bias voltage source (V BIAS ), but is not limited thereto. Figure 1

[0094] The voltage source 11 provides a supply / source voltage V S , and the load 13 has a load voltage V L , where V L may also be considered as the output voltage of the load 13. Although the embodiments are discussed in the context where the supply / source voltage V S is not higher than the load voltage V L , i.e., V S ≤ V L , the disclosed concepts are not limited thereto.

[0095] ​​Although the circuit topology is similar to a DC-to-DC switching power supply (e.g. a boost converter and / or a buck converter), the control mechanism of the switches S1 / S2 is actually closer to that of a conventional class D amplifier, which controls the switches S1 / S2 based on a pulse width modulation signal generated from the feedback signal FB1 and the input signal IN, and a pulse width modulation controller. The pulse width modulation controller will be described in detail later.

[0096] Unlike the driving circuits of the prior art (e.g. class D amplifier or class AB amplifier), the discharging circuit 14 discharges the current I dis back to the voltage source 11 from the load 13 instead of flowing to ground or another voltage source (e.g. a negative voltage source). It can be considered that the energy / charge stored in the capacitor within the load 13 is recovered and stored back to the voltage source 11. As a result, the power consumption of the driving circuit is significantly reduced.

[0097] As shown in the pulse width modulation controller 16, the input signal IN (which can be the output of an analog-to-digital converter, or entered via a parallel bus or a serial bus such as Sony / Philips Digital Interface Format (S / PDIF), Pulse Density Modulation (PDM), or Integrated Interchip Sound (I2S) bus) is to be amplified by the driving circuit 10, and can be encoded into a 16-bit or 24-bit per second (bps) pulse-code modulation (PCM) format at a data rate of 44.1 kilo samples per second (Ksps), 48 Ksps, 96 Ksps, or 192 Ksps. A phase-locked loop 104 can multiply the clock of the input signal IN by R to generate a clock signal CK0. A clock divider 105 can divide the clock signal CK0 by C to generate a clock signal CK1. The clock signal CK1 defines the "switching cycle" of the driving circuit 10, C is the number of clocks of the clock signal CK0 per switching cycle and the clock signal CK0 controls the operation of the driving circuit 10 in each switching cycle. For example, in the input signal IN has a data rate of 48 Ksps and R = 1024, C = 16, CK0 = 49.152 MHz (mega hertz), CK1 = 3.072 MHz. In another example, the input signal IN has a data rate of 48 Ksps and R = 336, C = 16, CK0 = 16.128 MHz, CK1 = 1.008 MHz.

[0098] In such a case, an up-sampler 101 can perform decimation and interpolation operations on the input signal IN with a clock signal CKl (i.e., an up-sampling rate). An up-sampling filter 102 can filter out or attenuate the higher frequency components caused by the up-sampler 101 and can be a low-pass filter to smooth the output of the up-sampler 101 to produce an up-sampled input signal IN^. Thus, when the clock signal CKl is set to a high rate, for a given output slew rate, the step size in the D-to-D switching period can be reduced, which results in better resolution and lower total harmonic distortion. In addition, the in-band quantization noise (<20 KHz) can also be reduced due to the higher up-sampling rate. However, since both the ADC 107 and the D-to-D are running at high rates, the total power consumption of the driving circuit 10 will increase. Thus, by setting R to different values, a trade-off between the output resolution (sound quality) and the internal power consumption can be made.

[0099] Note that the bit resolution from the up-sampler 101 and the low-pass filter 102 is typically higher than the bit resolution of IN, and the increase in resolution can typically be calculated as For example, if the sample rate of IN^ is 768 Ksps = 16 x 48 Ksps and the bit resolution of IN is 16 bps, then IN^(which has 4 times the resolution of IN) should use 18 bits per sample. In an alternative embodiment, the up-sampler 101 and the low-pass filter 102 can be replaced by a delta sigma modulator, which can produce an up-sampled (i.e., oversampled) IN^(which has a bit resolution per sample significantly lower than the input IN). With the noise shaping properties of delta sigma modulation and the high IN to IN^ oversampling rate, even if the bit resolution per sample of IN^ is substantially less than the bit resolution per sample of IN (e.g., 8 bits per sample), the quantization noise of IN^ will be shifted to the inaudible frequency band (>20 KHz), and a very high signal-to-noise ratio (SNR) can be achieved in the audible frequency band (<20 KHz), while the complexity of the amplification circuit 10 can be greatly reduced.

[0100] The feedback signal FB1 (i.e., the real-time across voltage across the load 13) is converted to a single-ended feedback signal Vp2n by a differential amplifier 108. At the beginning of each cycle of the clock signal CK1, the single-ended feedback signal Vp2n is sampled by a sample and hold (S / H) within an analog-to-digital converter 107 (e.g., a successive-approximation (SAR) analog-to-digital converter with a sample and hold input stage), and after k cycles of CK0 during which the analog-to-digital conversion is performed by the analog-to-digital converter 107, a digital value of the feedback signal FB corresponding to the value of the single-ended feedback signal Vp2n is latched at the output of the analog-to-digital converter 107.

[0101] It is noted that in some embodiments, the analog-to-digital converter 107 can comprise a differential input stage. In this case, the analog-to-digital converter 107 and the differential amplifier 108 can be an integral whole as indicated by the dashed box, and the differential amplifier 108 corresponds to the differential input stage of the analog-to-digital converter 107.

[0102] The control circuit 103 can generate a state control signal STA from the input signal IN and the feedback signal FB1 (e.g., the up-sampled input signal IN^ and the digital feedback signal FB).

[0103] In detail, the filter 106 of the control circuit 103 filters the digital feedback signal FB to generate a filtered digital feedback signal FB* having a bit per sample resolution matching that of the up-sampled input signal IN^. Then, the control circuit 103 calculates an actual difference DLT act (i.e., DLT act = IN^-FB*, representing a delta operation) between the up-sampled input signal IN^ and the filtered digital feedback signal FB*. If the actual difference DLT act is greater than a positive specific value, the control circuit 103 generates the state control signal STA to indicate a charging operation (i.e., STA = CHARGE) so that the drive circuit 10 forms a charging current from the voltage source 11 to the load 13 during a charging period. In this way, the charging current adds a unit voltage change (e.g., ΔV) or a first integer multiple of the unit voltage change (e.g., n x ΔV) to the load 13 in the next DC-DC switching period.

[0104] On the other hand, if the difference DLT actWhen the difference DLT is less than a negative certain value, the control circuit 103 generates the state control signal STA to indicate a discharging operation (i.e. STA = DISCHARGE) so that the driving circuit 10 forms a discharging current from the load 13 back to the voltage source 11 during the discharging period. As a result, the discharging current subtracts a unit voltage change (e.g. -ΔV) or a second integer multiple of the unit voltage change (e.g. -n' x ΔV) from the load 13 during the next DC-to-DC switching period.

[0105] Otherwise, if the difference DLT is greater than a positive certain value (i.e. DLT > MAX_DLT), the control circuit 103 generates the state control signal STA to indicate a charging operation (i.e. STA = CHARGE) so that the driving circuit 10 forms a charging current from the voltage source 11 to the load 13 during the charging period. As a result, the charging current adds a unit voltage change (e.g. +ΔV) or a second integer multiple of the unit voltage change (e.g. n' x ΔV) to the load 13 during the next DC-to-DC switching period. act Between the positive certain value and the negative certain value (e.g. -MIN_DLT ≤ DLT ≤ MIN_DLT), the control circuit 103 generates the state control signal STA to indicate an idle operation (i.e. STA = IDLE) so that the driving circuit 10 does not form a charging current or a discharging current, and the voltage V act of the load 13 remains unchanged during the next DC-to-DC switching period. L

[0106] It is noted that the difference DLT act is DLT act = IN - FB * used in an embodiment of the present application, but not limited thereto. In general, the actual difference DLT act may be expressed as DLT act = f1(IN) - f2(FB), where f1(·) / f2(·) represents a function corresponding to a signal processing of the signals IN / FB, in which the signal processing can be or include a data conversion operation (e.g. digital-to-analog conversion or analog-to-digital conversion), a filtering operation or a multi-rate signal processing (e.g. down-sampling or up-sampling operation). As long as DLT act reflects the difference between IN and FB, the present application is satisfied regardless of whether the signals IN / FB are processed or not.

[0107] ​Due to the charge storage nature of the capacitance in the load 13, the charge flowing into or out of the load 13 during each cycle of the DC-to-DC switching will be integrated with the charge in the load 13 from the previous cycle of the DC-to-DC switching. In other words, the capacitance in the load 13 implicitly performs a sigma (Σ) operation. Thus, by combining the sigma (Σ) operation of the load 13 with the delta (Δ) operation of the control circuit 103, a sigma-delta (ΣΔ) system can be created between the driver circuit 10 and the load 13. Since the sigma operation of the load 13 is a natural behavior of a capacitor, this feature can be referred to as "auto-ΣΔ". Due to this auto-ΣΔ nature of the driver circuit 10, the effective number of bits of the resolution of the driver circuit 10 can be significantly improved by properly designing the filter (e.g., 106). For example, when the resolution of the IN^ and the analog-to-digital converter is 8 bits, and the filter corresponds to a first order ΣΔ system (L = 1), with CK1 = 3.072 MHz, the oversampling is 64 times relative to 48 Ksps, the signal-to-noise ratio of the driver circuit 10 in the audible band (<20 KHz) can be > 110 decibels (dB), which exceeds the signal-to-noise ratio of a 16 bps pulse code modulation, 48 Ksps data stream.

[0108] Furthermore, when the actual value of the generated unit voltage change (e.g., ΔV) or the generated first integer multiple of the unit voltage change (e.g., n x ΔV) deviates from the target amount, this deviation or error will be integrated into the existing charge of the load 13 (including the present current across the voltage of the load 13), and will be converted into the digital feedback signal FB by the analog-to-digital converter 107 in the next CK1 cycle, then become FB* to be compared with the upsampled input signal IN^ to generate the pulse width modulation control signals SU and / or SD in the subsequent switching cycle. Thus, as long as the deviation (i.e., nonlinearity) from the target amount of the unit voltage change is not very large (e.g., + / - 35% of the unit voltage change), the deviation (or error) from the target amount of the unit voltage change ΔV can be suppressed by the auto-ΣΔ operation in the subsequent switching cycle, and the linearity of the driver circuit 10 will be mainly determined by the linearity of the analog-to-digital converter 107. In other words, the pulse width modulation control circuit 151, the charging circuit 12, the discharging circuit 14, the load 13, and the analog-to-digital converter 107 form a ΣΔ feedback control loop, in which the unit voltage change ΔV is accumulated by the load 13, re-digitized by the analog-to-digital converter 107, and compensated by the pulse width modulation control signals SU and / or SD in the next cycle of the DC-to-DC switching.

[0109] Note that in addition to the idle period, the feedback control loop involves a fixed value of unit voltage change ΔV, which is no different from the operation of a 1-bit DAC conversion. In comparison with the 1-bit DAC conversion operation, when the difference DLT act between the positive and negative specific values (e.g., -MIN_DLT ≤ DLT act ≤ MIN_DLT), the idle period suppresses switching. While this operation helps to avoid some switching activities to reduce power consumption, it can cause the output resolution to be reduced. Therefore, the specific values are usually small, and in some embodiments, the control circuit 103 can choose not to generate the state control signal STA = IDLE indicating the idle operation.

[0110] In addition, the analog amplifier needs to deal with closed-loop stability and phase margin, and the filter 106 can help the driving circuit 10 to deal with the same considerations. The filter 106 can be a scaler, a single register filter, a bi-quadratic (BiQuad) filter, or have a transfer function suitable for forming a Σ-Δ filter when combined with the auto Σ operation of the load 13.

[0111] Please refer to Figure 2 , Figure 2 for a schematic diagram of a conventional bi-quadratic filter. When more hardware resources are available, a general choice for the filter 106 is to use a bi-quadratic filter to achieve infinite impulse response (IIR), which is a direct-form-2 bi-quadratic filter as shown in Figure 2 . The direct-form-2 bi-quadratic filter as shown in Figure 2 is capable of more complex control than a scaler or a single register filter. This form of bi-quadratic filter requires 7 registers: 2 for states (e.g., z-1), 5 for coefficients (a1, a2, b1, b2, b3), and 9 calculation steps per signal period: 5 multiplications and 4 additions. In this way, the bi-quadratic filter has the benefit of having higher circuit complexity than a scaler or a single register filter.

[0112] If filter 106 is a biquad filter, then the computation of 5 multiplications and 4 additions needs to be done in a fraction of the switching period of every 3.072 MHz. To simplify the computation requirement, the biquad filter can be chosen such that the multiplications corresponding to coefficients b1, b2, b3 are reduced to be implemented by bit-wise shift operations. For example, in a system with a sampling rate of 3.072 Msps, for a 2nd order low-pass-filter (LPF2) with Q = 0.707, if the cut-off frequency fc= 196,647.43 Hz, the values of b1, b2, b3 are 0.03125, 0.0625, 0.03125, which are equivalent to right shifts of 5 bits, 4 bits, 5 bits, respectively; if fc= 131,964.5 Hz, the 2nd order low-pass-filter with Q = 0.841 has values of b1, b2, b3 which are equivalent to right shifts of 6 bits, 5 bits, 6 bits, respectively; if fc= 91,203.5 Hz, the 2nd order low-pass-filter with Q = 0.841 has values of b1, b2, b3 which are equivalent to right shifts of 7 bits, 6 bits, 7 bits, respectively; if fc= 63,915.6 Hz, the 2nd order low-pass-filter with Q = 0.707 has values of b1, b2, b3 which are equivalent to right shifts of 8 bits, 7 bits, 8 bits, and so on. Thus, by choosing fcappropriately, as shown in the above examples, the computation of the biquad filter can be greatly simplified. It is noted that this technique is applicable to filter 106 as well as up-sampling filter 102.

[0113] In the above embodiments, the dynamic range of differential amplifier 108 and analog-to-digital converter 107 matches the dynamic range of feedback signal FB1 (i.e. the voltage across load 13). For example, if the dynamic range of feedback signal FB1 is 31 V, i.e. max(FB1) - min(FB1) = 31 V, then the dynamic range of differential amplifier 108 and analog-to-digital converter 107 will also be 31 V. However, in normal music listening, it is likely that only a small fraction of the full dynamic range will be utilized. In this case, it would be beneficial to adjust the input dynamic range of differential amplifier 108 and analog-to-digital converter 107 accordingly and to enhance the resolution of the overall system.

[0114] Please refer to Figure 1 where a scaling control signal k is the power of the scaling factor, e.g. k = 2 if the scaling factor is 4, or k = 3 if the scaling factor is 8. When k ≠ 0, differential amplifier 108 will increase the signal gain by a factor of 2 k (i.e. the dynamic range will be reduced by a factor of 2 k ). By adjusting the dynamic range of analog-to-digital converter 107 as discussed above, the resolution of driver circuit 10 is improved (e.g. increased) by 2 bits when k = 2, or by 3 bits when k = 3.

[0115] The scaling control signal k can be generated by the control circuit 103 in real time by monitoring the current value of the up-sampled input signal IN^. For example, in a two-state implementation with k = {0, 2}, k = 2 when the current value of the up-sampled input signal IN^ is less than one quarter of the maximum value of the up-sampled input signal IN^; otherwise, k = 0.

[0116] Alternatively, k can be controlled by an application processor (AP) through a system bus, and the application processor can determine the value of k by the user's volume setting, by pre-scanning the music file, etc. to adjust the dynamic range of the analog-to-digital converter 107.

[0117] A unit voltage change (e.g. ΔV) of one level is applied in each non-idle switching cycle, and the unit voltage change ΔV depends on the voltage range (e.g. 31V peak-to-peak or 22V peak-to-peak) of the swing of the feedback signal FB1 (i.e. related to the load 13 across voltage), the upper limit of the frequency of the peak-to-peak voltage swing, and the resolution of the analog-to-digital converter 107. For example, please refer to the following Table 1, column 3, where the peak-to-peak swing Vp-p is 31V, the target full swing frequency ffull-swing is 4.732KHz, and the direct current-to-direct current switching rate fswtching is 3.072MHz, under these requirements, the maximum slew rate (or ΔV) per switching cycle can be calculated as 31 x 4.732K x π / 3.072M = 150mV. Since 31V / 150mV = 207, the ΔV per switching cycle of 150mV corresponds to a resolution per switching cycle of 7.7bps, which, after the auto-ΣΔ effect of the driving circuit 10, will increase to 13.7 bits relative to the 48Ksps sampling rate.

[0118] Table 1

[0119] Vp-p 31 31 31 31 f swtching MHz 3.072 3.072 3.072 3.072 f full-swing KHz 6.624 5.678 4.732 0.946 ΔV (mV) 210 180 150 30 Resolution 148 172 207 1033 bps / switching period 7.21 7.4 7.7 10.0 bps w / ∑Δ 13.2 13.4 13.7 16.0 48Ksps x 64 64 64 64

[0120] Upper frequency limit for peak-to-peak voltage swing: The frequency spectrum of human voice is generally below 5 kHz, while the frequency spectrum of some musical instruments can extend to 15 kHz. However, in either case, these high-pitch tones are always harmonics of some base note, which means that the amplitudes of these high-pitch tones are low and do not require a peak-to-peak voltage swing to produce. In view of this background, from the table of the above example, depending on the specific goal of the sound producing device (SPD), the designs corresponding to columns 1-3 (ΔV = 210-150 mV) would all be reasonable choices.

[0121] The energy stored in the perfect capacitor C can be expressed as Thus injected into or extracted from the load 13 at V L The energy produced by the change in ΔV can be expressed as:

[0122]

[0123] where C13(V L ) is the capacitance value of the load 13 at V L , which includes the change in dielectric constant due to the applied voltage. ΔE (Equation 1) is true for both the charging cycle and the discharging cycle, and represents the energy that needs to be transferred from the voltage source V S to the load 13 during the charging cycle or back to the voltage source V S from the load 13 during the discharging cycle.

[0124] On the other hand, the energy stored in the inductor can be expressed as: During the DC-to-DC switching cycle, the current produced in the inductor during the pulse width t PWM can be expressed as: where V m is the voltage across the inductor L. When V PWM is approximately constant (V m ≈ constant) during the pulse width t m , we have Substituting I into E L and simplifying terms, we have

[0125] Due to the principle of conservation of energy, the energy stored in the inductor L will be equal to the energy transferred into (during a charging cycle) or out of (during a discharging cycle) the capacitive load 13. In other words, E L = ΔE C13 is valid for both the charging cycle and the discharging cycle. Thus, we have which leads to

[0126] Although Formula 3 can be used for both charging and discharging cycles, it is not applicable to V. m The representation of V differs in charging and discharging circuits. For example, in circuit 10, V represents the charging circuit 12. m =V S For discharge circuit 14, Vm≈V L +ΔV / 2-V S Therefore, for an example of circuit 10: It can be used in circuit 12. It can be used in circuit 14.

[0127] The pulse width modulation control circuit 151 can determine the pulse width of the pulse width modulation signal S based on formula 3D, and determine the pulse width of the pulse width modulation signal SU based on formula 3C.

[0128] Please note the load voltage V during the discharge operation. L Very close to the power supply / source voltage V S At that time, the pulse width of the pulse width modulation signal SD used in the discharge circuit 14, as calculated by formula 3D, may be close to infinity. In other words, when the load voltage V L Very close power supply / source voltage V S During a switching cycle, V will be... L The goal of reducing the voltage by one unit (i.e., reducing a fixed ΔV) is not achievable for circuit 14. Therefore, a shunt circuit including switch S3 is added. When turned on by a control signal SD*, switch S3 creates a low-resistance path from load 13 to voltage source 11 (or from load 13 to ground in other embodiments) (i.e., forming another discharge current). Therefore, when t as in Equation 3D PWM The calculated pulse width T SW If the threshold is exceeded, a pulse of the control signal SD* is generated, and the pulse width of the control signal SD* varies with the pulse width T. SW The current increases as the control signal SD* initiates the current flow path through switch S3, and the discharge current of load 13 flows through both discharge circuit 14 and switch S3 to achieve a fixed ΔV in each switching cycle.

[0129] The above implementation applies a fixed ΔV in each switching cycle, therefore the resolution remains low even after the automatic ΣΔ effect (ranging from 13.2 bits to 13.7 bits in columns 1-3 of the table above). To improve the resolution of the drive circuit 10, a multi-level ΔV implementation is described below.

[0130] For a peak-to-peak swing Vp-p of 31 V and an ADC 107 of 10 bps, each step of the output of the ADC 107 corresponds to a voltage change of 31 V / (210-1) = 30 mV. If the fixed ΔV of each switching cycle is much larger than 30 mV (e.g., 120 mV), a phenomenon similar to ringing of an analog amplifier can occur, in which the output of the driving circuit 10 can jump between overshooting or undershooting, resulting in a jagged output waveform. Even though such roughness is mostly filtered out by the high signal-to-noise ratio and noise shaping characteristics of the ΔΣ operation, the total harmonic distortion can reach the audible band. However, such a phenomenon will cause an increase in power consumption, given that it occurs at high frequencies. On the other hand, if the fixed ΔV is significantly smaller than 30 mV (e.g., 10 mV), it will become difficult to increase the full voltage swing frequency f swing This is disastrous for high-fidelity (HiFi) audio amplifiers above 1 KHz.

[0131] Accordingly, the present embodiment includes a multi-ΔV system (i.e., a V L The fixed ΔV is changed by an integer multiple of a unit voltage change (e.g., ±n x ΔV) at each DC-DC switching cycle, where the step size of the ΔV is approximately the same as the resolution voltage level of the ADC 107 (e.g., 30 mV). With such a setup, the operations of the ADC 107, the charging circuit 12, and the discharging circuit 14 become well synchronized. For example, a multi-ΔV system with a range of -210 mV to +210 mV (step size of 30 mV), in conjunction with the auto-ΣΔ effect of the driving circuit 10, can operate with an ADC 107 of 10 bps to produce an equivalent resolution of 16 bps at the system level, while still satisfying the slew rate requirement of a peak-to-peak swing Vp-p of 31 V to 6.6 KHz as shown in Table 1, which can satisfy most audio enthusiasts.

[0132] In such a multi-ΔV system, the control circuit 103 can calculate the difference DLT act between the up-sampled input signal IN^ and the filtered digital feedback signal FB* to obtain a step-size number NSTP. That is, the step-size number NSTP is determined according to the actual difference DLT act between the up-sampled input signal IN^ and the filtered digital feedback signal FB*. For example, for a unit step size ΔV of 30 mV, in each non-idle switching cycle, the difference DLT act (e.g., the actual difference DLT indThis can correspond to NSTP values ​​in step sizes from 1 to 7, to adjust the voltage V. L By changing ±ΔV to ±7×ΔV, the expected difference DLT can be set in each non-idle switching cycle. ind The upper limit of its magnitude is no greater than 210mV. Expected difference DLT ind This can represent the voltage V when the charging circuit 12 performs a charging operation during the charging switching cycle. L The increment, or the voltage V when the discharge circuit 14 performs a discharge operation during the discharge switching cycle. L The decrease (decrease) in voltage V. L This indicates the load voltage (across) load 13 or the output voltage of load 13.

[0133] Control circuit 103 can determine the expected voltage difference DLT ind For DLT ind =NTSP × ΔV. From another perspective, once a given unit voltage change ΔV is fixed or constant, the expected voltage difference DLT is determined. ind And the determination of the step size value is equivalent to NSTP, which means that DLT ind Both NSTP and DLT are based on the actual difference. act That's for you to decide.

[0134] when Figure 1 When the system is functioning well, the signal-to-noise ratio is generally >50dB, and the measured V L The deviation from its ideal value is typically <1%. In this case, the actual V L The value can be estimated by G×IN^, where G is the gain, which means that Equations 3C and 3D can be obtained by replacing V. L The calculation is performed using G×IN^. Therefore, the pulse width modulation pulse width t required for charging (Equation 3C) and discharging (Equation 3D) is... PWM (For any combination of IN^ and NSTP) can be pre-calculated, encoded into pulse width control codes, and stored as addresses in a discharge pulse width lookup table and a charge pulse width lookup table using the corresponding IN^ and NSTP (denoted as (IN^, NSTP)). Note that the values ​​stored in the lookup tables are not the actual pulse width modulation pulse widths, but rather the control codes used to generate the required pulse width modulation pulses.

[0135] When this table is looked up (using a specific set of (IN^, NSTP) as addresses), for a specific combination of IN^ and NSTP, an entry corresponding to or representing a pre-calculated pulse width control code is retrieved, and this pulse width control code can be used to generate pulse width modulation pulses with a pulse width t.PWM The correct amount of current I will be generated ch (or I dis ) to generate the required energy injection (or the required energy extraction) according to equation 3C (or equation 3D) such that the load 13 sees a voltage V L NSTP x AV (or -NSTP x AV) is changed.

[0136] Therefore, in each switching cycle, corresponding to one period of the clock signal CK1, the values of the state control signal STA and the step value NSTP calculated by the control circuit 103 are combined with the value of the up-sampled input signal IN^ into an address (STA, IN^, NSTP) to select and access the contents of the discharge pulse width lookup table and the charge pulse width lookup table, and to retrieve a pre-computed control code to be used by the pulse width modulation control circuit 151 to generate the pulse width modulation signals SD, SU with corresponding pulse widths.

[0137] Please refer to Figure 3 , Figure 3 is a schematic diagram of the pulse width modulation control circuit 151 of the embodiment of the present application. As Figure 3As shown, the pulse width modulation control circuit 151 (or equivalently, the pulse width modulation controller 16) includes a memory 203, a digital-to-analog converter (DAC) 205, a comparator 206, a sawtooth waveform generator 204, and a multiplexor 208. The pulse width modulation control circuit 151 generates the pulse width modulation signals SU and SD by charging pulse width lookup table 201 and discharging pulse width lookup table 202, which are stored in the memory 203. The control signal SD* is generated in a similar manner and is omitted for brevity. The control circuit 103 calculates the state control signal STA to select a suitable one of the charging pulse width lookup table 201 (when STA = CHARGE) and the discharging pulse width lookup table 202 (when STA = DISCHARGE). A particular entry corresponding to a particular discharging pulse width or a particular charging pulse width can be selected using the up-sampled input signal IN^ and the step value NSTP as an address. The selected / particular entry (i.e., a pulse width control code) can be 6-bit to 10-bit wide, which is converted by the digital-to-analog converter 205 into a particular analog voltage level. The comparator 206 compares the particular analog voltage with a sawtooth pulse output by the one-shot sawtooth waveform generator 204 to generate a pulse whose width is determined by the intersection between the sawtooth waveform and the particular analog voltage. When the state control signal STA does not indicate an idle operation (i.e., STA ≠ IDLE), the sawtooth waveform generator 204 generates a sawtooth pulse during each switching period. Note that the sawtooth pulse can optionally have a flat tip whose width corresponds to a pre-set minimum pulse width. The pulse generated by the comparator 206 is output as the pulse width modulation signal SU or the pulse width modulation signal SD by the multiplexor 208 depending on whether the state control signal STA indicates a charging operation or a discharging operation (i.e., STA = CHARGE?).

[0138] In this application, the waveform of the sawtooth-like pulse with or without a flat tip is named as a sawtooth-like waveform. In Figure 4 、 6 , the curve of reference numeral 204 illustrates the sawtooth-like waveform with a flat tip. Modifications or changes can be made by those skilled in the art without being limited thereto.

[0139] Note that, Figure 3 the positive polarity of the sawtooth pulse and the pulse width modulation pulse is for illustration only and can be negative polarity in other embodiments. Furthermore, besides theFigure 3 The pulse SU or SD can also be generated using digital counters and digital comparators, in addition to the analog-to-digital converter and comparator of 151 (as just one alternative to generating the pulse SU or SD). Thus, the concepts disclosed herein are not limited to the details shown. Figure 3

[0140] To minimize the latency between latching the input of the digital-to-analog converter 205 and the start of the sawtooth waveform generator 204, the output of the digital-to-analog converter 205 can be pre-set to a certain value when the control circuit 103 is calculating the state control signal STA and the step value NSTP, so that the output of the digital-to-analog converter 205 is close to the starting voltage level of the sawtooth pulse.

[0141] For example, refer to Figure 4 , Figure 4 is a timing diagram of the operation of the pulse width modulation control circuit 151 of the present embodiment. As shown in Figure 4 , for an input of 0x3f (which is the maximum input value for a 6-bit input (or entry), which corresponds to the maximum discharge pulse width or the maximum charge pulse width), the output of the digital-to-analog converter 205 can correspond to a voltage level slightly above 0V, while for an input of 0x00 (the minimum input value), the output of the digital-to-analog converter 205 can correspond to a voltage level slightly below the flat tip portion of the sawtooth waveform generated by the sawtooth waveform generator 204. In Figure 4 , each CK1 cycle corresponds to 16 cycles of CK0 as shown by the vertical dashed lines. In the first 7 clock signal CK0 cycles of a cycle CY t , the digital-to-analog converter 205 can be in a pre-set state (to be discussed later), so that the output of the digital-to-analog converter 205 settles at 0V. Then, at the rising edge of the 8th clock signal CK0 (cycle) of the cycle CY t , the output of the charge pulse width lookup table 201 or the discharge pulse width lookup table 202 is latched by the digital-to-analog converter 205, and the output of the digital-to-analog converter 205 will have 1 clock signal CK0 cycle to settle before the sawtooth pulse generated by the sawtooth waveform generator 204 starts to rise. Note that for large signal transitions of the digital-to-analog converter 205 (such as the output swing when the input to the digital-to-analog converter is 0x30), the relevant voltage level of the sawtooth pulse will reach 6 clock signal CK0 cycles after the sawtooth pulse starts, and a low-power digital-to-analog converter circuit can be used as the digital-to-analog converter 205.

[0142] ​The resolution of the up-sampled input signal IN^ is significantly higher (up to 18 bits in the above example) than necessary. Therefore, the 8 most significant bits (MSB) of the up-sampled input signal IN^ (including the sign bit) are used as the address (as IN^[19:12] in the above example) to the charge pulse width look-up table 201 and the discharge pulse width look-up table 202, which yields a per-entry ΔV resolution of 31V / 256 = 121 mV per table, and should be sufficiently fine in most cases. Figure 3

[0143] With the charge pulse width look-up table 201 and the discharge pulse width look-up table 202, the drive circuit 10 can be viewed as a collection of 28 = 256 direct current to direct current converters, each optimized to generate the required voltage change nΔV corresponding to the step value NSTP within a strict specified range of V L In essence, by addressing the charge pulse width look-up table 201 and the discharge pulse width look-up table 202 with the address (STA, IN^, NSTP), a pre-optimized direct current to direct current converter is developed (for the charge circuit 12 or the discharge circuit 14). The task of this dedicated direct current to direct current converter is to generate the pre-optimized pulse width modulated pulse according to equation 3C and equation 3D, and to generate the required voltage change nΔV of V L according to the step value NSTP.

[0144] From a system point of view, the elements (201-208) of the system 10, the charge circuit 12 or the discharge circuit 14 combine to form a system in which the step value NSTP is mapped to a linearized voltage change nΔV (with a well-defined unit step ΔV). In other words, the charge pulse width look-up table 201 and the discharge pulse width look-up table 202 can be viewed as a collection of pre-distortion filters, in which the voltage dependence of V 13 (V PZT ), the combination non-linearity of the digital to analog converter 205, the comparator 206, the charge circuit 12 and the discharge circuit 14, the difference between equation 3C and equation 3D due to V m and so on, are incorporated into a full dynamic range, which is then piecewise linearized by subdividing the full dynamic range of V L into a collection of narrow ΔV L , and then filling in a pre-computed set of pulse widths for these ΔV L ​each of the sub-divisions (columns of the look-up table, corresponding to NSTP) such that the drive circuit 10 produces a resulting voltage change nΔV linearly related to the step number value NSTP at the load capacitor of the load 13.

[0145] Note that, Figure 3 The address of the charge pulse width look-up table 201 and the discharge pulse width look-up table 202 shown is (IN^[19:12], NSTP), which is the most flexible and direct way to encompass any kind of relationship of the up-sampled input signal IN^ and the step number value NSTP.

[0146] A conventional digital-to-analog converter receives a continuously varying input signal, and the output of the conventional digital-to-analog converter needs to produce a continuously analog signal to correspond to the input, and one of the key parameters of the conventional digital-to-analog converter is the time it takes for its output to settle between two successive input value changes (i.e. settling time). In other words, for each conversion period in the conventional digital-to-analog converter, the starting point (of both the input digital code and the output voltage level) can be anywhere within the specification of the conventional digital-to-analog converter, while the ending point can also be anywhere else within the specification of the conventional digital-to-analog converter, and the output of the conventional digital-to-analog converter needs to be able to convert from the starting voltage level to the ending voltage level within the period time. As Figure 4 The timing diagram shown in conjunction with the related discussion, these operating conditions do not need to restrict the implementation of the digital-to-analog converter 205, the ramp of the sawtooth waveform can start before the large amplitude swing of the digital-to-analog converter output is settled.

[0147] However, referring to Figure 5 , Figure 5 is a schematic of the pulse width modulation control circuit 155 of the embodiment one. When the pulse width modulation pulse width (or pulse width control code) T SW The up-sampled input signal IN^ for a given value of NSTP can be expressed as T SW = A x NSTP + B, then a table of 28 x NSTP entries can be simplified to a table of 28 x 2 entries (A and B are 2), and a particular entry for the input of the digital-to-analog converter 205 can be extracted by addition and multiplication: A x NSTP + B. Even though the size of the charge pulse width look-up table 201 and the discharge pulse width look-up table 202 is reduced, the complexity of generating the input of the digital-to-analog converter 205 will be increased. In addition, although Figure 3 The schematic of 151 can handle any relationship with respect to NSTP, Figure 5 The schematic of 155 can only handle the case of the pulse width modulation pulse width t PWM linearly related to NSTP.

[0148] Another way to minimize the size of the charge pulse width lookup table 201 and the discharge pulse width lookup table 202 is to examine the table entries, identify entries with the same output, replace these entries with a common entry, and then optimize the resulting address-content mapping using techniques such as logic minimization.

[0149] In the above embodiment, there is a 1-to-1 relationship between the ADC cycle and the DC-DC switching cycle. In other embodiments, one ADC cycle of the ADC 107 can correspond to multiple switching cycles.

[0150] Referring to Figure 6 , Figure 6 is another timing diagram for the pulse width modulation control circuit 151 of an embodiment. As shown in Figure 6 , the ADC 107 samples its input at the lower thick arrow (input) and completes the ADC at the upper thick arrow (output). The FB is generated at the falling edge of the 14th CK0 between the cycles CY t-2 &CY t-1 , CY t &CY t+1 , and CY t+2 &CY t+3 , and the step value NSTP and the state control signal STA are generated in the next eight cycles of the clock signal CK0, which will be used for two DC-DC switching cycles for each sample of the ADC 107.

[0151] In an embodiment, the controller 103 can perform linear interpolation between two table entries from the charge pulse width lookup table 201 or the discharge pulse width lookup table 202 to achieve a finer resolution of ΔV than the pre-computed steps. For example, from one DC-DC switching cycle according to a table entry corresponding to ΔV = 120 mV and from three DC-DC switching cycles according to a table entry corresponding to ΔV = 90 mV, the table entry for a voltage change ΔV of 97.5 mV of the output V L can be obtained, i.e., using Look_up(120 mV) + 3 x Look_up(90 mV) + 2) / 4 instead of Look_up(97.5 mV). The implementation of linear interpolation is more economical than scaling up the resolution of the circuit 12 and the circuit 14 by four times and expanding the charge pulse width lookup table 201 and the discharge pulse width lookup table 202 by four times.

[0152] Referring to Figure 7 , Figure 7 is another timing diagram for the pulse width modulation control circuit 151 of an embodiment. As shown in Figure 7As shown, the step size value NSTP and the state control signal STA calculated from each sample of the analog-to-digital converter 107 are applied to four DC-to-DC switching cycles, rather than the two DC-to-DC switching cycles as Figure 6 shown. Therefore, compared to the embodiment based on Figure 6 shown, the embodiment based on Figure 7 shown will cut the power consumption of the analog-to-digital converter 107, the charge pulse width look-up table 201, the discharge pulse width look-up table 202, and the digital-to-analog converter 205 in half at the cost of losing 1 / 2 of the output resolution level. The system designer can choose between Figure 6 and Figure 7 depending on the priority requirements of each design. Alternatively, the control circuit 103 can configure a dynamic switch between Figure 6 [[ID=1​​​​​​​​​​​​​​​​​​Figure 4 The timing relationship between the blocks in the drive circuit 10. It should be noted that the sampling in the analog-to-digital converter 107 is held within the period CY. t The sampled signal will be in period CY t+1 Generate current I ch / I dis The corresponding changes at both ends of the load 13 will be sampled in the analog-to-digital converter 107 and maintained during the period CY. t+2 Sampling. This means there is a 1-switching-cycle delay between these signals. Please also refer to... Figure 6 and Figure 7 This process may involve a delay exceeding one switching cycle. Such a delay, if overlooked, can lead to oscillations and therefore requires careful handling. Filter 106 manages this instability to achieve highly stable operation and a high signal-to-noise ratio.

[0155] It should be noted that in the above embodiments, a pulse width modulation controller 16 is used in the drive circuit 10 having a charging circuit 12 (as a boost converter) and a discharging circuit 14 (as a buck converter). In other embodiments, the pulse width modulation controller 16 may be applied to drive circuits with other charging and discharging circuit configurations (e.g., other circuit configurations of U.S. Application No. 17 / 022,106 or a 4-transistor bidirectional circuit capable of forming charging and discharging currents with different control signals).

[0156] From a broader perspective, the central concept of this application is about using mapping tables such as 201 and 202 to map any system (such as...) Figure 1 The input and output values ​​of the voltage amplifier 10) are subdivided into multiple small regions (e.g., Figure 3 The region corresponding to IN^[19:12] is 256), and then the system behavior within each small input-output mapping region is modeled using a set of pre-calculated output value control signals (e.g., by...). Figure 3 The NSTP addressing corresponds to multiple entries in each IN^[19:12]. Note that the application of this general scheme is not limited: it is not limited to system 10, not limited to charge and discharge operations, not limited to voltage output systems, and certainly not limited to any embodiment details such as 256 subdivisions.

[0157] On the other hand, when the output V of the charging circuit 12 L Very close to 0V (see Formula 3C) or the output V of discharge circuit 14 L Higher than V S In many cases (see Formula 3D), the pulse width modulation width TSW (i.e., t in formulas 3C and 3D) PWM The pulse width modulation (PWM) pulse width T can become very narrow and requires extremely precise control. To achieve this fine control, the PWM pulse width T... SW A high-resolution digital-to-analog converter (e.g., 12 or 14 bps) might be needed to implement the digital-to-analog converter 205. However, such fine resolution is only required when the pulse width is very narrow, thus corresponding to the output k. v An exponential digital-to-analog converter would be a more efficient implementation of the digital-to-analog converter 205. For example, 2 12 The range can be encoded using 1.1411463, where k = 1.14114 and v = 0 to 63. Therefore, this application uses 6 bits to represent the range that needs to be close to 2. 12 The range of linear codes is linearly represented, thus reducing the complexity of the digital-to-analog converter circuit by 2. (12-6) ≈64 times.

[0158] Please refer to Figure 8 and Figure 9 . Figure 8 This is a schematic diagram of the digital-to-analog converter 205 according to an embodiment of this application. Figure 9 This is an embodiment of the present application. Figure 8 The timing diagram of the digital-to-analog converter 205 is shown. Figure 8 As shown, the digital-to-analog converter 205 includes multiple reference modules M0 to M63, a pre-charge switch SC, an output capacitor CS, a common switch ST, and a discharge switch SP. The reference modules M0 to M63 are connected in parallel, and each reference module Mn includes a reference capacitor Cn and a reference resistor Rn connected in series.

[0159] The output capacitor CS includes a first terminal coupled to ground and a second terminal for outputting a specific analog voltage VA. A discharge switch SP is coupled between the first and second terminals of the output capacitor CS. A pre-charge switch SC includes a first terminal coupled to a reference voltage VREF and a second terminal. In an embodiment, reference switches S0-S63 include multiple first terminals connected to the second terminals of the pre-charge switch SC, and multiple second terminals. Reference capacitors C0-C63 include multiple first terminals individually coupled to the second terminals of their respective switches S0-S63, and multiple second terminals coupled to ground. A charge redistribution / shared switch ST is coupled between the first terminal of the output capacitor CS and the first terminals of the reference capacitors C0-C63.

[0160] In this structure, the digital-to-analog converter 205 can utilize a charge redistribution scheme to perform digital-to-analog conversion on specific entries (control codes) to generate a specific analog voltage VA. More specifically, as...Figure 8 and Figure 9 As shown in FIG. 6, in a pre-stage (denoted as time period TO), the discharge switch SP, the pre-charge switch SC and the reference switches S0-S63 are turned on (logic 1) while the charge redistribution switch ST is turned off (logic 0) to discharge the output capacitor CS (to bring the voltage across the output capacitor CS to 0V) and to pre-charge the reference capacitors C0-C63 (to bring the voltage across the reference capacitors C0-C63 to the reference voltage VREF). At the end of the pre-stage, a subset of the discharge switch SP, the pre-charge switch SC and the reference switches S0-S63 (which are not selected by the particular entry) are first turned on. After a short instant (sufficient to avoid direct current flow through VREF -> SC -> ST -> SP -> ground), the conversion stage (denoted as time period Tl) is started by turning on the charge redistribution / shared switch ST so that current starts to flow from the subset of the reference capacitors C0-C63 (selected by the particular entry to remain connected to the charge redistribution switch ST via the corresponding reference switches S0-S63) to charge the output capacitor CS to produce the particular analog voltage VA.

[0161] In addition, the digital-to-analog converter 205 further comprises a decoding circuit 24. The decoding circuit 24 is configured to receive the pulse width control code obtained by the pulse width modulation control circuit 151 / 155 (or equivalently by the pulse width modulation controller 16) and to perform a decoding operation according to the pulse width control code to generate a plurality of control signals S0-S63 to control the plurality of reference switches S0-S63. The decoding operation can be thermometer decoding, binary decoding or 1-hot decoding, etc. Figure 8 and Figure 9 In the above equations, SP, ST and S0-S63 represent not only the switches but also the corresponding switch control signals.

[0162] In the first embodiment of the digital-to-analog converter circuit 205, the reference capacitance values of the reference capacitors C0-C63 and the output capacitor CS are configured in an exponential order Cn = 12fF x 1.167n n , n = 0-63, CS = C63, and in the conversion stage, only one of the reference switches S0-S63 is turned on, i.e. 1-hot decoder. In the conversion stage, when the charge redistribution switch ST is turned on, the voltage at which the particular analog voltage VA is stabilized can be calculated as so that the particular analog voltage VA can have a voltage level between VREF / 2 (when n = 63) and slightly above the ground potential (when n = 0) depending on the digital value of the particular entry. In this way, for the charging circuit 12 when V L → 0V, the voltage variation +ΔV, or for the discharging circuit 14 when V L >> VS The voltage change - ΔV, the digital-to-analog converter 205 can precisely control the pulse width T SW .

[0163] In an alternative embodiment B of the digital-to-analog converter circuit 205, C0= 12 Ff, and for n = 1-63, Cn= 12 fF x (1.167 n -1.167 n-1 The (a plurality of sequentially added reference capacitance values are exponential order ), and the reference switches S0-S63 can be controlled by a thermometer decoder, i.e. at the end of the reset phase, when the discharge switch SP goes from a logic high level to a low level, the reference switches Sn+1-S63 are turned off, while the reference switches S0-Sn remain turned on, and (i.e. the total reference capacitance value of the plurality of reference capacitance values). Thus, embodiment B has the same voltage level for the n- dependent analog voltage VAas the previous embodiment A.

[0164] Embodiment B has the advantage of requiring less total capacitance values than embodiment A, since capacitance values consume silicon, it is obviously more advantageous to employ embodiment B. However, for small n, the capacitance values of the reference capacitors Cnmay be very small in embodiment B. For example, for C1= 12 fF x (1.167 - 1.1670) = 2 fF, this is very small, and in a single chip implementation, the actual capacitance values can easily have a large fluctuation ratio from chip to chip. Thus, a hybrid between embodiment A and embodiment B can be employed to implement embodiment C, i.e. for n < m, Cnis implemented as a single hot scheme, and for n > m, Cnis implemented as a thermometer code.

[0165] For example, in embodiment C assuming m = 13, the corresponding capacitance value for the reference capacitor C13under the thermometer code is C13= 12 fF x (1.16713- 1.16712) = 12.786 fF, i.e. with embodiment C using the hybrid encoding scheme, the smallest capacitance value will be C0= 12 fF. That is, the reference capacitance values of the reference capacitors C0-C12and the reference capacitance value of (the sequentially added reference capacitance values of the reference capacitors C13-C63) are exponential order, and the output capacitance value of the output capacitor CSis equal to the total reference capacitance value of the plurality of second reference capacitance values. Thus, embodiment C sets an upper limit to the size fluctuation of the capacitance values of the reference capacitors Cn, and reduces the total capacitance values required.

[0166] In another embodiment D of the digital-to-analog converter circuit 205, the reference capacitance values of the reference capacitors C0-C63may all be equal to 12 fF (which implies that the reference capacitance values of the reference capacitors C0-C63are the same or substantially the same), and the capacitance value of CSis When the reference switches Encoded / decoded using binary numbers or thermometer codes, the VA generated for use in control code n can be represented as: Note that the change in VA is non-linear and decreases as n increases. For example, for n = 0 → 1, ΔVA0 → 1 = VA1 – VA0 = 2 / 10 - 1 / 9 ≈ 0.088889 × VREF, and for n = 62 → 63, ΔVA 62→63 =VA 63 –VA 62 =64 / 72-63 / 71≈0.001565×VREF and the ratio ΔVA 0→1 : In other words, for pulse width modulation of n=62→n=63, the pulse width T SW The increment is 56.8, compared to the pulse width T of the pulse width modulation for n=0→n=1. SW The incremental refinement is achieved by replacing the upward-swinging sawtooth ramp. Figure 9 As shown, the downward swing ramp, and by replacing n with n' = 63-n, the digital-to-analog converter 205 based on embodiment D can generate a series of pulses with fine step widths T when n' is small. SW The quasi-exponential pulse width modulation pulse is suitable for controlling the charging circuit 12 or the discharging circuit 14.

[0167] In other words, in one embodiment, the reference capacitance values ​​of reference capacitors C0 to C63 are the same. Reference switches S0 to S63 are controlled by a control signal, and the control signal corresponds to or is generated based on a control code (e.g., a pulse width control code). In one embodiment, the control signal for reference switches S0 to S63 can be generated by the decoding circuit 24 based on the (pulse width) control code.

[0168] The digital-to-analog converter 205 converts the (pulse width) control code to an analog voltage VA. Unlike conventional digital-to-analog converters in the art, in this application, the analog difference ΔVA increases as n increases. n =ΔVA (n-1)→n =VA n –VA n-1 It can increase or decrease monotonically. Here, n can represent the (numerical) value represented by the corresponding control code or the control code itself. (n-1) represents the value of the control codes consecutive to control code n or the control codes themselves. ΔVA n Does it increase with increasing n or ΔVA? nIt decreases as n increases, depending on the decoding operation or how the decoding circuit 24 generates the control signal. As long as VA... n It has a monotonic (increasing or decreasing) relationship with the control code value n, which satisfies the requirements of this application.

[0169] In addition, the equivalent capacitance value C of reference modules M0 to M63 eq It can have a monotonically increasing (increasing or decreasing) relationship with the control code value n. Furthermore, assuming K represents the number of reference switches turned on corresponding to control code n during the transition phase, the number K can have a monotonically increasing (increasing or decreasing) relationship with the control code value n, especially when all reference capacitance values ​​are the same. Therefore, with the equivalent capacitance value C... eq Increase the simulated difference ΔVA n It can increase or decrease monotonically, or, as the quantity K increases, the simulated difference ΔVA n It can increase or decrease monotonically.

[0170] Furthermore, the analog voltage VA has a non-linear relationship with the control code value n. The degree of non-linearity indicates (from one perspective) that the analog voltage VA generated by the digital-to-analog converter 205 has a VA... n+k ≠VA n +VA k The attributes of VA n / k This represents the analog voltage corresponding to the control code n / k.

[0171] After the digital-to-analog converter 205 generates a specific analog voltage VA, the specific analog voltage VA is compared with the sawtooth pulses generated by the sawtooth waveform generator 204. For example... Figure 9 As shown ( Figure 9 and Figure 3 The sawtooth pulse shown is positive and slopes towards VREF / 2 or VREF. In other embodiments, the sawtooth pulse may be negative and slope towards ground (with corresponding modifications to the operation). The time period T1 exists between the start of the conversion phase of the digital-to-analog converter and the start of the ramp of the sawtooth pulse generated by the sawtooth waveform generator 204. The time period T1 allows current to flow through the common switch ST to stabilize before the sawtooth pulse ramp begins. The time period T1 is determined by the Ron values ​​of the charge redistribution switch ST and switch S0, the reference capacitor C0, and the output capacitor CS.

[0172] Compared to conventional digital-to-analog converters with R-2R structures, the capacitance value Cgs associated with the common switch ST can almost always be greater than that of conventional converters. The power consumption of the time period T1 is essentially independent of the overall power consumption of the digital-to-analog converter 205, which is 100 times smaller. It is mainly determined by the power consumption of the output capacitor CS and the reference capacitors C0 to C63, with its upper limit being C63 × VREF in embodiment A. 2 ×f In Example B,

[0173] In a pre-stage (time period TO) of a cycle TC, the reference capacitors CO-C63 can be pre-charged to the reference voltage VREF and the output capacitor CS is pre-discharged. In a subsequent conversion stage, some of the reference capacitors CO-C63 can be partially discharged via connection to the output capacitor CS. Note that for a capacitor Ci that is not connected to the output capacitor CS in the conversion stage (i.e., the corresponding reference switch Si is off), the charge is maintained to the next cycle TC and thus no power is consumed. Only a capacitor Cj that is connected to the output capacitor CS in the cycle TC will be recharged to replenish the charge transferred to CS during the conversion stage. In other words, based on the input code of a particular entry, the power consumption of each cycle TC is automatically minimized and the smaller the particular analog voltage VA, the smaller the power consumption of the cycle TC.

[0174] Note that the relationship between the sawtooth pulses generated by the sawtooth generator 204 and the reference capacitors CO-C63, and Figure 8 and Figure 9 The pre-discharge of the output capacitor CS shown, only the operation of the digital-to-analog converter 205 and the pulse width modulation control circuit 151 are depicted, other combinations can be utilized to achieve similar results, and all such variations are within the scope of the present application.

[0175] The topology of the bidirectional circuit is not limited to Figure 1 As shown, other bidirectional circuits such as Figure 10 A 4-transistor (4T) circuit disclosed in U.S. Patent Application No. 17 / 352,346. Figure 10 A drive circuit A0 including a pulse width modulation controller 16 and a bidirectional circuit A24 is shown, which is capable of forming a charging current I ch from the voltage source 11 to the load 13 and a discharging current I dis from the load 13 back to the voltage source 11. Furthermore, for a bidirectional circuit A24 sourced from a buck-boost converter, the limitation of V L > V S does not apply, and various schemes are described in the application No. 17 / 352,346 to allow the voltage level of V L to be higher, lower, or to cross the voltage level of V S as long as the pulse width modulation controller 16 adaptively generates the pulse width modulation control signals SP1-SP4, which are applicable to control the 4-transistor circuit of the application No. 17 / 352,346. Such modifications are obvious to those skilled in the art of electronic design, and are omitted here for brevity.

[0176] In summary, the operation of the drive circuit of the present application can be summarized as a flow B0. The flow B0 includes the following steps. Figure 11

[0177] Step B02: receiving an input signal and a feedback signal from a load.

[0178] Step B04: generating a plurality of pulse width modulation signals according to the input signal and the feedback signal.

[0179] Step B06: driving the load with the bidirectional circuit according to the plurality of pulse width modulation signals, such that the input signal and the feedback signal are substantially proportional (e.g., directly proportional) to each other, wherein the input signal is a time-varying signal.

[0180] The details of the step B02 can be shown as a flow C0. The flow C0 includes the following steps. Figure 12

[0181] Step C02: determining a difference according to the input signal and the feedback signal.

[0182] Step C04: generating a pulse width modulation signal with a pulse width, wherein the pulse width is determined according to the difference.

[0183] As discussed above, the pulse width can be obtained via retrieving a look-up table stored in a memory, but is not limited thereto. The pulse width can be obtained via on-line calculation, Simulation Program with Integrated Circuit Emphasis (SPICE) simulation, calibration, or physical measurement, which are also within the scope of the present application.

[0184] The details of the flows B0 and C0 can be referred to the above paragraphs, and are not repeated here for brevity.

[0185] In summary, the present application determines each switching period to be a charging period, a discharging period, or idle according to the difference between the input signal and the feedback signal in the digital domain, and determines the charging pulse in the charging period or the discharging pulse in the discharging period according to the pre-calculated charging / discharging pulse width control code look-up table. In addition, in order to approach 0 for the voltage change ΔV in the charging or to approach the maximum value for the voltage change ΔV in the discharging, the circuit configuration of the digital-to-analog converter of the present application can finely control the pulse width.

[0186] The above descriptions are only the preferred embodiments of the present application, and any equivalent changes and modifications made within the scope of the present application should be covered by the present application.​​

Claims

1. A digital-to-analog converter, characterized by, The D / A converter comprises: a plurality of reference modules, each of which comprises a reference capacitor and a reference switch, the plurality of reference modules being connected in parallel to each other, the reference capacitor and the reference switch being connected in series to each other; an output capacitor for outputting an analog voltage; and a common switch coupled between the output capacitor and the plurality of reference modules; wherein the plurality of reference capacitors have substantially the same reference capacitance value; wherein the plurality of reference switches are controlled by a plurality of control signals, and the plurality of control signals correspond to a control code; wherein the D / A converter generates the analog voltage according to the control code; wherein a first analog voltage corresponding to a first control code and a second analog voltage corresponding to a second control code have an analog difference value, the first control code corresponds to a first value, and the analog difference value monotonically increases or monotonically decreases as the first value increases; wherein the first control code and the second control code are consecutive. The analog difference value monotonically increases or monotonically decreases as a first number increases; 2. The digital-to-analog converter of claim 1, wherein, The first number represents the number of the reference switches turned on in a first stage corresponding to the first control code; The common switch is turned on in the first stage. The D / A converter converts the control code into the analog voltage, and the analog voltage and the value corresponding to the control code have a non-linear relationship.

3. The digital-to-analog converter of claim 1, wherein, The D / A converter comprises a decoding circuit for performing a decoding operation to generate the plurality of control signals to control the plurality of reference switches.

4. The digital-to-analog converter of claim 1, wherein, The decoding operation comprises a thermometer decoding operation or a binary decoding operation.

5. The digital-to-analog converter of claim 4, wherein, The D / A converter comprises:

6. The digital-to-analog converter of claim 1, wherein, a pre-charge switch coupled to the plurality of reference modules; and a discharge switch coupled between two ends of the output capacitor; wherein the pre-charge switch and the discharge switch are turned off in a first stage in which the common switch is turned on; wherein the pre-charge switch and the discharge switch are turned on in a second stage in which the common switch is turned off. In the first stage, a first number of the reference switches are turned on, and a second number of the reference switches are turned off. In the second stage, the reference switches are turned on.

7. The digital-to-analog converter of claim 6, wherein, One end of the pre-charge switch receives a reference voltage.

8. The digital-to-analog converter of claim 6, wherein, 10. The D / A converter of claim 1, wherein:

9. The digital-to-analog converter of claim 6, wherein, the D / A converter is disposed in a pulse width modulation controller, the pulse width modulation controller is disposed in a driving circuit; the pulse width modulation controller obtains a table entry from a lookup table stored in a memory, and obtains the control code according to the table entry; the pulse width modulation controller generates a pulse width modulation signal having a pulse width, the pulse width corresponding to the control code; the pulse width modulation signal is used to control a bidirectional circuit disposed in a corresponding driving circuit. ​ ​

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