Solid-state imaging device

Abstract

A solid-state imaging device according to the present application includes: a first substrate including, for each pixel, a photoelectric conversion section and a charge accumulator in which signal charges generated by the photoelectric conversion section are stored; a second substrate including a semiconductor layer and a pixel transistor facing a gate electrode of the semiconductor layer and for reading out the signal charges in the charge accumulator; and a through electrode provided in the first substrate and the second substrate, electrically connecting the first substrate and the second substrate, and a portion of the through electrode being in contact with the gate electrode.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device comprising multiple semiconductor layers stacked on top of each other. Background Technology

[0002] Recently, progress has been made in the development of CMOS (Complementary Metal-Oxide-Semiconductor) image sensors for solid-state imaging devices. For example, Patent Document 1 discloses a solid-state imaging device in which a semiconductor wafer including a pixel array and a semiconductor wafer including logic circuitry are stacked.

[0003] For example, a photodiode, a floating diffuser, and a pixel transistor are provided in the pixel array section.

[0004] List of cited references

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application No. 2010-245506 (Unexamined) Summary of the Invention

[0007] In such solid-state imaging devices, it is desirable to reduce the noise of the signal output from the pixel transistor.

[0008] Therefore, it is desirable to provide a solid-state imaging device that can reduce noise in the signal output from the pixel transistor.

[0009] A solid-state imaging device according to an embodiment of the present invention includes: a first substrate including a photoelectric conversion section and a charge accumulation section for each pixel, the charge accumulation section accumulating signal charge generated in the photoelectric conversion section; a second substrate including a semiconductor layer and a pixel transistor, the semiconductor layer being stacked on the first substrate, and the pixel transistor including a gate electrode opposite to the semiconductor layer and reading the signal charge of the charge accumulation section; and a through electrode disposed in the first substrate and the second substrate, electrically connecting the first substrate and the second substrate to each other and partially contacting the gate electrode.

[0010] In a solid-state imaging device according to an embodiment of the present invention, the gate electrode of the pixel transistor is configured to contact a portion of the through electrode. Therefore, the area of ​​the gate electrode is increased compared to a configuration where the gate electrode is arranged away from the through electrode. Attached Figure Description

[0011] [ Figure 1 ] Figure 1 This is a block diagram illustrating an example of the functional structure of a camera device according to an embodiment of the present invention.

[0012] [ Figure 2 ] Figure 2 yes Figure 1 A schematic plan view of the schematic structure of the camera device shown.

[0013] [ Figure 3 ] Figure 3 It is along Figure 2 A schematic diagram of the cross-sectional structure of line III-III' shown.

[0014] [ Figure 4 ] Figure 4 yes Figure 1 The equivalent circuit diagram of the pixel shared unit is shown.

[0015] [ Figure 5 ] Figure 5 This is a diagram illustrating an example of the connection pattern between multiple pixel shared units and multiple vertical signal lines.

[0016] [ Figure 6 ] Figure 6 yes Figure 3 A schematic cross-sectional view illustrating an example of the specific construction of the camera device shown.

[0017] [ Figure 7A ] Figure 7A yes Figure 6 A schematic diagram illustrating an example of the planar structure of the main portion of the first substrate.

[0018] [ Figure 7B ] Figure 7B The solder pads together Figure 7A A schematic diagram of the planar structure of the main parts of the first substrate shown.

[0019] [ Figure 8 ] Figure 8 yes Figure 6 A schematic diagram of an example of a planar structure of the second substrate (semiconductor layer).

[0020] [ Figure 9 ] Figure 9 It is the main part of the pixel circuit and the first substrate together Figure 6 A schematic diagram illustrating an example of a planar configuration of the first wiring layer together.

[0021] [ Figure 10 ] Figure 10 yes Figure 6 A schematic diagram illustrating an example of the planar construction of the first and second wiring layers.

[0022] [ Figure 11 ] Figure 11 yes Figure 6 A schematic diagram illustrating an example of the planar construction of the second and third wiring layers.

[0023] [ Figure 12 ] Figure 12 yes Figure 6 A schematic diagram illustrating an example of the planar construction of the third and fourth wiring layers.

[0024] [ Figure 13 ] Figure 13 yes Figure 6 A schematic diagram of the cross-sectional structure near the amplifying transistor and the through electrode.

[0025] [ Figure 14 ] Figure 14 yes Figure 13 The diagram shows a magnified schematic cross-sectional view of the amplifying transistor.

[0026] [ Figure 15 ] Figure 15 It is used to explain Figure 3 A schematic diagram of the input signal path of the camera device shown.

[0027] [ Figure 16 ] Figure 16 It is used for explanation Figure 3 A schematic diagram of the signal path of the pixel signal of the camera device shown.

[0028] [ Figure 17 ] Figure 17 This is a schematic diagram showing the cross-sectional structure of the main part of the camera device according to the comparative example.

[0029] [ Figure 18 ] Figure 18 It is used for explanation Figure 13 A schematic cross-sectional view showing the dimensions of the amplifying transistor.

[0030] [ Figure 19 ] Figure 19 This is a schematic diagram of the cross-sectional structure of the main part of the camera device according to Modified Example 1.

[0031] [ Figure 20 (A) is a schematic diagram of the cross-sectional structure of the main part of the camera device according to Modified Example 2, and (B) is a schematic diagram of the planar structure of the gate electrode shown in (A).

[0032] [ Figure 21 ] Figure 21 This is a schematic diagram of the cross-sectional structure of the main part of the camera device according to Modified Example 3.

[0033] [ Figure 22 ] Figure 22 This is a schematic diagram of the cross-sectional structure of the main part of the camera device according to Modification 4.

[0034] [ Figure 23 ] Figure 23 This is a schematic diagram of the cross-sectional structure of the main part of the camera device according to Modification 5.

[0035] [ Figure 24 ] Figure 24 yes Figure 8 A schematic diagram of a modified example of the planar structure of the second substrate (semiconductor layer) shown.

[0036] [ Figure 25 ] Figure 25 It is the main part of the first wiring layer and the first substrate together Figure 24 The diagram shows a planar structure of the pixel circuitry.

[0037] [ Figure 26 ] Figure 26 It is the second wiring layer together Figure 25 A schematic diagram illustrating an example of a planar configuration of the first wiring layer together.

[0038] [ Figure 27 ] Figure 27 It is the third wiring layer together with Figure 26 A schematic diagram illustrating an example of a planar configuration for the second wiring layer.

[0039] [ Figure 28 ] Figure 28 It is the fourth wiring layer together with Figure 27 A schematic diagram illustrating an example of a planar configuration with the third wiring layer shown.

[0040] [ Figure 29 ] Figure 29 yes Figure 7A A schematic diagram of a modified example of the planar structure of the first substrate shown.

[0041] [ Figure 30 ] Figure 30 It is stacked on Figure 29 A schematic diagram illustrating an example of a planar structure of a second substrate (semiconductor layer) on a first substrate.

[0042] [ Figure 31 ] Figure 31 It is the first wiring layer together Figure 30 A schematic diagram illustrating an example of a planar structure for pixel circuits together.

[0043] [ Figure 32 ] Figure 32 It is the second wiring layer and Figure 31 A schematic diagram illustrating an example of a planar configuration of the first wiring layer together.

[0044] [ Figure 33 ] Figure 33It is the third wiring layer together with Figure 32 The diagram shows an example of a flat configuration of the second wiring layer together.

[0045] [ Figure 34 ] Figure 34 It is the fourth wiring layer together Figure 33 A schematic diagram illustrating an example of a planar configuration with the third wiring layer shown.

[0046] [ Figure 35 ] Figure 35 yes Figure 29 A schematic diagram of another example of the planar structure of the first substrate shown.

[0047] [ Figure 36 ] Figure 36 It is stacked on Figure 35 A schematic diagram illustrating an example of a planar structure of a second substrate (semiconductor layer) on a first substrate.

[0048] [ Figure 37 ] Figure 37 It is the first wiring layer together Figure 36 A schematic diagram illustrating an example of a planar structure for pixel circuits together.

[0049] [ Figure 38 ] Figure 38 It is the second wiring layer together Figure 37 A schematic diagram illustrating an example of a planar configuration of the first wiring layer together.

[0050] [ Figure 39 ] Figure 39 It is the third wiring layer together Figure 38 A schematic diagram illustrating an example of a planar configuration for the second wiring layer.

[0051] [ Figure 40 ] Figure 40 It is the fourth wiring layer together Figure 39 A schematic diagram illustrating an example of a planar configuration with the third wiring layer shown.

[0052] [ Figure 41 ] Figure 41 yes Figure 3 A schematic cross-sectional view of another example of the camera device shown.

[0053] [ Figure 42 ] Figure 42 It is used to explain Figure 41 A schematic diagram of the input signal path of the camera device shown.

[0054] [ Figure 43 ] Figure 43 It is used for explanation Figure 41A schematic diagram of the signal path of the pixel signal of the camera device shown.

[0055] [ Figure 44 ] Figure 44 yes Figure 6 A schematic cross-sectional view of another example of the camera device shown.

[0056] [ Figure 45 ] Figure 45 It shows Figure 4 A diagram of another example of the equivalent circuit shown.

[0057] [ Figure 46 ] Figure 46 yes Figure 7A A schematic plan view of another example of the pixel separation section shown.

[0058] [ Figure 47 ] Figure 47 This is a cross-sectional view in the thickness direction of a construction example of a camera device according to a variation 13 of the present invention.

[0059] [ Figure 48 ] Figure 48 This is a cross-sectional view in the thickness direction of a construction example of a camera device according to a variation 13 of the present invention.

[0060] [ Figure 49 ] Figure 49 This is a cross-sectional view in the thickness direction of a construction example of a camera device according to a variation 13 of the present invention.

[0061] [ Figure 50 ] Figure 50 This is a horizontal cross-sectional view of a layout example of multiple pixel units according to a variation of 13 of the present invention.

[0062] [ Figure 51 ] Figure 51 This is a horizontal cross-sectional view of a layout example of multiple pixel units according to a variation of 13 of the present invention.

[0063] [ Figure 52 ] Figure 52 This is a horizontal cross-sectional view of a layout example of multiple pixel units according to a variation of 13 of the present invention.

[0064] [ Figure 53 ] Figure 53 This is a cross-sectional view in the thickness direction of a construction example of a camera device according to a combination of embodiments and variations 13 of the present invention.

[0065] [ Figure 54 ] Figure 54This is a cross-sectional view in the thickness direction of a construction example of a camera device according to a combination of embodiments and variations 13 of the present invention.

[0066] [ Figure 55 ] Figure 55 This is a diagram illustrating an example of a schematic construction of a camera system including a camera device according to any of the above embodiments and variations thereof.

[0067] [ Figure 56 ] Figure 56 It shows Figure 55 A diagram illustrating an example of the recording process of the camera system shown.

[0068] [ Figure 57 ] Figure 57 This is a block diagram illustrating an example of the schematic construction of a vehicle control system.

[0069] [ Figure 58 ] Figure 58 This diagram illustrates the installation locations of the vehicle exterior information detection unit and the camera unit.

[0070] [ Figure 59 ] Figure 59 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system.

[0071] [ Figure 60 ] Figure 60 This is a block diagram illustrating an example of the functional structure of a camera head and a camera control unit (CCU). Detailed Implementation Plan

[0072] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0073] 1. Implementation Scheme (Camera Device with Stacked Structure of Three Substrates)

[0074] 2. Modified Example 1 (Example of gate electrode contacting the front and side surfaces of the amplifying transistor)

[0075] 3. Variation 2 (Example of an amplifying transistor whose gate electrode includes a through hole)

[0076] 4. Variation Example 3 (Example including a connection to the fin)

[0077] 5. Variation Example 4 (Example of amplifying transistors including planar transistors)

[0078] 6. Variation 5 (Example of an amplifying transistor including a buried gate electrode)

[0079] 7. Variation Example 6 (Example 1 of planar construction)

[0080] 8. Variation Example 7 (Example 2 of planar construction)

[0081] 9. Variation Example 8 (Example 3 of planar construction)

[0082] 10. Modification 9 (Example where the middle portion of the pixel array includes a contact portion between substrates)

[0083] 11. Variation 10 (including an example of a planar transmission transistor)

[0084] 12. Variation Example 11 (Example of a pixel connected to a readout circuit)

[0085] 13. Variation Example 12 (Example of pixel separation section construction)

[0086] 14. Variation 13 (Example of setting one trap contact for every multiple sensor pixels)

[0087] 15. Application Example (Camera System)

[0088] 16. Practical Application Examples

[0089] <1. Implementation Plan>

[0090] [Functional Structure of Camera Device 1]

[0091] Figure 1 This is a block diagram illustrating an example of the functional structure of a solid-state imaging device (imaging device 1) according to an embodiment of the present invention.

[0092] Figure 1 The camera device 1 includes, for example, an input unit 510A, a row drive unit 520, a timing controller 530, a pixel array unit 540, a column signal processor 550, an image signal processor 560, and an output unit 510B.

[0093] In the pixel array section 540, pixels 541 are arranged repeatedly in an array. More specifically, pixel sharing units 539, each comprising multiple pixels, are repeating units and are arranged repeatedly in an array in both the row and column directions. It should be noted that, for convenience, in this specification, the row direction and the column direction perpendicular to the row direction are sometimes referred to as the "H direction" and the "V direction," respectively. Figure 1 In the example, a pixel-shared unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Pixels 541A, 541B, 541C, and 541D each include a photodiode PD (described later). Figure 6 (As shown in the diagram). Pixel sharing unit 539 shares a single pixel circuit (described later). Figure 3 The pixel array 540 comprises a unit of pixel circuit 210. In other words, one pixel circuit (pixel circuit 210, described later) is included for every four pixels (pixel 541A, pixel 541B, pixel 541C, and pixel 541D). The pixel circuit is driven in a time-division manner to sequentially read the pixel signals of each pixel 541A, 541B, 541C, and 541D. For example, pixels 541A, 541B, 541C, and 541D are arranged in two rows and two columns. In addition to pixels 541A, 541B, 541C, and 541D, the pixel array 540 also includes multiple row drive signal lines 542 and multiple vertical signal lines (column readout lines) 543. The row drive signal lines 542 drive pixels 541 arranged side by side in the row direction of the pixel array 540 and included in multiple pixel shared units 539. The row drive signal line 542 drives the individual pixels arranged side-by-side in the row direction of the pixel sharing unit 539. See below. Figure 4 The pixel sharing unit 539 includes multiple transistors. Multiple row drive signal lines 542 are connected to the pixel sharing unit 539 to drive each of the transistors. The pixel sharing unit 539 is connected to vertical signal lines (column readout lines) 543. Pixel signals are read from the individual pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal lines (column readout lines) 543.

[0094] The line drive unit 520 includes, for example, a line address controller, i.e., a line decoder unit, that determines the position of the line used to drive the pixels, and a line drive circuit unit that generates signals for driving pixels 541A, 541B, 541C and 541D.

[0095] The column signal processor 550 is connected, for example, to the vertical signal line 543, and includes a load circuit section that forms a source follower circuit with pixels 541A, 541B, 541C, and 541D (pixel common unit 539). The column signal processor 550 may include an amplification circuit section that amplifies the signal read from the pixel common unit 530 via the vertical signal line 543. The column signal processor 550 may include a noise processor. The noise processor removes the system noise level from the signal read as a result of photoelectric conversion from the pixel common unit 539, for example.

[0096] The column signal processor 550 includes, for example, an analog-to-digital converter (ADC). The ADC converts the signal read from the pixel sharing unit 539 or the analog signal after noise processing as described above into a digital signal. The ADC includes, for example, a comparator section and a counter section. The comparator section compares the analog signal, which is the conversion target, with a reference signal, which is the comparison target. The counter section measures the time until the comparison result in the comparator section is inverted. The column signal processor 550 may include a horizontal scan circuit section that controls the scanning of the readout column.

[0097] The timing controller 530 supplies control timing signals to the row drive unit 520 and the column signal processor 550 based on the reference clock signal and timing control signal input to the device.

[0098] The image signal processor 560 is a circuit that performs various types of signal processing on data obtained as a result of photoelectric conversion (i.e., data obtained as a result of the imaging operation of the imaging device 1). The image signal processor 560 includes, for example, an image signal processing circuit section and a data holding section. The image signal processor 560 may include a processor section.

[0099] One example of signal processing performed in the image signal processor 560 is tone curve correction processing, in which the grayscale is increased when the A / D converted image data is obtained by shooting a dark subject, and the grayscale is decreased when the A / D converted image data is obtained by shooting a bright subject. In this case, it is desirable to pre-store the characteristic data of the tone curve regarding the grayscale of the image data for correction in the data holding unit of the image signal processor 560.

[0100] The input unit 510A inputs, for example, the aforementioned reference clock signal, timing control signal, and feature data to the imaging device 1 from outside the device. Examples of timing control signals include vertical synchronization signals and horizontal synchronization signals. For example, the feature data is stored in the data holding unit of the image signal processor 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude variation unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0101] Input terminal 511 is an external terminal for inputting data. Input circuit section 512 inputs the signal input to input terminal 511 into imaging device 1. Input amplitude change section 513 converts the amplitude of the signal input by input circuit section 512 into an amplitude easily usable within imaging device 1. Input data conversion circuit section 514 changes the order of the data columns of the input data. Input data conversion circuit section 514 includes, for example, a serial-to-parallel conversion circuit. The serial-to-parallel conversion circuit converts the serial signal received as input data into a parallel signal. It should be noted that in input section 510A, input amplitude change section 513 and input data conversion circuit section 514 can be omitted. Power supply section uses power supplied from the outside to imaging device 1 to supply various types of voltage power required inside imaging device 1.

[0102] When the camera device 1 is connected to an external storage device, the input unit 510A may include a storage interface circuit for receiving data from the external storage device. Examples of external storage devices include flash memory, SRAM, DRAM, etc.

[0103] The output unit 510B outputs image data to an external device. Examples of image data include image data captured by the camera device 1, and image data processed by the image signal processor 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0104] The output data conversion circuit 515 includes, for example, a parallel-to-serial conversion circuit. The output data conversion circuit 515 converts the parallel signal used internally by the imaging device 1 into a serial signal. The output amplitude variation unit 516 changes the amplitude of the signal used internally by the imaging device 1. The signal with the changed amplitude can be easily used in an external device connected to the outside of the imaging device 1. The output circuit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit 517 drives the wiring connected to the output terminal 518 externally by the imaging device 1. At the output terminal 518, data is output from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit 515 and the output amplitude variation unit 516 can be omitted.

[0105] When the camera device 1 is connected to an external storage device, the output unit 510B may include a storage interface circuit that outputs data to the external storage device. Examples of external storage devices include flash memory, SRAM, DRAM, etc.

[0106] [Schematic diagram of camera device 1]

[0107] Figure 2 and Figure 3Examples of schematic structures of the camera device 1 are shown. The camera device 1 includes three substrates (first substrate 100, second substrate 200 and third substrate 300). Figure 2 The planar structures of each of the first substrate 100, the second substrate 200, and the third substrate 300 are schematically shown, and Figure 3 The schematic diagram shows the cross-sectional structure of the first substrate 100, the second substrate 200 and the third substrate 300 stacked on top of each other. Figure 3 Corresponding to along Figure 2 The cross-sectional structure of line III-III' is shown. The imaging device 1 is a three-dimensional structure having three substrates (first substrate 100, second substrate 200, and third substrate 300) bonded together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300, and the interlayer insulating film surrounding them, is referred to as the wiring layer (100T, 200T, or 300T) disposed in each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked sequentially, and a semiconductor layer 100S, a wiring layer 100T, a semiconductor layer 200S, a wiring layer 200T, a wiring layer 300T, and a semiconductor layer 300S are arranged sequentially in the stacking direction. The specific structure of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. Figure 3 The arrows shown indicate the direction in which light L is incident on the imaging device 1. In this specification, for convenience, in subsequent cross-sectional views, the light-incident side of the imaging device 1 is sometimes referred to as the "bottom," "lower side," or "below," and the side opposite to the light-incident side is sometimes referred to as the "top," "upper side," or "above." Furthermore, in this specification, for convenience, in a substrate including a semiconductor layer and a wiring layer, the side of the wiring layer is sometimes referred to as the front surface, and the side of the semiconductor layer is sometimes referred to as the rear surface. It should be noted that the description in this specification is not limited to those names. The imaging device 1 is, for example, a back-illuminated imaging device where light enters from the rear surface side of a first substrate 100 including a photodiode.

[0108] Both the pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are configured using the first substrate 100 and the second substrate 200. The first substrate 100 includes a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539. Each of the pixels 541 includes a photodiode (PD, described later) and a transmission transistor (TR, described later). The second substrate 200 includes pixel circuitry (pixel circuitry 210, described later) included in the pixel sharing unit 539. The pixel circuitry reads pixel signals transmitted from the photodiodes of each of the pixels 541A, 541B, 541C, and 541D via the transmission transistor, or resets the photodiodes. In addition to such pixel circuitry, the second substrate 200 also includes a plurality of row drive signal lines 542 extending along the row direction and a plurality of vertical signal lines 543 extending along the column direction. The second substrate 200 also includes power lines 544 extending along the row direction. The third substrate 300 includes, for example, an input section 510A, a row driver section 520, a timing controller 530, a column signal processor 550, an image signal processor 560, and an output section 510B. The row driver section 520 is, for example, disposed in a region that partially overlaps with the pixel array section 540 in the stacking direction (hereinafter referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver section 520 is disposed in the stacking direction ( Figure 2 The column signal processor 550 is disposed, for example, in the region that partially overlaps with the pixel array 540 in the stacking direction near its end. More specifically, the column signal processor 550 is disposed in the region that partially overlaps with the pixel array 540 in the stacking direction. Figure 2 The region overlapping with the portion near the end of the pixel array 540 in the V direction. Although not shown, for example, the input portion 510A and the output portion 510B may be arranged in a portion other than the third substrate 300, and may be arranged in the second substrate 200, for example. Alternatively, the input portion 510A and the output portion 510B may be provided on the rear surface (light incident surface) side of the first substrate 100. It should be noted that the pixel circuit provided in the second substrate 200 described above is also referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. In this specification, the term "pixel circuit" is used.

[0109] The first substrate 100 and the second substrate 200 are connected, for example, by a through electrode (described later). Figure 6The through electrodes 120E and 121E are electrically connected. The second substrate 200 and the third substrate 300 are electrically connected to each other, for example, through contact portions 201, 202, 301, and 302. The second substrate 200 is provided with contact portions 201 and 202, and the third substrate 300 is provided with contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 includes a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 includes a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. Contact areas 201R and 301R are disposed between the pixel array section 540 and the row drive section 520 in the stacking direction. Figure 3 In other words, contact regions 201R and 301R are, for example, disposed in the region where the row drive section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap each other in the stacking direction, or in the vicinity of such region. For example, contact regions 201R and 301R are arranged at the ends of such regions in the H direction. Figure 2 In the third substrate 300, the contact region 301R is provided, for example, at a location overlapping a portion of the row drive unit 520, specifically at the end of the row drive unit 520 in the H direction. Figure 2 and Figure 3 Contact portions 201 and 301, for example, connect the row drive unit 520 disposed in the third substrate 300 and the row drive line 542 disposed in the second substrate 200 to each other. Contact portions 201 and 301, for example, can connect the input unit 510A disposed in the third substrate 300 to the power supply line 544 and the reference potential line (VSS, described later). Contact regions 202R and 302R are disposed between the pixel array unit 540 and the column signal processor 550 in the stacking direction. Figure 3 In other words, contact regions 202R and 302R are, for example, disposed in the region where the column signal processor 550 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap each other in the stacking direction, or in the region near such region. Contact regions 202R and 302R are arranged at the ends of such regions in the V direction. Figure 2 In the third substrate 300, the contact region 301R is provided, for example, at a location overlapping a portion of the column signal processor 550, specifically at the end of the column signal processor 550 in the V direction. Figure 2 and Figure 3Contact portions 202 and 302, for example, connect pixel signals (corresponding to the amount of charge generated as a result of photoelectric conversion by photodiodes) output from each of the plurality of pixel sharing units 539 included in the pixel array unit 540 to a column signal processor 550 provided on the third substrate 300. The pixel signals are transmitted from the second substrate 200 to the third substrate 300.

[0110] Figure 3 This is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected to each other via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 includes an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other. Specifically, contact portions 201, 202, 301, and 302 are all formed using electrodes made of a conductive material. The conductive material is, for example, a metallic material such as copper (Cu), aluminum (Al), and gold (Au). Contact regions 201R, 202R, 301R, and 302R electrically connect the second and third substrates to each other, for example, by directly bonding wiring formed as electrodes, which enables signals to be input to and / or output from the second and third substrates 200 and 300.

[0111] An electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other can be provided at a desired location. For example, such as... Figure 3 The electrical connection portions, as contact regions 202R, 301R, and 302R, can be disposed in regions overlapping with the pixel array portion 540 in the stacking direction. Furthermore, the electrical connection portions can be disposed in regions not overlapping with the pixel array portion 540 in the stacking direction. Specifically, the electrical connection portions can be disposed in regions overlapping with the peripheral portion disposed outside the pixel array portion 540 in the stacking direction.

[0112] The first substrate 100 and the second substrate 200 include, for example, a connection hole H1 and a connection hole H2. The connection hole H1 and the connection hole H2 penetrate the first substrate 100 and the second substrate 200. Figure 3 The connecting hole portions H1 and H2 are disposed outside the pixel array portion 540 (or in portions overlapping with the pixel array portion 540). Figure 2For example, connection hole H1 is disposed on the outside of pixel array portion 540 in the H direction, and connection hole H2 is disposed on the outside of pixel array portion 540 in the V direction. For example, connection hole H1 reaches input portion 510A disposed in third substrate 300, and connection hole H2 reaches output portion 510B disposed in third substrate 300. Connection hole portions H1 and H2 may be hollow, or may at least partially comprise conductive material. For example, there is a configuration in which bonding lines are connected to electrodes formed as input portion 510A and / or output portion 510B. Alternatively, there is a configuration in which electrodes formed as input portion 510A and / or output portion 510B are connected to each other by conductive material disposed in connection hole portions H1 and H2. The conductive material disposed in the connecting hole portion H1 and the connecting hole portion H2 may be embedded in part or all of each of the connecting hole portion H1 and the connecting hole portion H2, or the conductive material may be formed on the sidewall of each of the connecting hole portion H1 and the connecting hole portion H2.

[0113] It is important to note that Figure 3 The diagram shows a configuration in which input portion 510A and output portion 510B are disposed in the third substrate 300, but this is not limiting. For example, transmitting signals from the third substrate 300 to the second substrate 200 via wiring layers 200T and 300T allows input portion 510A and / or output portion 510B to be disposed in the second substrate 200. Similarly, transmitting signals from the second substrate 200 to the first substrate 100 via wiring layers 100T and 200T allows input portion 510A and / or output portion 510B to be disposed in the first substrate 100.

[0114] Figure 4 This is an equivalent circuit diagram illustrating a construction example of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Figure 4The diagram shows four pixels 541 (i.e., pixels 541A, 541B, 541C, and 541D), a pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors: an amplifying transistor AMP, a selecting transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 operates the pixel circuit 210 in a time-division manner to sequentially output the pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. The mode in which a pixel circuit 210 is connected to a plurality of pixels 541, and in which the pixel signals of the plurality of pixels 541 are output in a time-division manner through a pixel circuit 210, implies that "a pixel circuit is shared by a plurality of pixels 541". Here, at least one transistor included in the pixel circuit 210 (e.g., an amplifying transistor AMP, a selection transistor SEL, a reset transistor RST, or an FD conversion gain switching transistor FDG) corresponds to a specific example of the “pixel transistor” of the present invention.

[0115] Pixels 541A, 541B, 541C, and 541D comprise the same components. In the following description, to distinguish the components of pixels 541A, 541B, 541C, and 541D from one another, identifier "1" is assigned to the end of the reference numeral for the component of pixel 541A, identifier "2" is assigned to the end of the reference numeral for the component of pixel 541B, identifier "3" is assigned to the end of the reference numeral for the component of pixel 541C, and identifier "4" is assigned to the end of the reference numeral for the component of pixel 541D. When it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D from one another, the identifiers at the end of the reference numerals for each of the components of pixels 541A, 541B, 541C, and 541D will be omitted.

[0116] Pixels 541A, 541B, 541C, and 541D, for example, each include a photodiode PD, a transmission transistor TR electrically connected to the photodiode PD, and a floating diffuser FD electrically connected to the transmission transistor TR. In the photodiode PD (PD1, PD2, PD3, and PD4), the cathode is electrically connected to the source of the transmission transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD photoelectrically converts incident light to generate a charge corresponding to the amount of received light. The transmission transistor TR (transmission transistor TR1, transmission transistor TR2, transmission transistor TR3, and transmission transistor TR4) is, for example, an n-type CMOS (complementary metal-oxide-semiconductor) transistor. In the transmission transistor TR, the drain is electrically connected to the floating diffuser FD, and the gate is electrically connected to a drive signal line. The drive signal line is a plurality of row drive signal lines 542 (refer to) connected to a pixel common unit 539. Figure 1 Part of the present invention. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion section FD. The floating diffusion section FD (floating diffusion section FD1, floating diffusion section FD2, floating diffusion section FD3, and floating diffusion section FD4) is an n-type diffusion layer region formed in the p-type semiconductor layer. The floating diffusion section FD is a charge holding device that temporarily holds the charge transferred from the photodiode PD, and a charge-to-voltage conversion device that generates a voltage corresponding to the amount of charge. Here, the photodiode PD corresponds to a specific example of the "photoelectric conversion section" of the present invention, and the floating diffusion section FD corresponds to a specific example of the "charge accumulation section" of the present invention.

[0117] Four floating diffusers FD (FD1, FD2, FD3, and FD4) within a pixel shared unit 539 are electrically connected to each other and to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel shared unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel shared unit 539. The gate of the amplifying transistor AMP is connected to the floating diffuser FD, the drain of the amplifying transistor AMP is connected to the power supply line VDD, and the source of the amplifying transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line 543, and the gate of the select transistor SEL is connected to the drive signal line. The drive signal line is part of a plurality of row drive signal lines 542 connected to a pixel shared unit 539.

[0118] In the case of the conducting transfer transistor TR, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion section FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is configured to be located from the semiconductor layer (described later). Figure 6 The front surface of the semiconductor layer 100S extends to the depth reaching the PD, as described later. Figure 6 The reset transistor RST resets the potential of the floating diffuser FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffuser FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a voltage signal corresponding to the level of charge held by the floating diffuser FD as a pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. The amplification transistor AMP, along with the load circuit section (see reference) connected to the vertical signal line 543 of the column signal processor 550, is also connected to the vertical signal line 543. Figure 1 Together, they form a source follower. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffuser FD to the column signal processor 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0119] The FD conversion gain switching transistor FDG is used to change the gain of the charge-to-voltage conversion of the floating diffuser FD. Typically, when shooting in low light, the pixel signal is small. When performing charge-to-voltage conversion based on Q=CV, a large capacitance of the floating diffuser FD (FD capacitance C) results in a small value V when converted to voltage at the amplifying transistor AMP. Meanwhile, in bright light, the pixel signal increases; therefore, the floating diffuser FD cannot receive charge from the photodiode PD unless the FD capacitance C is very large. Furthermore, the FD capacitance C needs to be large so that the value V when converted to voltage at the amplifying transistor AMP is not too large (in other words, small). Considering these factors, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FDG is increased, resulting in a larger overall FD capacitance C. Conversely, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, switching the FD conversion gain switching transistor FDG on / off makes the FD capacitance C variable, thereby enabling switching of the conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0120] It should be noted that it is feasible to construct the circuit without the FD conversion gain switching transistor FDG. In this case, the pixel circuit 210 includes, for example, three transistors: an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST. The pixel circuit 210 includes, for example, at least one of the pixel transistors such as the amplifying transistor AMP, the selecting transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0121] The select transistor SEL can be positioned between the power supply line VDD and the amplifying transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to both the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifying transistor AMP, and the gate of the select transistor SEL is electrically connected to the horizontal drive signal line 542 (see reference). Figure 1 The source of the amplifying transistor AMP (output of pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST. It should be noted that, although not shown, the number of pixels 541 sharing one pixel circuit 210 may not be four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0122] Figure 5 An example of the connection pattern between multiple pixel shared units 539 and vertical signal lines 543 is shown. For example, four pixel shared units 539 arranged side by side in the column direction are divided into four groups, and the vertical signal lines 543 are connected to each of the four groups. For simplicity, Figure 5 An example is shown where each of the four groups includes a single pixel sharing unit 539; however, each of the four groups may include multiple pixel sharing units 539. As described above, in the imaging device 1, multiple pixel sharing units 539 arranged side-by-side in the column direction can be divided into groups comprising one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing circuit 550 are connected to each group, enabling simultaneous reading of pixel signals from the respective groups. Alternatively, in the imaging device 1, a vertical signal line 543 may be connected to multiple pixel sharing units 539 arranged side-by-side in the column direction. In this case, pixel signals are read sequentially from the multiple pixel sharing units 539 connected to a single vertical signal line 543 in a time-division manner.

[0123] [Detailed Structure of Camera Device 1]

[0124] Figure 6 An example of a cross-sectional structure in the direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 is shown. For ease of understanding, Figure 6 The schematic diagram illustrates the positional relationship of the components and may differ from the actual cross-section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 also includes a light-receiving lens 401 on the rear surface side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light-receiving lens 401 and the first substrate. For example, the light-receiving lens 401 is provided for each of pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 includes a pixel array portion 540 disposed in the central portion and a peripheral portion 540B disposed outside the pixel array portion 540.

[0125] The first substrate 100, starting from the light-receiving lens 401 side, sequentially includes an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S, for example, includes a silicon substrate. The semiconductor layer 100S includes, for example, a portion of its front surface (the surface on the side of the wiring layer 100T) and a p-well layer 115 near that portion, and an n-type semiconductor region 114 included in a region outside the p-well layer 115 (a region deeper than the p-well layer 115). For example, a pn junction photodiode PD includes an n-type semiconductor region 114 and a p-well layer 115. The p-well layer 115 is a p-type semiconductor region.

[0126] Figure 7A An example of a planar structure of the first substrate 100 is shown. Figure 7AThe planar structure of the pixel separation section 117, photodiode PD, floating diffusion section FD, VSS contact region 118, and transmission transistor TR of the first substrate 100 is mainly shown. (The text then repeats itself, so the translation will only include the first instance.) Figure 7A Together Figure 6 The structure of the first substrate 100 will be explained together.

[0127] The floating diffuser FD and VSS contact region 118 are disposed near the front surface of semiconductor layer 100S. The floating diffuser FD includes an n-type semiconductor region disposed in p-well layer 115. The floating diffusers FD (floating diffuser FD1, floating diffuser FD2, floating diffuser FD3, and floating diffuser FD4) of each of pixels 541A, 541B, 541C, and 541D are, for example, disposed close to each other in the central portion of pixel common unit 539. Figure 7A As will be described in detail later, four floating diffusion sections (floating diffusion section FD1, floating diffusion section FD2, floating diffusion section FD3, and floating diffusion section FD4) included in the pixel common unit 539 are electrically connected to each other in the first substrate (more specifically in the wiring layer 100T) via electrical connection means (pad section 120, described later). Furthermore, the floating diffusion section FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical means (through electrode 120E, described later). In the second substrate 200 (more specifically inside the wiring layer 200T), the floating diffusion section FD is electrically connected via electrical means to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG.

[0128] The VSS contact area 118 is a region electrically connected to the reference potential line VSS and is arranged separately from the floating diffuser FD. For example, in pixels 541A, 541B, 541C, and 541D, the floating diffuser FD is arranged at one end in the V direction of each pixel, and the VSS contact area 118 is arranged at the other end. Figure 7A The VSS contact region 118 includes, for example, a p-type semiconductor region. For example, the VSS contact region 118 is connected to ground potential or a fixed potential. Therefore, a reference potential is supplied to the semiconductor layer 100S.

[0129] The first substrate 100 includes a transmission transistor TR, a photodiode PD, a floating diffuser FD, and a VSS contact region 118. The photodiode PD, the floating diffuser FD, the VSS contact region 118, and the transmission transistor TR are disposed in each of pixels 541A, 541B, 541C, and 541D. The transmission transistor TR is disposed on the front surface side of the semiconductor layer 100S (the side opposite to the light incident surface, on the second substrate 200 side). The transmission transistor TR includes a transmission gate TG. The transmission gate TG includes, for example, a horizontal portion TGb opposite to the front surface of the semiconductor layer 100S and a vertical portion TGa disposed within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. The vertical portion TGa includes one end that contacts the horizontal portion TGb and another end disposed within the n-type semiconductor region 114. The transmission transistor TR includes this vertical transistor, which avoids pixel signal transmission failures, thereby improving pixel signal readout efficiency.

[0130] The horizontal portion TGb of the transfer gate TG is in the H direction ( Figure 7A The pixel common unit 539 extends from a position opposite to the vertical portion TGa toward, for example, the middle portion of the pixel common unit 539. This allows the position in the H direction of the through electrode (through electrode TGV, described later) reaching the transfer gate TG to be close to the position in the H direction of the through electrodes (through electrodes 120E and through electrodes 121E, described later) connected to the floating diffusion portion FD and the VSS contact region 118. For example, the plurality of pixel common units 539 disposed in the first substrate 100 have the same configuration as each other. Figure 7A ).

[0131] The semiconductor layer 100S includes a pixel separation portion 117 that separates pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed to extend in a direction perpendicular to the semiconductor layer 100S (perpendicular to the front surface of the semiconductor layer 100S). The pixel separation portion 117 is configured to separate pixels 541A, 541B, 541C, and 541D from each other and has a planar grid shape. Figure 7A and Figure 7BFor example, the pixel separation section 117 electrically and optically separates pixels 541A, 541B, 541C, and 541D from each other. The pixel separation section 117 includes, for example, a light-shielding film 117A and an insulating film 117B. For example, tungsten (W) is used as the light-shielding film 117A. The insulating film 117B is disposed between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B includes, for example, silicon oxide (SiO). The pixel separation section 117 has, for example, an FTI (full trench isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation section 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, the pixel separation section 117 may have a DTI (deep trench isolation) structure that does not penetrate the semiconductor layer 100S. The pixel separation section 117 extends along a direction perpendicular to the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0132] The semiconductor layer 100S includes, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is disposed near the rear surface of the semiconductor layer 100S and is located between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is disposed on the side of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 each include, for example, a p-type semiconductor region.

[0133] A fixed-charge film 112 with a negative fixed charge is disposed between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S by an electric field induced by the fixed-charge film 112. This suppresses the generation of dark current caused by the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed-charge film 112 is formed, for example, using an insulating film with a negative fixed charge. Examples of materials for insulating films with a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0134] A light-shielding film 117A is disposed between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A can be disposed continuously with respect to the light-shielding film 117A included in the pixel separation section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 can be selectively disposed, for example, at a position opposite to the pixel separation section 117 inside the semiconductor layer 100S. The insulating film 111 is disposed to cover the light-shielding film 117A. The insulating film 111 includes, for example, silicon oxide.

[0135] The wiring layer 100T disposed between the semiconductor layer 100S and the second substrate 200 sequentially includes, from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. For example, the horizontal portion TGb of the transmission gate TG is disposed in the wiring layer 100T. The interlayer insulating film 119 is disposed on the entire front surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 includes, for example, a silicon oxide film. It should be noted that the structure of the wiring layer 100T is not limited to the above-described structure, and it is sufficient as long as the wiring layer 100T has a structure including wiring and an insulating film. Here, the pad portion 120 corresponds to a specific example of the "common connection portion" of the present invention.

[0136] Figure 7B Pad portion 120 and pad portion 121 together are shown. Figure 7A The diagram shows a planar structure. Pad portions 120 and 121 are disposed in a selected area on the interlayer insulating film 119. Pad portions 120 connect the floating diffuser portions FD (floating diffuser FD1, floating diffuser FD2, floating diffuser FD3, and floating diffuser FD4) of pixels 541A, 541B, 541C, and 541D to each other. For each pixel shared unit 539, the pad portion 120 is, for example, arranged in the center portion of the pixel shared unit 539 in the planar diagram. Figure 7B The pad portion 120 is configured to span the pixel separation portion 117 and is arranged to overlap at least a portion of each of the floating diffusion portions FD1, FD2, FD3, and FD4. Figure 6 and 7BSpecifically, the pad portion 120 is formed in a region that overlaps with at least a portion of each of the plurality of floating diffusion portions FD (floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4) of the common pixel circuit 210 in a direction perpendicular to the front surface of the semiconductor layer 100S, and at least a portion of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiode PD1, photodiode PD2, photodiode PD3, and photodiode PD4) of the common pixel circuit 210. The interlayer insulating film 119 includes a connection via 120C for electrically connecting the pad portion 120 to each of the floating diffusion portions FD1, FD2, FD3, and FD4. The connection via 120C is provided for each of pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad portion 120 is embedded in the connection hole 120C to electrically connect the pad portion 120 to each of the floating diffusion portions FD1, FD2, FD3 and FD4.

[0137] The pad portion 121 connects multiple VSS contact regions 118 to each other. For example, VSS contact regions 118 disposed in pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction, and VSS contact regions 118 disposed in pixels 541A and 541B of another pixel sharing unit 539, are electrically connected to each other via the pad portion 121. For example, the pad portion 121 is configured to span across the pixel separation portion 117 and is arranged to overlap at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps with at least a portion of each of the multiple VSS contact regions 118 and at least a portion of the pixel isolation portion 117 formed between the multiple VSS contact regions 118 in a direction perpendicular to the front surface of the semiconductor layer 100s. The interlayer insulating film 119 includes a connection via 121C for electrically connecting the pad portion 121 and each VSS contact region 118 to each other. A connection via 121C is provided for each of pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad portion 121 is embedded in the connection via 121C to electrically connect the pad portion 121 and each of the VSS contact areas 118 to each other. For example, the pad portions 120 and 121 of each of the plurality of pixel shared units 539 arranged side by side in the V direction are arranged at approximately the same position in the H direction. Figure 7B ).

[0138] By providing pad portion 120, the wiring for connecting from floating diffusion portion FD to pixel circuit 210 (e.g., the gate electrode of amplifying transistor AMP) can be reduced throughout the chip. Similarly, by providing pad portion 121, the wiring for supplying potential to each of the VSS contact regions 118 can be reduced throughout the chip. This enables a reduction in the overall chip area, suppression of electrical interference between wirings in miniaturized pixels, and / or cost reduction by reducing the number of components, etc.

[0139] Pad portions 120 and 121 can be provided at desired locations on the first substrate 100 and the second substrate 200. Specifically, pad portions 120 and 121 can be provided in one of the insulating regions 212 of the wiring layer 100T and the semiconductor layer 200S. When pad portions 120 and 121 are provided in the wiring layer 100T, pad portions 120 and 121 can be in direct contact with the semiconductor layer 100S. Specifically, pad portions 120 and 121 can be configured to be directly connected to at least a portion of the respective floating diffusion portions FD and / or VSS contact regions 118. Furthermore, a configuration can be adopted in which connection holes 120C and connection holes 121C are provided from the respective floating diffusion portions FD and / or VSS contact areas 118 connected to the pad portion 120 and the pad portion 121, and the pad portion 120 and the pad portion 121 are provided at desired locations in the insulating regions 212 of the wiring layer 100T and the semiconductor layer 200S.

[0140] Specifically, when pad portions 120 and 121 are provided in the wiring layer 100T, the wiring connecting the floating diffuser portion FD and / or VSS contact region 118 to the insulating region 212 of the semiconductor layer 200S can be reduced. This allows for a reduction in the area of ​​the insulating region 212 on the second substrate 200 where the pixel circuit 210 is formed, which is used to form through wiring for connecting the floating diffuser portion FD to the pixel circuit 210. Therefore, a large area of ​​the second substrate 200 where the pixel circuit 210 is formed can be ensured. Ensuring the area of ​​the pixel circuit 210 allows for the formation of large pixel transistors and contributes to improved image quality due to reduced noise, etc.

[0141] In particular, when the pixel separation section 117 uses an FTI structure, the floating diffusion section FD and / or VSS contact area 118 are preferably provided in each pixel 541. Therefore, the construction using pad section 120 and pad section 121 makes it possible to significantly reduce the wiring connecting the first substrate 100 and the second substrate 200 to each other.

[0142] In addition, such as Figure 7BAs shown, for example, pad portions 120 connecting multiple floating diffusers FD and pad portions 121 connecting multiple VSS contact regions 118 are arranged alternately in a straight line in the V direction. Furthermore, the pad portions 120 and 121 are formed at locations surrounded by multiple photodiodes PD, multiple transmission gates TG, and multiple floating diffusers FD. This allows for the free arrangement of components other than the floating diffusers FD and VSS contact regions 118 in the first substrate 100 where multiple components are formed, improving the overall chip layout efficiency. Furthermore, ensuring the layout symmetry of components formed in the individual pixel common units 539 allows for the suppression of differences in the characteristics of the pixel 541.

[0143] The pad portions 120 and 121 include, for example, polysilicon (Poly Si), and more specifically, doped polysilicon with impurities. The pad portions 120 and 121 preferably comprise conductive materials with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This allows the pixel circuit 210 to be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason for this will be explained below. It should be noted that, in the following description, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 and the second substrate 200 together is referred to as the first manufacturing method.

[0144] Here, it is conceivable to form a pixel circuit 210 in the second substrate 200 and then bond the pixel circuit 210 to the first substrate 100 (hereinafter referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are pre-formed on the front surface of the first substrate 100 (the front surface of the wiring layer 100T) and the front surface of the second substrate 200 (the front surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the front surfaces of the first substrate 100 and the second substrate 200 simultaneously come into contact with each other. Therefore, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, constructing the imaging device 1 using the second manufacturing method enables the use of a suitable process corresponding to the construction of the first substrate 100 and the second substrate 200 to manufacture an imaging device with high quality and high performance.

[0145] In this second manufacturing method, the manufacturing equipment used for bonding the first substrate 100 and the second substrate 200 may cause alignment errors. Furthermore, the first substrate 100 and the second substrate 200 each have a diameter of, for example, about several tens of centimeters, and during bonding, expansion and contraction of the substrates may occur in the microscopic regions of various portions of the first substrate 100 and the second substrate 200. This expansion and contraction is caused by slight deviations in the timing of contact between the substrates. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur in the positions of the electrodes for electrical connection formed on the front surfaces of the first substrate 100 and the second substrate 200. In this second manufacturing method, even if such errors occur, it is preferably possible to make the electrodes of the first substrate 100 and the second substrate 200 contact each other. Specifically, taking into account the aforementioned errors, at least one of the electrodes of the first substrate 100 and the second substrate 200, preferably both, is made relatively large. Therefore, when using the second manufacturing method, for example, the size (size in the plane direction of the substrate) of the electrode formed on the front surface of the first substrate 100 or the second substrate 200 is greater than the size of the internal electrode extending from the interior of the first substrate 100 or the second substrate 200 to the front surface in the thickness direction.

[0146] Meanwhile, pad portions 120 and 121 include a heat-resistant conductive material, which allows the use of the first manufacturing method described above. In the first manufacturing method, after forming a first substrate 100 including a photodiode PD, a transmission transistor TR, etc., the first substrate 100 and a second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state where the active elements, wiring layers, etc., included in the pixel circuit 210 are not patterned. The second substrate 200 is in a state before patterning. Therefore, even if an error in the bonding position occurs when the first substrate 100 and the second substrate 200 are bonded together, this error will not cause an alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. It should be noted that when forming the pattern of the second substrate, for example, in an exposure apparatus for pattern forming, the pattern is formed to be aligned with the pattern formed on the first substrate. For the reasons described above, in the first manufacturing method, no error occurs in the bonding position between the first substrate 100 and the second substrate 200 during the manufacturing of the imaging device 1. For similar reasons, errors caused by substrate expansion and contraction resulting in the second manufacturing method are also not a problem in the manufacturing of the imaging device 1 in the first manufacturing method.

[0147] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, an active element is formed on the second substrate 200. Then, through-electrode 120E and through-electrode 121E, as well as through-electrode TGV (…), are formed. Figure 6 In the formation of through electrodes 120E, 121E, and TGV, for example, the pattern of the through electrodes is formed from above the second substrate 200 using a reduced projection exposure via an exposure apparatus. Therefore, by using reduced projection exposure, even if an alignment error occurs between the second substrate 200 and the exposure apparatus, the magnitude of the error in the second substrate 200 is only a small fraction of the error in the second manufacturing method described above (the reciprocal of the magnification factor of the reduced projection exposure). Therefore, by arranging the imaging device 1 using the first manufacturing method, it is beneficial to align the elements formed in the first substrate 100 and the second substrate 200, which enables the manufacture of an imaging device with high quality and high performance.

[0148] The imaging device 1 manufactured using the first manufacturing method has characteristics different from those of the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrode 120E, through electrode 121E, and through electrode TGV all have a thickness (dimension in the plane of the substrate) that is substantially fixed from the second substrate 200 to the first substrate 100, or, if the through electrode 120E, through electrode 121E, and through electrode TGV all have a tapered shape, they have a tapered shape with a fixed slope. In the imaging device 1 including the through electrode 120E, through electrode 121E, and through electrode TGV, the pixel 541 can be easily miniaturized.

[0149] Here, when the imaging device 1 is manufactured using the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, active elements are formed on the second substrate 200. Therefore, the heat treatment required to form the active elements also affects the first substrate 100. For this reason, as described above, the pad portions 120 and 121 provided in the first substrate 100 are preferably made of conductive materials with high heat resistance. For example, the pad portions 120 and 121 are preferably made of materials having a higher melting point (i.e., higher heat resistance) than at least some of the wiring materials included in the wiring layer 200T of the second substrate 200. For example, the pad portions 120 and 121 use conductive materials with high heat resistance such as doped polysilicon, tungsten, titanium, titanium nitride, etc. This makes it possible to manufacture the imaging device 1 using the first manufacturing method described above.

[0150] For example, a passivation film 122 is disposed on the entire front surface of the semiconductor layer 100S to cover the pad portion 120 and the pad portion 121. Figure 6The passivation film 122 includes, for example, a silicon nitride (SiN) film. An interlayer insulating film 123 covers the pad portion 120 and the pad portion 121, with the passivation film 122 sandwiched between the interlayer insulating film and the pad portion. For example, the interlayer insulating film 123 is disposed on the entire front surface of the semiconductor layer 100S. The interlayer insulating film 123 includes, for example, a silicon oxide (SiO) film. A bonding film 124 is disposed on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is disposed on the entire main surface of the first substrate 100. The bonding film 124 includes, for example, a silicon nitride film.

[0151] For example, the light-receiving lens 401 is opposite to the semiconductor layer 100S, with the fixed charge film 112 and the insulating film 111 sandwiched between them. Figure 6 For example, a light-receiving lens 401 is positioned opposite the photodiodes PD of each of pixels 541A, 541B, 541C, and 541D.

[0152] The second substrate 200 sequentially includes a semiconductor layer 200S and a wiring layer 200T, starting from the side of the first substrate 100. The semiconductor layer 200S includes a silicon substrate. A well region 211 is provided in the semiconductor layer 200S in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 includes a pixel circuit 210 provided for each pixel common unit 539. For example, the pixel circuit 210 is provided on the front surface side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the rear surface side (semiconductor layer 200S side) of the second substrate 200 is opposite to the front surface side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0153] Figures 8 to 12 An example of the planar structure of the second substrate 200 is schematically shown. Figure 8 The structure of the pixel circuit 210 disposed near the front surface of the semiconductor layer 200S is shown. Figure 9 The schematic diagram illustrates the structure of the wiring layer 200T (specifically, the first wiring layer W1, which will be described later), the semiconductor layer 200S connected to the wiring layer 200T, and various portions of the first substrate 100. Figures 10 to 12 Examples of planar construction for a 200T wiring layer are shown below. Figures 8 to 12 Together Figure 6 The structure of the second substrate 200 will be explained together. Figure 8 and Figure 9In the diagram, the outline of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is shown by a broken line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or insulating region 212 in the portion overlapping with the gate electrodes of the individual transistors included in the pixel circuit 210 is shown by a dashed line. In the portion overlapping with the gate electrode of the amplifying transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213, and the boundary between the element isolation region 213 and the insulating region 212, are provided on one side in the channel width direction.

[0154] The second substrate 200 includes an insulating region 212 separating the semiconductor layer 200S and an element separation region 213 disposed in a portion of the thickness direction of the semiconductor layer 200S. Figure 6 For example, in an insulating region 212 provided between two adjacent pixel circuits 210 in the H direction, through electrodes 120E and 121E, as well as through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to two pixel shared units 539 of the two pixel circuits 210 are arranged. Here, through electrode 120E corresponds to a specific example of the "through electrode" of the present invention.

[0155] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S. Figure 6 The semiconductor layer 200S is divided by an insulating region 212. Through electrodes 120E, 121E, and TGV are disposed in the insulating region 212. The insulating region 212 includes, for example, silicon oxide.

[0156] Through-electrode 120E and through-electrode 121E are configured to penetrate the insulating region 212 in the thickness direction. The upper ends of through-electrode 120E and through-electrode 121E are connected to the wiring of wiring layer 200T (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4, which will be described later). Through-electrode 120E and through-electrode 121E are configured to penetrate the insulating region 212, bonding film 124, interlayer insulating film 123, and passivation film 122, and their lower ends are connected to pad portion 120 and pad portion 121. Figure 6The through electrode 120E electrically connects the pad portion 120 and the pixel circuit 210 to each other. That is, the floating diffusion portion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the through electrode 120E. The through electrode 121E electrically connects the pad portion 121 and the reference potential line VSS of the wiring layer 200T to each other. That is, the VSS contact area 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 through the through electrode 121E.

[0157] The through-electrode TGV is configured to penetrate the insulating region 212 in the thickness direction. The upper end of the through-electrode TGV is connected to the wiring of the wiring layer 200T. The through-electrode TGV is configured to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG ( Figure 6 The through-electrode TGV connects the transmission gate TG (transmission gate TG1, transmission gate TG2, transmission gate TG3, or transmission gate TG4) of each of pixels 541A, 541B, 541C, and 541D to the wiring of the wiring layer 200T (part of the row drive signal line 542, which will be described in detail later). Figure 11 The wirings TRG1, TRG2, TRG3, or TRG4 are electrically connected to each other. That is, the transmission gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV to transmit the drive signal to each transmission transistor TR (transmission transistor TR1, transmission transistor TR2, transmission transistor TR3, and transmission transistor TR4).

[0158] The insulating region 212 is a region used to insulate the through electrodes 120E and 121E, and the through electrode TGV, which electrically connect the first substrate 100 and the second substrate 200 to each other, from the semiconductor layer 200S. For example, in the insulating region 212 provided between two adjacent pixel circuits 210 (pixel sharing unit 539) in the H direction, through electrodes 120E and 121E, and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to the two pixel circuits 210 are arranged. For example, the insulating region 212 is configured to extend along the V direction ( Figure 8 and Figure 9 Here, by designing the arrangement of the horizontal portion TGb of the transmission gate TG, the through electrode TGV is arranged such that, compared to the position of the vertical portion TGA, the position of the through electrode TGV in the H direction is closer to the positions of the through electrodes 120E and 121E in the H direction (i.e., compared to the position of the vertical portion TGA). Figure 7A and9 For example, the through electrode TGV is arranged at approximately the same position in the H direction as the through electrodes 120E and 121E. This allows the through electrodes 120E, 121E, and TGV to be concentrated in the insulating region 212 extending along the V direction. As another construction example, it is conceivable to arrange the horizontal portion TGb only in the region overlapping with the vertical portion TGa. In this case, for example, the through electrode TGV is formed approximately directly above the vertical portion TGa, and the through electrode TGV is arranged approximately in the middle of the H and Y directions of each pixel 541. In this case, the position of the through electrode TGV in the H direction is significantly deviated from the positions of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is provided around, for example, the through electrodes TGV, 120E, and 121E to electrically insulate them from their adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is significantly separated from the positions of the through electrodes 120E and 121E in the H direction, it is necessary to independently provide an insulating region 212 around each through electrode 120E, through electrode 121E, and through electrode TGV. Therefore, the semiconductor layer 200S is subdivided. In contrast, a layout in which the through electrodes 120E, through electrodes 121E, and through electrode TGV are concentrated in the insulating region 212 extending along the V direction can increase the size of the semiconductor layer 200S in the H direction. This allows for ensuring a large area of ​​semiconductor element formation region within the semiconductor layer 200S. Therefore, it is possible to increase the size of the amplification transistor AMP and improve, for example, the transconductance gm. This allows for the reduction of RTS (Random Telegraph Signal) noise.

[0159] For reference Figure 4 The pixel sharing unit 539 has the following structure: floating diffuser portions FD disposed in a plurality of pixels 541 are electrically connected to each other, and the plurality of pixels 541 share a single pixel circuit 210. The electrical connections between the floating diffuser portions FD are then provided by a first substrate 100 (…). Figure 6 and Figure 7BThe pad portion 120 in the first substrate 100 is completed. The electrical connection portion (pad portion 120) provided in the first substrate 100 and the pixel circuit 210 provided in the second substrate 200 are electrically connected to each other through an electrode 120E. As another structural example, it is conceivable to provide an electrical connection portion between floating diffusion portions FD in the second substrate 200. In this case, four through electrodes connected to each of the floating diffusion portions FD1, FD2, FD3 and FD4 are provided in the pixel common unit 539. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S is increased, and the insulating region 212 that insulates the periphery of these through electrodes is enlarged. In contrast, the structure in the first substrate 100 where the pad portion 120 is provided ( Figure 6 and Figure 7B This allows for a reduction in the number of through electrodes and a smaller insulating region 212. Therefore, a large area for semiconductor element formation can be ensured within the semiconductor layer 200S. For example, this allows for an increase in the size of the amplification transistor AMP and noise suppression.

[0160] Component isolation region 213 is disposed on the front surface side of semiconductor layer 200S. Component isolation region 213 has an STI (shallow trench isolation) structure. In component isolation region 213, semiconductor layer 200S is etched in the thickness direction (perpendicular to the main surface of second substrate 200), and an insulating film is buried in the etched portion. The insulating film includes, for example, silicon oxide. Component isolation region 213 realizes component separation between multiple transistors included in pixel circuit 210 according to the layout of pixel circuit 210. Semiconductor layer 200S (specifically, well region 211) extends below component isolation region 213 (deep portion of semiconductor layer 200S).

[0161] In the following text, reference will be made to Figure 7A , Figure 7B and Figure 8 The difference between the outline shape (outline shape in the plane direction of the substrate) of the pixel sharing unit 539 of the first substrate 100 and the outline shape of the pixel sharing unit 539 of the second substrate 200 is explained.

[0162] In the imaging device 1, a pixel sharing unit 539 is disposed on both the first substrate 100 and the second substrate 200. For example, the outline shape of the pixel sharing unit 539 disposed on the first substrate 100 and the outline shape of the pixel sharing unit 539 disposed on the second substrate 200 are different from each other.

[0163] exist Figure 7A and Figure 7BIn the diagram, alternating long and short dashed lines represent the outlines of pixels 541A, 541B, 541C, and 541D, and thick lines represent the outline of the pixel sharing unit 539. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541A and 541C) arranged adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 includes four adjacent pixels 541 arranged in two rows and two columns, and the pixel sharing unit 539 of the first substrate 100 has a generally square outline shape. In the pixel array section 540, these pixel sharing units 539 are arranged adjacent to each other in the H direction with a distance of two pixel spacing (corresponding to the distance between two pixels 541) and in the V direction with a distance of two pixel spacing (corresponding to the distance between two pixels 541).

[0164] exist Figure 8 and Figure 9 In the diagram, alternating long and short dashed lines represent the outlines of pixels 541A, 541B, 541C, and 541D, and thick lines represent the outline of the pixel sharing unit 539. For example, the outline shape of the pixel sharing unit 539 of the second substrate 200 is smaller in the H direction than the outline shape of the pixel sharing unit 539 of the first substrate 100, and larger in the V direction than the outline shape of the pixel sharing unit 539 of the first substrate 100. For example, the pixel sharing unit 539 of the second substrate 200 is formed to have a size (region) corresponding to one pixel in the H direction and a size corresponding to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed to have a size corresponding to adjacent pixels arranged in a row of four columns, and the pixel sharing unit 539 of the second substrate 200 has a generally rectangular outline shape.

[0165] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged side by side in this order in the V direction. Figure 8 As described above, the outline shape of each element in the pixel circuit 210 is set to an approximately rectangular shape, which allows for operation in one direction ( Figure 8 Four transistors (selection transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) are arranged side-by-side in the V direction. This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to be shared in a single diffusion region (the diffusion region connected to the power line VDD). For example, the formation regions of each pixel circuit 210 can be arranged in a roughly square shape (see below). Figure 21In this case, two transistors are arranged in one direction, making it difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in a single diffusion region. Therefore, setting the formation region of the pixel circuit 210 to be approximately rectangular allows for easy arrangement of the four transistors close to each other and enables the formation region of the pixel circuit 210 to be smaller. That is, the pixel can be miniaturized. Furthermore, without needing to reduce the formation region of the pixel circuit 210, the formation region of the amplification transistor AMP can be enlarged and noise reduced.

[0166] For example, in addition to the select transistor SEL, amplify transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is also provided near the front surface of semiconductor layer 200S. VSS contact region 218 includes, for example, a p-type semiconductor region. VSS contact region 218 is electrically connected to VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via wiring of wiring layer 200T and through electrode 121E. For example, this VSS contact region 218 is located adjacent to the source of FD conversion gain switching transistor FDG, and element isolation region 213 is sandwiched between the source and VSS contact region 218. Figure 8 ).

[0167] Next, we will refer to Figure 7B and Figure 8 The positional relationship between the pixel sharing unit 539 disposed in the first substrate 100 and the pixel sharing unit 539 disposed in the second substrate 200 is explained. For example, one of the two pixel sharing units 539 arranged side by side in the V direction of the first substrate 100 (e.g., Figure 7B The upper side of the paper) is connected to one of the two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200 (e.g., Figure 8 (The left side of the paper). For example, another pixel sharing unit 539 of two pixel sharing units 539 arranged side by side in the V direction of the first substrate 100 (e.g., Figure 7B The lower side of the paper) is connected to another pixel shared unit 539 of the two pixel shared units 539 arranged side by side in the H direction of the second substrate 200 (e.g., the lower side of the paper) is connected to the other pixel shared unit 539 of the two pixel shared units 539 arranged side by side in the H direction of the second substrate 200 (e.g., the lower side of the paper) Figure 8 (The right side of the paper).

[0168] For example, in two pixel sharing units 539 arranged side by side in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is approximately equal to the layout obtained by reversing the internal layout of the other pixel sharing unit 539 in the V and H directions. The effect achieved by this layout will be explained below.

[0169] In the two pixel sharing units 539 arranged side by side in the V direction of the first substrate 100, each pad portion 120 is disposed in the middle portion of the outline shape of the pixel sharing unit 539, that is, in the V direction and H direction of the pixel sharing unit 539. Figure 7B The middle portion of the second substrate 200. Meanwhile, the pixel sharing unit 539 of the second substrate 200 has a generally rectangular outline shape that is longer in the V direction as described above. Therefore, for example, the amplifying transistor AMP connected to the pad portion 120 is arranged at a position offset from the middle of the pixel sharing unit 539 in the V direction towards the upper side of the paper. For example, when two pixel sharing units 539 arranged side-by-side in the H direction of the second substrate 200 have the same internal layout, the distance between the amplifying transistor AMP of one pixel sharing unit 539 and the pad portion 120 (e.g., the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper in FIG. 7) is relatively short. However, the distance between the amplifying transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (e.g., the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper in FIG. 7) is longer. Therefore, the wiring area required for connection between the amplifying transistor AMP and the pad portion 120 is increased, which may complicate the wiring layout of the pixel sharing unit 539. This will affect the miniaturization of the imaging device 1.

[0170] In contrast, the internal layout of the two pixel sharing units 539 arranged side-by-side in the H direction of the second substrate 200 is reversed at least in the V direction, which allows for a reduction in the distance between the amplification transistor AMP and the pad portion 120 of the two pixel sharing units 539. Therefore, compared to the same internal layout of the two pixel sharing units 539 arranged side-by-side in the H direction of the second substrate 200, it is easier to miniaturize the imaging device 1. It should be noted that the planar layout of each of the plurality of pixel sharing units 539 in the second substrate 200 is... Figure 8 The area shown is symmetrical from left to right. However, including those described later... Figure 9 The layout of the first wiring layer W1 shown is asymmetrical.

[0171] Furthermore, preferably, the internal layout of the two pixel-shared units 539 arranged side-by-side in the H direction of the second substrate 200 is also reversed relative to each other in the H direction. The reason for this will be explained below. Figure 9As shown, the two pixel sharing units 539 arranged side-by-side in the H direction of the second substrate 200 are both connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are arranged in the middle portion of the two pixel sharing units 539 arranged side-by-side in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged side-by-side in the H direction). Therefore, the internal layout of the two pixel sharing units 539 arranged side-by-side in the H direction of the second substrate 200 is also reversed in the H direction, which makes it possible to reduce the distance between each of the plurality of pixel sharing units 539 of the second substrate 200 and the pad portions 120 and 121. That is, it is easier to miniaturize the camera device 1.

[0172] Furthermore, the position of the outline of the pixel sharing unit 539 of the second substrate 200 may not be aligned with the position of the outline of one of the pixel sharing units 539 of the first substrate 100. For example, one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (e.g., Figure 9 On the left side of the paper, on one side in the V direction (e.g., Figure 9 The outline of the upper side of the paper) is arranged in the corresponding pixel common unit 539 of the first substrate 100 (e.g., Figure 7B The outer side of the contour on one side in the V direction (the upper side of the paper). Furthermore, another pixel sharing unit 539 (e.g., one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200) is located on the outer side of the paper. Figure 9 On the right side of the paper, on the other side in the V direction (e.g., Figure 9 The outline of the lower side of the paper) is arranged in the corresponding pixel common unit 539 of the first substrate 100 (e.g., Figure 9 The outer side of the contour on the other side in the V direction (the lower side of the paper). As described above, by arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 in relation to each other, the distance between the amplification transistor AMP and the pad portion 120 can be shortened. Therefore, the imaging device 1 can be easily miniaturized.

[0173] Furthermore, the outlines of the multiple pixel-sharing units 539 on the second substrate 200 can be misaligned. For example, two pixel-sharing units 539 arranged side-by-side in the H direction on the second substrate 200 can be arranged with their outlines offset in the V direction. This allows for a reduction in the distance between the amplification transistor AMP and the pad portion 120. This facilitates the miniaturization of the camera device 1.

[0174] Reference Figure 7B and Figure 9This describes the repeating arrangement of the pixel sharing units 539 in the pixel array section 540. The pixel sharing units 539 of the first substrate 100 have dimensions corresponding to two pixels 541 in the H direction and dimensions corresponding to two pixels 541 in the V direction. Figure 7B For example, in the pixel array portion 540 of the first substrate 100, pixel sharing units 539 having a size corresponding to four pixels are arranged adjacent to each other in the H direction with a distance of two pixel intervals (corresponding to the distance between two pixels 541) and in the V direction with a distance of two pixel intervals (corresponding to the distance between two pixels 541). Alternatively, in the pixel array portion 540 of the first substrate 100, a pair of pixel sharing units 539 arranged as two pixel sharing units 539 arranged adjacent to each other in the V direction may be provided. For example, in the pixel array portion 540 of the first substrate 100, pairs of pixel sharing units 539 are arranged adjacent to each other in the H direction with a distance of two pixel intervals (corresponding to the distance between two pixels 541) and in the V direction with a distance of four pixel intervals (corresponding to the distance between four pixels 541). The pixel sharing unit 539 of the second substrate 200 has a size corresponding to one pixel 541 in the H direction and a size corresponding to four pixels 541 in the V direction. Figure 9 For example, in the pixel array section 540 of the second substrate 200, a pair of pixel sharing units 539 are provided, each including two pixel sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and offset from each other in the V direction. For example, in the pixel array section 540 of the second substrate 200, multiple pairs of pixel sharing units 539 are arranged adjacent to each other without gaps in the H direction at a distance of two pixel intervals (corresponding to the distance between two pixels 541) and in the V direction at a distance of four pixel intervals (corresponding to the distance between four pixels 541). This repeating arrangement of the pixel sharing units 539 makes it possible to arrange the pixel sharing units 539 without gaps. This makes it easy to miniaturize the camera device 1.

[0175] Preferably, the amplifying transistor AMP has, for example, a fin-type ( Figure 6 Three-dimensional structures, such as fin-type amplifier transistors (AMPs), include a fin (described later) that contains a portion of the semiconductor layer 200S. Figure 13 Fin 230), and gate electrode having multiple flat surfaces opposite to the fin (described later). Figure 13 The transistor has a gate electrode 231 and a gate insulating film disposed between the gate electrode and the fin. A transistor with a three-dimensional structure is either a transistor in which multiple flat surfaces of a gate electrode opposite to the channel are disposed, or a transistor in which a curved surface of a gate electrode is disposed around the channel. Such a transistor with a three-dimensional structure has the same area as a planar transistor (…). Figure 8In the case of a three-dimensional transistor, the effective gate width of the transistor can be increased compared to a planar transistor. Therefore, a larger current flows through the transistor with the three-dimensional structure, thereby increasing the transconductance gm. Compared to a planar transistor, this allows for an increase in the operating speed of the transistor with the three-dimensional structure. Furthermore, RN (random noise) can be reduced. In addition, the transistor with the three-dimensional structure has a larger gate area compared to a planar transistor, which reduces RTS noise. Here, the amplifying transistor AMP corresponds to a specific example of the "pixel transistor" of the present invention. A more specific structure of the amplifying transistor AMP will be described later.

[0176] Using such a three-dimensional transistor in at least one of the amplifying transistor AMP, the selecting transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG improves transistor characteristics, for example, to enhance image quality. In particular, the amplifying transistor AMP includes a transistor with a three-dimensional structure, which allows for effective noise reduction and improved image quality. Furthermore, the amplifying transistor AMP, the selecting transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG can all be constructed using transistors with three-dimensional structures. This facilitates the fabrication of the pixel circuit 210.

[0177] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and multiple wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221, for example, contacts the front surface of the semiconductor layer 200S and covers the entire front surface of the semiconductor layer 200S. The passivation film 221 covers the respective gate electrodes of the select transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is disposed between the passivation film 221 and the third substrate 300. The multiple wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4) are separated by the interlayer insulating film 222. The interlayer insulating film 222 includes, for example, silicon oxide.

[0178] In the wiring layer 200T, for example, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202 are sequentially disposed starting from the semiconductor layer 200S side. The interlayer insulating film 222 includes a plurality of connection portions that connect the first wiring layer W1, the second wiring layer W1, the third wiring layer W3, or the fourth wiring layer W4 and the layers below them to each other. The connection portion is a portion in which conductive material is embedded in a connection hole provided in the interlayer insulating film 222. For example, the interlayer insulating film 222 includes a connection portion 218V that connects the first wiring layer W1 and the VSS contact region 218V of the semiconductor layer 200S to each other. For example, the aperture of such a connection portion that connects the components of the second substrate 200 to each other is different from the aperture of the through electrode 120E, the through electrode 121E, and the through electrode TGV. Specifically, the aperture of the connection holes connecting the components of the second substrate 200 to each other is preferably smaller than the apertures of the through electrodes 120E, 121E, and TGV. The reason for this is explained below. The depth of the connection portions (such as connection portion 218V) provided in the wiring layer 200T is less than the depth of the through electrodes 120E, 121E, and TGV. Therefore, conductive material can be easily embedded in the connection holes compared to the through electrodes 120E, 121E, and TGV. By making the aperture of the connection portions smaller than the apertures of the through electrodes 120E, 121E, and TGV, the imaging device 1 can be easily miniaturized.

[0179] For example, the through electrode 120E is connected to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG via the first wiring layer W1 (specifically, the connection hole reaches the source of the FD conversion gain switching transistor FDG). For example, the first wiring layer W1 connects the through electrode 121E and the connection portion 218V to each other, which electrically connects the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S to each other.

[0180] Next, we will refer to Figures 10 to 12 Explain the planar structure of the 200T wiring layer. Figure 10 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown. Figure 11 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown. Figure 12 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0181] For example, the third wiring layer W3 includes wiring TRG1, wiring TRG2, wiring TRG3 and wiring TRG4, wiring SELL, wiring RSTL and wiring FDGL extending along the H direction (row direction). Figure 11 These wirings correspond to the reference. Figure 4 The multiple row drive signal lines 542 are described above. Lines TRG1, TRG2, TRG3, and TRG4 transmit drive signals to the transmission gates TG1, TG2, TG3, and TG4, respectively. Lines TRG1, TRG2, TRG3, and TRG4 are connected to the transmission gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through electrode 120E, respectively. Line SELL transmits a drive signal to the gate of the select transistor SEL, line RSTL transmits a drive signal to the gate of the reset transistor RST, and line FDGL transmits a drive signal to the gate of the FD conversion gain switching transistor FDG. Lines SELL, RSTL, and FDGL are connected to the gates of the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG, respectively, via the second wiring layer W2, the first wiring layer W1, and the connecting portion.

[0182] For example, the fourth wiring layer W4 includes a power line VDD, a reference potential line VSS, and a vertical signal line 543 extending along the V direction (column direction). Figure 12 The power line VDD is connected to the drain of the amplifying transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. Furthermore, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0183] Contact portions 201 and 202 may be disposed at positions overlapping with the pixel array portion 540 in the plan view (e.g., Figure 3 Alternatively, it can be disposed in the peripheral portion 540B outside the pixel array portion 540 (e.g., Figure 6Contact portions 201 and 202 are disposed on the front surface of the second substrate 200 (the surface on the side of the wiring layer 200T). Contact portions 201 and 202 may comprise metals such as Cu (copper) and Al (aluminum). Contact portions 201 and 202 are exposed on the front surface of the wiring layer 200T (the surface on the side of the third substrate 300). Contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300, and for bonding between the second substrate 200 and the third substrate 300.

[0184] Figure 6 An example of peripheral circuitry disposed in the peripheral portion 540B of the second substrate 200 is shown. The peripheral circuitry may include a portion of the row drive unit 520, a portion of the column signal processor 550, etc. Furthermore, as... Figure 3 As shown, the peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, and the connection hole portion H1 and the connection hole portion H2 may be arranged near the pixel array portion 540.

[0185] For example, the third substrate 300 sequentially includes a wiring layer 300T and a semiconductor layer 300S starting from the second substrate 200 side. For example, the front surface of the semiconductor layer 300S is disposed on the second substrate 200 side. The semiconductor layer 300S includes a silicon substrate. Circuitry is disposed in a portion of the semiconductor layer 300S on the front surface side. Specifically, for example, at least a portion of the input section 510A, the row drive section 520, the timing controller 530, the column signal processor 550, the image signal processor 560, and the output section 510B are disposed on the front surface side of the semiconductor layer 300S. The wiring layer 300T disposed between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, multiple wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. Contact portions 301 and 302 are exposed on the front surface of the wiring layer 300T (the surface on the second substrate 200 side). Contact portion 301 is connected to contact portion 201 of the second substrate 200, and contact portion 302 is connected to contact portion 202 of the second substrate 200. Contact portions 301 and 302 are electrically connected to a circuit formed in the semiconductor layer 300S (e.g., at least one of input portion 510A, row drive portion 520, timing controller 530, column signal processor 550, image signal processor 560, and output portion 510B). Contact portions 301 and 302 may include metals such as Cu (copper) and aluminum (Al). For example, external terminal TA is connected to input portion 510A through connection hole portion H1, and external terminal TB is connected to output portion 510B through connection hole portion H2.

[0186] [The detailed structure of an amplifier transistor (AMP)]

[0187] The following section will explain the specific construction of the amplifying transistor AMP.

[0188] Figure 13 yes Figure 6 The schematic cross-sectional view shown is of the amplifying transistor AMP and the vicinity of the through electrode 120E. Figure 14 Shown in magnified form Figure 13 The amplifying transistor AMP is shown. For example, the amplifying transistor AMP is located closer to the through electrode 120E than other transistors included in the pixel circuit 210. The amplifying transistor AMP includes, for example, a fin 230 and a gate electrode 231. A gate insulating film (not shown) is disposed between the fin 230 and the gate electrode 231. The fin 230 is formed by partially etching the semiconductor layer 200S. For example, the amplifying transistor AMP includes a fin along the channel length direction (perpendicular to the channel). Figure 13 Two fins 230 extending in the direction of the paper. For example, the two fins 230 are configured to be separated from each other, with an insulating film 232 sandwiched between them. The insulating film 232 includes silicon oxide (SiO) and the like. An amplifying transistor AMP may include one fin 230 or may include three or more fins 230.

[0189] For example, a gate electrode 231 is provided from the semiconductor layer 200S to the wiring layer 200T. A portion of the thickness direction of the gate electrode 231 ( Figure 13 The lower part of the paper surface) is embedded in the semiconductor layer 200S (or insulating region 212), and another part ( Figure 13 The upper portion of the paper surface is disposed in the wiring layer 200T. A gate electrode 231 is also embedded between the two fins 230. An insulating region 212 or an insulating film 232 is disposed between the gate electrode 231 and the bonding film 124. Such a gate electrode 231 faces multiple surfaces of the fins 230. In other words, the gate electrode 231 faces the fins 230 in multiple directions. Specifically, the gate electrode 231 is configured to face a pair of side surfaces of each of the two fins extending along the trench length direction and a top surface connecting the pair of side surfaces of each of the two fins 230. For example, the upper portion of the pair of side surfaces of each fin 230 faces the gate electrode 231, and the lower portion of the pair of side surfaces of each fin 230 is covered with the insulating film 232 or the insulating region 212. For example, the bottom surface of each of the two fins 230 is in contact with the bonding film 124.

[0190] The gate electrode 231 has a front surface 231f opposite to the top surface of the fin 230 (the front surface of the semiconductor layer 200S), and a pair of side surfaces 231s disposed in a direction intersecting the front surface 231f. Figure 14For example, the front surface 231f is generally parallel to the first substrate 100 and is disposed in the wiring layer 200T. For example, a pair of side surfaces 231s are configured to be generally perpendicular to the front surface 231f. The pair of side surfaces 231s are opposite to each other, and two fins 230 are sandwiched between the pair of side surfaces 231s. In this embodiment, the gate electrode 231 is configured to contact the through electrode 120E. Therefore, as will be detailed later, the area of ​​the gate electrode 231 is increased compared to the case where the gate electrode 231 and the through electrode 120E are arranged separately, specifically, the area in the channel width direction.

[0191] One of the pair of side surfaces 231s of the gate electrode 231 is configured to be adjacent to and in contact with a portion of the through electrode 120E. More specifically, a portion of the through electrode 120E disposed in the wiring layer 200T and the semiconductor layer 200S (insulating region 212) partially contacts the side surface 231s of the gate electrode 231. For example, one side surface 231s contacts the through electrode 120E in the thickness direction of the gate electrode 231. A portion of the other side surface 231s in the thickness direction is covered by a passivation film 221, and the remaining portion is buried in the insulating region 212. For example, the front surface 231f is covered by the passivation film 221.

[0192] The characteristics of camera device 1 will be described below.

[0193] Typically, a camera device includes a photodiode and a pixel circuit as its main components. Here, increasing the area of ​​the photodiode increases the charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal, resulting in more favorable image data (image information) output by the camera device. Simultaneously, increasing the size of the transistors included in the pixel circuit (specifically, enlarging the size of the transistors) reduces the noise generated in the pixel circuit, thus improving the S / N ratio of the captured signal, resulting in more favorable image data (image information) output by the camera device.

[0194] However, it is conceivable that in an imaging device where the photodiode and pixel circuit are disposed on the same semiconductor substrate, increasing the area of ​​the photodiode within a limited area of ​​the semiconductor substrate would reduce the size of the transistors included in the pixel circuit. Furthermore, it is conceivable that increasing the size of the transistors included in the pixel circuit would reduce the area of ​​the photodiode.

[0195] To address these issues, the imaging device 1 according to this embodiment employs a structure in which multiple pixels 541 share a single pixel circuit 210, and the shared pixel circuit 210 is arranged superimposed on a photodiode PD. This allows the area of ​​the photodiode PD to be maximized within the limited area of ​​the semiconductor substrate, and the size of the transistors included in the pixel circuit 210 to be maximized. This enables an improvement in the signal-to-noise ratio (S / N) of the pixel signal, thereby allowing the imaging device 1 to output more favorable image data (image information).

[0196] In a structure where multiple pixels 541 share a single pixel circuit 210 and the pixel circuit 210 is arranged superimposed on a photodiode PD, multiple wirings extend from each of the floating diffuser portions FD of the multiple pixels 541 and connect to the pixel circuit 210. To ensure a large area of ​​the second substrate 200 in which the pixel circuit 210 is formed, for example, a connection wiring can be formed that connects the multiple extending wirings to each other to combine them into a single wiring. For multiple wirings extending from the VSS contact region 118, a connection wiring can be formed that connects the multiple wirings to each other to combine them into a single wiring.

[0197] For example, it is conceivable that when a connecting wire extending from the various floating diffusion portions FD of the plurality of pixels 541 to each other is formed in the second substrate 200 in which the pixel circuit 210 is formed, the area of ​​the transistors included in the pixel circuit 210 to be formed is reduced. Similarly, it is conceivable that when a connecting wire extending from the VSS contact regions 118 of the plurality of pixels 541 to each other to combine them into one is formed in the second substrate 200 in which the pixel circuit 210 is formed, the area of ​​the transistors included in the pixel circuit 210 to be formed is reduced.

[0198] To address these issues, for example, the camera device 1 according to this embodiment may have a structure in which a plurality of pixels 541 share a single pixel circuit 210, and the shared pixel circuit 210 is arranged superimposed on a photodiode PD, and a structure in which a connection wiring is provided in the first substrate 100 to connect the floating diffusion portions FD of the plurality of pixels 541 to each other to combine them into one, and a connection wiring to connect the connection VSS contact areas 118 included in the plurality of pixels 541 to each other to combine them into one.

[0199] Here, when using the second manufacturing method described above as a method for providing a connection wiring in the first substrate 100 that connects the floating diffuser portions FD of a plurality of pixels 541 to each other to form a single connection wiring, and connects the VSS contact areas 118 of a plurality of pixels 541 to each other to form a single connection wiring, a suitable process corresponding to the structure of the first substrate 100 and the second substrate 200 can be used for manufacturing, and an imaging device with high quality and high performance can be manufactured. Furthermore, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, when using the second manufacturing method described above, electrodes connected to the floating diffuser portions FD and electrodes connected to the VSS contact areas 118 are provided on the front surfaces of the first substrate 100 and the second substrate 200, which form the bonding interface between the first substrate and the second substrate. Furthermore, even if displacement occurs between the electrodes provided on the front surfaces of the first substrate 100 and the second substrate 200 when the two substrates are bonded together, it is preferable to enlarge the electrodes formed on the front surfaces of the two substrates in order to make the electrodes formed on the front surfaces of the two substrates contact each other. In this case, it is considered difficult to arrange the aforementioned electrodes in the limited area of ​​each pixel included in the imaging device 1.

[0200] To address the issue of requiring a large electrode at the interface between the first substrate 100 and the second substrate 200, for example, in the imaging device 1 according to this embodiment, the first manufacturing method described above can be used as a method for multiple pixels 541 sharing a single pixel circuit 210 and arranging the shared pixel circuit 210 to be superimposed on a photodiode PD. This facilitates the alignment of elements formed in the first substrate 100 and the second substrate 200 and enables the manufacture of an imaging device with high quality and high performance. Furthermore, unique structures formed using this manufacturing method can be included. That is, a structure in which the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 are stacked sequentially; that is, a structure in which the first substrate 100 and the second substrate 200 are stacked face to back, and includes through electrodes 120E and through electrodes 121E that penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front surface side of the semiconductor layer 200S of the second substrate 200 and reach the front surface of the semiconductor layer 100S of the first substrate 100.

[0201] In a structure in which the first substrate 100 is provided with a connection wiring that connects the floating diffuser portions FD of a plurality of pixels 541 to each other to combine them into one and a connection wiring that connects the VSS contact regions 118 of a plurality of pixels 541 to combine them into one, the first manufacturing method is used to stack the structure and the second substrate 200, and the pixel circuit 210 is formed in the second substrate 200, this causes the heat treatment required for forming the active elements included in the pixel circuit 210 to affect the aforementioned connection wiring formed in the first substrate 100.

[0202] Therefore, in order to solve the problem that the heat treatment used to form the above-mentioned active elements affects the connection wiring, in the imaging device 1 according to this embodiment, it is desirable to use a conductive material with high heat resistance for the connection wiring that connects the floating diffuser portions FD of a plurality of pixels 541 to each other to combine them into one, and for the connection wiring that connects the VSS contact areas 118 of a plurality of pixels 541 to each other to combine them into one. Specifically, as a conductive material with high heat resistance, a material having a higher melting point than at least some of the wiring materials included in the wiring layer 200T of the second substrate 200 can be used.

[0203] As described above, for example, the imaging device 1 according to this embodiment includes: (1) a structure in which a first substrate 100 and a second substrate 200 are stacked face-to-back (specifically, wherein the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 are stacked sequentially), (2) through electrodes 120E and 121E are configured to penetrate from the front surface side of the semiconductor layer 200S of the second substrate 200 through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 to the front surface of the semiconductor layer 100S of the first substrate 100, and (3) The connection wiring that connects the floating diffusers FD included in the plurality of pixels 541 to each other to combine them into one and the connection wiring that connects the VSS contact areas 118 included in the plurality of pixels 541 to each other to combine them into one are formed using a conductive material with high heat resistance. This makes it possible to provide the connection wiring that connects the floating diffusers FD included in the plurality of pixels 541 to each other to combine them into one and the connection wiring that connects the VSS contact areas 118 included in the plurality of pixels 541 to each other to combine them into one in the first substrate 100 without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.

[0204] [Operation of Camera Device 1]

[0205] Next, we will use Figure 15 and Figure 16 Explain the operation of camera device 1. Figure 15 and Figure 16Corresponding to Figure 3 Arrows have been added to indicate the paths of each signal. Figure 15 The path from the external input to the input signal, power supply potential, and reference potential of the camera device 1 is shown by arrows. Figure 16 The signal path of the pixel signal output from the imaging device 1 to the outside is shown by the arrow. For example, the input signal (e.g., pixel clock and synchronization signal) input to the imaging device 1 through the input unit 510A is transmitted to the row driving unit 520 of the third substrate 300, and a row driving signal is generated in the row driving unit 520. The row driving signal is transmitted to the second substrate 200 through the contact unit 301 and the contact unit 201. In addition, the row driving signal reaches the individual pixel common units 539 of the pixel array unit 540 through the row driving signal line 542 of the wiring layer 200T. Among the row driving signals that have reached the pixel common units 539 of the second substrate 200, the driving signal other than the driving signal for transmitting the gate TG is input to the pixel circuit 210 to drive the individual transistors included in the pixel circuit 210. The drive signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV to drive pixels 541A, 541B, 541C, and 541D. Figure 15 Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contact section 301 and contact section 201, and then supplied to the pixel circuit 210 of each pixel common unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to pixels 541A, 541B, 541C, and 541D of the first substrate 100 via through electrode 121E. At the same time, the pixel signals that are photoelectrically converted in pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to each pixel common unit 539 of the pixel circuit 210 of the second substrate 200 via through electrode 120E. The pixel signals based on these pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via vertical signal line 543 and contact section 202 and contact section 302. The pixel signal is processed in the column signal processor 550 and image signal processor 560 of the third substrate 300, and then output to the outside through the output unit 510B. Figure 16 ).

[0206] [Effect]

[0207] In the imaging device 1 according to this embodiment, the gate electrode 231 of the amplifying transistor AMP is configured to contact a portion of the through electrode 120E. Compared to the case where the gate electrode 231 is arranged separately from the through electrode 120E, this increases the area of ​​the gate electrode 231. The effect and benefits of this will be explained using comparative examples.

[0208] Figure 17 The cross-sectional structure of the main part of the camera device (camera device 1000) according to the comparative example is shown. Figure 17 With the camera device 1 shown Figure 13 Correspondingly, in the imaging device 1000, the gate electrode 231 of the amplifying transistor AMP is arranged separately from the through electrode 120E. The semiconductor layer 200S on which the channel of the amplifying transistor AMP is formed is set to be spaced apart from the through electrode 120E by a distance K1, and the imaging device 1000 differs from the imaging device 1 in this respect.

[0209] In such an imaging device 1000, the size of the amplifying transistor AMP is limited by the following distances K1 and K2. Distance K1 is the distance between the semiconductor layer 200S on which the channel of the amplifying transistor AMP is formed and the through electrode 120E. Distance K2 is the distance between the side surface of the fin 230 and the side surface 231s of the gate electrode 231. In the imaging device 1000, the gate electrode 231 and the through electrode 120E are disposed separately; therefore, it is difficult to increase distance K2. That is, it is difficult to sufficiently increase the area of ​​the gate electrode 231, which may degrade transistor characteristics such as transconductance gm. This increases RTS (Random Telegraph Signal) noise, and RTS noise may affect image data.

[0210] Figure 18 The distance K1, which specifies the size of the amplifying transistor AMP in the imaging device 1, is shown. In this embodiment, the side surface 231s of the gate electrode 231 contacts the through electrode 120E in such a way that the size of the amplifying transistor AMP is not affected by the distance between the fin 230 and the side surface 231s of the gate electrode 231. Figure 17 The limitation of distance K2). In other words, in the imaging device 1, it is sufficient to consider only the distance K1 between the semiconductor layer 200S on which the amplifying transistor is formed and the through electrode 120E. Therefore, the area of ​​the gate electrode 231 in the channel width direction can be increased. This makes it possible to increase the size of the amplifying transistor AMP and improve transistor characteristics such as transconductance gm. Therefore, in the imaging device 1, it is possible to reduce the RST noise of the signal output from the amplifying transistor AMP and output image data with high quality.

[0211] Furthermore, forming the through electrode 120E after forming the amplifying transistor AMP allows for self-alignment along the side surface 231s of the gate electrode 231. At this time, no misalignment occurs between the amplifying transistor AMP and the through electrode 120E. This allows for reduced design margins, making it easier to increase the area of ​​the gate electrode 231 in the channel width direction. Therefore, even in this respect, the size of the amplifying transistor AMP can be increased.

[0212] Furthermore, in this embodiment, pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and pixel circuit 210 are disposed on different substrates (first substrate 100 and second substrate 200). Compared to the case where pixels 541A, 541B, 541C, and 541D and pixel circuit 210 are formed on the same substrate, this allows for an increase in the area of ​​pixels 541A, 541B, 541C, and 541D and pixel circuit 210. This, in turn, increases the amount of pixel signal obtained through photoelectric conversion and reduces the transistor noise of pixel circuit 210. Therefore, the signal-to-noise ratio of the pixel signal can be improved, thereby enabling the imaging device 1 to output more favorable pixel data (image information). In addition, the imaging device 1 can be miniaturized (in other words, the pixel size is reduced and the size of the imaging device 1 is reduced). The reduction in pixel size allows for an increase in the number of pixels per unit area, thereby enabling the imaging device 1 to output images with high image quality.

[0213] Furthermore, in the camera device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other through through electrodes 120E and 121E disposed in the insulating region 212. For example, methods to bond the first substrate 100 and the second substrate 200 together by bonding pad electrodes together, and methods to connect the first substrate 100 and the second substrate 200 to each other by through-wires (e.g., TSVs) that penetrate the semiconductor layer, are conceivable. Compared to these methods, providing through electrodes 120E and 121E in the insulating region 212 makes it possible to reduce the area required for the connection between the first substrate 100 and the second substrate 200. This allows for a reduction in pixel size and further miniaturization of the imaging device 1. Furthermore, the further miniaturization of the pixel area allows for a further increase in resolution. Without reducing the chip size, the formation areas of pixels 541A, 541B, 541C, and 541D, as well as the pixel circuit 210, can be enlarged. This, in turn, makes it possible to increase the amount of pixel signal obtained by photoelectric conversion and reduce the noise of the transistors contained in the pixel circuit 210. This makes it possible to improve the signal-to-noise ratio of the pixel signal, thereby allowing the imaging device 1 to output more favorable pixel data (image information).

[0214] Furthermore, in the imaging device 1, the pixel circuit 210, column signal processor 550, and image signal processor 560 are disposed on different substrates (second substrate 200 and third substrate 300). Compared to the case where the pixel circuit 210, column signal processor 550, and image signal processor 560 are formed on the same substrate, the area of ​​the pixel circuit 210 and the areas of the column signal processor 550 and image signal processor 560 can be increased. This allows for the reduction of noise generated in the column signal processor 550 and the installation of more advanced image processing circuitry in the image signal processor 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, thereby enabling the imaging device 1 to output more favorable pixel data (image information).

[0215] Furthermore, in the imaging device 1, a pixel array section 540 is disposed in the first substrate 100 and the second substrate 200, and a column signal processor 550 and an image signal processor 560 are disposed in the third substrate 300. Additionally, contact portions 201, 202, 301, and 302 connecting the second substrate 200 and the third substrate 300 to each other are formed above the pixel array section 540. This allows for the free arrangement of the contact portions 201, 202, 301, and 302, unaffected by the various types of wiring included in the pixel array. Therefore, the contact portions 201, 202, 301, and 302 can be used for electrical connections between the second substrate 200 and the third substrate 300. For example, the use of contact portions 201, 202, 301, and 302 increases the flexibility of the layout in the column signal processor 550 and the image signal processor 560. This allows for the reduction of noise generated in the column signal processor 550 and the installation of more advanced image processing circuitry in the image signal processor 560. Therefore, the signal-to-noise ratio of the pixel signals can be improved, resulting in the camera device 1 outputting more favorable pixel data (image information).

[0216] Furthermore, in the imaging device 1, the pixel separation section 117 penetrates the semiconductor layer 100S. This allows color mixing between pixels 541A, 541B, 541C, and 541D to be suppressed even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) decreases due to the miniaturization of the pixel area. Therefore, the signal-to-noise ratio of the pixel signal can be improved, resulting in the imaging device 1 outputting more favorable pixel data (image information).

[0217] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for the shared unit 539 for each pixel. Therefore, compared to the case where the pixel circuit 210 is provided for each of pixels 541A, 541B, 541C, and 41D, the formation area of ​​the transistors (amplifier transistor AMP, reset transistor RST, select transistor SEL, and FD conversion gain switching transistor FDG) included in the pixel circuit 210 can be expanded. For example, expanding the formation area of ​​the amplifier transistor AMP can suppress noise. Therefore, the signal-to-noise ratio of the pixel signal can be improved, thereby enabling the imaging device 1 to output more favorable pixel data (image information).

[0218] Furthermore, in the imaging device 1, pad portions 120 electrically connecting the floating diffusion portions FD (floating diffusion portion FD1, floating diffusion portion FD2, floating diffusion portion FD3, and floating diffusion portion FD4) of four pixels (pixels 541A, 541B, 541C, and 541D) to each other are provided in the first substrate 100. Therefore, compared to providing such pad portions 120 in the second substrate 200, the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 200 to each other can be reduced. This allows for a smaller insulating region 212 and ensures a sufficiently large formation area (semiconductor layer 200S) for the transistors included in the pixel circuit 210. This enables the reduction of noise in the transistors included in the pixel circuit 210, which in turn improves the signal-to-noise ratio of the pixel signal, thereby allowing the imaging device 1 to output more favorable pixel data (image information).

[0219] Furthermore, in the imaging device 1, the transistors included in the pixel circuit 210, such as the amplifying transistor AMP, include transistors with a three-dimensional structure. Compared to the use of planar transistors, this allows for an increase in the effective gate width while maintaining the footprint. Therefore, transistor performance (e.g., operating speed and RN) can be improved without hindering pixel miniaturization. Moreover, the increased gate area allows for a reduction in RTS noise. This enables more effective suppression of the impact of noise on the image.

[0220] Furthermore, in this embodiment, regarding the second substrate 200, an example has been described in which the amplifying transistor AMP, the reset transistor RST, and the selection transistor SEL, which are permitted to be included in the pixel circuit 210, are formed in a single semiconductor layer 200S; however, at least one transistor may be formed in semiconductor layer 200S-1, and the remaining transistors may be formed in semiconductor layer 200S-2, which is different from semiconductor layer 100S and semiconductor layer 200S-1. Although semiconductor layer 200S-2 is not shown, for example, an insulating layer, interconnects, and interconnect wiring are formed above semiconductor layer 200S-1 (corresponding to semiconductor layer 200S), and semiconductor layer 200S-2 is further stacked thereon. This other semiconductor layer 200S-2 is stacked on the surface opposite to the surface of semiconductor layer 100S stacked on the interlayer insulating film 123, and the desired transistors can be formed in semiconductor layer 200S-2. As an example, an amplification transistor AMP can be formed in semiconductor layer 200S-1, and a reset transistor RST and / or a selection transistor SEL can be formed in semiconductor layer 200S-2.

[0221] Furthermore, multiple other semiconductor layers can be provided, and one of the desired transistors of the pixel circuit 210 can be provided in each of the other semiconductor layers. As an example, an amplification transistor AMP can be formed in semiconductor layer 200S-1. Furthermore, if an insulating layer, connection portion, and connection wiring are stacked on semiconductor layer 200S, and semiconductor layer 200S-2 is further stacked thereon, a reset transistor RST can be formed in semiconductor layer 200S-2. If an insulating layer, connection portion, and connection wiring are stacked on semiconductor layer 200S-2, and semiconductor layer 200S-3 is further stacked thereon, a selection transistor SEL can be formed in semiconductor layer 200S-3. The transistors formed in semiconductor layers 200S-1, 200S-2, and 200S-3 can be any transistor included in the pixel circuit 210.

[0222] Therefore, the structure of having multiple semiconductor layers in the second substrate 200 allows for a reduction in the area of ​​the semiconductor layer 200S occupied by one pixel circuit 210. If the area of ​​each pixel circuit 210 can be reduced or each transistor can be miniaturized, then the chip area can also be reduced. Furthermore, the area of ​​desired transistors, such as the amplifying transistor, reset transistor, and select transistor included in the pixel circuit 210, can be increased. In particular, increasing the area of ​​the amplifying transistor allows for the expectation of noise reduction effects.

[0223] It should be noted that, as described above, when the pixel circuit 210 is formed in multiple semiconductor layers (e.g., semiconductor layer 200S-1, semiconductor layer 200S-2, and semiconductor layer 200S-3), for example, as in the modified example 13 described later. Figure 53 As shown, in the substrate (wiring layer 1210) containing the gate electrode 23 of the amplifying transistor AMP, the gate electrode 231 can be configured to contact the wiring L1002 (corresponding to the through electrode 1210). Furthermore, as... Figure 54 As shown, wiring L1002 (corresponding to through electrode 120) is configured to contact the source of reset transistor RST disposed in semiconductor layer 1221.

[0224] The following describes variations of the camera device 1 according to the above embodiment. In the following variations, the same components as in the above embodiment are indicated by the same reference numerals.

[0225] <2. Variation Example 1>

[0226] Figure 19 A modified example of the cross-sectional structure of the main part of the camera device according to the above embodiment is shown. Figure 19 The schematic diagram illustrates the cross-sectional structure near the amplifying transistor AMP and the through electrode 120E, and corresponds to the embodiment described above. Figure 13 .

[0227] In this modified example, the side surface 231s and the front surface 231f of the gate electrode 231 are in contact with the through electrode 120E. The imaging device 1 according to this modified example differs in this respect from the imaging device described in the above embodiment.

[0228] For example, the end of the front surface 231f of the gate electrode 231 on the side of the through electrode 120E is exposed from the passivation film 221. The through electrode 120E contacts the portion of the gate electrode 231 from the end of the front surface 231f to the side surface 231s. Only the side surface 231s of the gate electrode contacts the through electrode 120E (e.g., Figure 13 Compared to the previous contact configuration, this allows for an increase in the contact area between the gate electrode 231 and the through electrode 120E.

[0229] The imaging device 1 according to this modification also achieves effects similar to those described in the above embodiments. Furthermore, the contact area between the gate electrode 231 and the through electrode 120E can be increased, which improves the stability of the connection between them.

[0230] <3. Variation Example 2>

[0231] Figure 20(A) and (B) show variations in the construction of the main parts of the camera device 1 according to this embodiment. Figure 20 (A) schematically illustrates the cross-sectional structure near the amplifying transistor AMP and the through electrode 120E, and corresponds to the embodiment described above. Figure 13 . Figure 20 (B) schematically shows Figure 20 The planar structure of the gate electrode 231 shown in (A).

[0232] In this modified example, a through-hole 231M through which the through electrode 120E is inserted is provided in the gate electrode 231. The imaging device 1 according to this modified example differs from the imaging device 1 described in the above embodiment in this respect.

[0233] The through-hole 231M penetrates the gate electrode 231 in the thickness direction from the front surface 231f to the rear surface opposite to the front surface 231f. Figure 20 (A)). The through-hole 231M is located at a position that does not overlap with the fin 230 in the plan view. For example, the through-hole 231M is arranged in the plan view at a position closer to the side surface 231s of the gate electrode 231 than multiple fins 230 arranged side by side in the channel width direction. Figure 20 (B)

[0234] A through-hole 120E is disposed at a position overlapping with the through-hole 231M of the gate electrode 231 in the plan view and is inserted into the through-hole 231M. The through-hole 120E contacts the gate electrode 231 on the inner circumferential surface of the through-hole 231M. For example, the through-hole 120E contacts the gate electrode 231 in the circumferential direction of the through-hole 231M and also contacts the gate electrode 231 in the length direction (thickness direction of the gate electrode 231) of the through-hole 231M. A configuration in which only the side surface of the gate electrode 231 contacts the through-hole 120E (e.g., Figure 13 In contrast, providing a through hole 231M in the gate electrode 231 into which the through electrode 120E is inserted increases the contact area between the gate electrode 231 and the through electrode 120E.

[0235] The imaging device 1 according to this modification also achieves effects similar to those described in the above embodiments. Furthermore, the contact area between the gate electrode 231 and the through electrode 120E can be increased, which improves the stability of the connection between them. Moreover, the through electrode 120E is inserted into the through hole 231M of the gate electrode 231, which further prevents misalignment between the gate electrode 231 and the through electrode 120E during its formation. In this respect, the stability of the connection between the gate electrode 231 and the through electrode 120E can also be improved.

[0236] <4. Variation Example 3>

[0237] Figure 21 A modified example of the cross-sectional structure of the main part of the camera device according to the above embodiment is shown. Figure 21 The schematic diagram illustrates the cross-sectional structure near the amplifying transistor AMP and the through electrode 120E, and corresponds to the embodiment described above. Figure 13 .

[0238] In this modified example, a connecting portion 230c is provided between adjacent fins 230. The camera device 1 according to this modified example differs from the camera device 1 described in the above embodiment in this respect.

[0239] A connection portion 230c connects to a plurality of fins 230 arranged side-by-side in the channel width direction. For example, when forming fins 230 from semiconductor layer 200S, the connection portion 230c is formed by leaving semiconductor layer 200S between adjacent fins 230. That is, the connection portion 230c is constructed using a portion of semiconductor layer 200S. The height of the connection portion 230c (the dimension in the thickness direction of semiconductor layer 200S) is, for example, smaller than the height of the fins 230. The connection portion 230c is configured to connect the lower portions (the portions on the first substrate 100 side) of adjacent fins 230 to each other. That is, the connection portion 230c can be provided to replace the insulating film 232 described in the above embodiment. Figure 13 Compared to a structure in which an insulating film 232 is provided between adjacent fins 230, the connection portion 230c that connects adjacent fins 230 to each other increases the area of ​​the channel forming the amplifying transistor AMP.

[0240] For example, the through electrode 120E makes partial contact with the gate electrode 231 from the end of the front surface 231f to the side surface 231s. This allows for improved stability of the connection between the gate electrode 231 and the through electrode 120E in a manner similar to that described in Modification 1 above. The through electrode 120E may only contact the side surface 231s of the gate electrode 231 (see Figure 1). Figure 13 Alternatively, a through-hole can be provided in the gate electrode 231, and the through electrode 120E can contact the gate electrode 231 on the inner circumferential surface of the through-hole (see reference). Figure 20 (A) and (B)).

[0241] The imaging device 1 according to this modification also achieves effects similar to those described in the above embodiments. Furthermore, the connection portion 230c provided between adjacent fins 230 allows for an increase in the size of the amplification transistor AMP. This enables more effective improvement of transistor characteristics such as transconductance gm.

[0242] <5. Variation Example 4>

[0243] Figure 22 A modified example of the cross-sectional structure of the main part of the camera device 1 according to the above embodiment is shown. Figure 22 The schematic diagram illustrates the cross-sectional structure near the amplifying transistor AMP and the through electrode 120E, and corresponds to the embodiment described above. Figure 13 .

[0244] In this variation, the amplifying transistor AMP includes a planar transistor. The imaging device 1 according to this variation differs in this respect from the imaging device 1 described in the above embodiment.

[0245] The amplifying transistor AMP includes a semiconductor layer 200S, a gate electrode 231 opposite to the semiconductor layer 200S, and a gate insulating film (not shown) disposed between the gate electrode 231 and the semiconductor layer 200S. The gate electrode 231 includes, for example, a horizontal portion 231H opposite to the front surface of the semiconductor layer 200S and a sidewall portion 231W intersecting the horizontal portion 231H. For example, the sidewall portion 231W is configured to be substantially perpendicular to the horizontal portion 231H.

[0246] The horizontal portion 231H is configured to be substantially parallel to the plane of the semiconductor layer 200S. The horizontal portion 231H is disposed between the semiconductor layer 200S and the passivation film 221, more specifically, between the gate insulating film and the passivation film 221. For example, the front surface 231f of the gate electrode 231 is disposed in the horizontal portion 231H, and the front surface 231f is covered by the passivation film 221.

[0247] The sidewall portion 231W is connected to the horizontal portion 231H. The sidewall portion 231W is disposed between the horizontal portion 231H and the through electrode 120E, and between the semiconductor layer 200S (more specifically, the gate insulating film) and the through electrode 120E. That is, the dimension of the sidewall portion 231W in the height direction is larger than the dimension of the horizontal portion 231H in the thickness direction. The sidewall portion 231W is configured to face one of a pair of side surfaces of the semiconductor layer 200S extending in the channel length direction (the side surface closer to the through electrode 120E). For example, the sidewall portion 231W is configured to cover one side surface of the semiconductor layer 200S in the thickness direction. For example, the side surface 231s of the gate electrode 231 is disposed in the sidewall portion 231W.

[0248] The through electrode 120E contacts the sidewall portion 231W of the gate electrode 231. For example, the through electrode 120E contacts the sidewall portion 231W in the height direction. As described above, the dimension of the sidewall portion 231W in the height direction is larger than the dimension of the horizontal portion 231H in the thickness direction. Compared to a configuration in which the end surface of the horizontal portion 230H (the surface perpendicular to the front surface 231f) contacts the through electrode 120E, this allows for an increase in the contact area between the through electrode 120E and the gate electrode 231. This improves the stability of the connection between the through electrode 120E and the gate electrode 231.

[0249] The imaging device 1 according to this modification also achieves effects similar to those described in the above embodiments. The amplifying transistor AMP can thus include a planar transistor.

[0250] <6. Variation Example 5>

[0251] Figure 23 A modified example of the cross-sectional structure of the main part of the camera device 1 according to the above embodiment is shown. Figure 23 The schematic diagram illustrates the cross-sectional structure near the amplifying transistor AMP and the through electrode 120E, and corresponds to the embodiment described above. Figure 13 .

[0252] In this variation, the amplifying transistor AMP comprises a planar transistor in a manner similar to that described in Variation 4 above. Furthermore, in the amplifying transistor AMP, a portion of the gate electrode 231 is embedded in the semiconductor layer 200S. The imaging device 1 according to this variation differs from the imaging device 1 described in the above embodiments in this respect.

[0253] In addition to the horizontal portion 231H and the sidewall portion 231W, the gate electrode 231 of the amplifying transistor AMP also includes a vertical portion 231V. The vertical portion 231V is a so-called vertical gate electrode and is embedded in the semiconductor layer 200S in the thickness direction. For example, the upper end of the vertical portion 231V is connected to the middle portion of the horizontal portion 231H.

[0254] The imaging device 1 according to this modification also achieves effects similar to those described in the above embodiments. The gate electrode 231 of the amplifying transistor AMP can include a vertical portion 231V embedded in the semiconductor layer 200S in this manner.

[0255] <7. Variation Example 6>

[0256] Figures 24 to 28 A modified example of the planar structure of the camera device 1 according to the above embodiment is shown. Figure 24The schematic diagram illustrates the planar structure near the front surface of the semiconductor layer 200S of the second substrate 200, and corresponds to the embodiment described above. Figure 8 . Figure 25 The schematic diagram illustrates the structure of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and various portions of the first substrate 100, corresponding to the embodiments described above. Figure 9 . Figure 26 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to the embodiment described above. Figure 10 . Figure 27 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to the embodiment described above. Figure 11 . Figure 28 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to the embodiment described above. Figure 12 .

[0257] In this variation, such as Figure 25 As shown, in two pixel sharing units 539 arranged side-by-side in the H direction of the second substrate 200, the internal layout of one pixel sharing unit 539 (e.g., on the right side of the paper) has a configuration obtained by reversing the internal layout of the other pixel sharing unit 539 (e.g., on the left side of the paper) only in the H direction. Furthermore, the deviation in the V direction between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 is greater than the deviation described in the above embodiment. Figure 9 In this way, increasing the deviation in the V direction makes it possible to reduce the size of the amplifying transistor AMP in the other pixel shared unit 539 and the pad portion connected to the amplifying transistor AMP. Figure 7B The distance between the pad portion 120 of the other (on the lower side of the paper) of the two pixel shared units 539 arranged side by side in the V direction shown. This arrangement allows for the arrangement of the two pixel shared units 539 without having to reverse their planar layout in the V direction. Figures 24 to 28 The modified example 6 of the imaging device 1 shown allows the area of ​​two pixel sharing units 539 arranged side-by-side in the H direction to be the same as the area of ​​the pixel sharing units 539 of the second substrate 200 described in the above embodiment. It should be noted that the planar layout of the pixel sharing units 539 of the first substrate 100 is the same as the planar layout described in the above embodiment (…). Figure 7A and Figure 7B Therefore, the imaging device 1 according to this modification can achieve effects similar to those of the imaging device 1 described in the above embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the above embodiments and this modification.

[0258] <8. Variation Example 7>

[0259] Figures 29 to 34 A modified example of the planar structure of the camera device 1 according to the above embodiment is shown. Figure 29 The planar structure of the first substrate 100 is schematically shown, and corresponds to the embodiment described above. Figure 7A . Figure 30 The schematic diagram illustrates the planar structure near the front surface of the semiconductor layer 200S of the second substrate 200, and corresponds to the embodiment described above. Figure 8 . Figure 31 The schematic diagram illustrates the structure of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and various portions of the first substrate 100, corresponding to the embodiments described above. Figure 9 . Figure 32 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to the embodiment described above. Figure 10 . Figure 33 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to the embodiment described above. Figure 11 . Figure 34 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to the embodiment described above. Figure 12 .

[0260] In this variant, the outlines of each pixel circuit 210 have a roughly square planar shape. Figure 30 (etc.). The planar structure of the camera device 1 according to this modification differs in this respect from the planar structure of the camera device 1 described in the above embodiments.

[0261] For example, the pixel sharing unit 539 of the first substrate 100 is formed above the two rows and two columns of pixel areas in a manner similar to that described in the above embodiment, and has a generally square planar shape. Figure 29For example, in each pixel sharing unit 539, the horizontal portions TGb of the transmission gates TG1 and TG3 of pixels 541A and 541C in one pixel column extend from their position superimposed on the vertical portion TGa toward the middle portion of the pixel sharing unit 539 in the H direction (more specifically, toward the outer edges of pixels 541A and 541C and toward the middle portion of the pixel sharing unit 539), and the horizontal portions TGb of the transmission gates TG2 and TG4 of pixels 541B and 541D in another pixel column extend from their position superimposed on the vertical portion TGa toward the outer side of the pixel sharing unit 539 in the H direction (more specifically, toward the outer edge of the pixel). Pad portions 120 connected to the floating diffusion portion FD are provided in the middle portion of the pixel sharing unit 539 (the middle portion of the pixel sharing unit 539 in the H direction and V direction), and pad portions 121 connected to the VSS contact area 118 are provided in the pixel sharing unit 539 at least in the H direction (in the V direction). Figure 29 The ends in the H and V directions.

[0262] As another arrangement example, it is conceivable that the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 are only disposed in the region opposite to the vertical portion TGa. In this case, the semiconductor layer 200S can be finely divided in a manner similar to that described in the above embodiment. Therefore, it is difficult to form large transistors in the pixel circuit 210. Conversely, when the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 extend along the H direction from the position superimposed on the vertical portion TGa as in the above variation, the width of the semiconductor layer 200S can be increased in a manner similar to that described in the above embodiment. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 in the H direction can be arranged near the position of the through electrode 120E in the H direction, and the positions of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 in the H direction can be arranged near the position of the through electrode 121E in the H direction. Figure 31 This allows the width (dimension along the H direction) of the semiconductor layer 200S extending along the V direction to be increased in a manner similar to that described in the above embodiment. Therefore, the size of the transistors in the pixel circuit 210, particularly the size of the amplification transistor AMP, can be increased. This, in turn, enables an improvement in the signal-to-noise ratio of the pixel signal, thereby allowing the imaging device 1 to output more favorable pixel data (image information).

[0263] The pixel sharing unit 539 of the second substrate 200, for example, has approximately the same size as the pixel sharing unit 539 of the first substrate 100 in the H and V directions, and is disposed above the region approximately corresponding to the two-row, two-column pixel region. For example, in each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side-by-side in the V direction in a semiconductor layer 200S extending along the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side-by-side in the V direction in a semiconductor layer 200S extending along the V direction. A semiconductor layer 200S with the selection transistor SEL and the amplification transistor AMP and a semiconductor layer 200S with the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side-by-side in the H direction, with an insulating region 212 sandwiched between them. The insulating region 212 extends in the V direction ( Figure 30 ).

[0264] Here, we will refer to Figure 30 and Figure 31 The outline of the pixel sharing unit 539 of the second substrate 200 is described. For example, Figure 29 The pixel sharing unit 539 of the first substrate 100 shown is connected to one side of the pad portion 120 in the H direction (in Figure 31 The amplifying transistor AMP and the selecting transistor SEL are located on the left side of the paper, and on the other side of the pad portion 120 in the H direction (in...). Figure 31 The FD conversion gain switching transistor FDG and the reset transistor RST are located on the right side of the paper. The outline of the pixel common unit 539 of the second substrate 200, which includes the amplification transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST, is determined by the following four outer edges.

[0265] The first outer edge is one end of the semiconductor layer 200S, which includes the selection transistor SEL and the amplification transistor AMP, in the V direction. Figure 31 The outer edge of the upper end of the paper. The first outer edge is disposed on the amplifying transistor AMP included in the pixel sharing unit 539 and on one side of the pixel sharing unit 539 in the V direction ( Figure 31 The upper side of the paper) is between the selection transistors SEL included in adjacent pixel shared units 539. More specifically, the first outer edge is disposed in the middle portion of the element isolation region 213 in the V direction between the amplifying transistor AMP and the selection transistor SEL. The second outer edge is the other end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP. Figure 31The outer edge of the lower end of the paper. The second outer edge is disposed on the selection transistor SEL included in the pixel sharing unit 539 and on the other side of the pixel sharing unit 539 in the V direction (at the end of the lower end of the paper). Figure 31 (On the lower side of the paper) Between the amplifying transistors AMP included in the adjacent pixel sharing unit 539. More specifically, the second outer edge is disposed in the middle portion of the element isolation region 213 in the V direction between the select transistor SEL and the amplifying transistor AMP. The third outer edge is the other end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. Figure 31 The third outer edge is located at the lower end of the paper surface in the pixel shared unit 539. The third outer edge is disposed between the FD conversion gain switching transistor FDG included in the pixel shared unit 539 and the reset transistor RST included in the pixel shared unit 539 adjacent to the other side of the pixel shared unit 539 in the V direction. More specifically, the third outer edge is disposed in the middle portion of the element isolation region 213 in the V direction between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is one end of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG in the V direction. Figure 31 The fourth outer edge is located at the outer edge of the upper end of the paper surface. The fourth outer edge is disposed between the reset transistor RST included in the pixel sharing unit 539 and the FD conversion gain switching transistor FDG (not shown) included in the pixel sharing unit 539, which is adjacent to one side (the upper side of the paper surface) of the pixel sharing unit 539 in the V direction. More specifically, the fourth outer edge is disposed in the middle portion of the element isolation region 213 (not shown) in the V direction between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0266] In the outline of the pixel common unit 539 of the second substrate 200, which includes the first outer edge, second outer edge, third outer edge, and fourth outer edge, the third outer edge and fourth outer edge are configured to be biased to one side in the V direction from the first outer edge and the second outer edge (in other words, biased to one side in the V direction). This arrangement allows the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG to be arranged as close as possible to the pad portion 120. This makes it easier to reduce the area of ​​the wiring connecting them and to miniaturize the imaging device 1. It should be noted that the VSS contact region 218 is disposed between the semiconductor layer 200S including the select transistor SEL and the amplifying transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, multiple pixel circuits 210 have the same arrangement as each other.

[0267] The imaging device 1, including this second substrate 200, also achieves effects similar to those described in the above embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the above embodiments and this variation.

[0268] <9. Variation Example 8>

[0269] Figures 35 to 40 A modified example of the planar structure of the camera device 1 according to the above embodiment is shown. Figure 35 The planar structure of the first substrate 100 is schematically shown, and corresponds to the embodiment described above. Figure 7B . Figure 36 The schematic diagram illustrates the planar structure near the front surface of the semiconductor layer 200S of the second substrate 200, and corresponds to the embodiment described above. Figure 8 . Figure 37 The diagram schematically illustrates the structure of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and various portions of the first substrate 100, corresponding to the embodiments described above. Figure 9 . Figure 38 An example of the planar construction of the first wiring layer W1 and the second wiring layer W2 is shown, corresponding to the embodiment described above. Figure 10 . Figure 39 An example of the planar construction of the second wiring layer W2 and the third wiring layer W3 is shown, corresponding to the embodiment described above. Figure 11 . Figure 40 An example of the planar construction of the third wiring layer W3 and the fourth wiring layer W4 is shown, corresponding to the embodiment described above. Figure 12 .

[0270] In this modified example, the semiconductor layer 200S of the second substrate 200 extends along the H direction ( Figure 37 That is, this variation roughly corresponds to the above... Figure 30 The structure obtained by rotating the planar structure of the camera device 1 shown in the figure by 90 degrees.

[0271] For example, the pixel sharing unit 539 of the first substrate 100 is formed above the two rows and two columns of pixel areas in a manner similar to that described in the above embodiment, and has a generally square planar shape. Figure 35For example, in each pixel shared unit 539, the transmission gates TG1 and TG2 of pixels 541A and 541B in one pixel row extend toward the middle portion of the pixel shared unit in the V direction, and the transmission gates TG3 and TG4 of pixels 541C and 541D in another pixel row extend toward the outside of the pixel shared unit 539 in the V direction. A pad portion 120 connected to the floating diffusion portion FD is provided in the middle portion of the pixel shared unit 539, and a pad portion 121 connected to the VSS contact area 118 is provided in the pixel shared unit 539 at least in the V direction. Figure 35 The ends in the H and V directions. At this time, the V-direction positions of the through electrodes TGV1 and TGV2 of the transmission gates TG1 and TG2 are close to the V-direction positions of the through electrode 120E, and the V-direction positions of the transmission gates TGV3 and TGV4 of the through electrodes TGV3 and TGV4 are close to the V-direction positions of the through electrode 121E. Figure 37 Therefore, for reasons similar to those described in the above embodiments, the width (dimension in the V direction) of the semiconductor layer 200S extending in the H direction can be increased. This makes it possible to increase the size of the amplification transistor AMP and suppress noise.

[0272] In each pixel circuit 210, the select transistor SEL and the amplify transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged adjacent to the select transistor SEL in the V direction. The insulating region 212 is sandwiched between the select transistor SEL and the reset transistor RST. Figure 36 The FD conversion gain switching transistor FDG and the reset transistor RST are arranged side-by-side in the H direction. The VSS contact region 218 is arranged in an island shape in the insulating region 212. For example, the third wiring layer W3 extends along the H direction ( Figure 39 ), and the fourth wiring layer W4 extends along the V direction ( Figure 40 ).

[0273] The imaging device 1, including this second substrate 200, also achieves effects similar to those described in the above embodiments. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the above embodiments and this variation. For example, the semiconductor layer 200S described in the above embodiments and variation 6 can extend along the H direction.

[0274] <10. Variation Example 9>

[0275] Figure 41 A modified example of the cross-sectional structure of the camera device 1 according to the above embodiment is shown schematically. Figure 41 Corresponding to the above implementation scheme Figure 3 In this modified example, in addition to contact portions 201, 202, 301, and 302, the imaging device 1 also includes contact portions 203, 204, 303, and 304 at a position opposite to the middle portion of the pixel array portion 540. The imaging device 1 of this modified example differs from the imaging device 1 described in the above-described embodiment in this respect.

[0276] Contact portions 203 and 204 are disposed in the second substrate 200 and exposed at the mating surface with the third substrate 300. Contact portions 303 and 304 are disposed in the third substrate 300 and exposed at the mating surface with the second substrate 200. Contact portions 203 and 304 are in contact with each other. That is, in the imaging device 1, in addition to contact portions 201, 202, 301, and 302, the second substrate 200 and the third substrate 300 are also connected to each other through contact portions 203, 204, 303, and 304.

[0277] Next, use Figure 42 and Figure 43 Explain the operation of camera device 1. Figure 42 The path from the external input to the input signal, power supply potential, and reference potential of the camera device 1 is shown by arrows. Figure 43The signal path of the pixel signal output from the imaging device 1 to the outside is shown by the arrows. For example, the input signal input to the imaging device 1 via the input unit 510A is transmitted to the row drive unit 520 of the third substrate 300, and a row drive signal is generated in the row drive unit 520. The row drive signal is transmitted to the second substrate 200 via the contact unit 303 and the contact unit 203. Furthermore, the row drive signal reaches the individual pixel common units 539 of the pixel array unit 540 via the row drive signal line 542 in the wiring layer 200T. Among the row drive signals that have reached the pixel common units 539 of the second substrate 200, the drive signal other than the drive signal for transmitting the gate TG is input to the pixel circuit 210 to drive the individual transistors included in the pixel circuit 210. The drive signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV to drive pixels 541A, 541B, 541C, and 541D. Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via contact sections 303 and 203, and then supplied to the pixel circuit 210 of the pixel common unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121. Simultaneously, for the pixel-shared unit 539, the pixel signals converted by photoelectric conversion in pixels 541A, 541B, 541C, and 541D of the first substrate 100 are transmitted to the pixel circuit 210 of the second substrate 200. Based on these pixel signals, the pixel signals are transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and contact portions 204 and 304. The pixel signals are processed in the column signal processor 550 and image signal processor 560 of the third substrate 300, and then output to the outside via the output portion 510B.

[0278] The imaging device 1, including contact portions 203, 204, 303, and 304, also achieves effects similar to those described in the above embodiments. The position and number of the contacts, which are the connection targets for wiring via contact portions 303 and 304, can be changed according to the circuit design of the third substrate 300.

[0279] <11. Variation Example 10>

[0280] Figure 44 A modified example of the cross-sectional structure of the camera device 1 according to the above embodiment is shown. Figure 44 Corresponding to the above implementation scheme Figure 6In this modified example, a transmission transistor TR with a planar structure is disposed in the first substrate 100. The imaging device 1 according to this modified example differs in this respect from the imaging device 1 described in the above embodiment.

[0281] The transfer transistor TR includes a transfer gate TG that comprises only the horizontal portion TGb. In other words, the transfer gate TG does not include the vertical portion TGa and is positioned opposite the semiconductor layer 100S.

[0282] The imaging device 1, including the transmission transistor TR with this planar structure, also achieves effects similar to those described in the above embodiments. Furthermore, compared to the case where a vertical transmission gate TG is provided in the first substrate, it is conceivable that providing a planar transmission gate TG in the first substrate 100 to form a photodiode PD closer to the front surface of the semiconductor layer 100S increases the saturation signal quantity (Qs). Moreover, it is conceivable that the method of forming a planar transmission gate TG in the first substrate 100 has fewer manufacturing steps compared to the method of forming a vertical transmission gate TG in the first substrate 100, which prevents negative impacts on the photodiode PD due to manufacturing steps.

[0283] <12. Variation Example 11>

[0284] Figure 45 A modified example of the pixel circuit of the camera device according to the above embodiment is shown. Figure 45 Corresponding to the above implementation scheme Figure 4 In this variation, a pixel circuit 210 is provided for each pixel (pixel 541A). That is, multiple pixels do not share the pixel circuit 210. The imaging device 1 according to this variation differs from the imaging device 1 described in the above embodiment in this respect.

[0285] The imaging device 1 according to this modification is similar to the imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are disposed on different substrates (first substrate 100 and second substrate 200). Therefore, the imaging device 1 according to this modification can also achieve effects similar to those described in the above embodiment.

[0286] <13. Variation Example 12>

[0287] Figure 46A modified example of the planar structure of the pixel separation portion 117 described in the above embodiment is shown. Gaps may be provided in the pixel separation portion 117 surrounding each of pixels 541A, 541B, 541C, and 541D. That is, the pixel separation portion 117 may not completely surround the outer periphery of each of pixels 541A, 541B, 541C, and 541D. For example, the gaps in the pixel separation portion 117 are provided near the pad portion 120 and the pad portion 121 (see reference). Figure 7B ).

[0288] In the above embodiment, it has been described that the pixel separation section 117 has an FTI structure that penetrates the semiconductor layer 100S (see reference). Figure 6 Examples of ), but the pixel separation section 117 may have a structure other than the FTI structure. For example, the pixel separation section 117 may be configured not to completely penetrate the semiconductor layer 100S and may have a so-called DTI (deep trench isolation) structure.

[0289] <14. Variation Example 13>

[0290] In the above embodiments, a structure has been described in which a wiring electrically connected to the floating diffuser FD (i.e., a floating diffuser contact) and a wiring electrically connected to the well layer WE (i.e., a well contact) are arranged in each of the plurality of sensor pixels. However, the embodiments of the present invention are not limited thereto. In the embodiments of the present invention, one floating diffuser can be provided for each plurality of sensor pixels. For example, a floating diffuser contact can be shared by four sensor pixels that are adjacent to each other. Similarly, one well contact can be provided for each plurality of sensor pixels. For example, a well contact can be shared by four sensor pixels that are adjacent to each other.

[0291] Figures 47 to 49 This is a cross-sectional view in the thickness direction of a construction example of the imaging device 1A according to a variation 13 of the present invention. Figures 50 to 52 This is a cross-sectional view in the horizontal direction of an example layout of multiple pixel units PU according to a variation 13 of the present invention. It should be noted that... Figures 47 to 49 The cross-section shown is for illustrative purposes only and is not intended to represent the actual structure with strict accuracy. Figures 47 to 49 In the cross-sectional view shown, in order to easily illustrate the arrangement of the imaging device 1A on paper, the positions of the transistor and the impurity diffusion layer in the horizontal direction are intentionally changed from position sec1 to position sec3.

[0292] Specifically, in Figure 47 In the pixel unit PU of the camera device 1A shown, the cross-section at position sec1 is along... Figure 50The cross-section of line A1-A1' at position sec2 is along... Figure 51 The cross-section of line B1-B1' at position sec3 is along... Figure 52 The cross-section of line C1-C1'. Similarly, in Figure 48 In the camera device 1A shown, the cross-section at position sec1 is along... Figure 50 The cross-section of line A2-A2' at position sec2 is along... Figure 51 The cross section of B2-B2', at position sec3, is along... Figure 52 The cross-section of line C2-C2'. Figure 49 In the camera device 1A shown, the cross-section at position sec1 is along... Figure 50 The cross-section of line A3-A3', at position sec2, is along... Figure 51 The cross section of B3-B3', at position sec3, is along... Figure 53 The cross section of line C3-C3'.

[0293] like Figure 48 and Figure 52 As shown, in the imaging device 1A, a common pad electrode 1102 spanning multiple sensor pixels 1012 and a wiring L1002 disposed on the common pad electrode 1102 are shared. For example, in the imaging device 1A, there exists a region in which the floating diffusers FD1 to FD4 of four sensor pixels 1012 are adjacent to each other in a plan view, with the element separation layer 1016 sandwiched between them. The common pad electrode 1102 is disposed in this region. The common pad electrode 1102 is configured to span the four floating diffusers FD1 to FD4 and is electrically connected to each of the four floating diffusers FD1 to FD4. The common pad electrode 1102, for example, comprises a polycrystalline silicon film doped with n-type or p-type impurities.

[0294] A wiring L1002 (i.e., floating diffuser contact) is provided in the central portion of the common pad electrode 1102. For example... Figure 48 and Figures 50 to 52 As shown, the wiring L1002 provided on the central portion of the common pad electrode 1102 extends from the first substrate 1010 through the lower substrate 1210 of the second substrate 1020 to the upper substrate 1220 of the second substrate 1020, and is connected to the gate electrode AG of the amplifying transistor AMP through wiring provided in the upper substrate 1220.

[0295] In addition, such as Figure 47 and Figure 52As shown, in the imaging device 1A, a common pad electrode 1110 spanning multiple sensor pixels 1012 and a wiring L1010 disposed on the common pad electrode 1110 are shared. For example, in the imaging device 1A, there is a region in which the well layers WE of four sensor pixels 1012 are adjacent to each other in a plan view and the component separation layer 1016 is sandwiched therebetween. The common pad electrode 1110 is disposed in this region. The common pad electrode 1110 is arranged to span the well layers WE of the four sensor pixels 1012 and is electrically connected to each of the well layers WE of the four sensor pixels 1012. As an example, the common pad electrode 1110 is disposed between a common pad electrode 1102 and another common pad electrode 1102 arranged side by side in the Y-axis direction. In the Y-axis direction, the common pad electrode 1102 and the common pad electrode 1110 are arranged side by side alternately. The common pad electrode 1110 includes, for example, a polycrystalline silicon film doped with n-type or p-type impurities.

[0296] A wiring L1010 (i.e., a well contact) is provided in the central portion of the common pad electrode 1110. For example... Figure 47 and Figures 49 to 52 As shown, the wiring L1010 provided on the central portion of the common pad electrode 1110 extends from the first substrate 1010 through the lower substrate 1210 of the second substrate 1020 to the upper substrate 1220 of the second substrate 1020, and is connected to a reference potential line that supplies a reference potential (e.g., ground potential: 0V) through wiring provided in the upper substrate 1220.

[0297] A wiring L1010 disposed in the central portion of the common pad electrode 1110 is electrically connected to the top surface of the common pad electrode 1110, the inner surface of the through hole disposed in the lower substrate 1210, and the inner surface of the through hole disposed in the upper substrate 1220. Therefore, the well layer WE of the semiconductor substrate 1011 of the first substrate portion 1010 and the well layers of the lower substrate 1210 and the upper substrate 1220 of the second substrate portion 1020 are connected to a reference potential (e.g., ground potential: 0V).

[0298] The imaging device 1A according to Modification 13 of the present invention has effects similar to those of the imaging device 1 according to the embodiment. Furthermore, the imaging device 1A also includes a common pad electrode 1102 and a common pad electrode 1110 disposed on one side of the front surface 11a of the semiconductor substrate 1011 included in the first substrate portion 1010 and arranged to span a plurality (e.g., four) of adjacent sensor pixels 1012. The common pad electrode 1102 is electrically connected to the floating diffusion region FD of the four sensor pixels 1012. The common pad electrode 1110 is electrically connected to the well layer WE of the four sensor pixels 1012. This allows the wiring L1002 connected to the floating diffusion region FD to be shared by every four sensor pixels 1012. This allows the wiring L1010 connected to the well layer WE to be shared by every four sensor pixels 1012. This allows the number of wirings L1002 and L1010 to be reduced, which allows the area of ​​the sensor pixels 1012 to be reduced and the size of the imaging device 1A to be smaller.

[0299] <23. Application Examples>

[0300] Figure 55 An example of a schematic construction of a camera system 7 including a camera device 1 according to any of the above embodiments and their variations is shown.

[0301] The camera system 7 is an electronic device. Examples of electronic devices include camera devices such as digital cameras or camcorders, and portable terminal devices such as smartphones or tablet computers. The camera system 7 includes, for example, a camera device 1, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248 according to any of the above embodiments and their variations. In the camera system 7, the camera device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, operation unit 247, and power supply unit 248 according to any of the above embodiments and their variations are interconnected via a bus 249.

[0302] The imaging device 1, according to any of the above embodiments and their variations, outputs image data corresponding to the incident light. The DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the imaging device 1 according to any of the above embodiments and their variations. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 in units of frames. The display unit 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL (electroluminescent) panel, and displays moving or still images captured by the imaging device 1 according to any of the above embodiments and their variations. The storage unit 246 records the image data of the moving or still images captured by the imaging device 1 according to any of the above embodiments and their variations in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 according to the user's operation. The power supply unit 248 supplies various types of power for operation to the camera device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246 and operation unit 247, which are the supply targets according to any of the above embodiments and their modifications.

[0303] Next, the recording process of camera system 7 will be explained.

[0304] Figure 56 An example flowchart of the camera operation of the camera system 7 is shown. The user instructs to start recording by operating the operation unit 247 (step S101). Then, the operation unit 247 sends a recording command to the camera device 1 (step S102). Upon receiving the recording command, the camera device 1 (specifically, the system control circuit 36) performs recording using a predetermined recording method (step S103).

[0305] The imaging device 1 outputs the image data acquired through imaging to the DSP circuit 243. Here, image data refers to the data of all pixels based on the pixel signal generated by the charge temporarily held in the floating diffuser FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 causes the frame memory 244 to hold the image data after predetermined signal processing, and the frame memory 244 causes the storage unit 246 to store the image data (step S105). In this way, imaging in the imaging system 7 is performed.

[0306] In this application example, the camera device 1 according to any of the above embodiments and their variations is applied to the camera system 7. This makes the camera device 1 smaller or more accurate, enabling the provision of a small or high-resolution camera system 7.

[0307] <24. Practical Application Examples>

[0308] [Practical Application Example 1]

[0309] The technology according to the present invention (the technology) can be applied to various products. For example, the technology according to the present invention can be implemented in the form of a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, robots, etc.

[0310] Figure 57 This is a block diagram illustrating an example of a schematic construction of a vehicle control system, which is an example of a mobile body control system to which the technology according to embodiments of the present invention can be applied.

[0311] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 57 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / visual output unit 12052, and an in-vehicle network interface (I / F) 12053, which are functional components of the integrated control unit 12050, are shown.

[0312] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for devices such as internal combustion engines, drive motors and other drive force generating devices for generating vehicle driving force, drive force transmission mechanisms for transmitting driving force to the wheels, steering mechanisms for adjusting the vehicle's steering angle, and braking devices for generating vehicle braking force.

[0313] The body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, and fog lights. In this case, radio waves or signals from various switches sent from a keyless entry device can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locks, power windows, or lights, etc.

[0314] The exterior information detection unit 12030 detects information about the exterior of the vehicle, which includes the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to image the exterior of the vehicle and receives the image. Based on the received image, the exterior information detection unit 12030 can perform processing to detect objects such as people, vehicles, obstacles, signs, characters on the road surface, or to detect the distance to the aforementioned objects.

[0315] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image, or it can output the electrical signal as information about the measured distance. Furthermore, the light received by the camera unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0316] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0317] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of advanced driver assistance systems (ADAS), including collision avoidance or impact mitigation, following distance-based driving, speed maintenance driving, vehicle collision warning, and lane departure warning.

[0318] Furthermore, by controlling the driving force generating device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control aimed at achieving autonomous driving, etc., which enables the vehicle to drive autonomously without relying on the operation of the driver.

[0319] Furthermore, based on information about the vehicle's exterior obtained by the exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, the microcomputer 12051 can, for instance, perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beam to low beam, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0320] The sound and image output unit 12052 sends an output signal of at least one of sound or image to an output device capable of visually or audibly notifying passengers of the vehicle or external to the vehicle. Figure 57 In the example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. Display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0321] Figure 58 This is a schematic diagram illustrating an example of the installation location of the camera unit 12031.

[0322] exist Figure 58 In the middle, the camera unit 12031 includes camera unit 12101, camera unit 12102, camera unit 12103, camera unit 12104 and camera unit 12105.

[0323] Camera units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper part of the windshield inside the vehicle. Camera unit 12101 on the front nose and camera unit 12105 on the upper part of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Camera units 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Camera unit 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Camera unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0324] Incidentally, Figure 58An example of the imaging range of camera units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of camera unit 12101 located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of camera units 12102 and 12103 located on the side mirrors, respectively. Imaging range 12114 represents the imaging range of camera unit 12104 located on the rear bumper or rear cover. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by camera units 12101 to 12104.

[0325] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0326] For example, based on distance information acquired from camera units 12101 to 12104, microcomputer 12051 can determine the distances of various three-dimensional objects within the camera range 12111 to 12114 and the time changes of said distances (relative speeds relative to vehicle 12100), and thereby extract the closest three-dimensional object, particularly on the driving path of vehicle 12100, traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as vehicle 12100, as the vehicle ahead. Furthermore, microcomputer 12051 can preset the required vehicle-to-vehicle distance and perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, it is possible to perform cooperative control such as autonomous driving, which aims to enable the vehicle to drive automatically without relying on driver operation.

[0327] For example, based on distance information acquired from camera units 12101 to 12104, microcomputer 12501 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 classifies obstacles around vehicle 12100 into obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines the collision risk to indicate the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is therefore a possibility of collision, microcomputer 12051 issues a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering through drive system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collision.

[0328] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. This pedestrian identification is performed, for example, by: extracting feature points from the images captured by the camera units 12101 to 12104 (which are infrared cameras); and performing pattern matching processing on a series of feature points representing object outlines to determine whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. Furthermore, the audio-visual output unit 12052 can also control the display unit 12062 to display icons or similar symbols representing pedestrians at desired locations.

[0329] An example of a mobile body control system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be applied to the camera unit 12031 in the above configuration. Specifically, the camera device 1 according to any of the above embodiments and their variations can be applied to the camera unit 12031. Applying the technology according to the present invention to the camera unit 12031 enables the acquisition of high-resolution captured images with less noise, which enables high-precision control to be performed using the captured images in the mobile body control system.

[0330] [Practical Application Example 2]

[0331] Figure 59 This is a view illustrating an example of a schematic construction of an endoscopic surgical system to which the technology (the technology) according to embodiments of the present invention can be applied.

[0332] exist Figure 59 The image shows a surgeon (physician) 11131 using an endoscopic surgery system 11000 to perform surgery on a patient 11132 in a hospital bed 11133. As shown, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 (such as a pneumoperitoneum tube 11111 and an energy device 11112), a support arm assembly 11120 (on which the endoscope 11100 is supported), and a trolley 11200 on which various devices for endoscopic surgery are mounted.

[0333] Endoscope 11100 includes a tube 11101 and a camera 11102 connected to the proximal end of the tube 11101. The tube 11101 has a region of predetermined length from its distal end for insertion into a body cavity of a patient 11132. In the illustrated example, endoscope 11100 is described as a rigid endoscope having a rigid tube 11101. However, endoscope 11100 may also be a flexible endoscope having a flexible tube 11101.

[0334] The endoscope tube 11101 has an opening at its distal end for mounting an objective lens. A light source device 11203 is connected to the endoscope 11100, such that light generated by the light source device 11203 is guided through a light guide extending inside the endoscope tube 11101 to the distal end of the tube and illuminates the target for observation within the body cavity of the patient 11132 via the objective lens. It should be noted that the endoscope 11100 can be a forward-looking endoscope, or a slant-looking endoscope, or a lateral-looking endoscope.

[0335] An optical system and an image sensor are housed inside the camera 11102, such that reflected light (observation light) from the observed target is focused onto the image sensor by the optical system. The image sensor performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is transmitted as raw data to the camera control unit (CCU) 11201.

[0336] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and centrally controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera 11102 and performs various image processing operations on the image signals for displaying images based on the image signals, such as image processing (de-mosaic processing).

[0337] The display device 11202 displays an image based on an image signal that has been image processed by the CCU 11201 under the control of the CCU 11201.

[0338] The light source device 11203 includes a light source such as a light-emitting diode (LED) and provides illumination light to the endoscope 11100 when imaging the surgical area, etc.

[0339] Input device 11204 is an input interface for endoscopic surgical system 11000. Users can input various types of information or commands into endoscopic surgical system 11000 via input device 11204. For example, users can input commands through endoscope 11100 to change image acquisition conditions (type of illumination light, magnification, or focal length, etc.).

[0340] Treatment tool control device 11205 controls the drive of energy device 11112 used for cauterizing or cutting tissue, sealing blood vessels, etc. Pneumoperitoneum device 11206 delivers gas into the patient's body cavity 11132 via pneumoperitoneum tube 11111 to inflate the cavity, ensuring the field of vision of endoscope 11100 and ensuring the surgeon's working space. Recorder 11207 is a device capable of recording various types of information related to the surgery. Printer 11208 is a device capable of printing various types of information related to the surgery in various formats (e.g., text, images, or graphics).

[0341] It should be noted that the light source device 11203, which provides illumination to the endoscope 11100 when the surgical area is to be imaged, may include a white light source such as an LED, a laser light source, or a combination thereof. When the white light source includes a combination of red, green, and blue (RGB) laser light sources, the white balance adjustment of the captured image can be performed by the light source device 11203 because the output intensity and timing of each color (each wavelength) can be controlled with high precision. Furthermore, in this case, if the laser beams from each RGB laser light source are time-divisionally irradiated onto the observation target, and the driving of the imaging element of the camera 11102 is controlled synchronously with the irradiation timing, images corresponding to each of the R, G, and B colors can also be captured time-divisionally. According to this method, color images can be obtained even without providing a color filter for the imaging element.

[0342] Furthermore, the light source device 11203 can be controlled so that the intensity of the light to be output changes every predetermined time interval. By controlling the driving of the camera device 11102 in sync with the timing of the change in light intensity, images can be acquired in a time-division multiplexing manner and the images can be synthesized, enabling the creation of high dynamic range images without underexposed shadows and overexposed highlights.

[0343] Furthermore, the light source device 11203 can be configured to provide light of a predetermined wavelength band suitable for special light observation. In special light observation, for example, narrow-band light observation can be performed to image a predetermined tissue (e.g., blood vessels on the surface of a mucosa) with high contrast by irradiating light with a narrower wavelength band than that used for ordinary observation (i.e., white light) using wavelength-dependent light absorption in human tissue. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence from body tissue can be observed by irradiating body tissue with excitation light (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent (such as indocyanine green (ICG)) and irradiating the human tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for the special light observation described above.

[0344] Figure 60 It shows Figure 59 A block diagram illustrating an example of the functional construction of camera 11102 and CCU 11201.

[0345] Camera 11102 includes a lens unit 11401, an image capture unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are connected to each other via a transmission cable 11400 for communication.

[0346] Lens unit 11401 is an optical system disposed at the connection position with lens barrel 11101. Observation light captured from the distal end of lens barrel 11101 is guided to camera 11102 and introduced into lens unit 11401. Lens unit 11401 includes a combination of multiple lenses, including zoom lenses and focusing lenses.

[0347] The imaging unit 11402 can contain one (single-plate type) or multiple (multi-plate type) imaging elements. For example, when the imaging unit 11402 is configured as a multi-plate type imaging unit, image signals corresponding to R, G, and B are generated by the imaging elements, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be configured to have a pair of imaging elements for acquiring image signals for the right eye and image signals for the left eye, respectively, for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately understand the depth of living tissue in the surgical area. It should be noted that when the imaging unit 11402 is configured as a stereoscopic imaging unit, multiple systems of lens units 11401 are provided corresponding to each imaging element.

[0348] Furthermore, the camera unit 11402 does not necessarily have to be mounted on the camera 11102. For example, the camera unit 11402 can be mounted inside the lens barrel 11101, immediately behind the objective lens.

[0349] The drive unit 11403 includes an actuator and, under the control of the camera control unit 11405, moves the zoom lens and focusing lens of the lens unit 11401 along the optical axis by a predetermined distance. Therefore, the magnification and focus of the image captured by the camera unit 11402 can be appropriately adjusted.

[0350] Communication unit 11404 includes communication means for sending various types of information to CCU 11201 and receiving various types of information from CCU 11201. Communication unit 11404 transmits image signals acquired from camera unit 11402 as RAW data to CCU 11201 via transmission cable 11400.

[0351] In addition, the communication unit 11404 receives control signals from the CCU 11201 for controlling the drive of the camera 11102 and provides these control signals to the camera control unit 11405. The control information includes information related to shooting conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value when capturing the image, and / or information specifying the magnification and focus of the captured image.

[0352] It should be noted that image capture conditions such as frame rate, exposure value, magnification, or focus can be specified by the user or automatically set by the control unit 11413 of CCU 11201 based on the acquired image signal. In the latter case, endoscope 11100 includes automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions.

[0353] The camera control unit 11405 controls the driving of the camera 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0354] The communication unit 11411 includes communication means for sending various types of information to and receiving various types of information from the camera 11102. The communication unit 11411 receives image signals sent to it from the camera 11102 via a transmission cable 11400.

[0355] In addition, the communication unit 11411 sends control signals to the camera 11102 to control the camera 11102. The image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0356] The image processing unit 11412 performs various image processing operations on the image signal in RAW data form sent to it from the camera 11102.

[0357] The control unit 11413 performs various types of control related to imaging the surgical area, etc., by the endoscope 11100 and displaying the images obtained by imaging the surgical area, etc. For example, the control unit 11413 creates control signals for controlling the drive of the camera 11102.

[0358] Furthermore, the control unit 11413 controls the display device 11202 to display a captured image of the surgical area, etc., based on the image signal that has been processed by the image processing unit 11412. Therefore, the control unit 11413 can use various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can identify surgical tools such as forceps, specific living areas, bleeding, fog when the energy device 11112 is used, etc., by detecting the shape, color, etc., of the edges of objects contained in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition results to display various types of surgical support information in an overlapping manner with the image of the surgical area. When the surgical support information is displayed in an overlapping manner and presented to the surgeon 11131, the workload of the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery with confidence.

[0359] The transmission cable 11400 connecting the camera 11102 and the CCU 11201 is an electrical signal cable capable of electrical signal communication, an optical fiber capable of optical communication, or a composite cable capable of both electrical and optical communication.

[0360] Here, although communication is performed via wired communication using transmission cable 11400 in the illustrated example, communication between camera 11102 and CCU 11201 can also be performed via wireless communication.

[0361] An example of an endoscopic surgical system to which the technology according to the invention can be applied has been described above. In the above configuration, the technology according to the invention can be suitably applied to the camera unit 11402 disposed in the camera 11102 of the endoscope 11100. Applying the technology according to the invention to the camera unit 11402 enables a smaller size or higher resolution of the camera unit 11402, which makes it possible to provide an endoscope 11100 with a small size or high resolution.

[0362] Although the present invention has been described with reference to embodiments, variations thereof, application examples, and practical application examples, the present invention is not limited to the above embodiments and can be modified in various ways. It should be noted that the effects described herein are merely illustrative. The effects of the present invention are not limited to those described herein. The present invention can have effects other than those described herein.

[0363] Furthermore, for example, the present invention can also have the following configuration. In a solid-state imaging device having any of the following configurations, the gate electrode of the pixel transistor is configured to contact a portion of the through electrode, which allows for an increase in the area of ​​the gate electrode and an improvement in the characteristics of the pixel transistor. This allows for a reduction in noise in the signal output from the pixel transistor. (1)

[0365] A solid-state imaging device, comprising:

[0366] The first substrate includes a photoelectric conversion unit and a charge accumulation unit for each pixel, wherein the charge accumulation unit accumulates the signal charge generated in the photoelectric conversion unit;

[0367] A second substrate includes a semiconductor layer and a pixel transistor, the semiconductor layer being stacked on the first substrate, and the pixel transistor including a gate electrode facing the semiconductor layer, and the pixel transistor reading the signal charge of the charge accumulation portion; and

[0368] A through electrode is disposed in the first substrate and the second substrate and electrically connects the first substrate and the second substrate to each other, and the through electrode is in partial contact with the gate electrode. (2)

[0370] According to the solid-state imaging device of (1), the gate electrode faces the semiconductor layer in multiple directions. (3)

[0372] According to the solid-state imaging device described in (1) or (2), wherein

[0373] The semiconductor layer includes at least one fin, and

[0374] The gate electrode faces multiple surfaces of the fin. (4)

[0376] According to the solid-state imaging device described in (3), wherein

[0377] The semiconductor layer includes a plurality of the fins, and

[0378] The semiconductor layer also includes an insulating film disposed between adjacent fins. (5)

[0380] According to the solid-state imaging device described in (3), wherein

[0381] The semiconductor layer includes a plurality of the fins, and

[0382] The semiconductor layer also includes a connection portion that connects adjacent fins. (6)

[0384] The solid-state imaging device according to any one of (1) to (5), wherein the gate electrode has a front surface facing the first substrate and a side surface disposed in a direction intersecting the front surface and in contact with the through electrode. (7)

[0386] According to the solid-state imaging device described in (6), wherein

[0387] The gate electrode includes a horizontal portion and a sidewall portion. The horizontal portion has the front surface, and the sidewall portion has the side surface and is disposed between the semiconductor layer and the through electrode.

[0388] The sidewall portion is disposed in the thickness direction of the semiconductor layer. (8)

[0390] The solid-state imaging device according to (7) further includes a vertical portion connected to the horizontal portion and embedded in a portion of the semiconductor layer in the thickness direction. (9)

[0392] According to the solid-state imaging device of (6), a portion of the front surface of the gate electrode is also in contact with the through electrode. (10)

[0394] The solid-state imaging device according to any one of (1) to (6), wherein

[0395] A through-hole is provided in the gate electrode, and

[0396] The through electrode is in contact with the inner circumferential surface of the through hole. (11)

[0398] The solid-state imaging device according to any one of (1) to (10), wherein

[0399] The second substrate further includes an insulating region separating the semiconductor layer, and

[0400] The through electrode is configured to penetrate the insulating region. (12)

[0402] The solid-state imaging device according to any one of (1) to (11), wherein the pixel transistor is an amplifying transistor. (13)

[0404] According to any one of (1) to (12) the solid-state imaging device, wherein the through electrode electrically connects the charge accumulation portion to the gate electrode of the pixel transistor. (14)

[0406] The solid-state imaging device according to any one of (1) to (13) further includes a common connection portion connected to the plurality of said charge accumulation portions and disposed in the first substrate, wherein

[0407] One end of the through electrode is in contact with the common connection portion.

[0408] List of reference numerals

[0409] This application claims priority to Japanese Patent Application JP2019-118474, filed with the Japan Patent Office on June 26, 2019, the entire contents of which are incorporated herein by reference.

[0410] Those skilled in the art will understand that, within the scope of the appended claims or their equivalents, various modifications, combinations, sub-combinations and variations may occur depending on design requirements and other factors.

Claims

1. A solid-state imaging device, comprising: The first substrate includes a photoelectric conversion unit and a charge accumulation unit for each pixel, wherein the charge accumulation unit accumulates the signal charge generated in the photoelectric conversion unit; A second substrate includes a semiconductor layer and a pixel transistor, the semiconductor layer being stacked on the first substrate, and the pixel transistor including a gate electrode facing the semiconductor layer, and the pixel transistor reading the signal charge of the charge accumulation portion; as well as A through electrode is disposed in the first substrate and the second substrate and electrically connects the first substrate and the second substrate to each other, and the through electrode is in partial contact with the gate electrode, wherein one end of the through electrode is connected to the wiring layer of the second substrate and the other end of the through electrode is connected to the pad portion of the first substrate.

2. The solid-state imaging device according to claim 1, wherein, The gate electrode faces the semiconductor layer in multiple directions.

3. The solid-state imaging device according to claim 1, wherein... The semiconductor layer includes at least one fin, and The gate electrode faces multiple surfaces of the fin.

4. The solid-state imaging device according to claim 3, wherein... The semiconductor layer includes a plurality of the fins, and The semiconductor layer also includes an insulating film disposed between adjacent fins.

5. The solid-state imaging device according to claim 3, wherein... The semiconductor layer includes a plurality of the fins, and The semiconductor layer also includes a connection portion that connects adjacent fins.

6. The solid-state imaging device according to any one of claims 1 to 5, wherein, The gate electrode has a front surface facing the first substrate and a side surface disposed in a direction intersecting the front surface and in contact with the through electrode.

7. The solid-state imaging device according to claim 6, wherein... The gate electrode includes a horizontal portion and a sidewall portion. The horizontal portion has the front surface, and the sidewall portion has the side surface and is disposed between the semiconductor layer and the through electrode. The sidewall portion is disposed in the thickness direction of the semiconductor layer.

8. The solid-state imaging device according to claim 7, further comprising: A vertical portion, which is connected to the horizontal portion and embedded in a portion of the semiconductor layer in the thickness direction.

9. The solid-state imaging device according to claim 6, wherein, A portion of the front surface of the gate electrode also contacts the through electrode.

10. The solid-state imaging device according to any one of claims 1 to 5, wherein A through-hole is provided in the gate electrode, and The through electrode is in contact with the inner circumferential surface of the through hole.

11. The solid-state imaging device according to any one of claims 1 to 5, wherein The second substrate further includes an insulating region separating the semiconductor layer, and The through electrode is configured to penetrate the insulating region.

12. The solid-state imaging device according to any one of claims 1 to 5, wherein, The pixel transistor is an amplifying transistor.

13. The solid-state imaging device according to any one of claims 1 to 5, wherein, The through electrode electrically connects the charge accumulation portion to the gate electrode of the pixel transistor.

14. The solid-state imaging device according to any one of claims 1 to 5, further comprising a common connection portion connected to the plurality of said charge accumulation portions and disposed in the first substrate, wherein One end of the through electrode is in contact with the common connection portion.

Images