Detection circuit and detection method

Abstract

The embodiments of the present application relate to a detection circuit and a detection method, wherein the detection circuit is used to detect the phase information between two clock signals of different frequencies, wherein the two clock signals include a low-frequency clock signal and a high-frequency clock signal, and the detection circuit includes: a signal generation module, which is used to detect the low-frequency clock signal at the edge of the high-frequency clock signal to generate a signal to be sampled, and when the high-frequency clock signal maintains a preset level and the low-frequency clock signal meets a preset condition, a target sampling signal is generated; and a sampling module, which is connected to the signal generation module, is used to detect the signal to be sampled at the edge of the target sampling signal to generate a detection result signal. Based on the detection circuit of the embodiments of the present application, even if the first pulse in a single cycle of the high-frequency clock signal is filtered out, it will not affect the detection result, thereby realizing a detection circuit with high reliability.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of signal detection technology, and in particular, to a detection circuit and a detection method. Background Art

[0002] Phase detection is a method of detecting the phase relationship between two clock signals and generating an output signal corresponding to the phase relationship. Initially, the frequencies of the two clock signals for phase detection were the same, and the traditional phase detection circuit could meet the demand. The continuous development of science and technology has put forward new requirements for phase detection, namely, phase detection for a high-frequency clock signal and a low-frequency clock signal. On the basis of the original phase detection method, by dividing the high-frequency clock signal and then performing phase detection, the function of phase detection for clock signals of different frequencies can be basically realized.

[0003] However, in actual use, the clock signal needs to pass through the input buffer first to improve the performance of the clock signal. However, the clock signal may be delayed after passing through the input buffer, and even the first pulse of the high-frequency clock signal may be filtered out due to factors such as unstable working state, thereby causing the phase detection result to be wrong. Therefore, the reliability of the existing phase detection circuit and detection method is insufficient. Summary of the invention

[0004] Based on this, it is necessary to provide a detection circuit and a detection method to address the problem of insufficient reliability of the phase detection circuit and the detection method.

[0005] A detection circuit for detecting phase information between two clock signals of different frequencies, wherein the two clock signals include a low-frequency clock signal and a high-frequency clock signal, and the detection circuit includes:

[0006] A signal generation module, configured to detect the low-frequency clock signal at the edge of the high-frequency clock signal to generate a signal to be sampled, and to generate a target sampling signal when the high-frequency clock signal maintains a preset level and the low-frequency clock signal meets a preset condition;

[0007] The sampling module is connected to the signal generating module and is used to detect the signal to be sampled at the edge of the target sampling signal to generate a detection result signal.

[0008] In one embodiment, the signal generation module includes:

[0009] a first generating module, wherein a data end of the first generating module is connected to the low-frequency clock signal, a clock end of the first generating module is connected to the high-frequency clock signal, and the first generating module is used to detect the low-frequency clock signal at an edge of the high-frequency clock signal to generate a signal to be sampled;

[0010] A second generating module, wherein a data end of the second generating module is connected to a preset signal, a clock end of the second generating module is connected to the low-frequency clock signal, a control end of the second generating module is connected to the high-frequency clock signal, and the second generating module is used to detect the preset signal at the edge of the low-frequency clock signal when the high-frequency clock signal maintains a preset level to generate a target sampling signal.

[0011] In one embodiment, the data end of the sampling module is connected to the first generation module, the clock end of the sampling module is connected to the second generation module, and the sampling module is used to detect the signal to be sampled at the edge of the target sampling signal to generate a detection result signal.

[0012] In one embodiment, the second generation module includes:

[0013] a first sampling unit, wherein a data end of the first sampling unit is connected to the preset signal, a clock end of the first sampling unit is connected to the low-frequency clock signal, a control end of the first sampling unit is connected to the high-frequency clock signal, and the first sampling unit is used to generate a first sampling signal having the same level state as the preset signal when the low-frequency clock signal outputs a level signal of a first preset condition;

[0014] a second sampling unit, wherein a data end of the second sampling unit is connected to the preset signal, a clock end of the second sampling unit is connected to the low-frequency clock signal, a control end of the second sampling unit is connected to the high-frequency clock signal, and the second sampling unit is used to generate a second sampling signal with the same level state as the preset signal when the low-frequency clock signal outputs a level signal of a second preset condition;

[0015] A logic gate unit, wherein two input ends of the logic gate unit are respectively connected to the first sampling unit and the second sampling unit, and is used to generate the target sampling signal according to the first sampling signal and the second sampling signal.

[0016] In one embodiment, the preset signal is a high level signal, the logic gate unit is an OR gate circuit, and the control end of the first sampling unit and the control end of the second sampling unit are both reset ends.

[0017] In one embodiment, the preset signal is a low level signal, the logic gate unit is a NAND gate circuit, and the control end of the first sampling unit and the control end of the second sampling unit are both set ends.

[0018] In one of the embodiments, the first preset condition is that the low-frequency clock signal continuously outputs a falling edge signal and a rising edge signal in sequence; the second preset condition is that the low-frequency clock signal continuously outputs a rising edge signal and a falling edge signal in sequence.

[0019] In one embodiment, the first sampling unit comprises:

[0020] a first trigger, wherein a data terminal of the first trigger is connected to the preset signal, a clock terminal of the first trigger is connected to the low-frequency clock signal through an inverter, a control terminal of the first trigger is connected to the high-frequency clock signal, and the first trigger is used to generate a first condition signal when the falling edge signal in the first preset condition is detected;

[0021] A second trigger is connected to the first trigger, a clock end of the second trigger is connected to the low-frequency clock signal, a control end of the second trigger is connected to the high-frequency clock signal, and the second trigger is used to delay the first conditional signal to generate the first sampling signal.

[0022] In one embodiment, the second sampling unit comprises:

[0023] a third trigger, wherein a data terminal of the third trigger is connected to the preset signal, a clock terminal of the third trigger is connected to the low-frequency clock signal, a control terminal of the third trigger is connected to the high-frequency clock signal, and the third trigger is used to generate a second condition signal when the rising edge signal in the second preset condition is detected;

[0024] A fourth trigger, wherein the data end of the fourth trigger is connected to the third trigger, the clock end of the fourth trigger is connected to the low-frequency clock signal, the control end of the fourth trigger is connected to the high-frequency clock signal, and the fourth trigger is used to delay the second conditional signal to generate the second sampling signal.

[0025] In one embodiment, each cycle of the high-frequency clock signal includes an odd number of pulse signals, and the first generating module includes:

[0026] A fifth trigger, wherein the data end of the fifth trigger is connected to the low-frequency clock signal, the clock end of the fifth trigger is connected to the high-frequency clock signal, the output end of the fifth trigger is connected to the data end of the sampling module, and the fifth trigger is used to detect the low-frequency clock signal at the edge of the high-frequency clock signal to generate the signal to be sampled.

[0027] In one embodiment, each cycle of the high-frequency clock signal includes an even number of pulse signals, and the first generating module includes:

[0028] a sixth flip-flop, wherein a data terminal of the sixth flip-flop is connected to the low-frequency clock signal, a clock terminal of the sixth flip-flop is connected to the high-frequency clock signal, and the sixth flip-flop is used to detect the low-frequency clock signal at an edge of the high-frequency clock signal to generate an initial signal to be sampled;

[0029] A seventh trigger, wherein the data end of the seventh trigger is connected to the sixth trigger, the clock end of the seventh trigger is connected to the high-frequency clock signal, the output end of the seventh trigger is connected to the data end of the sampling module, and the seventh trigger is used to delay the initial signal to be sampled to generate the signal to be sampled.

[0030] A detection method for detecting phase information between two clock signals of different frequencies, wherein the two clock signals include a low-frequency clock signal and a high-frequency clock signal, and the detection method includes:

[0031] Detecting the low-frequency clock signal at the edge of the high-frequency clock signal to generate a signal to be sampled, and generating a target sampling signal when the high-frequency clock signal maintains a preset level and the low-frequency clock signal meets a preset condition;

[0032] The signal to be sampled is detected at the edge of the target sampling signal to generate a detection result signal.

[0033] In one embodiment, when the high-frequency clock signal maintains a preset level and the low-frequency clock signal satisfies a preset condition, generating a target sampling signal includes:

[0034] When the high-frequency clock signal maintains a preset level, a preset signal is detected at an edge where the low-frequency clock signal meets the preset condition to generate a target sampling signal.

[0035] The detection circuit and detection method described above, the detection circuit is used to detect the phase information between two clock signals of different frequencies, the two clock signals include a low-frequency clock signal and a high-frequency clock signal, and the detection circuit includes: a signal generation module, used to detect the low-frequency clock signal at the edge of the high-frequency clock signal to generate a signal to be sampled, and when the high-frequency clock signal maintains a preset level and the low-frequency clock signal meets a preset condition, a target sampling signal is generated; a sampling module, connected to the signal generation module, used to detect the signal to be sampled at the edge of the target sampling signal to generate a detection result signal. The high-frequency clock signal of the above detection circuit continuously outputs the preset level between two cycles, that is, after the high-frequency clock signal stops, the detection result is output only when the low-frequency clock signal meets the preset condition. Therefore, even if the first pulse in a single cycle of the high-frequency clock signal is filtered out, it will not affect the detection result, thereby realizing a detection circuit with high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a timing diagram of a phase detection result in the prior art;

[0037] Figure 2 is a timing diagram of another phase detection result in the prior art;

[0038] Figure 3 is a schematic block diagram of a detection circuit of an embodiment;

[0039] Figure 4 A timing diagram generated by a detection circuit of an embodiment detecting a low level of a low-frequency clock signal;

[0040] Figure 5 A timing diagram generated by a detection circuit of an embodiment detecting a high level of a low-frequency clock signal;

[0041] Figure 6 is a structural diagram of a detection circuit according to an embodiment;

[0042] Figure 7 is a structural diagram of a detection circuit according to another embodiment;

[0043] Figure 8 FIG. 4 is a structural diagram of a detection circuit according to yet another embodiment.

[0044] Component number description:

[0045] Signal generation module: 100; first generation module: 110; fifth trigger: 111; sixth trigger: 112; seventh trigger: 113; second generation module: 120; first sampling unit: 121; first trigger: 1211; second trigger: 1212; second sampling unit: 122; third trigger: 1221; fourth trigger: 1222; logic gate unit: 123; sampling module: 200 DETAILED DESCRIPTION

[0046] In order to facilitate understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the embodiments of the present application. The terms used herein in the specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0048] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, the first trigger 1211 may be referred to as the second trigger 1212, and similarly, the second trigger 1212 may be referred to as the first trigger 1211. Both the first trigger 1211 and the second trigger 1212 are triggers, but they are not the same trigger.

[0049] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0051] Figure 1 is a timing diagram of a phase detection result in the prior art, refer to Figure 1 , the two clock signals to be detected are CK1 and CK2 respectively, the low-frequency clock signal after passing through the input buffer is CK1_internal, and the high-frequency clock signal is CK2_internal. In the prior art, it is necessary to perform frequency division processing on the high-frequency clock signal CK2_internal to obtain a signal CK2 / 2 with the same frequency as the low-frequency clock signal CK1_internal, and then compare the signal CK2 / 2 with the low-frequency clock signal CK1_internal, so as to obtain the phase information between the two clock signals to be detected. It should be noted that the high frequency and low frequency in the low-frequency clock signal CK1_internal and the high-frequency clock signal CK2_internal refer to the relativity of the frequencies of the two clock signals, that is, the lower frequency of the two clock signals is used as the low-frequency clock signal CK1_internal, and the higher frequency is used as the high-frequency clock signal CK2_internal, and it does not specifically refer to the signal within a certain frequency range as a low-frequency clock signal or a high-frequency clock signal.

[0052] like Figure 1 As shown, in the first cycle, the low level state of the low-frequency clock signal CK1_internal is sampled at the rising edge of the signal CK2 / 2, that is, the low level is detected to generate a detection result. In the second cycle, the first pulse in the high-frequency clock signal CK2_internal is filtered out, and the pulse in the circle of the signal CK2 is lost, resulting in a change in the timing of the divided signal CK2 / 2. The high level state of the low-frequency clock signal CK1_internal is sampled at the rising edge of the signal CK2 / 2, that is, the high level is detected to generate a detection result, and an error occurs in the detection result. Among them, the first cycle and the second cycle refer to the first cycle and the second cycle of the high-frequency clock signal CK2_internal, and refer to Figure 1Each cycle includes multiple rising edge signals set at equal time intervals t1, and each rising edge signal is used to sample the low-frequency clock signal CK1_internal once. Furthermore, the high-frequency clock signal CK2_internal maintains a preset level for a preset duration t2 between two adjacent cycles, and the duration t2 is longer than the above time interval t1. For example, the duration t2 can be equal to the duration of two time intervals t1, thereby distinguishing different cycles.

[0053] Figure 2 is another timing diagram of phase detection results in the prior art, refer to Figure 2 In the first cycle, the high level state of the low-frequency clock signal CK1_internal is sampled at the rising edge of the signal CK2 / 2, that is, the high level is detected to generate a detection result. In the second cycle, the first pulse in the high-frequency clock signal CK2_internal is filtered out, and the pulse in the circle of the signal CK2 is lost, resulting in a change in the timing of the divided signal CK2 / 2. The low level state of the low-frequency clock signal CK1_internal is sampled at the rising edge of the signal CK2 / 2, that is, the low level is detected to generate a detection result, and the detection result is erroneous.

[0054] Therefore, reference Figure 1 to Figure 2 The detection circuit in the prior art may have a problem that the first pulse in the high-frequency clock signal CK2_internal is filtered out, resulting in an erroneous detection result.

[0055] Figure 3 1 is a schematic block diagram of a detection circuit of an embodiment. In this embodiment, the detection circuit is used to detect phase information between two clock signals of different frequencies. The two clock signals include a low-frequency clock signal CK1_internal and a high-frequency clock signal CK2_internal. The above two signals refer to the signals output after the clock signals CK1 and CK2 to be detected pass through the input buffers respectively. It should be noted that in other embodiments, the definitions of the low-frequency clock signal CK1_internal and the high-frequency clock signal CK2_internal are the same as those in this embodiment and will not be repeated.

[0056] refer to Figure 3 The detection circuit includes a signal generating module 100 and a sampling module 200 .

[0057] The signal generating module 100 is used to detect the low-frequency clock signal CK1_internal at the edge of the high-frequency clock signal CK2_internal to generate a sampled signal CK1m2, and to generate a target sampling signal NoCK2 when the high-frequency clock signal CK2_internal maintains a preset level and the low-frequency clock signal CK1_internal meets a preset condition.

[0058] Among them, the low-frequency clock signal CK1_internal and the high-frequency clock signal CK2_internal in the prior art are the same. The low-frequency clock signal CK1_internal of this embodiment is a continuous clock signal, and the high-frequency clock signal CK2_internal is an intermittent clock signal. In each cycle of the high-frequency clock signal, it includes a plurality of high-frequency clock signal pulses, and there is an interval time between two adjacent cycles. During the interval time, the high-frequency clock signal CK2_internal maintains a preset level. Therefore, when the high-frequency clock signal CK2_internal maintains a preset level greater than or equal to a preset duration, it indicates that it is currently in the interval time between two adjacent cycles. It should be noted that in other embodiments, the low-frequency clock signal CK1_internal may also be an intermittent clock signal, and the present invention does not limit this.

[0059] Figure 4 FIG. 1 is a timing diagram of a detection circuit according to an embodiment of the present invention detecting a low level of a low frequency clock signal, referring to FIG. Figure 4 In this embodiment, the rising edge of the target sampling signal NoCK2 is not generated in response to the rising edge or falling edge of the signal within the cycle of the high-frequency clock signal CK2_internal, but is generated between two adjacent cycles of the high-frequency clock signal CK2_internal. Therefore, even if part of the pulses of the signal within the cycle are filtered out or other distortion phenomena occur, it will not affect the target sampling signal NoCK2. The signal to be sampled is generated in response to the edge of the high-frequency clock signal CK2_internal, and the preliminary sampling of the low-frequency clock signal CK1_internal is realized to generate the signal to be sampled CK1m2 that matches the cycle of the high-frequency clock signal CK2_internal.

[0060] Continue to refer Figure 3The sampling module 200 is connected to the signal generating module 100, and is used to detect the sampled signal CK1m2 at the edge of the target sampling signal NoCK2 to generate a detection result signal. Based on the above circuit structure, each cycle of the high-frequency clock signal CK2_internal corresponds to a pulse signal in the target sampling signal NoCK2, and the pulse signal is generated between two adjacent cycles of the high-frequency clock signal CK2_internal. Therefore, like the target sampling signal NoCK2, the detection result signal is not affected by the pulse change within the cycle of the high-frequency clock signal CK2_internal.

[0061] The high-frequency clock signal CK2_internal of the above-mentioned detection circuit continuously outputs a preset level between two cycles, that is, after each cycle of the high-frequency clock signal CK2_internal, the detection result will be output when the low-frequency clock signal meets the preset conditions. Therefore, even if the first pulse in a single cycle of the high-frequency clock signal CK2_internal is filtered out, it will not affect the detection result, thereby realizing a detection circuit with high reliability.

[0062] In one embodiment, continue to refer to Figure 3 The signal generating module 100 includes a first generating module 110 and a second generating module 120 .

[0063] The data end of the first generating module 110 is connected to the low-frequency clock signal CK1_internal, and the clock end of the first generating module 110 is connected to the high-frequency clock signal CK2_internal. The first generating module 110 is used to detect the low-frequency clock signal CK1_internal at the edge of the high-frequency clock signal CK2_internal to generate the sampled signal CK1m2.

[0064] The data end of the second generation module 120 is connected to the preset signal, the clock end of the second generation module 120 is connected to the low-frequency clock signal CK1_internal, and the control end of the second generation module 120 is connected to the high-frequency clock signal CK2_internal. The second generation module 120 is used to detect the preset signal at the edge of the low-frequency clock signal CK1_internal when the high-frequency clock signal CK2_internal maintains the preset level, so as to generate the target sampling signal NoCK2. The preset signal can be a high-level signal or a low-level signal. After the preset signal is detected at the edge of the low-frequency clock signal CK1_internal, the target sampling signal NoCK2 is switched to the same level state as the preset signal to generate a rising edge or a falling edge. For example, if the preset signal is a high-level signal, in response to the edge of the low-frequency clock signal CK1_internal, the target sampling signal NoCK2 is switched from a low-level state to a high-level state to generate a rising edge, thereby sampling the signal to be sampled CK1m2.

[0065] In one embodiment, continue to refer to Figure 3 The data end of the sampling module 200 is connected to the first generation module 110, and the clock end of the sampling module 200 is connected to the second generation module 120. The sampling module 200 is used to detect the sampling signal CK1m2 at the edge of the target sampling signal NoCK2 to generate a detection result signal.

[0066] In one embodiment, the second generation module 120 includes a first sampling unit 121 , a second sampling unit 122 , and a logic gate unit 123 .

[0067] The data end of the first sampling unit 121 is connected to the preset signal, the clock end of the first sampling unit 121 is connected to the low-frequency clock signal CK1_internal, and the control end of the first sampling unit 121 is connected to the high-frequency clock signal CK2_internal. The first sampling unit 121 is used to generate a first sampling signal Z2e with the same level state as the preset signal when the low-frequency clock signal CK1_internal outputs a level signal of a first preset condition.

[0068] The data end of the second sampling unit 122 is connected to the preset signal, the clock end of the second sampling unit 122 is connected to the low-frequency clock signal, the control end of the second sampling unit 122 is connected to the high-frequency clock signal CK2_internal, and the second sampling unit 122 is used to generate a second sampling signal Z2o with the same level state as the preset signal when the low-frequency clock signal CK1_internal outputs a level signal of a second preset condition.

[0069] Among them, continue to refer to Figure 4In the first cycle, the first pulse of the high-frequency clock signal CK2_internal is not filtered out. When the high-frequency clock signal CK2_internal maintains the preset level (in Figure 4 In the embodiment, when the first pulse of the high-frequency clock signal CK2_internal is kept at a low level, the low-frequency clock signal CK1_internal first continuously outputs a rising edge and a falling edge; in the second cycle, the first pulse of the high-frequency clock signal CK2_internal is filtered out, and when the high-frequency clock signal CK2_internal maintains a preset level, the low-frequency clock signal CK1_internal first continuously outputs a rising edge and a falling edge. Therefore, by setting the first sampling unit 121 and the second sampling unit 122, and making the two sampling units sample when the low-frequency clock signal CK1_internal outputs level signals of different preset conditions, it can be ensured that a correct sampling signal can be generated regardless of whether the first pulse of the high-frequency clock signal CK2_internal is filtered out.

[0070] Continue to refer Figure 3 , the two input ends of the logic gate unit 123 are respectively connected to the first sampling unit 121 and the second sampling unit 122, and are used to generate the target sampling signal NoCK2 according to the first sampling signal Z2e and the second sampling signal Z2o. The logic gate unit 123 performs logic processing on the first sampling signal Z2e and the second sampling signal Z2o to select the required sampling signal, i.e., the target sampling signal NoCK2, from the two sampling signals, so as to output the correct phase detection result. Among them, the logic gate unit 123 can be one of the logic gates such as an AND gate, an OR gate, an AND-OR gate, and a NAND gate that can realize the above functions.

[0071] Further, when the preset signal is a high-level signal, in response to the low-frequency clock signal CK1_internal that meets the preset conditions, the first sampling signal Z2e and the second sampling signal Z2o are both switched from a low-level state to a high-level state; when the preset signal is a low-level signal, in response to the low-frequency clock signal CK1_internal that meets the preset conditions, the first sampling signal Z2e and the second sampling signal Z2o are both switched from a high-level state to a low-level state, and different level states need to correspond to different logic gate units 123 to generate the target sampling signal NoCK2. Therefore, there is a corresponding relationship between the logic function of the logic gate unit 123 and the preset signal input by the second generation module 120.

[0072] In one embodiment, the first preset condition is that the low-frequency clock signal CK1_internal continuously outputs a falling edge signal and a rising edge signal in sequence; the second preset condition is that the low-frequency clock signal CK1_internal continuously outputs a rising edge signal and a falling edge signal in sequence. The first sampling unit 121 generates a first sampling signal Z2e in response to the first preset condition, and the second sampling unit 122 generates a second sampling signal Z2o in response to the second preset condition. In this embodiment, regardless of whether the first pulse of the high-frequency clock signal CK2_internal is filtered out, the second sampling signal Z2o is used as the target sampling signal NoCK2 through the logic gate unit 123, thereby ensuring that a correct sampling signal can be generated regardless of whether the first pulse of the high-frequency clock signal CK2_internal is filtered out.

[0073] In one embodiment, the preset signal is a high-level signal, the logic gate unit 123 is an OR gate circuit, and the control end of the first sampling unit 121 and the control end of the second sampling unit 122 are both reset ends. That is, when the control end of the first sampling unit 121 and the control end of the second sampling unit 122 input an enable signal, that is, when the control end inputs a non-preset level signal (for example, in one embodiment, if the preset level is a low level, the control end inputs a high-level signal), the first sampling unit 121 and the second sampling unit 122 both output 0 as the initial output state of the first sampling unit 121 and the second sampling unit 122, so that when the low-frequency clock signal CK1_internal outputs a level signal that meets the first preset condition or the second preset condition, the first sampling signal Z2e or the second sampling signal Z2o is correspondingly switched to the high-level state of the preset signal, that is, the "1" state.

[0074] In one embodiment, the preset signal is a low level signal, the logic gate unit 123 is a NAND gate circuit, and the control end of the first sampling unit 121 and the control end of the second sampling unit 122 are both set ends. That is, when the control end of the first sampling unit 121 and the control end of the second sampling unit 122 input an enable signal, that is, when the control end inputs a non-preset level signal (for example, in one embodiment, if the preset level is a low level, the control end inputs a high level signal), the first sampling unit 121 and the second sampling unit 122 both output 1 as the initial output state of the first sampling unit 121 and the second sampling unit 122, so that when the low-frequency clock signal CK1_internal outputs a level signal that meets the first preset condition or the second preset condition, the first sampling signal Z2e or the second sampling signal Z2o is correspondingly switched to the low level state of the preset signal, that is, the "0" state.

[0075] Figure 6 is a structural diagram of a detection circuit according to an embodiment, Figure 4 and Figure 6 In this embodiment, the first sampling unit 121 includes a first trigger 1211 and a second trigger 1212 .

[0076] The data end of the first trigger 1211 is connected to the preset signal, the clock end of the first trigger 1211 is connected to the low-frequency clock signal CK1_internal through an inverter, the control end of the first trigger 1211 is connected to the high-frequency clock signal CK2_internal, and the first trigger 1211 is used to generate a first condition signal Z1e when a falling edge signal in the first preset condition is detected.

[0077] exist Figure 6 In the embodiment shown, all triggers are D triggers, the control terminals of all triggers are reset terminals, and the reset terminals are enabled at a high level, and the preset signal is a high level signal. When the high-frequency clock signal CK2_internal is at a high level, the first trigger 1211 outputs 0; when the high-frequency clock signal CK2_internal is at a low level, the preset signal Vcc is sampled in response to the rising edge of the inverted signal of the low-frequency clock signal CK1_internal, which is the signal input at the clock terminal of the first trigger 1211, or in other words, the preset signal Vcc is sampled in response to the falling edge of the low-frequency clock signal CK1_internal.

[0078] It can be understood that in this embodiment, when in the pulse period of the high-frequency clock signal CK2_internal, the falling edge of the low-frequency clock signal CK1_internal is in the high-level time period of the high-frequency clock signal CK2_internal, that is, the first trigger 1211 will not sample the preset signal Vcc inputted at the input end. Therefore, during the pulse period of the high-frequency clock signal CK2_internal, the output end of the first trigger 1211 always outputs a low level, and outside the pulse period of the high-frequency clock signal CK2_internal, that is, between two adjacent periods, the first trigger 1211 will sample the preset signal Vcc and generate a rising edge in the first conditional signal Z1e. It should be noted that the above description is only for exemplary explanation. Figure 4 The timing diagram shown is not used to specifically limit the protection scope of the present application, that is, the interval length between adjacent rising edges of the low-frequency clock signal CK1_internal and the interval length between adjacent rising edges of the high-frequency clock signal CK2_internal are not limited to Figure 4In other embodiments, the low-frequency clock signal CK1_internal and the high-frequency clock signal CK2_internal can be adjusted accordingly according to the test requirements, and are not limited to the case where the falling edge of the low-frequency clock signal CK1_internal is in the high-level time period of the high-frequency clock signal CK2_internal. Moreover, for the adjusted other low-frequency clock signal CK1_internal and high-frequency clock signal CK2_internal, the detection circuit based on the embodiment of the present application can also output a correct detection signal.

[0079] The second flip-flop 1212 is connected to the first flip-flop 1211, the clock end of the second flip-flop 1212 is connected to the low-frequency clock signal CK1_internal, the control end of the second flip-flop 1212 is connected to the high-frequency clock signal CK2_internal, the input end of the second flip-flop 1212 is connected to the output end of the first flip-flop 1211, and the second flip-flop 1212 is used to delay the first condition signal Z1e to generate the first sampling signal Z2e. The second flip-flop 1212 is similar to the first flip-flop 1211. Outside the pulse cycle of the high-frequency clock signal CK2_internal, that is, between two adjacent cycles, the first condition signal Z1e is sampled in response to the rising edge of the low-frequency clock signal CK1_internal to generate the first sampling signal Z2e. That is, the first flip-flop 1211 realizes the recognition of the falling edge in the first preset condition, and the second flip-flop 1212 realizes the recognition of the rising edge in the first preset condition, thereby jointly generating the first sampling signal Z2e.

[0080] Continue to refer Figure 6 In one embodiment, the second sampling unit 122 includes a third trigger 1221 and a fourth trigger 1222 .

[0081] The data end of the third trigger 1221 is connected to the preset signal Vcc, the clock end of the third trigger 1221 is connected to the low-frequency clock signal CK1_internal, the control end of the third trigger 1221 is connected to the high-frequency clock signal CK2_internal, and the third trigger 1221 is used to generate a second condition signal Z1o when a rising edge signal in the second preset condition is detected.

[0082] When the high-frequency clock signal CK2_internal is at a high level, the third flip-flop 1221 outputs 0; when the high-frequency clock signal CK2_internal is at a low level, the preset signal Vcc is sampled in response to the signal input at the clock end of the third flip-flop 1221, that is, the rising edge of the low-frequency clock signal CK1_internal. It can be understood that when it is in the pulse cycle of the high-frequency clock signal CK2_internal, the rising edge of the low-frequency clock signal CK1_internal is in the high-level time period of the high-frequency clock signal CK2_internal, that is, the preset signal Vcc input at the input end will not be sampled. Therefore, within the pulse cycle of the high-frequency clock signal CK2_internal, the output end of the third flip-flop 1221 always outputs a low level, and outside the pulse cycle of the high-frequency clock signal CK2_internal, that is, between two adjacent cycles, the third flip-flop 1221 will sample the preset signal Vcc and generate a rising edge in the second conditional signal Z1o.

[0083] The data end of the fourth flip-flop 1222 is connected to the third flip-flop 1221, the clock end of the fourth flip-flop 1222 is connected to the low-frequency clock signal CK1_internal, the control end of the fourth flip-flop 1222 is connected to the high-frequency clock signal CK2_internal, the input end of the fourth flip-flop 1222 is connected to the output end of the third flip-flop 1221, and the fourth flip-flop 1222 is used to delay the second condition signal Z1oZ2e to generate the second sampling signal Z2o. The fourth flip-flop 1222 is similar to the third flip-flop 1221. Outside the pulse cycle of the high-frequency clock signal CK2_internal, that is, between two adjacent cycles, the first condition signal Z1e is sampled in response to the falling edge of the low-frequency clock signal CK1_internal to generate the second sampling signal Z2oZ2e. That is, the third flip-flop 1221 realizes the recognition of the falling edge in the second preset condition, and the fourth flip-flop 1222 realizes the recognition of the rising edge in the second preset condition, thereby jointly generating the second sampling signal Z2o.

[0084] Figure 5 This is a timing diagram generated by a detection circuit of an embodiment for detecting a high level of a low-frequency clock signal, referring to Figure 5 When detecting a high level, the sampling logic and Figure 4The logic for detecting a low level is similar. That is, when the high-frequency clock signal CK2_internal maintains a low level, in response to the falling edge and rising edge generated successively in the low-frequency clock signal CK1_internal, the detection circuit generates a rising edge in the first sampling signal Z2e, and in response to the rising edge and falling edge generated successively in the low-frequency clock signal CK1_internal, the detection circuit generates a rising edge in the second sampling signal Z2o. Figure 4 and Figure 5 It can be seen that the detection circuit of this embodiment can be applied to two different sampling modes, namely high-level sampling and low-level sampling, and has high flexibility and compatibility.

[0085] Furthermore, the logic gate circuit of this embodiment is an OR gate, that is, when at least one of the first sampling signal Z2e and the second sampling signal Z2o is at a high level, the target sampling signal NoCK2 is at a high level, thereby obtaining an accurate target sampling signal NoCK2.

[0086] Figure 7 is a structural diagram of a detection circuit of another embodiment, refer to Figure 7 In this embodiment, the control terminals of all triggers are set terminals, and the set terminals are enabled at a high level, and the preset signal is a low level signal. When the high-frequency clock signal CK2_internal is at a high level, each trigger outputs 1; when the high-frequency clock signal CK2_internal is at a low level, each trigger responds to the signal input at the clock terminal and samples the preset signal Vss input at the input terminal. Therefore, when the high-frequency clock signal CK2_internal is at a low level, the first trigger 1211 samples the preset signal Vss in response to the falling edge of the low-frequency clock signal CK1_internal to generate a falling edge in the first condition signal Z1e, and delays the first condition signal Z1e through the second trigger 1212 to generate a first sampling signal Z2e. Correspondingly, the third trigger 1221 samples the preset signal Vss in response to the rising edge of the low-frequency clock signal CK1_internal to generate a falling edge in the second condition signal Z1o, and delays the second condition signal Z1o through the second trigger 1212 to generate a second sampling signal Z2o.

[0087] Furthermore, the logic gate unit 123 of this embodiment is a NAND gate, that is, when at least one of the first sampling signal Z2e and the second sampling signal Z2o is at a low level, the target sampling signal NoCK2 is at a high level, thereby obtaining an accurate target sampling signal NoCK2.

[0088] Figure 8FIG. 2 is a structural diagram of a detection circuit of another embodiment. The detection circuit of this embodiment is applicable to a high-frequency clock signal CK2_internal including an odd number of pulse signals in each cycle. Figure 8 The first generating module 110 includes a fifth trigger 111, a data end of the fifth trigger 111 is connected to the low-frequency clock signal CK1_internal, a clock end of the fifth trigger 111 is connected to the high-frequency clock signal CK2_internal, an output end of the fifth trigger 111 is connected to the data end of the sampling module 200, and the fifth trigger 111 is used to detect the low-frequency clock signal CK1_internal at the edge of the high-frequency clock signal CK2_internal to generate an initial signal to be sampled CK1m1, and use the initial signal to be sampled CK1m1 as the signal to be sampled CK1m2.

[0089] Continue to refer Figure 6 and Figure 7 When each cycle of the high-frequency clock signal CK2_internal includes an even number of pulse signals, the first generating module 110 includes a sixth flip-flop 112 and a seventh flip-flop 113 .

[0090] The sixth flip-flop 112 has a data terminal connected to the low-frequency clock signal CK1_internal, a clock terminal connected to the high-frequency clock signal CK2_internal, and is used to detect the low-frequency clock signal CK1_internal at the edge of the high-frequency clock signal CK2_internal to generate an initial signal to be sampled CK1m1.

[0091] The seventh trigger 113, the data end of the seventh trigger 113 is connected to the sixth trigger 112, the clock end of the seventh trigger 113 is connected to the high-frequency clock signal CK2_internal, the output end of the seventh trigger 113 is connected to the data end of the sampling module 200, and the seventh trigger 113 is used to delay the initial signal to be sampled CK1m1 to generate the signal to be sampled CK1m2.

[0092] In this embodiment, the seventh flip-flop 113 is set to delay the initial signal to be sampled CK1m1 to flip the level state of the initial signal to be sampled CK1m1 and generate a signal to be sampled CK1m2, thereby sampling the target level state of the low-frequency clock signal CK1_internal.

[0093] A detection method for detecting phase information between two clock signals of different frequencies, wherein the two clock signals include a low-frequency clock signal CK1_internal and a high-frequency clock signal CK2_internal, and the detection method includes:

[0094] Detect the low-frequency clock signal CK1_internal at the edge of the high-frequency clock signal CK2_internal to generate a signal to be sampled CK1m2, and generate a target sampling signal NoCK2 when the high-frequency clock signal CK2_internal maintains a preset level and the low-frequency clock signal CK1_internal meets a preset condition;

[0095] The signal to be sampled CK1m2 is detected at the edge of the target sampling signal NoCK2 to generate a detection result signal.

[0096] In one embodiment, when the high-frequency clock signal CK2_internal maintains a preset level and the low-frequency clock signal CK1_internal meets a preset condition, generating a target sampling signal NoCK2 includes:

[0097] When the high-frequency clock signal CK2_internal maintains a preset level, a preset signal is detected at an edge where the low-frequency clock signal CK1_internal meets a preset condition to generate a target sampling signal NoCK2 .

[0098] In this embodiment, after each cycle of the high-frequency clock signal CK2_internal, the detection result is output only when the low-frequency clock signal meets the preset conditions. Therefore, even if the first pulse in a single cycle of the high-frequency clock signal CK2_internal is filtered out, it will not affect the detection result, thereby realizing a highly reliable detection method.

[0099] The detection method in the above embodiment corresponds to the detection circuit in the above embodiment. For specific description, reference may be made to the corresponding embodiment of the detection circuit, which will not be described in detail here.

[0100] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments only express several implementation methods of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application. Therefore, the protection scope of the patent of the embodiments of the present application shall be subject to the attached claims.

Claims

1. A detection circuit for detecting phase information between two clock signals of different frequencies, wherein the two clock signals include a low-frequency clock signal and a high-frequency clock signal, characterized in that: The detection circuit comprises: A signal generation module, configured to detect the low-frequency clock signal at the edge of the high-frequency clock signal to generate a signal to be sampled, and to generate a target sampling signal when the high-frequency clock signal maintains a preset level and the low-frequency clock signal meets a preset condition; The sampling module is connected to the signal generating module and is used to detect the signal to be sampled at the edge of the target sampling signal to generate a detection result signal.

2. The detection circuit according to claim 1, characterized in that: The signal generation module comprises: a first generating module, wherein a data end of the first generating module is connected to the low-frequency clock signal, a clock end of the first generating module is connected to the high-frequency clock signal, and the first generating module is used to detect the low-frequency clock signal at an edge of the high-frequency clock signal to generate a signal to be sampled; A second generating module, wherein a data end of the second generating module is connected to a preset signal, a clock end of the second generating module is connected to the low-frequency clock signal, a control end of the second generating module is connected to the high-frequency clock signal, and the second generating module is used to detect the preset signal at the edge of the low-frequency clock signal when the high-frequency clock signal maintains a preset level to generate a target sampling signal.

3. The detection circuit according to claim 2, characterized in that: The data end of the sampling module is connected to the first generating module, the clock end of the sampling module is connected to the second generating module, and the sampling module is used to detect the signal to be sampled at the edge of the target sampling signal to generate a detection result signal.

4. The detection circuit according to claim 3, characterized in that: The second generation module comprises: a first sampling unit, wherein a data end of the first sampling unit is connected to the preset signal, a clock end of the first sampling unit is connected to the low-frequency clock signal, a control end of the first sampling unit is connected to the high-frequency clock signal, and the first sampling unit is used to generate a first sampling signal having the same level state as the preset signal when the low-frequency clock signal outputs a level signal of a first preset condition; a second sampling unit, wherein a data end of the second sampling unit is connected to the preset signal, a clock end of the second sampling unit is connected to the low-frequency clock signal, a control end of the second sampling unit is connected to the high-frequency clock signal, and the second sampling unit is used to generate a second sampling signal with the same level state as the preset signal when the low-frequency clock signal outputs a level signal of a second preset condition; A logic gate unit, wherein two input ends of the logic gate unit are respectively connected to the first sampling unit and the second sampling unit, and is used to generate the target sampling signal according to the first sampling signal and the second sampling signal.

5. The detection circuit according to claim 4, characterized in that: The preset signal is a high level signal, the logic gate unit is an OR gate circuit, and the control end of the first sampling unit and the control end of the second sampling unit are both reset ends.

6. The detection circuit according to claim 4, characterized in that: The preset signal is a low level signal, the logic gate unit is a NAND gate circuit, and the control end of the first sampling unit and the control end of the second sampling unit are both set ends.

7. The detection circuit according to claim 4, characterized in that: The first preset condition is that the low-frequency clock signal continuously outputs a falling edge signal and a rising edge signal in sequence; the second preset condition is that the low-frequency clock signal continuously outputs a rising edge signal and a falling edge signal in sequence.

8. The detection circuit according to claim 7, characterized in that: The first sampling unit comprises: a first trigger, wherein a data terminal of the first trigger is connected to the preset signal, a clock terminal of the first trigger is connected to the low-frequency clock signal through an inverter, a control terminal of the first trigger is connected to the high-frequency clock signal, and the first trigger is used to generate a first condition signal when the falling edge signal in the first preset condition is detected; A second trigger is connected to the first trigger, a clock end of the second trigger is connected to the low-frequency clock signal, a control end of the second trigger is connected to the high-frequency clock signal, and the second trigger is used to delay the first conditional signal to generate the first sampling signal.

9. The detection circuit according to claim 7, characterized in that: The second sampling unit comprises: a third trigger, wherein a data terminal of the third trigger is connected to the preset signal, a clock terminal of the third trigger is connected to the low-frequency clock signal, a control terminal of the third trigger is connected to the high-frequency clock signal, and the third trigger is used to generate a second condition signal when the rising edge signal in the second preset condition is detected; A fourth trigger, wherein the data end of the fourth trigger is connected to the third trigger, the clock end of the fourth trigger is connected to the low-frequency clock signal, the control end of the fourth trigger is connected to the high-frequency clock signal, and the fourth trigger is used to delay the second conditional signal to generate the second sampling signal.

10. The detection circuit according to claim 2, characterized in that: Each cycle of the high-frequency clock signal includes an odd number of pulse signals, and the first generating module includes: A fifth trigger, wherein the data end of the fifth trigger is connected to the low-frequency clock signal, the clock end of the fifth trigger is connected to the high-frequency clock signal, the output end of the fifth trigger is connected to the data end of the sampling module, and the fifth trigger is used to detect the low-frequency clock signal at the edge of the high-frequency clock signal to generate the signal to be sampled.

11. The detection circuit according to claim 2, characterized in that: Each cycle of the high-frequency clock signal includes an even number of pulse signals, and the first generating module includes: a sixth flip-flop, wherein a data terminal of the sixth flip-flop is connected to the low-frequency clock signal, a clock terminal of the sixth flip-flop is connected to the high-frequency clock signal, and the sixth flip-flop is used to detect the low-frequency clock signal at an edge of the high-frequency clock signal to generate an initial signal to be sampled; A seventh trigger, wherein the data end of the seventh trigger is connected to the sixth trigger, the clock end of the seventh trigger is connected to the high-frequency clock signal, the output end of the seventh trigger is connected to the data end of the sampling module, and the seventh trigger is used to delay the initial signal to be sampled to generate the signal to be sampled.

12. A detection method for detecting phase information between two clock signals of different frequencies, wherein the two clock signals include a low-frequency clock signal and a high-frequency clock signal, characterized in that: The detection method comprises: Detecting the low-frequency clock signal at the edge of the high-frequency clock signal to generate a signal to be sampled, and generating a target sampling signal when the high-frequency clock signal maintains a preset level and the low-frequency clock signal meets a preset condition; The signal to be sampled is detected at the edge of the target sampling signal to generate a detection result signal.

13. The detection method according to claim 12, characterized in that: When the high-frequency clock signal maintains a preset level and the low-frequency clock signal meets a preset condition, generating a target sampling signal comprises: When the high-frequency clock signal maintains a preset level, a preset signal is detected at an edge where the low-frequency clock signal meets the preset condition to generate a target sampling signal.

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