Method for Adjusting Operating Conditions of Semiconductor Memory Device

Abstract

An embodiment provides a method for adjusting operation conditions of a semiconductor memory device capable of achieving high-speed operation. The method for adjusting operation conditions of the semiconductor memory device according to the embodiment is related to a semiconductor memory device including: a substrate; a plurality of first conductive layers arranged in a direction intersecting with the surface of the substrate; a plurality of first semiconductor layers facing the plurality of first conductive layers; a second semiconductor layer connected to one end portion of the plurality of first semiconductor layers; and a charge accumulation layer provided between the plurality of first conductive layers and the plurality of first semiconductor layers. At a specific timing of a programming operation, a programming voltage or a write path voltage is supplied to a second conductive layer which is one of the plurality of first conductive layers. In the adjustment method, a first operation and a second operation are performed. The first operation is to supply a write path voltage to the second conductive layer and supply a programming voltage to a third conductive layer which is one of the plurality of first conductive layers. The second operation is to supply a verification voltage smaller than the write path voltage to the second conductive layer and supply a voltage smaller than the programming voltage to the third conductive layer.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2020-139918 (filing date: August 21, 2020). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] The present embodiment relates to a method for adjusting operating conditions of a semiconductor memory device. Background Art

[0004] There is known a semiconductor memory device including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a plurality of first semiconductor layers extending in the first direction and facing the plurality of first conductive layers; a second semiconductor layer spaced from the substrate in the first direction or being a part of the substrate and connected to one end portion of the plurality of first semiconductor layers in the first direction; and a charge accumulation layer provided between the plurality of first conductive layers and the plurality of first semiconductor layers. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a method for adjusting operating conditions of a semiconductor memory device capable of achieving high-speed operation.

[0006] The method for adjusting operating conditions of a semiconductor memory device according to an embodiment is related to a semiconductor memory device including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a plurality of first semiconductor layers extending in the first direction and facing the plurality of first conductive layers; a second semiconductor layer spaced from the substrate in the first direction or being a part of the substrate and connected to one end portion of the plurality of first semiconductor layers in the first direction; and a charge accumulation layer provided between the plurality of first conductive layers and the plurality of first semiconductor layers. In the semiconductor memory device, at a specific timing of a programming operation, a programming voltage or a write path voltage less than the programming voltage is supplied to a second conductive layer which is one of the plurality of first conductive layers. In the adjustment method, a first operation and a second operation are performed. The first operation is to supply a write path voltage to the second conductive layer and supply a programming voltage to a third conductive layer which is one of the plurality of first conductive layers. The second operation is to supply a verification voltage less than the write path voltage to the second conductive layer and supply a voltage less than the programming voltage to the third conductive layer. Brief Description of the Drawings

[0007] Figure 1 is a schematic block diagram showing the configuration of a semiconductor memory device according to the first embodiment.

[0008] Figure 2It is a schematic circuit diagram showing a part of the semiconductor memory device.

[0009] Figure 3 It is a schematic perspective view showing a part of the semiconductor memory device.

[0010] Figure 4 It is a schematic cross-sectional view showing a part of the semiconductor memory device.

[0011] Figure 5 It is Figure 4 a schematic enlarged view of the part shown at A of

[0012] Figure 6 It is a schematic bar graph for explaining the threshold voltage of the memory cell MC for recording 4-bit data.

[0013] Figure 7 It is a schematic cross-sectional view for explaining the read operation.

[0014] Figure 8 It is a schematic flowchart for explaining the write sequence.

[0015] Figure 9 It is a schematic cross-sectional view for explaining the programming operation.

[0016] Figure 10 It is a schematic cross-sectional view for explaining the verification operation.

[0017] Figure 11 It is a schematic flowchart for explaining the current adjustment sequence of the first embodiment.

[0018] Figure 12 It is a schematic waveform diagram for explaining the current adjustment sequence.

[0019] Figure 13 It is a schematic cross-sectional view for explaining the SGS programming operation.

[0020] Figure 14 It is a schematic cross-sectional view for explaining the SGS programming operation.

[0021] Figure 15 It is a schematic cross-sectional view for explaining the WL verification operation.

[0022] Figure 16 It is a schematic waveform diagram for explaining the current adjustment sequence of the second embodiment.

[0023] Figure 17 It is a schematic cross-sectional view for explaining the SGS programming operation.

[0024] Figure 18 It is a schematic cross-sectional view for explaining the SGS programming operation.

[0025] Figure 19 It is a schematic waveform diagram for explaining the current adjustment sequence of the third embodiment.

[0026] Figure 20 It is a schematic cross-sectional view for explaining the SGS programming operation.

[0027] Figure 21 It is a schematic cross-sectional view for explaining the SGS programming operation.

[0028] Figure 22 It is a schematic flow chart for explaining the current adjustment sequence of the fourth embodiment.

[0029] Figure 23 It is a schematic waveform diagram for explaining the current adjustment sequence.

[0030] Figure 24 It is a schematic cross-sectional view for explaining the TCWL programming operation.

[0031] Figure 25 It is a schematic cross-sectional view for explaining the WL verification operation.

[0032] Figure 26 It is a schematic cross-sectional view showing a part of the semiconductor memory device of the fifth embodiment. Detailed Embodiments

[0033] Next, with reference to the drawings, the semiconductor memory device of the embodiment will be described in detail. In addition, the following embodiments are merely examples and are not shown for limiting the present invention. Further, the following drawings are schematic diagrams, and sometimes a part of the configuration and the like are omitted for convenience of explanation. In addition, sometimes the same reference numerals are assigned to parts common to a plurality of embodiments and the description thereof is omitted.

[0034] In addition, in the case of referring to a "semiconductor memory device" in this specification, it sometimes means a memory die, sometimes means a memory chip, a memory card, a memory system including a controller die such as an SSD (Solid State Drive), and further sometimes means a configuration including a host computer such as a smart phone, a tablet terminal, and a personal computer.

[0035] In addition, in the case of referring to a "control circuit" in this specification, it sometimes means a peripheral circuit such as a sequence generator provided in a memory die, sometimes means a controller die or a controller chip connected to the memory die, and sometimes means a configuration including both of them.

[0036] In addition, in this specification, when it is said that a first component is "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via a wiring, a semiconductor component, a transistor, or the like. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0037] In addition, in this specification, when it is said that a first component is "intermediately connected" between a second component and a third component, it sometimes means that the first component, the second component, and the third component are connected in series, and the second component is connected to the third component via the first component.

[0038] In addition, in this specification, when it is said that two wirings or the like of a circuit or the like are "conducted", for example, it sometimes means that the circuit or the like includes a transistor or the like, the transistor or the like is provided in a current path between two wirings, and the transistor or the like is in an ON state.

[0039] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0040] In addition, in this specification, sometimes a direction along a specific surface is referred to as a first direction, a direction intersecting the first direction along the specific surface is referred to as a second direction, and a direction intersecting the specific surface is referred to as a third direction. These first direction, second direction, and third direction may or may not correspond to any one of the X direction, Y direction, and Z direction.

[0041] In addition, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, a direction away from the substrate along the Z direction is referred to as upper, and a direction close to the substrate along the Z direction is referred to as lower. In addition, when a certain component is referred to as a lower surface or a lower end, it means the surface or end on the substrate side of the component, and when it is referred to as an upper surface or an upper end, it means the surface or end on the side opposite to the substrate of the component. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface or the like.

[0042] [First Embodiment]

[0043] [Circuit Configuration of Semiconductor Memory Device]

[0044] Figure 1 is a schematic block diagram showing the configuration of a semiconductor memory device according to the first embodiment. Figure 2 is a schematic circuit diagram of a part of the configuration of the semiconductor memory device.

[0045] In addition, Figure 1 illustrates a plurality of control terminals and the like. The plurality of control terminals are sometimes represented as control terminals corresponding to a high-validity signal (positive logic signal), sometimes represented as control terminals corresponding to a low-validity signal (negative logic signal), and sometimes represented as two control terminals corresponding to both a high-validity signal and a low-validity signal. Figure 1 In, the symbol of the control terminal corresponding to the low-validity signal includes an overline (upper line). In this specification, the symbol of the control terminal corresponding to the low-validity signal includes a slash (" / "). In addition, Figure 1 taking the description of as an example, the specific aspects can be appropriately adjusted. For example, a part or all of the high-validity signals can be set as low-validity signals, or a part or all of the low-validity signals can be set as high-validity signals.

[0046] As Figure 1 shown, the semiconductor memory device includes a memory cell array MCA for storing data, and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequence generator SQC. In addition, the peripheral circuit PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. In addition, the peripheral circuit PC includes an input / output control circuit I / O and a logic circuit CTR.

[0047] [Circuit Configuration of Memory Cell Array MCA]

[0048] As Figure 2 shown, the memory cell array MCA includes a plurality of memory blocks BLK. The plurality of memory blocks BLK each include a plurality of string units SU. The plurality of string units SU each include a plurality of memory strings MS. One ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC via bit lines BL. In addition, the other ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC via a common source line SL.

[0049] The memory string MS includes: a drain-side selection transistor STD connected in series between the bit line BL and the source line SL, a plurality of dummy memory cells DMC on the bit line BL side, a plurality of memory cells MC, a plurality of dummy memory cells DMC on the source line SL side, a source-side selection transistor STS, and a source-side selection transistor STSb. Hereinafter, the drain-side selection transistor STD, the source-side selection transistor STS, and the source-side selection transistor STSb are sometimes simply referred to as selection transistors (STD, STS, STSb).

[0050] A memory cell MC is a field-effect transistor comprising a semiconductor layer functioning as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of a memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of the multiple memory cells MC corresponding to a single memory string MS. These word lines WL are commonly connected to all memory strings MS within a single memory block BLK.

[0051] Dummy memory cells DMC have the same structure as memory cells MC. However, they do not store data. Furthermore, dummy word lines DWL are connected to the gate electrodes of the multiple dummy memory cells DMC corresponding to a single memory string MS. These dummy word lines DWL are commonly connected to all memory strings MS within a single memory block BLK.

[0052] The select transistors (STD, STS, and STSb) are field-effect transistors (FETs) that include a semiconductor layer, a gate insulating film, and a gate electrode that functions as a channel region. The gate electrodes of the select transistors (STD, STS, and STSb) are connected to select gate lines (SGD, SGS, and SGSb), respectively. The drain-side select gate line SGD is provided corresponding to the string unit SU and is commonly connected to all memory strings MS within a single string unit SU. The source-side select gate line SGS and the source-side select gate line SGSb are commonly connected to all memory strings MS within a single memory block BLK.

[0053] [Circuit Configuration of Voltage Generating Circuit VG]

[0054] like Figure 2 As shown, the voltage generating circuit VG( Figure 1 ) is connected to a plurality of voltage supply lines 31. The voltage generating circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down circuits and step-up circuits are connected to the supply voltage V CC and ground voltage V SS Voltage supply line ( Figure 1 For example, the voltage generating circuit VG generates a variety of operating voltages to be applied to the bit lines BL, source lines SL, word lines WL, dummy word lines DWL, and select gate lines (SGD, SGS, SGSb) when performing read, write, and erase operations on the memory cell array MCA, following control signals from the sequencer SQC. These voltages are then simultaneously output to a plurality of voltage supply lines 31. Following the control signals from the sequencer SQC, the operating voltages output from the voltage supply lines 31 are appropriately adjusted.

[0055] [Circuit Configuration of Row Decoder RD]

[0056] As shown Figure 2 , the row decoder RD( Figure 1 ) includes, for example: an address decoder 22 that decodes address data D ADD , a block selection circuit 23 that transmits an operation voltage to the memory cell array MCA according to the output signal of the address decoder 22, and a voltage selection circuit 24.

[0057] The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22, for example, follows the control signal from the sequence generator SQC, sequentially refers to the row address RA of the address register ADR( Figure 1 ), decodes the row address RA, sets a specific block selection transistor 35 and a voltage selection transistor 37 corresponding to the row address RA to the ON state, and sets the other block selection transistors 35 and voltage selection transistors 37 to the OFF state. For example, the voltages of a specific block selection line BLKSEL and a voltage selection line 33 are set to the "H" state, and the other voltages are set to the "L" state. In addition, when a P-channel transistor is used instead of an N-channel transistor, a reverse voltage is applied to these wirings.

[0058] In addition, in the illustrated example, in the address decoder 22, one block selection line BLKSEL is provided for each memory block BLK. However, the configuration can be appropriately changed. For example, one block selection line BLKSEL can be provided for each of two or more memory blocks BLK.

[0059] The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory blocks BLK. The plurality of block selection units 34 each include a plurality of block selection transistors 35 corresponding to the word line WL, the dummy word line DWL, and the selection gate lines (SGD, SGS, SGSb). The block selection transistor 35 is, for example, a field effect withstand voltage transistor. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word line WL, dummy word line DWL, or selection gate lines (SGD, SGS, SGSb) respectively. The source electrodes are electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24 respectively. The gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

[0060] In addition, the block selection circuit 23 further includes a plurality of transistors (not shown). The plurality of transistors are field effect withstand voltage transistors connected between the selection gate lines (SGD, SGS, SGSb) and the voltage supply line that supplies the ground voltage V SS . The plurality of transistors supply the ground voltage V SS to the selection gate lines (SGD, SGS, SGSb) included in the non-selected memory block BLK. In addition, the plurality of word lines WL included in the non-selected memory block BLK become floating states.

[0061] The voltage selection circuit 24 includes a plurality of voltage selection units 36 corresponding to the word line WL, the dummy word line DWL, and the select gate lines (SGD, SGS, SGSb). Each of the plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistor 37 is, for example, a field-effect withstand voltage transistor. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word line WL, dummy word line DWL, or select gate line (SGD, SGS, SGSb) via the wiring CG and the block selection circuit 23, respectively. The source terminals are electrically connected to the corresponding voltage supply line 31, respectively. The gate electrodes are connected to the corresponding voltage selection line 33, respectively.

[0062] In addition, in the illustrated example, an example is shown in which the wiring CG is connected to the voltage supply line 31 via one voltage selection transistor 37. However, this configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, the wiring CG may also be connected to the voltage supply line 31 via two or more voltage selection transistors 37.

[0063] [Circuit configuration of the sense amplifier module SAM]

[0064] The sense amplifier module SAM includes, for example, a plurality of sense amplifier units corresponding to a plurality of bit lines BL. Each sense amplifier unit includes: a sense node electrically connected to the bit line BL, a sense transistor electrically connected to the sense node, a data wiring electrically connected to the sense transistor, and a plurality of latch circuits electrically connected to the data wiring. In addition, each sense amplifier unit includes: a voltage transfer circuit electrically connected to the bit line BL, and a control latch circuit electrically connected to the voltage transfer circuit. The sense node is conducted to the bit line BL at a specific timing such as a read operation. The sense transistor has a gate electrode electrically connected to the sense node. The sense transistor becomes an ON state or an OFF state corresponding to the voltage of the sense node. The data wiring is charged or discharged depending on whether the sense transistor is in an ON state or an OFF state. The plurality of latch circuits and the control latch circuit latch data of "1" or "0" corresponding to the voltage of the data wiring. The voltage transfer voltage conducts the bit line BL to any one of the two voltage supply lines corresponding to the data latched in the control latch circuit.

[0065] [Circuit configuration of the cache memory CM]

[0066] The cache memory CM ( Figure 1 ) includes a plurality of latch circuits connected to a plurality of latch circuits in the sense amplifier module SAM via the wiring DBUS. The data DAT included in the plurality of latch circuits is sequentially transmitted to the sense amplifier module SAM or the input / output control circuit I / O.

[0067] In addition, in the cache memory CM, there are connected a decoding circuit and a switching circuit (not shown). The decoding circuit decodes the row address CA held in the address register ADR( Figure 1 ). The switching circuit, based on the output signal of the decoding circuit, conducts the latch circuit corresponding to the row address CA to the bus DB( Figure 1 ).

[0068] [Circuit Configuration of Sequence Generator SQC]

[0069] The sequence generator SQC( Figure 1 ) follows the command data D CMD held in the command register CMR, and outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. In addition, the sequence generator SQC outputs status data D ST appropriately representing its own state to the status register STR.

[0070] In addition, the sequence generator SQC generates a ready / busy signal and outputs it to the terminal RY / ( / BY). During the period when the terminal RY / ( / BY) is in the "L" state (busy period), access to the semiconductor memory device is basically prohibited. In addition, during the period when the terminal RY / ( / BY) is in the "H" state (ready period), access to the semiconductor memory device is permitted.

[0071] [Circuit Configuration of Input / Output Control Circuit I / O]

[0072] The input / output control circuit I / O includes: data signal input / output terminals DQ0 to DQ7, trigger signal input / output terminals DQS, / DQS, an input circuit such as a comparator connected to the data signal input / output terminals DQ0 to DQ7, and an output circuit such as an OCD (OffChip Driver) circuit. In addition, the input / output circuit I / O includes a shift register and a buffer circuit connected to these input and output circuits. The input circuit, output circuit, shift register, and buffer circuit are respectively connected to the terminals for supplying the power supply voltage V CCQ and the ground voltage V SS . The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR corresponding to the internal control signal from the logic circuit CTR. In addition, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit corresponding to the internal control signal from the logic circuit CTR.

[0073] [Circuit Configuration of Logic Circuit CTR]

[0074] Logic circuit CTR( Figure 1 ) receives external control signals from the controller via the external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0075] [Structure of semiconductor memory device]

[0076] Figure 3 It is a schematic perspective view showing a part of the semiconductor memory device. Figure 4 It is a schematic cross-sectional view showing a part of the semiconductor memory device. Figure 5 It is Figure 4 A schematic enlarged view of the part shown in A of

[0077] As Figure 3 shown, the semiconductor memory device includes, for example: a semiconductor substrate 100, a transistor layer L TR provided on the semiconductor substrate 100, TR a wiring layer D0 - D2 provided on the upper part of the transistor layer L MCA , a memory cell array layer L MCA provided above the wiring layer D0 - D2, and a plurality of wiring layers provided above the memory cell array layer L

[0078] [Structure of semiconductor substrate 100]

[0079] The semiconductor substrate 100 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). For example, on the surface of the semiconductor substrate 100, an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), a semiconductor substrate region where neither the N-type well region nor the P-type well region is provided, and an insulating region STI are provided.

[0080] [Structure of transistor layer L TR

[0081] For example, as Figure 3 shown, on the upper surface of the semiconductor substrate 100, a plurality of electrodes gc are provided with an insulating layer in between. In addition, each region of the semiconductor substrate 100 and the plurality of electrodes gc are respectively connected to contacts CS.

[0082] The N-type well region, P-type well region, and semiconductor substrate of the semiconductor substrate 100 function as the channel regions of a plurality of transistors Tr Figure 1 , Figure 2 constituting the peripheral circuit PC(

[0083] ​A plurality of electrodes gc function as gate electrodes of a plurality of transistors Tr constituting the peripheral circuit PC, the other electrodes of a plurality of capacitors, and the like.

[0084] The contact CS extends in the Z direction and is connected to the upper surface of the semiconductor substrate 100 or the electrode gc at the lower end. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the contact CS and the semiconductor substrate 100. The contact CS may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0085] [Structure of wiring layers D0 to D2]

[0086] For example, as Figure 3 shown, a plurality of wirings included in the wiring layers D0 to D2 are electrically connected to at least one of the components in the memory cell array MCA and the components in the peripheral circuit PC.

[0087] The plurality of wirings included in the wiring layers D0 to D2 may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0088] [Structure of memory cell array layer L MCA

[0089] For example, as Figure 3 shown, in the memory cell array layer L MCA , a memory block BLK and an inter-block insulating layer ST such as silicon oxide (SiO2) are provided. The memory block BLK includes: a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0090] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0091] Below the conductive layer 110, a conductive layer 111 is provided. The conductive layer 111 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 111 and the conductive layer 110.

[0092] ​Below the conductive layer 111, a conductive layer 112 is provided. The conductive layer 112 includes: a semiconductor layer 113 connected to the lower end of the semiconductor layer 120, and a conductive layer 114 connected to the lower surface of the semiconductor layer 113. The semiconductor layer 113 may also include, for example, polysilicon containing N-type impurities such as phosphorus (P). The conductive layer 114 may also include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 112 and the conductive layer 111.

[0093] The conductive layer 112 functions as a source line SL ( Figure 2 ). The source line SL is commonly provided for a plurality of memory blocks BLK.

[0094] The conductive layer 111 functions as a source side selection gate line SGSb ( Figure 2 ) and the gate electrodes of a plurality of source side selection transistors STSb connected to the source side selection gate line SGSb. The conductive layer 111 is electrically independent for each memory block BLK.

[0095] In addition, among the plurality of conductive layers 110, the lowermost plurality of conductive layers 110 function as a source side selection gate line SGS ( Figure 2 ) and the gate electrodes of a plurality of source side transistors STS connected to the source side selection gate line SGS. The plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0096] In addition, the upper plurality of conductive layers 110 function as dummy word lines DWL and the gate electrodes of a plurality of dummy memory cells DMC connected to the dummy word lines DWL. The plurality of conductive layers 110 are electrically independent for each memory block BLK respectively.

[0097] In addition, the upper plurality of conductive layers 110 function as word lines WL ( Figure 2 ) and the gate electrodes of a plurality of memory cells MC ( Figure 2 ) connected to the word lines WL. The plurality of conductive layers 110 are electrically independent for each memory block BLK respectively.

[0098] In addition, the upper plurality of conductive layers 110 function as dummy word lines DWL and the gate electrodes of a plurality of dummy memory cells DMC connected to the dummy word lines DWL. The plurality of conductive layers 110 are electrically independent for each memory block BLK respectively.

[0099] In addition, one or more upper conductive layers 110 function as a drain side selection gate line SGD and the gate electrodes of a plurality of drain side selection transistors STD ( Figure 2The gate electrode of () functions. The multiple conductive layers 110 are separated into multiple parts by the string unit isolation layer SHE and are electrically independent in each string unit SU.

[0100] At the X-direction ends of the multiple conductive layers 110, connection points CC extending in the Z direction are provided. The multiple conductive layers 110 are connected to the peripheral circuit PC via the multiple connection points CC.

[0101] The semiconductor layer 120 is arranged in a specific pattern in the X direction and the Y direction. The semiconductor layer 120 functions as the channel regions of multiple memory cells MC, multiple dummy memory cells DMC, and selection transistors (STD, STS, STSb) included in one memory string MS ( Figure 2 ). The semiconductor layer 120 is, for example, a semiconductor layer such as polysilicon (Si). As Figure 4 shown, the semiconductor layer 120 has, for example, a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central part. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by the conductive layer 110 with a gate insulating film 130 interposed therebetween and face the conductive layer 110. The outer peripheral surfaces of the semiconductor layer 120 are also surrounded by the conductive layer 111 with a gate insulating film 130 interposed therebetween and face the conductive layer 111. In addition, Figure 4 in the example of, the upper end portion and the lower end portion of the semiconductor layer 120 are indicated by dashed lines.

[0102] At the upper end portion of the semiconductor layer 120, an impurity region 121 containing N-type impurities such as phosphorus (P) is provided. Figure 4 in the example of, the boundary line between the upper end portion of the semiconductor layer 120 and the impurity region 121 is indicated by a dashed line. The impurity region 121 is connected to the conductive layer 150 extending in the Y direction via the connection point Ch and the connection point Vy ( Figure 3 ). The conductive layer 150 functions as a bit line BL. The conductive layer 150 may also be, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0103] As Figure 4 shown, at the lower end portion of the semiconductor layer 120, for example, an impurity region 122 containing N-type impurities such as phosphorus (P) is provided. Figure 4 in the example of, the boundary line between the lower end portion of the semiconductor layer 120 and the impurity region 122 is indicated by a dashed line. The impurity region 122 is connected to the semiconductor layer 113 of the conductive layer 112. In the semiconductor layer 120, the portion directly above the impurity region 122 functions as the channel region of the source-side selection transistor STSb. The outer peripheral surface of the impurity region 122 is surrounded by the conductive layer 111 with a gate insulating film 130 interposed therebetween and faces the conductive layer 111.

[0104] The gate insulating film 130 has a substantially bottomed cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 is, for example, as Figure 5 shown, and includes: a channel insulating film 131, a charge accumulation film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The channel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2), for example. The charge accumulation film 132 is a film capable of accumulating charges such as silicon nitride (Si3N4), for example. The channel insulating film 131, the charge accumulation film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0105] In addition, Figure 5 shows an example in which the gate insulating film 130 includes a charge accumulation film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polysilicon containing N-type or P-type impurities, for example.

[0106] [Threshold voltage of the memory cell MC]

[0107] Next, with reference to Figure 6 , the threshold voltage of the memory cell MC will be described.

[0108] As described above, the memory cell array MCA includes a plurality of memory cells MC. When writing in order to the plurality of memory cells MC, the threshold voltages of these memory cells MC are controlled to a plurality of states.

[0109] Figure 6 is a histogram for explaining the threshold voltage of the memory cell MC for recording 4-bit data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0110] Figure 6 In the example of, the threshold voltage of the memory cell MC is controlled to 16 states. For example, the threshold voltage of the memory cell MC controlled to the S1 state is greater than Figure 6 the read voltage V CG1R and the verification voltage V VFY1 , and less than the read voltage V CG2R and the verification voltage V VFY2 . In addition, the threshold voltages of all the memory cells MC are less than the read path voltage V READ .

[0111] For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erased state). Data "1111" may also be assigned, for example, to the memory cell MC corresponding to the Er state.

[0112] In addition, the S1 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. Data such as "1011" can also be assigned to the memory cell MC corresponding to the S1 state.

[0113] In addition, the S2 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the S1 state. Data such as "0011" can also be assigned to the memory cell MC corresponding to the S2 state.

[0114] Similarly hereinafter, the threshold voltages corresponding to the S3 state to S15 state in the figure are respectively higher than the threshold voltages corresponding to the S2 state to S14 state. Data such as "1111", "1011", and "0011" can also be assigned to the memory cell MC corresponding to these distributions, and other 4-bit data can be assigned.

[0115] In addition, the number of bits of the data recorded in the memory cell MC, the number of states, the assignment of data to each state, etc. can be appropriately changed.

[0116] For example, when all the fourth bits in the Er state and the S1 state to S7 state are assigned "1", and all the fourth bits in the S8 state to S15 state are assigned "0", when reading the data of the fourth bit, a read voltage V is supplied to the word line WL CG8R .

[0117] In addition, for example, when all the third bits in the Er state and the S1 state to S3 state are assigned "1", all the third bits in the S4 state to S11 state are assigned "0", and all the third bits in the S12 state to S15 state are assigned "1", when reading the data of the third bit, a read voltage V is supplied to the word line WL CG4R , V CG12R .

[0118] [Read operation]

[0119] Next, with reference to Figure 7 etc., the read operation of the semiconductor memory device of this embodiment will be described. Figure 7 is a schematic cross-sectional view for explaining the read operation.

[0120] In addition, in the following description, the word line WL that becomes the operation object is sometimes referred to as the selected word line WL S , and the word line WL other than this is referred to as the non-selected word line WL U . In addition, in the following description, among the multiple memory cells MC included in the string unit SU, the connection to the selected word line WL SAn example of the read operation performed by the memory cell MC (hereinafter sometimes referred to as "selected memory cell MC") will be described. In addition, in the following description, a configuration including a plurality of selected memory cells MC is sometimes referred to as a selected page PG.

[0121] When reading from the memory cell MC, for example, the bit line BL or the like is charged. That is, a voltage V Figure 1 、 Figure 2 ) is supplied to the sense node in the sense amplifier module SAM( DD and these are charged. In addition, for example, a voltage V Figure 2 ) is supplied to the source line SL( SRC and the charging is started. The voltage V SRC has, for example, a magnitude similar to that of the ground voltage V SS . The voltage V SRC is, for example, greater than the ground voltage V SS and less than the voltage V DD .

[0122] In addition, a plurality of selected memory cells MC included in the selected page PG are made conductive to the bit line BL and the source line SL. For example, a voltage V SG is supplied to the select gate lines (SGD, SGS, SGSb), and the select transistors (STD, STS, STSb) are set to the ON state. In addition, a read path voltage V U is supplied to the unselected word line WL READ , and all the memory cells MC connected to the unselected word line WL U are set to the ON state. In addition, a voltage V READ' is supplied to the dummy word line DWL, and all the dummy memory cells DMC are set to the ON state. Also, the voltage V READ ' is greater than the ground voltage V SS and less than the read path voltage V READ .

[0123] In addition, a read voltage V S is supplied to the selected word line WL CGSR ( Figure 6 of the read voltage V CG1R ~V CG15R ). As a result, a general memory cell MC becomes the ON state, and other memory cells MC become the OFF state.

[0124] In addition, the sense amplifier module SAM( Figure 1 、 Figure 2) Detect the ON / OFF state of the selected memory cell MC. For example, make the sense node in the sense amplifier module SAM conduct with the bit line BL, maintain or discharge the charge of the sense node, and set the sense transistor to the ON state or the OFF state. In addition, charge or discharge the charge of the data wiring according to the state of the sense transistor, and latch the data corresponding to the voltage of the wiring through any one of the multiple latch circuits connected to the data wiring. Thus, the data indicating the state of the selected memory cell MC is latched into the latch circuit.

[0125] Hereinafter, the read voltage V supplied to the selected word line WL is sequentially switched as needed S CGSR , and detect the ON / OFF state of the selected memory cell MC. Then, perform arithmetic processing such as AND and OR between the detected data to calculate the data stored in the selected memory cell MC. After that, output the calculated data to the cache memory CM. After that, for example, the data latched into the cache memory CM is output via the bus DB ( Figure 1 ) and the input / output control circuit I / O ( Figure 1 ).

[0126] [Write Sequence]

[0127] Next, referring to Figures 8 - 10 , the write sequence of the semiconductor memory device will be described. Figure 8 is a schematic flowchart for explaining the write sequence. Figure 9 is a schematic cross-sectional view for explaining the programming operation included in the write sequence. Figure 10 is a schematic cross-sectional view for explaining the verification operation included in the write sequence.

[0128] In step S101 ( Figure 8 ), set the loop count n W to 1. The loop count n W is recorded in a register or the like.

[0129] In step S102, a programming operation is performed.

[0130] During the programming operation, for example, supply the voltage V SRC to the bit line BL of the memory cell MC (hereinafter, sometimes referred to as "write memory cell MC") that is connected to multiple selected memory cells MC and whose threshold voltage is adjusted. Supply the voltage V DD ​For example, "L" is latched into the control latch circuit of the voltage transfer circuit connected to the sense amplifier module SAM, corresponding to the control latch circuit for writing to the memory cell MC, and "H" is latched into the control latch circuit corresponding to the disabled memory cell MC. In addition, different voltages are supplied to the memory cell MC for writing and the disabled memory cell MC via the two voltage supply lines.

[0131] In addition, as Figure 9 shown, the memory cell MC for writing is selectively connected to the bit line BL. For example, a voltage V SGD is supplied to the drain-side select gate line SGD. The voltage V SGD is, for example, less than Figure 7 the voltage V SG . Thereby, the drain-side select transistor STD corresponding to the bit line BL supplied with the voltage V SRC becomes in the on state, and the drain-side select transistor STD corresponding to the bit line BL supplied with the voltage V DD becomes in the off state. In addition, a write path voltage V U is supplied to the non-selected word line WL PASS . The write path voltage V PASS is, for example, greater than Figure 6 the read path voltage V READ and Figure 7 the voltage V SG . That is, the read path voltage V READ and the voltage V SG are less than the write path voltage V PASS . In addition, a voltage V PASS ' is supplied to the dummy word line DWL on the drain-side select transistor STD side. The voltage V PASS ' is greater than the voltage V SGD , and less than the write path voltage V PASS . In addition, a ground voltage V SS is supplied to the source-side select gate lines SGS2, SGS1, SGS0, SGSb. In addition, a voltage V PASS ” is supplied to the dummy word line DWL on the source-side select transistor STS side. The voltage V PASS ” is greater than the ground voltage V SS , and less than the write path voltage V PASS .

[0132] In addition, as Figure 9 shown, a programming voltage V S is supplied to the selected word line WL PGM . The programming voltage V PGM is greater than the write path voltage V PASS and the voltage V SG. That is, the write path voltage V PASS and the voltage V SG are less than the programming voltage V PGM . Thus, electrons are accumulated in the charge accumulation film 132 ( Figure 5 ) of the write memory cell MC, and the threshold voltage of the write memory cell MC increases.

[0133] In step S103 ( Figure 8 ), a verification operation is performed.

[0134] During the verification operation, for example, the bit line BL etc. is charged. In addition, the selected memory cell MC is selectively made conductive to the bit line BL and the source line SL. In addition, as Figure 10 shown, a verification voltage V S is supplied to the selected word line WL VFYS ( Figure 6 any one of the verification voltages V VFY1 to V VFY15 ), and the ON / OFF state of the selected memory cell MC is detected. In addition, if necessary, the verification voltage V S supplied to the selected word line WL VFYS is sequentially switched, and the ON / OFF state of the selected memory cell MC is detected.

[0135] In addition, during the verification operation, the detection of the ON / OFF state of the prohibited memory cell MC can also be omitted. In this case, for example, during the verification operation, "H" can be latched into the control latch circuit of the voltage transfer circuit connected to the sense amplifier module SAM, the latch circuit connected to the write memory cell MC, and "L" can be latched into the latch circuit connected to the prohibited memory cell MC.

[0136] In step S104 ( Figure 8 ), the result of the verification operation is determined. For example, when the data indicating the state of the memory cell MC contains a certain amount or more of "L", it is determined that the verification fails (FAIL), and the process proceeds to step S105. On the other hand, when the data indicating the state of the memory cell MC does not contain a certain amount or more of "L", it is determined that the verification passes (PASS), and the process proceeds to step S107.

[0137] In step S105, it is determined whether the loop count n W has reached a specific number N W . If not, the process proceeds to step S106. If so, the process proceeds to step S108.

[0138] In step S106, for the loop count n WIncrement by 1 and proceed to step S102. In addition, in step S106, for example, a specific voltage ΔV is added to the programming voltage V PGM add a specific voltage ΔV.

[0139] In step S107, in the status register STR( Figure 1 ), store the status data D ST indicating the normal end of the writing sequence, and end the writing sequence.

[0140] In step S108, in the status register STR( Figure 1 ), store the status data D ST indicating the abnormal end of the writing sequence, and end the writing sequence.

[0141] [Non-uniformity of the current flowing in the memory cell MC]

[0142] As described with reference to Figure 4 , the semiconductor layer 113 contains N-type impurities such as phosphorus (P). In addition, at the lower end of the semiconductor layer 120, an impurity region 122 containing N-type impurities such as phosphorus (P) is provided. In such a structure, for example, during the manufacturing process, the N-type impurities contained in the semiconductor layer 113 and the impurity region 122 of the semiconductor layer 120 may diffuse due to heat or the like, resulting in non-uniformity in the range of the impurity region 122. In addition, corresponding to the non-uniformity in the range of the impurity region 122, non-uniformity in the magnitude of the current may occur between the semiconductor layers 120.

[0143] Here, in the writing sequence, based on the current flowing in the semiconductor layer 120, it is determined whether the threshold voltage of the memory cell MC reaches the target value. Therefore, when non-uniformity in the magnitude of the current occurs between the semiconductor layers 120, it is determined that the memory cell MC corresponding to the semiconductor layer 120 where the current does not easily flow is the memory cell MC whose threshold voltage reaches the target value at an earlier stage. On the other hand, it is determined that the memory cell MC corresponding to the semiconductor layer 120 where the current easily flows is the memory cell MC whose threshold voltage reaches the target value at a later stage. Therefore, sometimes the conditions suitable for controlling the threshold voltage are different between these, resulting in an increase in the number of loops n Figure 8 ) in the writing sequence( W increase.

[0144] Therefore, in the present embodiment, in order to suppress such current non-uniformity caused by the semiconductor layer 120, charges are accumulated in a part of the charge accumulation film 132 corresponding to the current non-uniformity. For example, for the semiconductor layer 120 where the current easily flows, charges are accumulated in the charge accumulation film 132 corresponding to the semiconductor layer 120, in the part of the charge accumulation film 132 corresponding to the plurality of conductive layers 110 that function as the source-side selection gate lines SGS. Thereby, the ease of current flow between the semiconductor layers 120 is adjusted.

[0145] According to this method, current non-uniformity between the semiconductor layers 120 can be suppressed. Thereby, the number of loops n in the write sequence ( Figure 8 ) can be reduced W , and high-speed operation of the semiconductor memory device can be achieved. In addition, sometimes depending on the situation, the verification operation can be omitted in the write sequence. In this case, even higher-speed operation of the semiconductor memory device can be achieved.

[0146] [Current adjustment sequence]

[0147] Next, with reference to Figures 11 - 14 , the current adjustment sequence of the semiconductor memory device of the present embodiment will be described. Figure 11 is a schematic flowchart for explaining the current adjustment sequence. Figure 12 is a schematic waveform diagram for explaining the current adjustment sequence of the present embodiment. Figure 13 and Figure 14 are schematic cross-sectional views for explaining the SGS programming operation included in the current adjustment sequence. Figure 15 is a schematic cross-sectional view for explaining the WL verification operation included in the current adjustment sequence.

[0148] In addition, in the following description, an example will be described in which, among the plurality of conductive layers 110 arranged in the Z direction, the lowermost three conductive layers 110 function as the source-side select gate lines SGS. Further, in the following description, the configuration corresponding to the lowermost conductive layer 110 is referred to as the source-side select gate line SGS0, the configuration corresponding to the second conductive layer 110 from the bottom is referred to as the source-side select gate line SGS1, and the configuration corresponding to the third conductive layer 110 from the bottom is referred to as the source-side select gate line SGS2.

[0149] In step S201 ( Figure 11 ), the number of loops n I is set to 1. The number of loops n I is recorded in a register or the like.

[0150] In step S202 ( Figure 11 ), the SGS programming operation is performed.

[0151] For example, Figure 12 in the example of, at timing t101, the SGS programming operation is started.

[0152] In addition, at timing t102, a write path voltage V is supplied to the word line WL PASS . In addition, a ground voltage V is supplied to the drain-side select gate line SGD SSIn addition, a write path voltage V is supplied to the source-side selection gate lines SGS2, SGS1, and SGS0. PASS In addition, a ground voltage V is supplied to the source-side selection gate line SGSb. SS In addition, as Figure 13 shown, a voltage V is supplied to the source line SL. SRC In addition, a write pulse voltage V is supplied to the dummy word line DWL on the source line SL side. PASS In addition, a voltage V is supplied to the dummy word line DWL on the bit line BL side. PASS '.

[0153] Here, Figure 13 in the example of, a part of the source-side selection transistor STSb becomes in an ON state, and the electron channel formed on the outer peripheral surface of a corresponding part of the semiconductor layer 120 is electrically connected to the conductive layer 112. In addition, a part of the source-side selection transistor STSb becomes in an OFF state, and the electron channel formed on the outer peripheral surface of a corresponding part of the semiconductor layer 120 is electrically separated from the conductive layer 112. This phenomenon is caused, for example, by unevenness in the range of the impurity region 122.

[0154] In addition, at timing t103, as Figure 12 shown, a programming voltage V is supplied to the source-side selection gate lines SGS0 and SGS1. PGM .

[0155] Here, as Figure 14 shown, the electron channel formed on the outer peripheral surface of the semiconductor layer 120 corresponding to the source-side selection transistor STSb in the ON state is electrically connected to the source line SL, and the voltage V is supplied. SRC Therefore, a potential difference of the magnitude of the programming voltage V PGM is generated between the channel and the source-side selection gate lines SGS0 and SGS1. As a result, electrons are accumulated in the charge accumulation film 132 contained in the gate insulating film of the source-side selection transistor STS, and the threshold voltages of these source-side selection transistors STS increase.

[0156] On the other hand, as Figure 14 shown, the electron channel formed on the outer peripheral surface of the semiconductor layer 120 corresponding to the source-side selection transistor STSb in the OFF state is electrically separated from the source line SL and becomes a floating state. In addition, the voltage of the channel becomes the magnitude of the write path voltage V PASS by capacitive coupling with the word line WL. Therefore, a potential difference between the programming voltage V PGM and the write path voltage V PASSThe potential difference of the magnitude of the differential amount. The threshold voltage of this source-side selection transistor STS does not increase.

[0157] In addition, at timing t104, as Figure 12 shown, a write path voltage V is supplied to the source-side selection gate lines SGS0 and SGS1. PASS .

[0158] In addition, at timing t105, a ground voltage V is supplied to the word line WL and the selection gate lines (SGD, SGS2, SGS1, SGS0, SGSb). SS .

[0159] In step S203 ( Figure 11 ), a WL verification operation is performed.

[0160] For example, Figure 12 in the example of, at timing t111, the WL verification operation starts.

[0161] In addition, at timing t111, a voltage V is supplied to one or more word lines WL. In addition, a read path voltage V is supplied to other word lines WL. In addition, a voltage V is supplied to the drain-side selection gate line SGD and the source-side selection gate lines SGS2, SGS1, SGS0, SGSb. In addition, as VFYW . READ . SG shown, a voltage V is supplied to the bit line BL. In addition, a voltage V is supplied to the source line SL. The voltage V Figure 15 . DD . SRC . The voltage V SRC is, for example, less than the voltage V VFYW . In addition, a voltage V is supplied to the dummy word lines DWL on the source line SL side and the bit line BL side. READ' .

[0162] In addition, from timing t111 to timing t112, it is detected whether the current flowing through the electron channel formed on the outer peripheral surface of the semiconductor layer 120 is below a specific magnitude, and data representing the current magnitude is obtained. This is performed by, for example, the same method as the method for detecting the on / off state of the memory cell MC.

[0163] In addition, at timing t112, as Figure 12 shown, a ground voltage V is supplied to the word line WL and the selection gate lines (SGD, SGS2, SGS1, SGS, SGSb). SS .

[0164] Step S204 ( Figure 11) Determine the result of the WL verification operation. For example, when the data representing the current magnitude contains a certain amount or more of "L", it is determined that the WL verification fails (FAIL), and the process proceeds to step S205. On the other hand, when the data representing the current magnitude does not contain a certain amount or more of "L", it is determined that the WL verification passes (PASS), and the process proceeds to step S207.

[0165] In step S205, determine whether the loop count n I has reached a specific number N I . If it has not reached, the process proceeds to step S206. If it has reached, the process proceeds to step S208.

[0166] In step S206, increment the loop count n I by 1, and the process proceeds to step S202. For example, Figure 12 in the example of, the operations corresponding to the timings t101 to t112 are performed at the timings t121 to t132. In addition, in step S206, for example, a specific voltage ΔV is added to the programming voltage V PGM . Therefore, as Figure 12 shown, the programming voltage V PGM supplied to the source-side select gate lines SGS1 and SGS0 at the timing t123 is greater than the programming voltage V PGM supplied to the source-side select gate lines SGS1 and SGS0 at the timing t103.

[0167] In step S207, in the status register STR ( Figure 1 ), store the status data D indicating the normal end of the current adjustment sequence ST , and end the current adjustment sequence.

[0168] In step S208, in the status register STR ( Figure 1 ), store the status data D indicating that the current adjustment sequence has not ended normally ST , and end the current adjustment sequence.

[0169] [Second Embodiment]

[0170] Next, with reference to Figures 16 - 18 , the current adjustment sequence of the semiconductor memory device according to the second embodiment will be described. Figure 16 is a schematic waveform diagram for explaining the current adjustment sequence. Figure 17 and Figure 18 are schematic cross-sectional views for explaining the SGS programming operation included in the current adjustment sequence.

[0171] The current adjustment sequence of the second embodiment is basically executed in the same manner as the current adjustment sequence of the first embodiment. However, a part of the current adjustment sequence of the second embodiment is different from the current adjustment sequence of the first embodiment.

[0172] That is, in the current adjustment sequence of the first embodiment, corresponding to the non-uniformity of the range of the impurity region 122, the source-side selection transistor STS that becomes the object of the SGS programming operation is selected.

[0173] On the other hand, in the voltage adjustment sequence of the second embodiment, the source-side selection transistor STS that becomes the object of the SGS programming operation is selected by adjusting the voltage of the bit line BL. In addition, at this time, since the source-side selection transistor STSb is set to the OFF state regardless of the non-uniformity of the range of the impurity region 122, a voltage V with a negative polarity is supplied to the source-side selection gate line SGSb. OFF .

[0174] Hereinafter, the current adjustment sequence of the second embodiment will be described in more detail.

[0175] For example, Figure 16 in the example of, at timing t201, the SGS programming operation is started. Here, during the SGS programming operation of the present embodiment, for example, a voltage V is supplied to the bit line BL connected to the source-side selection transistor STS (hereinafter, sometimes referred to as the "write selection transistor".) among the plurality of source-side selection transistors STS for which the threshold voltage is adjusted. SRC A voltage V is supplied to the bit line BL connected to the source-side selection transistor STS (hereinafter, sometimes referred to as the "forbidden selection transistor".) among the plurality of source-side selection transistors STS for which the threshold voltage is not adjusted. DD For example, "L" is latched into the control latch circuit of the voltage transfer circuit connected to the sense amplifier module SAM, and "H" is latched into the control latch circuit corresponding to the write selection transistor and "H" is latched into the control latch circuit corresponding to the forbidden selection transistor. In addition, different voltages are supplied to the write selection transistor and the forbidden selection transistor via the two voltage supply lines.

[0176] In addition, at timing t202, a write path voltage V is supplied to the word line WL. PASS In addition, a voltage V is supplied to the drain-side selection gate line SGD. SGD In addition, a write path voltage V is supplied to the source-side selection gate lines SGS2, SGS1, and SGS0. PASS In addition, a voltage V with a negative polarity less than the ground voltage V is supplied to the source-side selection gate line SGSb. SS OFF In addition, as . Figure 17As shown, a voltage V is supplied to the dummy word line DWL on the bit line BL side. PASS '. In addition, a write path voltage V is supplied to the dummy word line DWL on the source line SL side. PASS .

[0177] In addition, at timing t203, as Figure 16 and Figure 18 shown, a programming voltage V is supplied to the source side selection gate lines SGS0 and SGS1. PGM . As a result, electrons are accumulated in the charge accumulation film 132 of the write selection transistor, and the threshold voltage of the write selection transistor increases.

[0178] In addition, at timing t204, as Figure 16 shown, a write path voltage V is supplied to the source side selection gate lines SGS0 and SGS1. PASS .

[0179] In addition, at timing t205, a ground voltage V is supplied to the word line WL and the selection gate lines (SGD, SGS2, SGS1, SGS0, SGSb). SS .

[0180] In addition, at timings t211 to t212, a WL verification operation is performed. The WL verification operation is performed in the same manner as the WL verification operation of the first embodiment. However, in the second embodiment, a part of the write selection transistors is updated to prohibited selection transistors in accordance with the data indicating the current magnitude obtained in the WL verification operation.

[0181] Other operations are performed in the same manner as the operations in the current adjustment sequence of the first embodiment.

[0182] [Third Embodiment]

[0183] Next, with reference to Figures 19 - 21 , the current adjustment sequence of the semiconductor memory device according to the third embodiment will be described. Figure 19 is a schematic waveform diagram for explaining the current adjustment sequence. Figure 20 and Figure 21 are schematic cross-sectional views for explaining the SGS programming operation included in the current adjustment sequence.

[0184] The current adjustment sequence of the third embodiment is basically performed in the same manner as the current adjustment sequence of the second embodiment. However, a part of the current adjustment sequence of the third embodiment is different from the current adjustment sequence of the second embodiment.

[0185] That is, in the current adjustment sequence of the second embodiment, for example, as described with reference to Figure 16 and Figure 18 when the voltage V is applied, as explained.SRC In a state where a programming voltage V is supplied to bit lines BL corresponding to all write select transistors, at a timing t203 of the SGS programming operation, etc., the programming voltage V is supplied simultaneously with source side select gate lines SGS0 and SGS1 PGM .

[0186] On the other hand, in the current adjustment sequence of the third embodiment, for example, as Figure 19 and Figure 20 shown, in a state where a voltage V SRC is supplied to bit lines BL corresponding to all write select transistors, at a timing t313, the programming voltage V is supplied to the source side select gate line SGS0 PGM . Further, for example, as Figure 19 and Figure 21 shown, in a state where a voltage V SRC is supplied to bit lines BL corresponding to a part of write select transistors, at a timing t323, the programming voltage V is supplied to the source side select gate line SGS1 PGM .

[0187] Hereinafter, the current adjustment sequence of the third embodiment will be described in more detail.

[0188] For example, Figure 19 in the example of, at timings t301 to t302, a WL verification operation is performed. The WL verification operation is performed in the same manner as the WL verification operation of the second embodiment. However, in the third embodiment, in the WL verification operation, data indicating the magnitude of the current is acquired twice. Further, when acquiring data indicating the magnitude of the current, the discharge time of the sense node in the sense amplifier module SAM( Figure 1 , Figure 2 ) is made different between the first time and the second time. Thereby, data indicating whether the current flowing in each semiconductor layer 120 is greater than a first target value, and data indicating whether the current flowing in each semiconductor layer 120 is greater than a second target value are acquired. The second target value is, for example, greater than the first target value.

[0189] Further, at a timing t311, the SGS programming operation is started. Here, in the SGS programming operation of the present embodiment, for example, a voltage V SRC is supplied to the bit line BL connected to: among a plurality of source side select transistors STS, source side select transistors STS (hereinafter, sometimes referred to as "first write select transistors") in which the current flowing in the WL verification operation is greater than the first target value and less than the second target value; and source side select transistors STS (hereinafter, sometimes referred to as "second write select transistors") greater than the second target value. Further, a voltage V DD, the bit line is connected to a plurality of source-side selection transistors STS, and the source-side selection transistor STS (hereinafter, sometimes referred to as "forbidden selection transistor") in which the current flowing in the WL verification operation is less than the first target value.

[0190] In addition, at timing t312, a write path voltage V is supplied to the word line WL PASS . In addition, a voltage V is supplied to the drain-side selection gate line SGD SGD . In addition, a write path voltage V is supplied to the source-side selection gate lines SGS2, SGS1, SGS0 PASS . In addition, a voltage V is supplied to the source-side selection gate line SGSb OFF . In addition, as Figure 20 shown, a voltage V is supplied to the dummy word line DWL on the bit line BL side PASS '. In addition, a write path voltage V is supplied to the dummy word line DWL on the source line SL side PASS .

[0191] In addition, at timing t313, as Figure 20 shown, a programming voltage V is supplied to the source-side selection gate line SGS0 PGM . As a result, electrons are accumulated in the charge accumulation films 132 of the first write selection transistor and the second write selection transistor, and the threshold voltages of the first write selection transistor and the second write selection transistor increase.

[0192] In addition, at timing t314, as Figure 19 shown, a write path voltage V is supplied to the source-side selection gate line SGS0 PASS .

[0193] In addition, at timing t315, a ground voltage V is supplied to the word line WL and the selection gate lines (SGD, SGS2, SGS1, SGS0, SGSb) SS .

[0194] In addition, at timing t321, a voltage V is supplied to the bit line BL connected to the second write selection transistor SRC . In addition, a voltage V is supplied to the bit line BL connected to the first write selection transistor and the forbidden selection transistor DD .

[0195] In addition, at timing t322, a write path voltage V is supplied to the word line WL PASS . In addition, a voltage V is supplied to the drain-side selection gate line SGD SGD . In addition, a write path voltage V is supplied to the source-side selection gate lines SGS2, SGS1, SGS0 PASS . In addition, a voltage V is supplied to the source-side selection gate line SGSb OFF . In addition, asFigure 21 As shown, a voltage V is supplied to the dummy word line DWL on the bit line BL side. PASS In addition, a write path voltage V is supplied to the dummy word line DWL on the source line SL side. PASS .

[0196] In addition, at timing t323, as Figure 21 shown, a programming voltage V is supplied to the source side selection gate line SGS1. PGM Thereby, electrons are accumulated in the charge accumulation film 132 of the second write selection transistor, and the threshold voltage of the second write selection transistor increases.

[0197] In addition, at timing t324, as Figure 19 shown, a write path voltage V is supplied to the source side selection gate line SGS1. PASS .

[0198] In addition, at timing t325, a ground voltage V is supplied to the word line WL and the selection gate lines (SGD, SGS2, SGS1, SGS0, SGSb). SS .

[0199] [Fourth Embodiment]

[0200] Next, with reference to Figures 22 - 25 , the current adjustment sequence of the semiconductor memory device according to the fourth embodiment will be described. Figure 22 is a schematic flowchart for explaining the current adjustment sequence. Figure 23 is a schematic waveform diagram for explaining the current adjustment sequence. Figure 24 is a schematic cross-sectional view for explaining the TCWL programming operation included in the current adjustment sequence. Figure 25 is a schematic cross-sectional view for explaining the WL verification operation included in the current adjustment sequence.

[0201] The current adjustment sequence of the fourth embodiment is basically executed in the same manner as the current adjustment sequence of the second embodiment. However, a part of the current adjustment sequence of the fourth embodiment is different from the current adjustment sequence of the second embodiment.

[0202] That is, in the current adjustment sequence of the second embodiment, the current non-uniformity between the semiconductor layers 120 is suppressed by adjusting the threshold voltage of the source side selection transistor STS.

[0203] However, this method is merely illustrative, and the specific method and so on can be appropriately adjusted. For example, in order to suppress the current imbalance between the semiconductor layers 120, the threshold voltage of the drain-side selection transistor STD can be adjusted, or the threshold voltage of the dummy memory cell DMC on the source line SL side or the bit line BL side can be adjusted. In addition, any one of the multiple memory cells MC can be used to suppress the current imbalance between the semiconductor layers 120 instead of data recording. Hereinafter, such a memory cell MC is sometimes referred to as a "memory cell for threshold voltage adjustment". In addition, the word line connected to the memory cell MC is sometimes referred to as a "word line for threshold voltage adjustment TCWL".

[0204] For example, in the fourth embodiment, an example of a memory cell MC located on the source line SL side (the memory cell MC adjacent to the dummy memory cell DMC on the source line SL side) among the multiple memory cells MC arranged in the Z direction is described as an example of a memory cell for threshold voltage adjustment.

[0205] Next, the current adjustment sequence of the fourth embodiment will be described in more detail.

[0206] As Figure 22 shown, the current adjustment sequence of the fourth embodiment is basically implemented in the same manner as the current adjustment sequence of the second embodiment. However, in the fourth embodiment, the TCWL programming operation (step S402) is performed instead of the SGS programming operation.

[0207] For example, Figure 23 in the example of, at time t401, the TCWL programming operation starts. Here, during the TCWL programming operation of the present embodiment, for example, a voltage V SRC is supplied to the bit line BL connected to the memory cell (hereinafter, sometimes referred to as a "memory cell for write adjustment".) for threshold voltage adjustment among the multiple memory cells for threshold voltage adjustment. A voltage V DD is supplied to the bit line BL connected to the memory cell (hereinafter, sometimes referred to as a "memory cell for prohibited adjustment".) that does not perform threshold voltage adjustment among the multiple memory cells for threshold voltage adjustment. For example, "L" is latched into the control latch circuit of the voltage transfer circuit connected to the sense amplifier module SAM, and "H" is latched into the latch circuit corresponding to the memory cell for prohibited adjustment corresponding to the latch circuit corresponding to the memory cell for write adjustment. In addition, different voltages are supplied to the memory cell for write adjustment and the memory cell for prohibited adjustment via the two voltage supply lines.

[0208] In addition, at time t402, a write path voltage V PASS is supplied to the threshold voltage adjustment word line TCWL and other word lines WL. In addition, a voltage V SGDIn addition, a ground voltage V is supplied to the source-side select gate line SGS. SS In addition, as Figure 24 shown, a voltage V PASS ' is supplied to the dummy word line DWL on the bit line BL side. In addition, a voltage V PASS ” is supplied to the dummy word line DWL on the source line SL side.

[0209] In addition, at timing t403, as Figure 24 shown, a programming voltage V PGM is supplied to the threshold voltage adjustment word line TCWL. Thereby, electrons are accumulated in the charge accumulation film 132 of the write adjustment storage cell, and the threshold voltage of the write adjustment storage cell increases.

[0210] In addition, at timing t404, as Figure 23 shown, a write path voltage V PASS is supplied to the threshold voltage adjustment word line TCWL.

[0211] In addition, at timing t405, a ground voltage V is supplied to the threshold voltage adjustment word line TCWL, other word lines WL, and select gate lines (SGD, SGS, SGSb). SS

[0212] In addition, at timings t411 to t412, a WL verification operation is performed. The WL verification operation is performed in the same manner as the WL verification operation of the second embodiment. However, in the fourth embodiment, as Figure 25 shown, the same voltage V READ ' as the dummy word line DWL on the source line SL side is supplied to the threshold voltage adjustment word line TCWL. In addition, in the fourth embodiment, a part of the write adjustment storage cells is updated to prohibited adjustment storage cells corresponding to the data indicating the magnitude of the current obtained in the WL verification operation.

[0213] Other operations are performed in the same manner as the operations in the current adjustment sequence of the second embodiment.

[0214] In addition, in the fourth embodiment, one of the plurality of storage cells MC arranged in the Z direction is used as the threshold voltage adjustment storage cell. However, this method is merely an example, and the specific method and the like can be appropriately adjusted. For example, two or more of the plurality of storage cells MC arranged in the Z direction can also be used as the threshold voltage adjustment storage cell.

[0215] In addition, in this case, for example, similar to the third embodiment, in the verification operation, data indicating whether the current flowing through each semiconductor layer 120 is greater than the first target value and data indicating whether the current flowing through each semiconductor layer 120 is greater than the second target value are obtained. In addition, in the TCWL programming operation, a programming voltage V is supplied to a specific threshold voltage adjustment word line TCWL PGM When, a voltage V is supplied to the bit line BL SRC , the bit line is connected to: a memory cell in which the current flowing in the WL verification operation is greater than the first target value and less than the second target value (hereinafter, sometimes referred to as "the first write adjustment memory cell"); and a memory cell in which the current is greater than the second target value (hereinafter, sometimes referred to as "the second write adjustment memory cell"), and a voltage V is supplied to other bit lines BL DD . In addition, when a programming voltage V is supplied to other threshold voltage adjustment word lines TCWL PGM , a voltage V is supplied to the bit line BL connected to the second write adjustment memory cell SRC , and a voltage V is supplied to other bit lines BL DD .

[0216] [Fifth Embodiment]

[0217] Next, with reference to Figure 26 , the current adjustment sequence of the semiconductor memory device according to the fifth embodiment will be described. Figure 26 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device of this embodiment.

[0218] The semiconductor memory device of the fifth embodiment is basically configured in the same manner as the semiconductor memory devices of the first to fourth embodiments. However, a part of the configuration of the semiconductor memory device of the fifth embodiment is different from that of the semiconductor memory devices of the first to fourth embodiments.

[0219] For example, in the first to fourth embodiments, as described with reference to Figure 4 and the like, a conductive layer 111 that functions as a source-side gate line SGSb is provided below the plurality of conductive layers 110, and a conductive layer 112 that functions as a source line SL is provided below the conductive layer 111. However, this configuration is merely an example, and the specific configuration and the like can be appropriately adjusted.

[0220] For example, Figure 26 in the example of, a conductive layer 511 is provided below the plurality of conductive layers 110. The conductive layer 511 includes a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 511 functions as a source-side select gate line SGSb ( Figure 2), and the gate electrodes of a plurality of source - side selection transistors STSb connected thereto function.

[0221] In addition, Figure 26 In the example of [], the semiconductor memory device includes a semiconductor layer 520 replacing the semiconductor layer 120. The semiconductor layer 520 is substantially configured in the same manner as the semiconductor layer 120 of the first to fourth embodiments. However, at the lower end of the semiconductor layer 520, the impurity region 122 is not connected.

[0222] In addition, Figure 26 In the example of [], the lower end of the semiconductor layer 520 is connected to the P - type well region of the semiconductor substrate 100 via a semiconductor layer 522 such as single - crystal silicon (Si). In addition, an insulating film 523 such as silicon oxide (SiO2) is provided between the semiconductor layer 522 and the conductive layer 511.

[0223] Here, in such a configuration, in the manufacturing process, the contact area between the lower end of the semiconductor layer 520 and the semiconductor layer 522 may sometimes be uneven. Along with this, the magnitude of the current may sometimes be uneven between the semiconductor layers 520.

[0224] Therefore, in the fifth embodiment, the current adjustment procedure in any one of the first to fourth embodiments is performed. Thereby, the current unevenness between the semiconductor layers 520 can be suppressed.

[0225] [Other Embodiments]

[0226] Above, the semiconductor memory device of the first to fifth embodiments and the method for adjusting its operating conditions have been described. However, the above description is merely an example, and the specific configuration and method can be adjusted as appropriate.

[0227] For example, as illustrated with reference to Figure 11 , in the current adjustment procedures of the first to third embodiments, while increasing the loop count n I , the SGS programming operation and the WL verification operation are repeatedly executed. In addition, as illustrated with reference to Figure 22 , in the current adjustment procedure of the fourth embodiment, while increasing the loop count n I , the TCWL programming operation and the WL verification operation are repeatedly executed. However, such operations are merely examples, and the specific method can be adjusted as appropriate. For example, in the first to fifth embodiments, only one WL verification operation can be performed, and then only one SGS programming operation or TCWL programming operation can be performed.

[0228] In addition, for example, the semiconductor memory devices of the first to fifth embodiments can also be configured to execute the current adjustment procedure according to the input of a specific command.

[0229] [Others]

[0230] Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. The embodiments or their variations are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents.

[0231] [Description of Reference Signs]

[0232] MC storage unit

[0233] MCA storage unit array

[0234] ADD address data

[0235] CMD command data

[0236] PC peripheral circuit.

Claims

1. A method for adjusting the operating conditions of a semiconductor memory device, wherein the semiconductor memory device includes: a substrate; a plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate; a plurality of first semiconductor layers extending in the first direction and facing the plurality of first conductive layers; a second semiconductor layer spaced from the substrate in the first direction and connected to one end portion of the plurality of first semiconductor layers in the first direction; and a charge accumulation layer provided between the plurality of first conductive layers and the plurality of first semiconductor layers; and at a specific timing of a programming operation, a programming voltage or a write path voltage less than the programming voltage is supplied to a second conductive layer which is one of the plurality of first conductive layers, a first operation and a second operation are performed in the adjustment method, the first operation is to supply the write path voltage to the second conductive layer and supply the programming voltage to a third conductive layer which is one of the plurality of first conductive layers, the second operation is to supply a verification voltage less than the write path voltage to the second conductive layer and supply a voltage less than the programming voltage to the third conductive layer, if a plurality of first conductive layers closest to the second semiconductor layer among the plurality of first conductive layers are set as a plurality of fourth conductive layers, then at a specific timing of the programming operation, a voltage less than the write path voltage is supplied to the plurality of fourth conductive layers, the third conductive layer is one of the plurality of fourth conductive layers.

2. The method for adjusting the operating conditions of the semiconductor memory device according to claim 1, wherein the first operation and the second operation are repeatedly performed.

3. The method for adjusting the operating conditions of the semiconductor memory device according to claim 1, wherein in the first operation and the second operation, a first voltage less than the verification voltage is supplied to the second semiconductor layer.

4. The method for adjusting the operating conditions of the semiconductor memory device according to claim 1, wherein if a plurality of first conductive layers farthest from the second semiconductor layer among the plurality of first conductive layers are set as a plurality of fifth conductive layers, then in the first operation, a second voltage less than the verification voltage is supplied to the plurality of fifth conductive layers.

5. The method for adjusting the operating conditions of the semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a plurality of bit lines connected to the other end portion of the plurality of first semiconductor layers in the first direction, at a specific timing of the first operation, different voltages are supplied to a first bit line which is one of the plurality of bit lines and a second bit line which is one of the plurality of bit lines.

6. The method for adjusting the operating conditions of the semiconductor memory device according to claim 5, wherein the plurality of first conductive layers include a sixth conductive layer closer to the second semiconductor layer than the third conductive layer, at a specific timing of the first operation, a third voltage having a negative polarity is supplied to the sixth conductive layer.

7. The method for adjusting the operating conditions of the semiconductor memory device according to claim 1, wherein at a first timing of the first operation, Apply the write path voltage to the second conductive layer. Apply the programming voltage to the third conductive layer. Apply the write path voltage to the seventh conductive layer, which is one of the plurality of first conductive layers. At the second timing of the first operation. Apply the write path voltage to the second conductive layer. Apply the write path voltage to the third conductive layer. Apply the programming voltage to the seventh conductive layer.

8. The method for adjusting the operating conditions of the semiconductor memory device according to claim 7, wherein The plurality of first conductive layers include an eighth conductive layer, and the eighth conductive layer is closer to the second semiconductor layer than the third conductive layer and the seventh conductive layer. At the first timing, apply a third voltage with a negative polarity to the eighth conductive layer. At the second timing, apply the third voltage to the eighth conductive layer.

9. The method for adjusting the operating conditions of the semiconductor memory device according to claim 1, wherein The semiconductor memory device includes a third semiconductor layer, which is disposed between the second semiconductor layer and the plurality of first conductive layers and faces the plurality of first semiconductor layers. The second semiconductor layer contains N-type impurities.

10. A method for adjusting the operating conditions of a semiconductor memory device, wherein The semiconductor memory device includes: A substrate; A plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate; A plurality of first semiconductor layers extending in the first direction and facing the plurality of first conductive layers; A second semiconductor layer, which is a part of the substrate and is connected to one end portion of the plurality of first semiconductor layers in the first direction; And A charge accumulation layer disposed between the plurality of first conductive layers and the plurality of first semiconductor layers; and At a specific timing of the programming operation, apply a programming voltage or a write path voltage less than the programming voltage to the second conductive layer, which is one of the plurality of first conductive layers. In the adjustment method, perform a first operation and a second operation. The first operation is to apply the write path voltage to the second conductive layer and apply the programming voltage to the third conductive layer, which is one of the plurality of first conductive layers. The second operation is to apply a verification voltage less than the write path voltage to the second conductive layer and apply a voltage less than the programming voltage to the third conductive layer. If the plurality of first conductive layers closest to the second semiconductor layer are set as a plurality of fourth conductive layers. Then at a specific timing of the programming operation, apply a voltage less than the write path voltage to the plurality of fourth conductive layers. The third conductive layer is one of the plurality of fourth conductive layers.

11. The method for adjusting the operating conditions of the semiconductor memory device according to claim 10. It repeatedly performs the first operation and the second operation.

12. The method for adjusting the operating conditions of the semiconductor memory device according to claim 10, wherein In the first operation and the second operation, apply a first voltage less than the verification voltage to the second semiconductor layer.

13. A method for adjusting the operating conditions of a semiconductor memory device according to claim 10, wherein if among the plurality of first conductive layers, the plurality of first conductive layers farthest from the second semiconductor layer are set as a plurality of fifth conductive layers, then in the first operation, a second voltage less than the verification voltage is supplied to the plurality of fifth conductive layers.

14. A method for adjusting the operating conditions of a semiconductor memory device according to claim 10, wherein the semiconductor memory device includes a plurality of bit lines, and the bit lines are connected to the other end portions of the plurality of first semiconductor layers in the first direction, at a specific timing of the first operation, different voltages are supplied to a first bit line which is one of the plurality of bit lines and a second bit line which is one of the plurality of bit lines.

15. A method for adjusting the operating conditions of a semiconductor memory device according to claim 14, wherein the plurality of first conductive layers include a sixth conductive layer closer to the second semiconductor layer than the third conductive layer, at a specific timing of the first operation, a third voltage having a negative polarity is supplied to the sixth conductive layer.

16. A method for adjusting the operating conditions of a semiconductor memory device according to claim 10, wherein at a first timing of the first operation, the write path voltage is supplied to the second conductive layer, the programming voltage is supplied to the third conductive layer, the write path voltage is supplied to a seventh conductive layer which is one of the plurality of first conductive layers, at a second timing of the first operation, the write path voltage is supplied to the second conductive layer, the write path voltage is supplied to the third conductive layer, the programming voltage is supplied to the seventh conductive layer.

17. A method for adjusting the operating conditions of a semiconductor memory device according to claim 16, wherein the plurality of first conductive layers include an eighth conductive layer, and the eighth conductive layer is closer to the second semiconductor layer than the third conductive layer and the seventh conductive layer, at the first timing, a third voltage having a negative polarity is supplied to the eighth conductive layer, at the second timing, the third voltage is supplied to the eighth conductive layer.

18. A method for adjusting the operating conditions of a semiconductor memory device, wherein the semiconductor memory device includes: a substrate; a plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate; a plurality of first semiconductor layers extending in the first direction and facing the plurality of first conductive layers; a second semiconductor layer spaced apart from the substrate in the first direction and connected to one end portion of the plurality of first semiconductor layers in the first direction; and a charge accumulation layer provided between the plurality of first conductive layers and the plurality of first semiconductor layers; and at a specific timing of a programming operation, a programming voltage is supplied to a second conductive layer which is one of the plurality of first conductive layers, and a write path voltage less than the programming voltage is supplied to a plurality of third conductive layers included in the plurality of first conductive layers, a first operation and a second operation are performed in the adjustment method, The first operation is to supply the write path voltage to the second conductive layer and the plurality of third conductive layers, and supply the programming voltage to a fourth conductive layer which is one of the plurality of first conductive layers. The second operation is to supply a verification voltage smaller than the write path voltage to the second conductive layer, supply a read path voltage smaller than the write path voltage and larger than the verification voltage to the plurality of third conductive layers, and supply a voltage smaller than the write path voltage to the fourth conductive layer.

19. A method for adjusting operation conditions of a semiconductor memory device, wherein the semiconductor memory device includes: a substrate; a plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate; a plurality of first semiconductor layers extending in the first direction and facing the plurality of first conductive layers; a second semiconductor layer which is a part of the substrate and is connected to one end portion of the plurality of first semiconductor layers in the first direction; and a charge accumulation layer provided between the plurality of first conductive layers and the plurality of first semiconductor layers; and at a specific timing of a programming operation, supply a programming voltage to a second conductive layer which is one of the plurality of first conductive layers, and supply a write path voltage smaller than the programming voltage to the plurality of third conductive layers included in the plurality of first conductive layers. In the adjustment method, a first operation and a second operation are performed. The first operation is to supply the write path voltage to the second conductive layer and the plurality of third conductive layers, and supply the programming voltage to a fourth conductive layer which is one of the plurality of first conductive layers. The second operation is to supply a verification voltage smaller than the write path voltage to the second conductive layer, supply a read path voltage smaller than the write path voltage and larger than the verification voltage to the plurality of third conductive layers, and supply a voltage smaller than the write path voltage to the fourth conductive layer.

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