Integrated circuit memory and preparation method thereof, semiconductor integrated circuit device

Abstract

The present invention relates to an integrated circuit memory and a method for preparing the same, and a semiconductor integrated circuit device, comprising: providing a substrate; forming a bit line extending in a first direction on the substrate; forming a word line extending in a second direction on the bit line; forming a vertical storage transistor on an overlapping region where the word line and the bit line intersect in space, wherein the vertical storage transistor is located in the word line and connected to the bit line. The present application omits the step of preparing a bit line contact hole to connect the bit line and the drain region of the storage transistor, and the unit configuration size of the vertical storage transistor on the substrate is relatively small, so the size of the memory can be further reduced accordingly. In addition, the vertical storage transistor also has better arrangement flexibility, which is conducive to the dense arrangement of the vertical storage transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated circuit memory and a method for preparing the same, and a semiconductor integrated circuit device. Background Art

[0002] With the increasing integration in semiconductor manufacturing processes, it has become a trend to improve the integration density of memory. However, current technological development has been limited by the resolution of the lithography equipment available at the time. Specifically, the size of semiconductor integrated circuit devices, such as the minimum size of line width CD (Critical Dimension) and line spacing S (spaces), depends on the resolution capability of the lithography equipment. Therefore, under the limitation of the minimum feature size that can be obtained by the lithography equipment, graphics smaller than the minimum feature size cannot be stably obtained. This will limit the further reduction of the size of semiconductor devices and will not be able to further increase the density of the arrangement of unit elements in semiconductor devices.

[0003] For a memory (e.g., a dynamic random access memory DRAM), its storage unit includes a storage transistor and a storage capacitor connected thereto, and the storage capacitor is used to store charges representing stored information. An active region, a drain region, and a gate are formed in the storage transistor, and the gate is used to control the current flow between the source region and the drain region and is connected to the word line, the drain region is used to form a bit line contact region to connect to the bit line, and the source region is used to form a storage node contact region to connect to the storage capacitor. The source region, channel region, and drain region of the storage transistor are horizontally distributed along a direction parallel to the surface of the substrate. When the storage transistor of the storage unit is normally turned on, its channel current generally flows between the source region and the drain region in a horizontal direction. Then, when the storage transistor is reduced to a predetermined size, the short channel effect of the storage transistor will be easily generated. It can be seen that the size of the existing memory is not only limited by the resolution of the lithography equipment, but also needs to consider the short channel effect brought about by the reduction in size. Summary of the invention

[0004] Based on this, it is necessary to provide an integrated circuit memory and a method for preparing the same, and a semiconductor integrated circuit device to address the above problems.

[0005] A method for preparing an integrated circuit memory, comprising:

[0006] providing a substrate;

[0007] forming a bit line on the substrate, wherein the bit line extends along a first direction;

[0008] forming a word line on the bit line, the word line extending along a second direction;

[0009] A vertical memory transistor is formed in an overlapping region where the word line and the bit line spatially intersect, the vertical memory transistor being located in the word line and connected to the bit line.

[0010] In one embodiment, the step of forming a vertical storage transistor in the overlapping region where the word line and the bit line intersect spatially comprises:

[0011] Opening a through hole in the overlapping area, wherein the through hole exposes the bit line;

[0012] forming an active pillar of the vertical storage transistor and a gate dielectric layer surrounding the active pillar in the through hole;

[0013] Wherein, the diameter of the through hole is smaller than the width of the word line.

[0014] In one embodiment, the step of opening a through hole in the overlapping area comprises:

[0015] forming a first sacrificial layer pattern, wherein the first sacrificial layer pattern covers a preset area of ​​the through hole and exposes an area outside the preset area;

[0016] The through hole is opened in the preset area through a pattern transfer process.

[0017] In one embodiment, the step of forming an active pillar of the vertical storage transistor and a gate dielectric layer surrounding the active pillar in the through hole comprises:

[0018] forming an annular gate dielectric layer on the sidewall of the through hole;

[0019] An active column is formed in the through hole, a first doping region is formed in the bottom end of the active column and connected to the bit line, a second doping region is formed in the top end of the active column, the second doping region is used to connect the storage element, and a third doping region is formed between the bottom end and the top end of the active column;

[0020] The first doping region, the second doping region and the third doping region respectively constitute the drain, source and channel region of the vertical storage transistor.

[0021] In one embodiment, before forming a word line on the bit line, the method further includes:

[0022] An insulating dielectric layer is formed on the substrate, wherein the insulating dielectric layer fills the gaps between adjacent bit lines and covers the bit lines.

[0023] In one embodiment, after forming the word line on the substrate, the method further comprises:

[0024] A spacer dielectric layer is formed on the substrate, and the spacer dielectric layer fills the gaps between adjacent word lines and covers the word lines.

[0025] In one embodiment, the width of the word line, the width of the bit line, the spacing between adjacent word lines, and the spacing between adjacent bit lines are all preset values, and the preset values ​​are greater than or equal to 30 nanometers and less than or equal to 60 nanometers.

[0026] In one embodiment, the second direction in which the word line extends and the first direction in which the bit line extends intersect each other on the substrate and have a first angle, and the first angle is greater than or equal to 60 degrees and less than or equal to 90 degrees.

[0027] In one embodiment, the step of forming an annular gate dielectric layer on the sidewall of the through hole comprises:

[0028] Forming a gate dielectric layer film in the through hole, wherein the gate dielectric layer film covers the side wall and the bottom wall of the through hole;

[0029] forming a protective layer film on the gate dielectric layer film;

[0030] Removing the gate dielectric layer film and the protective layer film on the bottom wall by an etching process, and opening the through hole to expose the bit line;

[0031] The distance between the bottom of the opening and the top of the bit line is greater than or equal to 5 nanometers and less than or equal to 8 nanometers; the distance between the bottom of the through hole and the top of the bit line is greater than or equal to 3 nanometers and less than or equal to 5 nanometers.

[0032] In one embodiment, one of the overlapping regions corresponds to one of the vertical memory transistors, and a unit configuration size of the vertical memory transistor on the substrate is greater than or equal to 4 times the square of a minimum feature size.

[0033] The manufacturing method of the integrated circuit memory forms a vertical memory transistor in the overlapping area where the word line and the bit line intersect in space, that is, the source region, the channel region and the drain region are arranged vertically along the height direction, and the vertical memory transistor is located in the word line and connected to the bit line, eliminating the step of preparing a bit line contact hole to connect the bit line and the drain region of the memory transistor, and the manufacturing process is simple; and the unit configuration size of the vertical memory transistor on the substrate is small (for example, the unit configuration size can reach 4F 2 ), so the size of the memory can be further reduced accordingly.

[0034] An integrated circuit memory, comprising:

[0035] substrate;

[0036] A bit line formed on the substrate and extending along a first direction;

[0037] A word line formed on the bit line and extending along the second direction;

[0038] A vertical storage transistor is formed in an overlapping area where the word line and the bit line intersect in space, is located in the word line, and is connected to the bit line.

[0039] In one embodiment, the integrated circuit memory further includes a through hole, which is opened on the overlapping area and exposes the bit line, and the active pillar of the vertical storage transistor and the gate dielectric layer surrounding the active pillar are arranged in the through hole; wherein the diameter of the through hole is smaller than the width of the word line.

[0040] In one embodiment, the vertical storage transistor comprises:

[0041] An annular gate dielectric layer, located on the sidewall of the through hole;

[0042] An active pillar is located in the through hole, a first doped region is formed in the bottom end of the active pillar and is connected to the bit line, a second doped region is formed in the top end of the active pillar, the second doped region is used to connect the storage element, a third doped region is formed between the bottom end and the top end of the active pillar, the first doped region, the second doped region and the third doped region respectively constitute the drain, source and channel region of the vertical storage transistor.

[0043] In one embodiment, the integrated circuit memory comprises:

[0044] an insulating dielectric layer, the insulating dielectric layer filling the gaps between adjacent bit lines and covering the bit lines;

[0045] A spacer dielectric layer is provided, wherein the spacer dielectric layer fills the gaps between adjacent word lines and covers the word lines.

[0046] In one embodiment, the width of the word line, the width of the bit line, the spacing between adjacent word lines, and the spacing between adjacent bit lines are all preset values, and the preset values ​​are greater than or equal to 30 nanometers and less than or equal to 60 nanometers.

[0047] In one embodiment, the second direction in which the word line extends and the first direction in which the bit line extends intersect each other when projected on the substrate and have a first angle, and the first angle is greater than or equal to 60 degrees and less than or equal to 90 degrees;

[0048] One of the overlapping regions corresponds to one of the vertical memory transistors, and a unit configuration size of the vertical memory transistor on the substrate is greater than or equal to 4 times the square of a minimum feature size.

[0049] In the integrated circuit memory, the vertical storage transistor is formed in the overlapping area where the word line and the bit line intersect in space, that is, the source region, the channel region and the drain region are arranged vertically along the height direction, and the vertical storage transistor is located in the word line and connected to the bit line, eliminating the bit line contact hole connecting the bit line and the drain region of the storage transistor; and the unit configuration size of the vertical storage transistor on the substrate is small (for example, the unit configuration size can reach 4F 2 ), so the size of the memory can be further reduced accordingly.

[0050] A semiconductor integrated circuit device, comprising:

[0051] substrate;

[0052] A first conductive line formed on the substrate and extending along a first direction;

[0053] a second conductive line formed on the first conductive line and extending along a second direction;

[0054] The vertical storage transistor is formed in an overlapping area where the second conductive line and the first conductive line intersect in space, is located in the second conductive line, and is connected to the first conductive line.

[0055] In the semiconductor integrated circuit device, the vertical storage transistor is formed in the overlapping region where the second conductive line and the first conductive line intersect in space, that is, the source region, the channel region and the drain region are arranged vertically along the height direction, and the vertical storage transistor is located in the second conductive line and connected to the first conductive line, eliminating the second conductive line contact hole connecting the first conductive line and the drain region of the storage transistor, and the unit configuration size of the vertical storage transistor on the substrate is small (for example, the unit configuration size can reach 4F 2 ), so the size of the memory can be further reduced accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 It is a schematic diagram of the structure of a typical integrated circuit memory;

[0058] Figure 2 is a flow chart of a method for preparing an integrated circuit memory in one embodiment;

[0059] Figure 3 is a top view of an integrated circuit memory after executing step S104 in one embodiment;

[0060] Figure 4 for Figure 3 A cross-sectional view of the integrated circuit memory shown along the AA' direction;

[0061] Figure 5 Figure 4 A cross-sectional view of the integrated circuit memory along the AA' direction before the corresponding step S106 is executed;

[0062] Figure 6 Figure 5 A top view of the integrated circuit memory after executing step S106;

[0063] Figure 7 for Figure 6 The corresponding cross-sectional view along the BB' direction;

[0064] Figure 8 is a cross-sectional view of an integrated circuit memory after an isolation dielectric layer is formed on a substrate;

[0065] Fig. 9 A flow chart of forming a vertical storage transistor in the extension direction of a word line in one embodiment;

[0066] Fig.10 is a flow chart of opening a through hole in the extending direction of a word line in one embodiment;

[0067] Fig.11 A top view of an integrated circuit memory after a transition sacrificial layer pattern along a word line direction is obtained in a process of forming a first sacrificial layer pattern through an etching process;

[0068] Fig.12 for Fig.11 The cross-sectional view of the integrated circuit memory shown is taken along the BB' direction, wherein BB' is the first direction in which the bit lines extend;

[0069] Fig.13 A top view of the integrated circuit memory after forming a first sacrificial layer pattern;

[0070] Fig.14 for Fig.13 The cross-sectional view of the integrated circuit memory shown is taken along the AA' direction, wherein AA' is the second direction in which the word lines extend;

[0071] Fig.15 A cross-sectional view of the integrated circuit memory along the BB' direction after the through hole is formed in step S304;

[0072] Fig.16 A cross-sectional view of the integrated circuit memory along the AA' direction after the through hole is formed in step S304;

[0073] Fig.17 It is a cross-sectional view of the integrated circuit memory along the AA' direction after the gate dielectric layer film is formed;

[0074] Fig.18 A cross-sectional view of the integrated circuit memory along the AA' direction after the annular gate dielectric layer is formed;

[0075] Fig.19 A cross-sectional view of the integrated circuit memory along the AA' direction after forming a vertical memory transistor;

[0076] Fig. 20 Flowchart for forming a vertical memory transistor. DETAILED DESCRIPTION

[0077] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0079] It should be understood that when an element or layer is referred to as being "on, "adjacent to, " "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to," or "directly coupled to," other elements or layers, there are no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0080] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0081] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0082] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0083] Figure 1 A typical schematic diagram of a memory structure is shown in FIG. Figure 1 The memory comprises:

[0084] A substrate, wherein a plurality of active regions 10 are defined in the substrate, wherein the active region 10 has a first doping region and two second doping regions located on both sides of the first doping region;

[0085] A word line 20 is formed on the substrate and intersects with the corresponding active area 10, and the portion where the word line 20 intersects with the active area 10 is used to form a gate of a storage transistor;

[0086] The bit line 30 is formed on the substrate and electrically connected to the first doped region of the corresponding active region 10 to lead out the first doped region.

[0087] The active area 10 of the storage transistor is formed by horizontal diffusion, that is, the first doped area and the second doped area are horizontally distributed in a direction parallel to the surface of the substrate, thereby forming a storage transistor with a horizontal structure. When the size of the storage transistor is reduced, the size of the active area 10 is correspondingly reduced, which will easily increase the risk of short channel effect. In addition, even if the short channel effect of the storage transistor is not considered, the size of the storage transistor cannot be further reduced due to the resolution limitation of the lithography equipment. The width dimension D2 of a storage transistor in the direction perpendicular to the word line 20 is 3F, and the width dimension D1 in the direction perpendicular to the bit line 30 is 2F. The area required to configure a storage transistor on the substrate is 6F. 2 (3F*2F, i.e. 3×2 buried word line structure), where F is the minimum feature size, i.e. the minimum limit line width and minimum limit line spacing that can be obtained based on the resolution of the current lithography equipment. The minimum limit line width and the minimum limit line spacing are equal. That is, based on the resolution of the existing lithography equipment, the unit size of the prepared memory transistor can only reach 6F.2 , and cannot be further reduced.

[0088] also, Figure 1 In the memory shown, a bit line contact hole needs to be additionally prepared above the second doped region of the active region to connect the second doped region and the bit line, and the preparation process is relatively complicated.

[0089] See also Figure 2 The present invention provides a method for preparing an integrated circuit memory, comprising the following steps:

[0090] S102, providing a substrate.

[0091] The substrate may be a semiconductor material substrate such as silicon, germanium, silicon germanium, gallium arsenide, or an insulating substrate silicon-on-insulator (SOI), etc., and examples are not given one by one here.

[0092] S104, forming a bit line on the substrate, wherein the bit line extends along a first direction.

[0093] S106, forming a word line on the bit line, wherein the word line extends along a second direction.

[0094] S108 , forming a vertical storage transistor in an overlapping region where the word line and the bit line spatially intersect, wherein the vertical storage transistor is located in the word line and connected to the bit line.

[0095] The above-mentioned method for preparing the integrated circuit memory forms a memory in which the memory transistor is a vertical transistor, which is more conducive to reducing the size of a single memory transistor compared to a memory transistor with a horizontal structure, thereby effectively reducing the size of the entire memory. In addition, the vertical memory transistor is located in the word line and connected to the bit line, eliminating the step of preparing a bit line contact hole connecting the bit line and the drain region of the memory transistor, and the preparation process is simple.

[0096] The various steps of the preparation method in this embodiment are described in detail below with reference to the accompanying drawings.

[0097] Figure 3 is a top view of the integrated circuit memory after executing step S104 in one embodiment, Figure 4 for Figure 3 A cross-sectional view of the integrated circuit memory shown along the AA' direction;

[0098] Combination Figure 3 and Figure 4In one embodiment, the bit line is a stacked structure, and step S104 includes: sequentially forming a first isolation layer film, a bit line conductive layer film, a bit line work function film, and a bit line contact layer film on the surface of the substrate, forming a first mask pattern on the surface of the substrate by a photolithography process, wherein the first mask pattern exposes the bit line contact layer film to be removed; after removing the first isolation layer film, the bit line conductive layer film, the bit line work function film, and part of the bit line contact layer film in the area exposed by the first mask pattern by an etching process, forming a bit line on the surface of the substrate. The bit line 102 and the first opening 104 located between adjacent bit lines 102; the bit line 120 is composed of a bit line contact layer 202, a bit line work function layer (not shown), a bit line conductive layer 204 and a bit line isolation layer 206 from the top surface to the substrate, wherein a distance H1 between the top and the bottom of the bit line isolation layer 206 is greater than or equal to 10 nanometers and less than or equal to 20 nanometers, wherein the bit line isolation layer 206 is formed by etching a first isolation layer film, and the remaining unetched first isolation layer film constitutes a first insulating layer between the bit line and the substrate.

[0099] The material of the bit line isolation layer 206 includes silicon nitride, the material of the bit line conductive layer 204 includes tungsten (W), the material of the bit line work function layer includes at least one of tungsten silicide and titanium nitride (TiN), and the material of the bit line contact layer 202 includes doped polysilicon (Poly).

[0100] It should be noted that the conductivity type of the doped ions in the doped polysilicon layer of the bit line contact layer 202 can be adjusted accordingly according to the conductivity type of the vertical memory transistor. For example, if the conductivity type of the vertical memory transistor is P-type, the doped polysilicon layer in the bit line contact layer can also be doped with P-type accordingly.

[0101] In one embodiment, the bit line 102 further includes an adhesion layer (not shown) between the bit line contact layer 202 and the bit line work function layer. The material of the adhesion layer includes, for example, one or more of titanium, titanium nitride, and tungsten silicide.

[0102] In other embodiments, before step S104, a step of forming a stress buffer layer between the substrate and the first insulating layer is also included. The material of the stress buffer layer includes, for example, an oxide layer. The thickness of the oxide layer can be 5 nanometers. In actual processes, the material, thickness and process of the stress buffer layer can be selected as needed.

[0103] Exemplarily, step S104 is specifically as follows: first, forming an oxide layer (e.g., 5 nm) for buffering stress on the surface of the substrate by a thermal oxidation process; second, forming a silicon nitride film (e.g., 100 nm) on the oxide layer by a furnace tube process; third, depositing a tungsten metal film (e.g., 21 nm) on the silicon nitride by a physical vapor deposition process (PVD); fourth, depositing a tungsten silicide film (e.g., 2.5 nm) on the tungsten metal film by a chemical vapor deposition process (CVD), and the ratio of tungsten to silicon in the tungsten silicide film can be adjusted according to the needs of the bit line resistance; fifth, depositing a tungsten metal film (e.g., 21 nm) on the silicon nitride by a physical vapor deposition process (PVD); fifth, depositing a tungsten silicide film (e.g., 2.5 nm) on the tungsten metal film by a chemical vapor deposition process (CV ... The D process deposits a titanium nitride film (e.g., 8 nm) on the tungsten silicide film; the sixth step is to deposit a titanium film (e.g., 3 nm) on the titanium nitride film by a PVD process; the seventh step is to deposit a doped polysilicon film (e.g., 10 nm) on the titanium film by a furnace tube process; the eighth step is to form a bit line 102 and a first opening 104 located between adjacent bit lines 102 by a photolithography process and an etching process, wherein the etching process stops in the silicon nitride film on the oxide layer film, and the silicon nitride film is divided into a bit line isolation layer 206 composed of an etched portion and a first insulating layer composed of an unetched portion by an etching process.

[0104] Figure 5 for Figure 4 A cross-sectional view of the integrated circuit memory along the AA′ direction of the integrated circuit memory before the corresponding step S106 is performed;

[0105] Combination Figure 5 In one embodiment, before forming a word line on the bit line, the method further includes:

[0106] An insulating dielectric layer 106 is formed on the integrated circuit memory where the bit lines are formed. The insulating dielectric layer 106 fills the gaps between the adjacent bit lines 102 and covers the bit lines 102 .

[0107] By forming an insulating dielectric layer 106 on the integrated circuit memory forming the bit line, the bit line 102 is isolated from the bit line 102 and from the subsequently formed word line. In addition, the parasitic capacitance between the bit line 200 and the subsequently formed word line can be further improved by adjusting the thickness of the insulating dielectric layer 106.

[0108] In one embodiment, the step of forming an insulating dielectric layer 106 on the integrated circuit memory for forming bit lines includes: sequentially forming a graphic protection layer 101 and a first filling layer 103 on the integrated circuit memory for forming bit lines. The graphic protection layer 101 can protect the shape of the bit line 102 formed on the substrate, thereby preventing the subsequent process from affecting the shape of the bit line, thereby protecting the memory performance.

[0109] Exemplarily, the step of forming an insulating dielectric layer 106 on the integrated circuit memory forming the bit line includes: first, depositing a layer of silicon nitride film (graphic protection layer 101) on the surface of the integrated circuit memory forming the bit line by an ALD process, the silicon nitride film covering the surface of the integrated circuit memory forming the bit line, the surface and sidewall of the bit line, and the bottom of the first opening 104, wherein the thickness of the silicon nitride film is much smaller than the width of the first opening 104 (i.e., the distance between adjacent bit lines 104); then, depositing a silicon oxide film on the silicon nitride film by a CVD process to fill the first opening 104 between adjacent bit lines 102, the top surface of the silicon oxide film being higher than the top surface of the bit line 102; finally, performing a planarization process (CMP process) on the surface of the substrate to obtain an insulating dielectric layer 106 composed of a silicon nitride film and a remaining silicon oxide film, wherein the top surface of the insulating dielectric layer 106 is higher than the top surface of the bit line 102.

[0110] Combination Figure 6 , Figure 7 In one embodiment, the word line is a stacked structure, and step S106 includes:

[0111] A word line work function film and a word line conductive layer film are sequentially formed on the substrate surface, and a second mask pattern is formed on the substrate surface by a photolithography process, wherein the second mask pattern exposes the word line conductive layer film to be removed; after the word line conductive layer film and the word line work function film in the exposed area of ​​the second mask pattern are removed by an etching process, a word line 108 and a second opening 110 located between adjacent word lines 108 are formed on the substrate surface. The word line 108 is sequentially formed from the top surface to the top surface of the insulating dielectric layer 106 as a word line conductive layer 304 and a word line work function layer 302.

[0112] The material of the word line work function layer 302 includes at least one of titanium, titanium nitride, and tungsten silicide, for example. The material of the word line conductive layer 304 includes tungsten (W), for example.

[0113] In one embodiment, step S106 further includes: forming a word line protection film on the word line conductive layer film; and the word line 108 formed by the etching process has a word line protection layer 306. The word line protection film plays a role in maintaining the shape of the word line 108 and adjusting the etching process rate during the process of forming the word line 108 by the etching process. The material of the word line protection layer 306 includes, for example, silicon nitride.

[0114] In one embodiment, the etching process for forming the word line 108 is an over-etching process, and the over-etching process makes the first distance between the bottom of the second opening 110 and the word line work function layer 302 greater than the second distance between the top surface of the insulating dielectric layer 106 and the word line work function layer 302. The word line 108 is formed by the over-etching process, thereby avoiding the short circuit problem caused by the word line work function film residue between adjacent word lines 108 caused by process deviation, so that the word lines 108 are isolated by the insulating dielectric layer 106.

[0115] Exemplarily, step S106 is specifically as follows: first, a titanium nitride film (e.g., 3 nm) is formed on the surface of the bit line (i.e., the surface of the integrated circuit memory forming the bit line) by a CVD process; second, a tungsten film (e.g., 20 nm) is deposited on the titanium nitride film by a PVD process; third, a silicon nitride film (e.g., 50 nm) is deposited on the tungsten film by a furnace tube process; fourth, a word line 108 and a second opening 110 are formed on the surface of the substrate by a photolithography process and an etching process, and the word line 108 is isolated by an insulating dielectric layer 106 located below the word line 108. Wherein, a distance H2 between the lower surface of the word line 108 and the bottom of the second opening 110 is greater than or equal to 5 nm and less than or equal to 10 nm.

[0116] In one embodiment, the second direction in which the word line 108 extends and the first direction in which the bit line 102 extends are projected on the substrate and intersect and have a first angle φ, and the first angle φ is greater than or equal to 50 degrees and less than or equal to 90 degrees, for example, the first angle φ is greater than or equal to 60 degrees and less than or equal to 90 degrees, or the first angle φ is greater than or equal to 50 degrees and less than or equal to 70 degrees, and so on.

[0117] In one embodiment, the width of the word line 108, the width of the bit line 102, the spacing between adjacent word lines 108, and the spacing between adjacent bit lines 102 are all preset values, and the preset values ​​are greater than or equal to 30 nanometers and less than or equal to 60 nanometers. That is, the bit line 102 and the first opening 104 are arranged at an equal distance on the substrate surface at a preset value, and the word line 108 and the second opening 110 are arranged at an equal distance on the substrate surface at a preset value.

[0118] Combination Figure 8 In one embodiment, after forming the word line 108 on the bit line, the method further includes:

[0119] After the word lines are formed, a spacer dielectric layer 112 is formed on the integrated circuit memory, and the spacer dielectric layer 112 fills the gaps between the adjacent word lines 108 and covers the word lines 108. That is, the spacer dielectric layer 112 fills the second openings 110 between the word lines 108 and covers the top surface of the word lines 108. The spacer dielectric layer 112 isolates the word lines 108 and protects the graphic shape of the word lines 108. The material of the spacer dielectric layer 112 includes, for example, one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0120] Exemplarily, the step of forming an isolation dielectric layer 112 on the integrated circuit memory after forming the word line includes: depositing a layer of silicon nitride film on the surface of the integrated circuit memory after forming the word line, wherein the silicon nitride film fills the second opening 110, and the top surface of the silicon nitride film is higher than the top surface of the word line 108, and then performing a planarization process (CMP process) to obtain the isolation dielectric layer 112 composed of the remaining silicon nitride film. Among them, a silicon nitride film can be formed on the surface of the integrated circuit memory after the word line is formed by a CVD process or an ALD process, and the step of forming the silicon nitride film can also be divided into the following two steps: the first step is to deposit a first silicon nitride film (for example, 5 nm) on the surface of the integrated circuit memory after the word line is formed by an ALD process, and the first silicon nitride film covers the surface of the integrated circuit memory after the word line is formed, the surface and side wall of the word line, and the bottom of the second opening 110. The first silicon nitride film protects the shape of the word line 108 and avoids damage to the word line 108 on the side wall of the through hole during the subsequent etching process to form the through hole when the silicon nitride film is formed only by the CVD process; the second step is to deposit a second silicon nitride film (for example, 80 nm) on the first silicon nitride film by a CVD process, and the second silicon nitride film fills the second opening 110, and the top surface of the second silicon nitride film is higher than the top surface of the word line 108; when the silicon nitride film is formed by the ALD process only, the problem of too long process time when the silicon nitride film of the same thickness is formed is avoided.

[0121] Combination Fig. 9 In one embodiment, the step of forming a vertical storage transistor in an overlapping region where the word line and the bit line intersect in space comprises:

[0122] S202, opening a through hole in the overlapping area, wherein the through hole exposes the bit line.

[0123] Wherein, the diameter of the through hole is smaller than the width of the word line.

[0124] Combination Fig.10 In one embodiment, the step of opening a through hole in the overlapping area comprises:

[0125] S302, forming a first sacrificial layer pattern on the integrated circuit memory after the word line is formed, wherein the first sacrificial layer pattern covers a preset area of ​​the through hole and exposes an area outside the preset area.

[0126] Fig.11 A top view of an integrated circuit memory after a transition sacrificial layer pattern along a word line direction is obtained in a process of forming a first sacrificial layer pattern through an etching process;

[0127] Fig.12 for Fig.11 The cross-sectional view of the integrated circuit memory shown is taken along the BB' direction, wherein BB' is the first direction in which the bit lines extend;

[0128] Fig.13 A top view of the integrated circuit memory after forming a first sacrificial layer pattern;

[0129] Fig.14 for Fig.13 The cross-sectional view of the integrated circuit memory shown is taken along the AA' direction, wherein AA' is the second direction in which the word lines extend;

[0130] Combination Figure 11-Figure 14 The step of forming a first sacrificial layer pattern on the integrated circuit memory (i.e., substrate) after forming the word line includes: a first step of forming a first sacrificial layer film on the surface of the integrated circuit memory after forming the word line, the first sacrificial layer film may be a stacked film, for example, including a polysilicon layer (e.g., 50 nm), SOC (80 nm), and SION (20 nm) formed sequentially on the surface of the integrated circuit memory after forming the word line; a second step of removing a portion of the first sacrificial layer film by a photolithography process and an etching process along a second direction to obtain a transition sacrificial layer pattern 402 consisting of the remaining first sacrificial layer film located on the word line 108, the transition sacrificial layer pattern 402 extending along the second direction of the word line 108, and the projection width of the transition sacrificial layer pattern 402 on the surface of the word line 108 along the second direction is smaller than the width of the word line 108 (e.g., Fig.11 As shown); in the third step, after removing part of the transition sacrificial layer pattern 402 by a photolithography process and an etching process along the first direction, a first sacrificial layer pattern 404 consisting of the transition sacrificial layer pattern 402 located on the word line 108 is obtained; wherein, the etching processes of the second step and the third step both use the spacing dielectric layer 112 as an etching stop layer. The first sacrificial layer pattern 404 is symmetrical about the center line of the word line and the bit line. The distance CD2 between the edge of the projection of the first sacrificial layer pattern 404 on the substrate and the edge of the projection of the word line 108 on the substrate, and the distance CD1 between the edge of the projection of the first sacrificial layer pattern 404 on the substrate and the edge of the projection of the underlying bit line 102 on the substrate are equal, and are both greater than or equal to 3 nanometers and less than or equal to 8 nanometers.

[0131] S304, opening the through hole in the preset area through a pattern transfer process.

[0132] Combination Fig.15 , Fig.16 , step S304 specifically includes: the first step, forming an etching protection layer (not shown) on the surface of the integrated circuit memory after the word line is formed, the top surface of the etching protection layer and the top surface of the first sacrificial layer pattern 404 are on the same horizontal plane; the material of the etching protection layer includes silicon oxide, and the step of forming the etching protection layer is: depositing a layer of oxide film (for example, 100 nm) on the surface of the integrated circuit memory after the word line is formed to fill the gaps between the through holes and the top surface is on the top surface of the first sacrificial layer pattern 404, and then performing a planarization process until the top surface of the first sacrificial layer pattern 404, at which time the remaining oxide film constitutes the etching protection layer; the second step, removing the first sacrificial layer pattern 404 and the spacer dielectric layer 112, the word line 108, the insulating dielectric layer 106 in the preset area below it until the bit line 102 through a photolithography process and an etching process, to form a through hole 114. The third step, removing the etching protection layer on the surface of the integrated circuit memory after the word line is formed.

[0133] In one embodiment, the etching process for forming the through hole 114 is an over-etching process, and the over-etching process makes it possible to prevent the insulating dielectric layer 106 from remaining at the bottom of the through hole 114, thereby avoiding the insulating dielectric layer remaining at the bottom of the through hole 114 caused by process deviation, thereby affecting the contact between the vertical transistor subsequently formed in the through hole 114 and the bit line 102. In one embodiment, the distance between the bottom of the through hole 114 and the top (top surface) of the bit line 102 is greater than or equal to 3 nanometers and less than or equal to 5 nanometers.

[0134] S204, forming an active pillar of the vertical storage transistor and a gate dielectric layer surrounding the active pillar in the through hole.

[0135] Combination Figure 17-Figure 20 In one embodiment, the step of forming an active pillar of the vertical storage transistor and a gate dielectric layer surrounding the active pillar in the through hole 114 includes:

[0136] S402, forming an annular gate dielectric layer on the sidewall of the through hole.

[0137] In one embodiment, the step of forming an annular gate dielectric layer on the sidewall of the through hole comprises:

[0138] forming a gate dielectric layer thin film in the through hole 114, wherein the gate dielectric layer thin film covers the side wall and the bottom wall of the through hole;

[0139] forming a protective layer film on the gate dielectric layer film;

[0140] Removing the gate dielectric layer film and the protective layer film on the substrate surface and the bottom wall by an etching process, and openings are formed in the through holes to expose the bit lines;

[0141] Among them, the distance between the bottom of the opening and the top of the bit line is greater than or equal to 5 nanometers and less than or equal to 8 nanometers, so that the bit line 102 below the opening is completely exposed, avoiding the residual gate oxide layer or protective layer on the bit line 102 caused by process deviation, which affects the connection between the drain of the vertical transistor and the bit line; the distance between the bottom and the top of the bit line is greater than or equal to 3 nanometers and less than or equal to 5 nanometers.

[0142] Combination Fig.17 , Fig.18 The steps of forming a ring-shaped gate dielectric layer on the sidewall of the through hole 114 typically include: first, forming an oxide film 502 (e.g., 8 nm) on the surface of the integrated circuit memory after the word line is formed by the ALD process, and the oxide film 502 covers the surface of the integrated circuit memory after the word line is formed, the surface of the spacer dielectric layer 112, and the sidewall and bottom of the through hole 114; second, depositing a silicon film 504 on the surface of the oxide film 502, and the silicon film 504 plays a role in protecting the oxide film 502 on the sidewall of the through hole 114. At this time, a first gate dielectric layer 502 is formed in the through hole 114. Three openings 506; again, the silicon film 504, the oxide layer film 502 and part of the bit line contact layer 202 (for example, 6 nm) on the surface of the substrate, the surface of the spacing dielectric layer 112 and the bottom of the through hole 114 are removed by an etching process to obtain an annular gate dielectric layer 116 composed of the oxide layer film 502 on the side wall of the through hole 114 and a fourth opening 508 located in the through hole 114. The annular gate dielectric layer 116 surrounds the side wall of the through hole 114, thereby improving the control of the gate over the formed vertical transistor, thereby improving the operating efficiency of the integrated circuit memory.

[0143] S404, forming a drain, a source and a channel region of a vertical storage transistor in the through hole.

[0144] An active pillar is formed in the through hole, a first doping region 118 is formed in the bottom end of the active pillar, connected to the bit line, a second doping region 122 is formed in the top end of the active pillar, the second doping region 122 is used to connect a storage element (not shown), and a third doping region 120 is formed between the bottom end and the top end of the active pillar; wherein the first doping region 118, the second doping region 122 and the third doping region 120 respectively constitute the drain, source and channel region of the vertical storage transistor, and the second doping region 122 is used to connect to a storage element (e.g., a storage capacitor, etc.). The word line 108 connected to the annular gate dielectric layer 116 also serves as the metal gate of the vertical storage transistor.

[0145] In one embodiment, the first doping region 118 and the second doping region 122 are doped with a first conductivity type, and the third doping region 120 is doped with a second conductivity type, wherein the first conductivity type doping and the second conductivity type doping are opposite conductivity type dopings. For example, the first conductivity type doping is N-type doping, and the second conductivity type doping is P-type doping.

[0146] Combination Fig.19 The step of forming the drain, source and channel region of the vertical storage transistor in the through hole includes: sequentially performing three silicon depositions with different doping concentrations in the fourth opening 508 (other substrate materials, such as indium gallium arsenide (InGaAs) and gallium arsenide (GaAs), etc.), and then forming a first doping region 118, a channel region 120 and a second doping region 122 from the bit line 102 in the fourth opening 508. Specifically, for example, an in-situ doping process can be used to form the first doping region 118, the channel region 120 and the second doping region 122.

[0147] In one embodiment, one of the overlapping regions corresponds to one of the vertical memory transistors, and a unit configuration size of the vertical memory transistor on the substrate is greater than or equal to 4 times the square of a minimum feature size.

[0148] In one embodiment, six vertical memory transistors that are equidistantly adjacent to the same vertical memory transistors are arranged in a hexagonal array.

[0149] "Cell configuration size" refers to: the cell configuration size that needs to be configured on the substrate for a memory cell, specifically including: the size that a memory cell actually needs to occupy on the substrate, and the spacing size that needs to be reserved between the memory cell and the adjacent memory cell. For example, if the size occupied by N memory transistors on the substrate is M, then the cell configuration size of a memory transistor on the substrate is N / M. For a vertical memory transistor based on a vertical structure, the word line 108 and the bit line 102 intersect in space and have an overlapping area, wherein one overlapping area corresponds to a vertical memory transistor. According to the existing preparation process, a bit line 102 and a word line 108 with a minimum characteristic size F can be formed, and the line spacing between adjacent bit lines and adjacent word lines formed is also greater than or equal to the minimum characteristic size F. Then, the width size D1' of a vertical memory transistor in the direction perpendicular to the bit line is 2F, and the width size D2' in the direction perpendicular to the word line is also 2F, so the cell configuration size of the vertical memory transistor can be correspondingly made to reach 4F. 2 (2F*2F). That is, the unit configuration size of the vertical memory transistor is greater than or equal to 4 times the square of the minimum feature size.

[0150] The manufacturing method of the integrated circuit memory forms a vertical memory transistor in the overlapping area where the word line and the bit line intersect in space, that is, the source region, the channel region and the drain region are arranged vertically along the height direction, and the vertical memory transistor is located on the bit line and connected to the bit line, eliminating the step of preparing a bit line contact hole to connect the bit line and the drain region of the memory transistor, and the unit configuration size of the vertical memory transistor on the substrate is small (for example, the unit configuration size can reach 4F 2 ), so the size of the memory can be further reduced accordingly. In addition, the vertical memory transistor also has better arrangement flexibility, which is conducive to the dense arrangement of the vertical memory transistor.

[0151] Combination Fig.19 In one embodiment, an integrated circuit memory is provided, comprising:

[0152] substrate;

[0153] A bit line 102, formed on the substrate and extending along a first direction;

[0154] A word line 108, formed on the bit line and extending along the second direction;

[0155] A vertical storage transistor is formed in an overlapping region where the word line 108 and the bit line 102 intersect in space, is located in the word line 102 , and is connected to the bit line 102 .

[0156] In one embodiment, the bit line 102 is a stacked structure, for example, the bit line 120 includes a bit line isolation layer 206, a bit line conductive layer 204, a bit line work function layer (not shown) and a bit line contact layer 202 stacked in sequence on a substrate, the material of the bit line isolation layer 206 includes, for example, silicon nitride, the material of the bit line conductive layer 204 includes, for example, tungsten (W), the material of the bit line work function layer includes, for example, at least one of tungsten silicide and titanium nitride (TiN), and the material of the bit line contact layer 202 includes, for example, doped polysilicon (Poly).

[0157] It should be noted that the conductivity type of the doped ions in the doped polysilicon layer of the bit line contact layer 202 can be adjusted accordingly according to the conductivity type of the vertical memory transistor. For example, if the conductivity type of the vertical memory transistor is P-type, the doped polysilicon layer in the bit line contact layer can also be doped with P-type accordingly.

[0158] In one embodiment, the bit line 102 further includes an adhesion layer (not shown) between the bit line contact layer 202 and the bit line work function layer. The material of the adhesion layer includes, for example, one or more of titanium, titanium nitride, and tungsten silicide.

[0159] In one embodiment, the integrated circuit memory further includes an insulating dielectric layer 106 formed on the integrated circuit memory forming the bit lines (i.e., on the substrate), and the insulating dielectric layer 106 fills the gaps between the adjacent bit lines 102 and covers the bit lines 102. The insulating dielectric layer 106 isolates the bit lines 102 from each other and from the subsequently formed word lines. In addition, the parasitic capacitance between the bit lines 200 and the subsequently formed word lines can be further improved by adjusting the thickness of the insulating dielectric layer 106.

[0160] In one embodiment, the insulating dielectric layer 106 includes: a graphic protection layer 101 and a first filling layer 103. The graphic protection layer 101 can protect the shape of the bit line 102 formed on the substrate to avoid the influence of subsequent processes on the shape of the bit line, thereby protecting the memory performance.

[0161] In one embodiment, the word line 108 is a stacked structure, for example, including a word line work function layer 302 and a word line conductive layer 304 stacked in sequence. In one embodiment, the word line 108 further includes a word line protection layer 306 located on the word line conductive layer 304 .

[0162] In one embodiment, the integrated circuit memory comprises:

[0163] The spacer dielectric layer 112 fills the gaps between the adjacent word lines 108 and covers the word lines 108. The spacer dielectric layer 112 isolates the word lines 108 and protects the shape of the word lines 108. The material of the spacer dielectric layer 112 includes silicon nitride, for example.

[0164] In one embodiment, the integrated circuit memory further includes a through hole 114, which is opened on the overlapping area and exposes the bit line 102, and the active pillar of the vertical storage transistor and the gate dielectric layer 116 surrounding the active pillar are arranged in the through hole 114; wherein the diameter of the through hole 114 is smaller than the width of the word line 108.

[0165] In one embodiment, the vertical storage transistor comprises:

[0166] An annular gate dielectric layer 116 is located on the sidewall of the through hole 114;

[0167] An active pillar is located in the through hole 114, a first doped region 118 is formed in the bottom end of the active pillar, connected to the bit line 102 (directly in contact with the bit line 102), a second doped region 122 is formed in the top end of the active pillar, the second doped region 112 is used to connect a storage element (not shown), a third doped region 120 is formed between the bottom end and the top end of the active pillar, the first doped region 118, the second doped region 122 and the third doped region 120 respectively constitute the drain, source and channel regions of the vertical storage transistor.

[0168] In one embodiment, the width of the word line, the width of the bit line, the spacing between adjacent word lines, and the spacing between adjacent bit lines are all preset values, and the preset values ​​are greater than or equal to 30 nanometers and less than or equal to 60 nanometers.

[0169] In one embodiment, the second direction in which the word line 108 extends and the first direction in which the bit line 102 extends are projected on the substrate and intersect and have a first angle, the first angle being greater than or equal to 50 degrees and less than or equal to 90 degrees, for example, the first angle being greater than or equal to 60 degrees and less than or equal to 90 degrees, or the first angle being greater than or equal to 50 degrees and less than or equal to 70 degrees, and so on. One of the overlapping regions corresponds to one of the vertical memory transistors, and the unit configuration size of the vertical memory transistor on the substrate is greater than or equal to 4 times the square of the minimum feature size.

[0170] In one embodiment, the integrated circuit memory further includes: a storage element (not shown) formed above the vertical storage transistor and electrically connected to the second doped region 122 .

[0171] In the integrated circuit memory, the vertical storage transistor is formed on the overlapping area where the word line and the bit line intersect in space, that is, the source region, the channel region and the drain region are arranged vertically along the height direction, and the vertical storage transistor is located on the bit line and connected to the bit line, eliminating the bit line contact hole connecting the bit line and the drain region of the storage transistor, and the unit configuration size of the vertical storage transistor on the substrate is small (for example, the unit configuration size can reach 4F 2 ), so the size of the memory can be further reduced accordingly. In addition, the vertical memory transistor also has better arrangement flexibility, which is conducive to the dense arrangement of the vertical memory transistor.

[0172] In one embodiment, a semiconductor integrated circuit device is provided, comprising:

[0173] substrate;

[0174] A first conductive line formed on the substrate and extending along a first direction;

[0175] a second conductive line formed on the first conductive line and extending along a second direction;

[0176] The vertical storage transistor is formed in an overlapping area where the second conductive line and the first conductive line intersect in space, is located in the second conductive line, and is connected to the first conductive line.

[0177] In the semiconductor integrated circuit device, the vertical storage transistor is formed on the overlapping region where the second conductive line and the first conductive line intersect in space, that is, the source region, the channel region and the drain region are arranged vertically along the height direction, and the vertical storage transistor is located in the second conductive line and connected to the first conductive line, eliminating the second conductive line contact hole connecting the first conductive line and the drain region of the storage transistor, and the unit configuration size of the vertical storage transistor on the substrate is small (for example, the unit configuration size can reach 4F 2 ), so the size of the memory can be further reduced accordingly. In addition, the vertical memory transistor also has better arrangement flexibility, which is conducive to the dense arrangement of the vertical memory transistor.

[0178] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0179] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0180] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An integrated circuit memory, characterized in that: include: substrate; A bit line formed on the substrate and extending along a first direction; A word line formed on the bit line and extending along the second direction; A vertical storage transistor is formed in an overlapping region where the word line and the bit line intersect in space, is located in the word line, and is connected to the bit line; The bottom of the vertical memory transistor is embedded in the bit line.

2. The integrated circuit memory according to claim 1, characterized in that: The integrated circuit memory also includes a through hole, which is opened on the overlapping area and exposes the bit line. The active column of the vertical storage transistor and the gate dielectric layer surrounding the active column are arranged in the through hole; wherein the diameter of the through hole is smaller than the width of the word line.

3. The integrated circuit memory according to claim 2, characterized in that: The vertical storage transistor comprises: An annular gate dielectric layer, located on the sidewall of the through hole; An active pillar is located in the through hole, a first doped region is formed in the bottom end of the active pillar and is connected to the bit line, a second doped region is formed in the top end of the active pillar, the second doped region is used to connect the storage element, a third doped region is formed between the bottom end and the top end of the active pillar, the first doped region, the second doped region and the third doped region respectively constitute the drain, source and channel region of the vertical storage transistor.

4. The integrated circuit memory according to claim 1, wherein: The integrated circuit memory comprises: an insulating dielectric layer, the insulating dielectric layer filling the gaps between adjacent bit lines and covering the bit lines; A spacer dielectric layer is provided, wherein the spacer dielectric layer fills the gaps between adjacent word lines and covers the word lines.

5. The integrated circuit memory according to claim 1, characterized in that: The width of the word line, the width of the bit line, the spacing between adjacent word lines, and the spacing between adjacent bit lines are all preset values, and the preset values ​​are greater than or equal to 30 nanometers and less than or equal to 60 nanometers.

6. The integrated circuit memory according to any one of claims 1 to 5, characterized in that: The second direction in which the word line extends and the first direction in which the bit line extends intersect each other when projected on the substrate and have a first angle, wherein the first angle is greater than or equal to 60 degrees and less than or equal to 90 degrees; One of the overlapping regions corresponds to one of the vertical memory transistors, and a unit configuration size of the vertical memory transistor on the substrate is greater than or equal to 4 times the square of a minimum feature size.

7. A semiconductor integrated circuit device, characterized in that: include: substrate; A first conductive line formed on the substrate and extending along a first direction; a second conductive line formed on the first conductive line and extending along a second direction; a vertical storage transistor, formed in an overlapping region where the second conductive line and the first conductive line intersect in space, located in the second conductive line, and connected to the first conductive line; The bottom of the vertical storage transistor is embedded in the first conductive line.

8. A method for preparing an integrated circuit memory according to any one of claims 1 to 6, characterized in that: include: providing a substrate; forming a bit line on the substrate, wherein the bit line extends along a first direction; forming a word line on the bit line, the word line extending along a second direction; forming a vertical storage transistor in an overlapping region where the word line and the bit line intersect in space, wherein the vertical storage transistor is located in the word line and connected to the bit line; The bottom of the vertical memory transistor is embedded in the bit line.

9. The preparation method according to claim 8, characterized in that: The step of forming a vertical storage transistor in an overlapping area where the word line and the bit line intersect in space comprises: Opening a through hole in the overlapping area, wherein the through hole exposes the bit line; forming an active pillar of the vertical storage transistor and a gate dielectric layer surrounding the active pillar in the through hole; Wherein, the diameter of the through hole is smaller than the width of the word line.

10. The preparation method according to claim 9, characterized in that: The step of opening a through hole in the overlapping area comprises: forming a first sacrificial layer pattern, wherein the first sacrificial layer pattern covers a preset area of ​​the through hole and exposes an area outside the preset area; The through hole is opened in the preset area through a pattern transfer process.

11. The preparation method according to claim 9, characterized in that: The step of forming an active pillar of the vertical storage transistor in the through hole and a gate dielectric layer surrounding the active pillar comprises: forming an annular gate dielectric layer on the sidewall of the through hole; An active column is formed in the through hole, a first doping region is formed in the bottom end of the active column and connected to the bit line, a second doping region is formed in the top end of the active column, the second doping region is used to connect the storage element, and a third doping region is formed between the bottom end and the top end of the active column; The first doping region, the second doping region and the third doping region respectively constitute the drain, source and channel region of the vertical storage transistor.

12. The preparation method according to claim 8, characterized in that: Before forming a word line on the bit line, the method further includes: An insulating dielectric layer is formed on the substrate, wherein the insulating dielectric layer fills the gaps between adjacent bit lines and covers the bit lines.

13. The preparation method according to claim 8, characterized in that: After forming the word line on the bit line, the method further comprises: A spacer dielectric layer is formed on the substrate, and the spacer dielectric layer fills the gaps between adjacent word lines and covers the word lines.

14. The preparation method according to claim 8, characterized in that: The width of the word line, the width of the bit line, the spacing between adjacent word lines, and the spacing between adjacent bit lines are all preset values, and the preset values ​​are greater than or equal to 30 nanometers and less than or equal to 60 nanometers.

15. The preparation method according to claim 8, characterized in that: The second direction in which the word line extends and the first direction in which the bit line extends intersect each other when projected on the substrate and have a first angle, and the first angle is greater than or equal to 60 degrees and less than or equal to 90 degrees.

16. The preparation method according to claim 11, characterized in that: The step of forming an annular gate dielectric layer on the sidewall of the through hole comprises: forming a gate dielectric layer film in the through hole, wherein the gate dielectric layer film covers the side wall and the bottom wall of the through hole; forming a protective layer film on the gate dielectric layer film; Removing the gate dielectric film and the protective layer film on the bottom wall by an etching process, and opening the through hole to expose the bit line; The distance between the bottom of the opening and the top of the bit line is greater than or equal to 5 nanometers and less than or equal to 8 nanometers; the distance between the bottom of the through hole and the top of the bit line is greater than or equal to 3 nanometers and less than or equal to 5 nanometers.

17. The preparation method according to any one of claims 8 to 16, characterized in that: One of the overlapping regions corresponds to one of the vertical memory transistors, and a unit configuration size of the vertical memory transistor on the substrate is greater than or equal to 4 times the square of a minimum feature size.

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