Semiconductor assembly with redistribution structure for die stacking signal routing

Abstract

The present application relates to a semiconductor assembly having a redistribution structure for die stack signal routing. Semiconductor devices having a redistribution structure and associated systems and methods are disclosed herein. In some embodiments, a semiconductor assembly includes: a die stack, which includes a plurality of semiconductor dies; and a routing substrate, which is mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors that couple the redistribution structure to at least some of the die stacks. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface facing the upper surface of the routing substrate and electrically coupled to the redistribution structure, so that the routing substrate and the semiconductor die are electrically coupled to the controller die via the redistribution structure.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 066,436, filed on August 17, 2020, the entirety of which is incorporated herein by reference. Technical Field

[0003] The present technology relates generally to semiconductor devices, and more particularly, to semiconductor devices having a redistribution structure configured to route signals between vertically stacked semiconductor dies. Background Art

[0004] Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and enclosed in a protective covering. The semiconductor die may include functional features, such as memory cells, processor circuits, and imager devices, and bonding pads electrically connected to the functional features. The bonding pads may be electrically connected to terminals external to the protective covering to allow the semiconductor die to be connected to higher-level circuitry.

[0005] Market pressures continue to drive semiconductor manufacturers to reduce the size of die packages to accommodate space constraints of electronic devices, while also driving them to increase the functional capacity of each package to meet operating parameters. One method for increasing the processing power of a semiconductor package without significantly increasing the surface area covered by the package (the "footprint" of the package) is to stack multiple semiconductor dies vertically on top of each other in a single package. The dies in such vertically stacked packages may be electrically coupled to each other and / or to a substrate via wires, interconnects, or other conductive structures. However, conventional techniques for routing signals to and from vertically stacked semiconductor dies may rely on complex multi-layer routing structures within the package substrate, which may result in reduced signal integrity, larger package size, and increased manufacturing costs. Summary of the invention

[0006] One aspect of the present application relates to a semiconductor assembly comprising: a die stack including a plurality of semiconductor dies; a routing substrate mounted on the die stack, the routing substrate including an upper surface having a redistribution structure; a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies of the die stack; and a controller die mounted on the routing substrate, wherein the controller die includes an active surface facing the upper surface of the routing substrate and electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor die are electrically coupled to the controller die via the redistribution structure.

[0007] Another aspect of the present application relates to a method of manufacturing a semiconductor assembly, the method comprising: forming a redistribution structure on an upper surface of a routing substrate; mounting a controller die on the upper surface of the routing substrate so that an active surface of the controller die faces the upper surface and is electrically coupled to the redistribution structure; and coupling a lower surface of the routing substrate to a die stack comprising a plurality of semiconductor dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Many aspects of the present technology may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale. Instead, emphasis is placed on clearly illustrating the principles of the present technology.

[0009] Figure 1A is a side cross-sectional view of a semiconductor package configured in accordance with an embodiment of the present technology.

[0010] Figure 1B yes Figure 1A A top view of a semiconductor package.

[0011] Figure 1C yes Figure 1A A close-up of the interconnect structure of a semiconductor package.

[0012] Figure 2A is a side cross-sectional view of a semiconductor package including multiple electrical connectors configured in accordance with an embodiment of the present technology.

[0013] Figure 2B is a side cross-sectional view of another semiconductor package including a plurality of electrical connectors configured in accordance with embodiments of the present technology.

[0014] Figure 2C is a side cross-sectional view of another semiconductor package including a plurality of electrical connectors configured in accordance with embodiments of the present technology.

[0015] Figure 3 is a side cross-sectional view of a semiconductor package configured in accordance with an embodiment of the present technology.

[0016] Figure 4 is a schematic diagram of a system including a semiconductor device or package configured according to an embodiment of the present technology. DETAILED DESCRIPTION

[0017] Specific details of several embodiments of semiconductor devices and associated systems and methods are described below. In some embodiments, for example, a semiconductor assembly includes one or more die stacks each having a plurality of semiconductor dies, and a routing substrate (e.g., another semiconductor die or an interposer) mounted on the die stack(s). The routing substrate includes an upper surface having a redistribution structure and a lower surface coupled to the (several) uppermost semiconductor dies of the die stack(s). The redistribution structure may be coupled to some or all of the semiconductor dies via a plurality of electrical connectors (e.g., wire bonding). The semiconductor assembly may further include a controller die mounted on the routing substrate (e.g., via a flip chip process). The controller die may include an upper surface facing the routing substrate and electrically coupled to an active surface of the redistribution structure, such that the routing substrate and the semiconductor die are electrically coupled to the controller die via the redistribution structure. Thus, the redistribution structure and the electrical connector may route signals between the controller die and the die stack(s). Compared to devices in which the controller die is mounted on a packaging substrate and separated from the die stack(s), the devices described herein can reduce and / or simplify signal routing through the packaging substrate because the controller die can communicate with the die stack(s) via a redistribution structure and wire bonding (or other electrical connectors) rather than the packaging substrate. As a result, a thinner and simpler packaging substrate can be used, which reduces package height and manufacturing costs. The present technology can also improve signal integrity and impedance, such as reducing or eliminating crosstalk from overlapping signals that may occur from substrate routing because the signals are routed through the redistribution structure. In addition, the technology described herein allows the controller die to be mounted directly onto the routing substrate via a flip-chip process without any intervening spacers or supports, which can simplify the manufacturing process and further reduce the package size. In addition, the routing substrate can be used to physically and electrically bridge multiple die stacks on a single packaging substrate, which can improve the mechanical strength of the overall package and reduce warping.

[0018] Those skilled in the relevant art will recognize that the appropriate stages of the methods described herein may be performed at the wafer level or at the die level. Thus, depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, conventional semiconductor manufacturing techniques may be used to form the structures disclosed herein. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques may be used to deposit the material. Similarly, the material may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0019] Numerous specific details are disclosed herein to provide a thorough and enabling description of embodiments of the present technology. However, those skilled in the art will appreciate that the technology may have additional embodiments and may be described without the following references. Figures 1A to 4The technology is practiced without the need for some details of the described embodiments. For example, some details of semiconductor devices and / or packaging well known in the art have been omitted to avoid obscuring the technology. In general, it should be understood that various other devices and systems besides those specific embodiments disclosed herein may also be within the scope of the technology.

[0020] As used herein, the terms "vertical," "lateral," "up," "down," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "uppermost" may refer to a feature that is closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / under, up / down, and left / right may be interchanged depending on the orientation.

[0021] Figure 1A and 1B A semiconductor package 100 configured according to an embodiment of the present technology is described. More specifically, Figure 1A is a side cross-sectional view of package 100 and Figure 1B 1 is a top view of package 100. Package 100 includes a die stack 102 mounted on a package substrate 104 and a routing substrate 106 (e.g., a semiconductor die or an interposer) mounted on die stack 102. Die stack 102 includes a plurality of vertically stacked semiconductor dies 108a-c (collectively referred to as “first die 108”; for purposes of clarity only, first die 108a-c is shown in FIG. Figure 1B The first die 108 is omitted). The first die 108 may be arranged in a shingled or stepped configuration, with each die horizontally offset from the die below to allow electrical interconnection, as discussed in more detail below. Figure 1A The die stack 102 is depicted as including three first dies 108a-c, but in other embodiments, the die stack 102 may include fewer or more first dies 108 (e.g., one, two, four, five, six, seven, eight, nine, ten, or more dies). The package 100 further includes a second semiconductor die 110 ("second die 110") mounted on the routing substrate 106. The second die 110 may be a controller die (e.g., a microcontroller) configured to control the operation of the routing substrate 106 and / or the first die 108, as discussed in more detail below.

[0022] The first and second dies 108, 110 may each include a semiconductor substrate (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.). In some embodiments, the first and second dies 108, 110 each include a front and / or active surface having various types of semiconductor components. For example, the first die 108 and / or the second die 100 may each have a memory circuit (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory (e.g., NAND, NOR), or other types of memory circuits), a controller circuit (e.g., a DRAM controller circuit), a logic circuit, a processing circuit, a circuit element (e.g., wires, traces, interconnects, transistors, etc.), an imaging component, and / or other semiconductor features. In some embodiments, the first dies 108 may each be arranged in a "face-up" configuration, wherein their front surfaces are oriented upward and away from the packaging substrate 104. However, in other embodiments, one or more of the first dies 108 may be in a "face-down" configuration, wherein their front surfaces are oriented downward and toward the packaging substrate 104. Optionally, one or more of the first dies 108 may be a "blank" substrate that does not include semiconductor components and is formed of, for example, crystalline, semi-crystalline and / or ceramic substrate materials, such as silicon, polysilicon, aluminum oxide (Al2O3), sapphire and / or other suitable materials.

[0023] The routing substrate 106 includes a redistribution structure 112 configured to route signals (e.g., control signals, ONFI signals, power signals, test signals, etc.) between the second die 110 and the first die 108 of the die stack 102. For example, in embodiments where the routing substrate 106 is a semiconductor die or otherwise includes functional components, the redistribution structure 112 may also route signals between the second die 110 and the routing substrate 106. Figure 1A As best seen in FIG. 1 , routing substrate 106 may include an upper (e.g., front) surface 114 a and a lower (e.g., rear) surface 114 b, and redistribution structure 112 may have pads or other terminals exposed at upper surface 114 a. In some embodiments, redistribution structure 112 is or includes a redistribution layer (RDL) (e.g., formed after wafer probe testing) or an inline redistribution layer (iRDL) (e.g., formed before wafer probe testing).

[0024] The redistribution structure 112 may include one or more conductive components, such as contacts, traces, pads, pins, wiring, circuit systems, etc., and one or more dielectric materials. The conductive components of the redistribution structure 112 may be made of any suitable conductive material, such as one or more metals (e.g., copper, gold, titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). Although Figure 1AThe redistribution structure 112 is illustrated as having a single routing or metallization layer, but in other embodiments, the redistribution structure 112 may include multiple routing or metallization layers (eg, two, three, four, five, or more layers).

[0025] The routing substrate 106 may be any component that is a suitable substrate for manufacturing the redistribution structure 112. In some embodiments, the routing substrate 106 is a semiconductor die, such as a semiconductor die having similar features to the first and / or second dies 108, 110. For example, the routing substrate 106 may be a memory die (e.g., a NAND die, an SRAM die, etc.), and the first die 108 may also be a memory die (e.g., a NAND die). Alternatively, the routing substrate 106 may be an interposer, such as an inorganic interposer (e.g., silicon, glass, ceramic, etc.) or an organic interposer (e.g., FR-4, polyimide, coreless laminate, etc.). The redistribution structure 112 may be formed on the routing substrate 106 using any suitable technology known to those skilled in the art, such as a semiconductor manufacturing process (e.g., if the routing substrate 106 is a semiconductor die, an inorganic interposer or other inorganic substrate) or a circuit board manufacturing process (e.g., if the routing substrate 106 is an organic interposer or other organic substrate).

[0026] Optionally, in addition to the redistribution structure 112, the routing substrate 106 may also include other functional components. For example, the routing substrate 106 may include active circuit elements (e.g., transistors, memory circuits, controller circuits, logic circuits, or other semiconductor elements) and the redistribution structure 112 is formed on or over the active circuit elements. In some embodiments, the routing substrate 106 is a memory die (e.g., a NAND die, an SRAM die, etc.) and the redistribution structure 112 is formed on or over the memory circuits of the memory die. As another example, the routing substrate 106 may include passive circuit elements, such as capacitors, inductors, and / or resistors. The passive circuit elements may be formed in the routing substrate 106 using semiconductor manufacturing techniques, or may be surface mount components attached to the routing substrate 106, as discussed in more detail below. However, in other embodiments, the routing substrate 106 may be used only to route signals between the second die 110 and the first die 108 of the die stack 102, and may not include any additional active and / or passive circuit elements.

[0027] The second die 110 is electrically and mechanically coupled to the redistribution structure 112 on the routing substrate 106 through the interconnect structure 118. Figure 1AAs best seen in FIG. 1 , the second die 110 may include an upper (e.g., rear) surface 116a and a lower (e.g., active and / or front) surface 116b. The second die 110 may be mounted to the routing substrate 106 in a face-to-face (F2F) configuration, with the lower surface 116b of the second die 110 facing the upper surface 114a of the routing substrate 106 and the redistribution structure 112. In some embodiments, the second die 110 is directly connected to the routing substrate 106 without any intervening spacers, supports, other dies, etc. between the second die 110 and the routing substrate 106.

[0028] Reference together Figure 1A and 1C ( Figure 1C yes Figure 1A ), the interconnect structure 118 may be a bump, microbump, pillar, column, stud, etc. between the lower surface 116b of the second die 110 and the redistribution structure 112. Figure 1C As shown in , each interconnect structure 118 can connect a pin or pad 120 (eg, a data pin, an address pin, a control pin) on the second die 110 to a corresponding contact 122 of the redistribution structure 112. Figure 1C A single pin 120 and a single contact 122 are illustrated, but it will be appreciated by those skilled in the art that the second die 110 may include a plurality of pins 120 and the redistribution structure 112 may include a corresponding plurality of contacts 122. The interconnect structure 118 may include any suitable conductive material, such as copper, nickel, gold, silicon, tungsten, solder (e.g., SnAg-based solder), conductive epoxy, combinations thereof, etc., and may be formed by electroplating, electroless plating, or other suitable processes. In some embodiments, the interconnect structure 118 also includes a barrier material (e.g., nickel, nickel-based intermetallic compounds, and / or gold; not shown) formed over an end portion of the interconnect structure 118. The barrier material may facilitate bonding and / or prevent or at least inhibit electromigration of copper or other metals used to form the interconnect structure 118. Optionally, the interconnect structure 118 may be surrounded by an underfill material (not shown) between the routing substrate 106 and the second die 110.

[0029] Reference together Figure 1B and 1C , the redistribution structure 112 may include a plurality of traces 124 extending above the upper surface 114a of the routing substrate 106 to route signals from the second die 110 to the periphery of the routing substrate 106. The second die 110 may be located on the routing substrate 106 ( Figure 1B ), and the trace 124 can be connected from the interconnect structure 118 and the contact 122 ( Figure 1C ) extends to a plurality of bonding pads 126 at a peripheral portion of the routing substrate 106. Each trace 124 can connect a corresponding contact 122 ( Figure 1C ) is electrically connected to corresponding bonding pads 126 at the peripheral portion of routing substrate 106 ( Figure 1B ). The traces 124 may be separated from each other by an insulating material (eg, a dielectric material; not shown) to reduce or eliminate interference and / or crosstalk between individual traces 124.

[0030] The number, geometry, and arrangement of traces 124 may be designed to provide different signal routing configurations and may be customized for a particular device or package. Figure 1B 106. The traces 124 shown in FIG. 104 may extend to each of the four edges of the routing substrate 106. However, in other embodiments, the traces 124 may extend to fewer edges of the routing substrate 106, such as one edge, two edges, or three edges. In addition, some or all of the traces 124 may have different geometries (e.g., different lengths, widths, shapes, etc.). For example, trace 124a is wider than trace 124b, which is wider than trace 124c. In some embodiments, different geometries are used to accommodate different types of signals, for example, wider traces may be used for power delivery, while narrower traces may be used for high-speed data signals.

[0031] Let’s refer to it again Figure 1A and 1B , the package 100 further includes a plurality of electrical connectors 128a-d (e.g., wire bonds) that couple the redistribution structure 112, the package substrate 104, and the first die 108 to each other to route signals (e.g., control signals, ONFI signals, power signals, test signals, etc.) between these components. In some embodiments, an end of each electrical connector is attached to a corresponding bonding pad on a corresponding package component (represented only for clarity purposes). Figure 1A The redistribution structure 112 and the bonding pads on the first die 108 are omitted in the figure. For example, the redistribution structure 112 can be connected to the bonding pads 126 ( Figure 1B ) and one or more electrical connectors 128a extending between the second die 110 and the corresponding bonding pads 130 on the packaging substrate 104 are electrically coupled to the packaging substrate 104. Thus, the redistribution structure 112 and the electrical connectors 128a can directly route signals (e.g., power signals, signals to and / or from a host device) between the second die 110 and the packaging substrate 104.

[0032] The redistribution structure 112 and the electrical connectors 128b-c may route signals between the second die 110 and each of the first dies 108 of the die stack 102. For example, in the illustrated embodiment, the package 100 includes at least one electrical connector 128b that electrically couples the redistribution structure 112 to the uppermost first die 108a to route signals directly between the second die 110 and the uppermost first die 108a. The package 100 may also include a series of cascaded electrical connectors 128c that connect the first dies 108a-c to each other. For example, the uppermost first die 108a is electrically coupled to the first die 108b through one electrical connector 128c, and the first die 108b is electrically coupled to the lowermost first die 108c through another electrical connector 128c. Thus, the redistribution structure 112, the electrical connectors 128b-c, and the uppermost first die 108a may collectively route signals between the second die 110 and the first die 108b. Similarly, the redistribution structure 112, the electrical connectors 128b-c, and the first dies 108a-b may collectively route signals between the second die 110 and the lowermost first die 108c. Optionally, the package 100 may include at least one electrical connector 128d that electrically couples the lowermost first die 108c directly to the package substrate 104. The electrical connector 128d may route signals (e.g., test signals) directly between the lowermost first die 108c and the package substrate 104.

[0033] Despite Figure 1A and 1B In the configuration of , the electrical connectors 128a-d are depicted as wire bonds, but the package 100 may include other types of electrical connectors for electrically coupling the redistribution structure 112, the package substrate 104, the routing substrate 106, and / or the first die 108 to each other. In other embodiments, for example, Figure 1A and 1B Any of the die-to-die connections (e.g., between routing substrate 106 and uppermost first die 108a and / or between any first die 108) and / or die-to-substrate connections (e.g., between lowermost first die 108c and packaging substrate 104) shown in the drawings may instead be implemented using through silicon vias (TSVs), interconnect structures (e.g., bumps, micro-bumps, pillars, columns, studs, etc.), and / or any other interconnect technology known to those skilled in the art. Furthermore, in other embodiments, one or more of electrical connectors 128a-d may be omitted. Figures 2A to 2C Additional examples of configurations of the electrical connectors 128a - d are discussed further.

[0034] The package substrate 104 may be or include an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable substrate. In some embodiments, the package substrate 104 includes additional semiconductor components (e.g., a doped silicon wafer or a gallium arsenide wafer), non-conductive components (e.g., various ceramic substrates, such as aluminum oxide (Al2O3), etc.), aluminum nitride, and / or conductive portions (e.g., interconnect circuitry, TSVs, etc.). The package substrate 104 may further include an electrical connector 134 (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements) electrically coupled to the package substrate 104 and configured to electrically couple the package 100 to an external device (not shown) (e.g., a host device as further discussed below). Optionally, the package substrate 104 may include one or more signal routing structures or layers (not shown) that include conductive components, such as traces, vias, etc., that transmit signals between the electrical connector 134 and the second die 110 and / or the die stack 102. As previously discussed, the configuration of the die stack 102, the second die 110, and the redistribution structure 112 described herein can reduce routing of signals through the package substrate 104, such that the package substrate 104 can be thinner and / or simpler than conventional systems that route controller signals through the package substrate. For example, the package substrate 104 can include no more than one, two, three, or four signal routing layers. The thickness of the package substrate 104 can be less than or equal to 250 μm, 200 μm, 150 μm, 125 μm, 100 μm, or 75 μm.

[0035] The package 100 may further include a molding material or encapsulant 140 (removed from the figure for purposes of clarity only) formed over at least a portion of the packaging substrate 104 and / or at least partially surrounding the routing substrate 106 and the first and second dies 108, 110. Figure 1B Molding material 140 is omitted). Molding material 140 may be a resin, epoxy, silicon-based material, polyimide, or any other material suitable for encapsulating at least a portion of routing substrate 106, first and second dies 108, 110, and / or packaging substrate 104 to protect these components from contamination and / or physical damage.

[0036] Optionally, package 100 may include surface mount components 150 ( Figure 1A and 1B Surface mount components may be provided on the packaging substrate 104 (e.g., at a peripheral portion away from the die stack 102 and the bonding pads 130), on the routing substrate 106 (e.g., at a location away from the traces 124 and the second die 110), or on the routing substrate 106 (e.g., at a location away from the traces 124 and the second die 110). Figure 1B) and / or at any other suitable location. In some embodiments, semiconductor package 100 includes other components, such as an external heat sink, a housing (eg, a thermally conductive housing), an electromagnetic interference (EMI) shielding component, etc.

[0037] In some embodiments, package 100 is operably connected to a host device (not shown) via electrical connector 134. The host device may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or a component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device may be a networking device (e.g., a switch, a router, etc.), a digital image, audio and / or video recorder, a vehicle, an appliance, a toy, or any of a number of other products. In some embodiments, the host device is directly connected to package 100, while in other embodiments, the host device may be indirectly connected to package 100 (e.g., through a networking connection or through an intermediate device).

[0038] For example, in some embodiments, package 100 is a memory device and is configured to be connected to a host device or a component thereof that utilizes memory to temporarily or permanently store information. In such embodiments, first die 108 may be a memory die (e.g., a NAND memory die), and second die 110 may be a memory controller. Routing substrate 106 may also be a memory die (e.g., a NAND memory die, an SRAM memory die). For example, routing substrate 106 may be an SRAM memory die or other memory die that provides data storage for the operation of a memory controller. Alternatively, routing substrate 106 may not include any memory circuits and may only function to route signals between a memory controller and individual memory dies. The memory device may include a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus to receive command signals CMD and address signals ADDR, respectively. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI and DMI for receiving data signals and / or power supply terminals VDD, VSS and VDDQ.

[0039] The package 100 may be manufactured using any suitable process known to those skilled in the art. In some embodiments, for example, the manufacturing process of the package 100 includes forming a redistribution structure 112 on the routing substrate 106 using a wafer-level or chip-level process. Subsequently, the routing substrate 106 is mounted on the die stack 102 (e.g., via a die attach film or other suitable technique). The die stack 102 may be mounted on the packaging substrate 104 before, during, or after the routing substrate 106 is mounted on the die stack 102. The second die 110 may be mounted on the routing substrate 106 before, during, or after the routing substrate 106 is mounted on the die stack 102. In some embodiments, the second die 110 is mechanically and electrically coupled to the routing substrate 106 via the interconnect structure 118 using a thermocompression bonding (TCB) operation. Then, electrical connectors 128a-d may be formed and attached to the routing substrate 106, the first and second dies 108, 110, and the packaging substrate 104 to electrically couple these components to each other, as discussed above.

[0040] Figures 2A to 2C Semiconductor packages having various electrical connector arrangements configured in accordance with embodiments of the present technology are described. Figures 2A to 2C The packaging shown in Figures 1A to 1C The described packages 100 are generally similar. Therefore, like numbers are used to identify similar or identical components, and Figures 2A to 2C The description of the packages shown in the Figures 1A to 1C The package has 100 different features.

[0041] Figure 2A A semiconductor package 200a is illustrated that includes a plurality of electrical connectors 248a-c (e.g., wire bonds) for interconnecting a die stack 102, a package substrate 104, a routing substrate 106, and a second die 110. Electrical connector 248a couples the redistribution structure 112 directly to the package substrate 104; electrical connector 248b couples the redistribution structure 112 directly to the uppermost first die 108a; and cascade electrical connector 248c couples the first die 108a-c in series with each other. Figures 1A to 1C Unlike package 100 of the prior art, package 200a does not include any electrical connectors that directly couple the lowermost first die 108c to the package substrate 104. Instead, electrical connectors 248a-c, redistribution structure 112, and first dies 108a-b collectively route signals between the lowermost first die 108c and the package substrate 104.

[0042] Figure 2BA semiconductor package 200b is illustrated that includes a plurality of electrical connectors 248a-c (e.g., wire bonds) for interconnecting a die stack 102, a packaging substrate 104, a routing substrate 106, and a second die 110. An electrical connector 258a directly couples a redistribution structure 112 to the packaging substrate 104. In the illustrated embodiment, each first die 108 is directly electrically coupled to the redistribution structure 112 via a set of respective electrical connectors. For example, electrical connector 258b directly couples the uppermost first die 108a to the redistribution structure 112; electrical connector 258c directly couples the first die 108b to the redistribution structure 112; and electrical connector 258d directly couples the lowermost first die 108c to the redistribution structure 112. Thus, the redistribution structure 112 and the electrical connectors 258b-d can transmit signals directly between the respective first die 108 and the second die 1102.

[0043] Figure 2C A semiconductor package 200c is illustrated that includes a plurality of electrical connectors 268a-c (e.g., wire bonds) for interconnecting a die stack 102, a packaging substrate 104, a routing substrate 106, and a second die 110. The electrical connector 268a directly couples the redistribution structure 112 to the packaging substrate 104. In the illustrated embodiment, some of the first dies 108 are directly electrically coupled to the redistribution structure 112, while some of the first dies 108 are indirectly coupled via other first dies 108. For example, the electrical connectors 268b-c respectively directly couple the first dies 108a-b to the redistribution structure 112 to provide direct signal transmission between the second die 110 and each of the first dies 108a-b. However, the lowermost first die 108c is not directly coupled to the redistribution structure 112. Instead, electrical connector 268d couples lowermost first die 108c to first die 108b, and first die 108b routes signals between lowermost first die 108c and second die 110. However, in other embodiments, package 200c may include different routing configurations between second die 110 and first die 108.

[0044] Figure 3 is a schematic cross-sectional view of a semiconductor package 300 configured in accordance with an embodiment of the present technology. The package 300 may be used with respect to Figures 1A to 2C The packages described are generally similar, except that package 300 includes multiple die stacks (e.g., first die stack 302a and second die stack 302b) rather than a single die stack. Therefore, like numbers are used to identify similar or identical components (e.g., routing substrate 306 versus routing substrate 106), and the description of package 300 will be limited to the same as Figures 1A to 2C The encapsulation has different features.

[0045] The first and second die stacks 302a-b are mounted on the package substrate 104. The first and second die stacks 302a-b may each be Figures 1A to 1C The die stacks 102 of the embodiment of the present invention are the same or substantially similar. For example, the first die stack 302a includes a first group of first semiconductor dies 308a (e.g., a first group of memory dies) and the second die stack 302b includes a second group of first semiconductor dies 308b (e.g., a second group of memory dies). In the illustrated embodiment, both the first and second die stacks 302a-b are arranged in a shingled configuration and are angled toward each other. In other embodiments, the first and second die stacks 302a-b may be angled away from each other, angled in parallel directions, or any other suitable configuration. In addition, although the first and second die stacks 302a-b are depicted as each including four dies, in other embodiments, the first and / or second die stacks 302a-b may include fewer or more dies (e.g., one, two, three, five or more dies). The first and second die stacks 302a-b may include the same number of dies and / or otherwise have the same or substantially similar heights.

[0046] The package 300 further includes a routing substrate 306 (eg, another semiconductor die or an interposer), wherein a redistribution structure 312 is formed on an upper surface 314a of the routing substrate 306. The routing substrate 306 may be connected to a Figures 1A to 2C The routing substrate 106 of FIG. 1 is the same or substantially similar to the routing substrate 106 of FIG. 1 , except that the routing substrate 306 is mounted on a plurality of die stacks (eg, the first and second die stacks 302a-b). Figure 3 , the lower surface 314b of the routing substrate 306 is coupled to the uppermost die in each of the first and second die stacks 302a-b. By bridging the first and second die stacks 302a-b, the routing substrate 306 can increase the mechanical strength of the package 300 (e.g., improve three-point bending performance) and reduce warping (e.g., due to heating during manufacturing and / or operation).

[0047] The redistribution structure 312 (eg, iRDL or RDL structure) is configured to route signals between the first and second die stacks 302a-b and a second die 310 (eg, a controller die) mounted on the routing substrate 306. The redistribution structure 312 may be configured to communicate with the first and second die stacks 302a-b. Figures 1A to 2C The redistribution structure 112 is the same or substantially similar to the redistribution structure 112 of the embodiment, except that the redistribution structure 312 routes signals to multiple die stacks (e.g., the first and second die stacks 302a-b). Similarly, the second die 310 can be connected to Figures 1A to 2CThe second die 310 may be identical or substantially similar to the second die 110 of the routing substrate 306, except that the second die 310 communicates with a plurality of die stacks (e.g., the first and second die stacks 302a-b). The second die 310 may include an upper (e.g., rear) surface 316a facing away from the routing substrate 306, and a lower (e.g., active and / or front) surface 316b facing the upper surface 314a of the routing substrate 306 and the redistribution structure 312. The second die 310 may be electrically and mechanically coupled to the redistribution structure 312 via an interconnect structure 318.

[0048] In some embodiments, the redistribution structure 312 is electrically coupled to the package substrate 104, the first die stack 302a, and / or the second die stack 302b via a plurality of electrical connectors 328a-c (e.g., wire bonds). For example, the package 300 may include a set of electrical connectors 328a that connect the redistribution structure 312 to the package substrate 104, a set of electrical connectors 328b that connect the redistribution structure 312 to the first set of first dies 308a of the first die stack 302a, and / or a set of electrical connectors 328c that connect the redistribution structure 312 to the second set of first dies 308b of the second die stack 302b. Thus, the electrical connectors 328a-c and the redistribution structure 312 may route signals (e.g., control signals, ONFI signals, power signals, test signals, etc.) between the second die 310, the first die stack 302a, the second die stack 302b, the package substrate 104, and / or the routing substrate 306. In the illustrated embodiment, electrical connector 328b is arranged in cascade series, while electrical connector 328c includes both cascade connectors and connectors that connect directly to individual dies. However, in other embodiments, any of electrical connectors 328a-c may be arranged differently (e.g., as previously described with respect to Figures 2A to 2C ), or may be omitted entirely. In addition, package 300 may include Figure 3 Additional electrical connectors not shown, such as electrical connectors between the die and the packaging substrate 104.

[0049] Optionally, the package 300 may include one or more surface mount components 150, such as capacitors, resistors, inductors, and / or other circuit elements. The surface mount components may be on the package substrate 104 (e.g., at a peripheral portion away from the first and second die stacks 302a-b, between the first and second die stacks 302a-b), on the routing substrate 106, or on any other suitable location.

[0050] The package 300 may be manufactured using any suitable process known to those skilled in the art. In some embodiments, for example, the manufacturing process of the package 300 includes mounting the first and second die stacks 302a-b on the package substrate 104. The process further includes forming a redistribution structure 312 on the routing substrate 306 using a wafer-level or chip-level process. Subsequently, the routing substrate 306 is mounted on the first and second die stacks 302a-b (e.g., via a die attach film or other suitable technique). The second die 310 may be mounted on the routing substrate 306 before, during, or after the routing substrate 306 is mounted on the first and second die stacks 302a-b. Then, electrical connectors 328a-c may be formed and attached to the routing substrate 306, the first and second die stacks 302a-b, and the package substrate 104 to electrically couple these components to each other, as discussed above.

[0051] although Figure 3 The package 300 is illustrated with a routing substrate 306 configured to transmit signals between two die stacks, but in other embodiments, the package 300 may include a greater number of die stacks, such as three, four, five, or more die stacks. In such embodiments, the routing substrate 306 may be mechanically and electrically coupled to each of the die stacks to route signals between the die stacks, a controller die (e.g., the second die 310), and / or the package substrate 104.

[0052] With above reference Figures 1A to 3 Any of the semiconductor devices and / or packages of the described features may be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is Figure 4 Schematically shown in the system 400. The system 400 may include a processor 402, a memory 404 (eg, SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 406, and / or other subsystems or components 408. Figures 1A to 3 The semiconductor die and / or package described may be included in Figure 4. The resulting system 400 may be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Thus, representative examples of system 400 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 400 include lights, cameras, vehicles, and the like. With respect to these and other examples, system 400 may be housed in a single unit or distributed over multiple interconnected units, such as via a communications network. Components of system 400 may therefore include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0053] It will be understood from the foregoing that specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from the present disclosure. Therefore, the present invention is not limited except by the appended claims. In addition, certain aspects of the new technology described in the context of a specific embodiment may also be combined or eliminated in other embodiments. In addition, although the advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments necessarily exhibit such advantages and fall within the scope of the present technology. Therefore, the present disclosure and associated technology may cover other embodiments that are not explicitly shown or described herein.

Claims

1. A semiconductor assembly comprising: a die stack comprising a plurality of semiconductor dies; a routing substrate mounted on the die stack, the routing substrate comprising an upper surface having a redistribution structure; a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies of the die stack; and A controller die is mounted on the routing substrate, wherein the controller die includes an active surface facing the upper surface of the routing substrate and electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor die are electrically coupled to the controller die via the redistribution structure.

2. The semiconductor assembly of claim 1, wherein the routing substrate is a semiconductor die.

3. The semiconductor assembly of claim 2, wherein the routing substrate is a memory die.

4. The semiconductor assembly of claim 1, wherein the routing substrate is an organic or inorganic interposer.

5. The semiconductor assembly of claim 1, wherein the redistribution structure comprises a plurality of routing layers.

6. The semiconductor assembly of claim 1, further comprising a plurality of interconnect structures coupling the active surface of the controller die to the redistribution structure of the routing substrate.

7. The semiconductor assembly of claim 6, wherein the redistribution structure comprises: a plurality of contacts at an interior portion of the routing substrate, wherein each contact is coupled to a respective interconnect structure; a plurality of bond pads at a peripheral portion of the routing substrate, wherein each bond pad is coupled to a respective electrical connector; and A plurality of traces, wherein each trace connects a respective contact to a respective bond pad.

8. The semiconductor assembly of claim 7, wherein at least some of the traces have different widths.

9. The semiconductor assembly of claim 1, wherein the semiconductor die is a memory die.

10. The semiconductor assembly of claim 1, wherein: The die stack is a first die stack and the semiconductor die is a first semiconductor die; The semiconductor assembly further includes a second die stack comprising a plurality of second semiconductor dies; and The routing substrate is mounted on the first and second die stacks such that the second semiconductor die is electrically coupled to the controller die through the redistribution structure.

11. The semiconductor assembly of claim 10, wherein the electrical connector is a first electrical connector, and the semiconductor assembly further comprises a plurality of second electrical connectors coupling the redistribution structure to at least some of the second semiconductor dies of the second die stack.

12. The semiconductor assembly of claim 1, further comprising a packaging substrate supporting the die stack, wherein the packaging substrate is coupled to the die stack and the controller die via the redistribution structure and the electrical connector.

13. The semiconductor assembly of claim 12, wherein the packaging substrate includes no more than two routing layers.

14. The semiconductor assembly of claim 1, wherein the routing substrate further comprises one or more passive circuit elements.

15. A method of manufacturing a semiconductor assembly, the method comprising: forming a redistribution structure on an upper surface of a routing substrate; mounting a controller die on the upper surface of the routing substrate such that an active surface of the controller die faces the upper surface and is electrically coupled to the redistribution structure; and A lower surface of the routing substrate is coupled to a die stack including a plurality of semiconductor dies.

16. The method of claim 15, wherein the active surface of the controller die is electrically coupled to the redistribution structure via a thermocompression bonding process.

17. The method of claim 16, wherein the thermocompression bonding process comprises connecting the active surface to the redistribution structure using a plurality of interconnect structures.

18. The method of claim 15, further comprising electrically coupling the redistribution structure to at least some of the semiconductor dies using a plurality of wire bonds.

19. The method of claim 15, further comprising mounting the die stack on a packaging substrate.

20. The method of claim 19, further comprising electrically coupling the redistribution structure to the package substrate using one or more wire bonds.

21. The method of claim 15, wherein the die stack is a first die stack and the semiconductor die is a first semiconductor die, and the method further comprises coupling the lower surface of the routing substrate to a second die stack comprising a plurality of second semiconductor dies.

22. The method of claim 15, wherein the redistribution structure is formed using a wafer level process.

23. The method of claim 15, wherein forming the redistribution structure comprises forming a plurality of traces, at least some of the traces having different widths.

24. The method of claim 15, wherein the redistribution structure is configured to route signals between the controller die and the die stack.

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